阅读说明：本技术 一种显示基板及其制作方法、显示装置 (Display substrate, manufacturing method thereof and display device ) 是由 李然 田宏伟 李良坚 于 2021-07-27 设计创作，主要内容包括：本发明提供了一种显示基板及其制作方法、显示面板,涉及显示技术领域,该显示基板具有窄边框。该显示基板包括：第一晶体管包括第一栅极、第一有源部和第一栅绝缘部；第一栅绝缘部设置在第一栅极和第一有源部之间、且沿垂直于衬底的方向至少与第一栅极交叠；第二晶体管包括第二栅极、第二有源部和第二栅绝缘部；第二栅绝缘部设置在第二栅极和第二有源部之间、且沿垂直于衬底的方向至少与第二栅极交叠；第一晶体管的第一栅绝缘部中沿垂直于衬底的方向与第一栅极交叠的部分的厚度,小于至少一个第二晶体管的第二栅绝缘部中沿垂直于衬底的方向与第二栅极交叠的部分的厚度。(The invention provides a display substrate, a manufacturing method thereof and a display panel, and relates to the technical field of display. The display substrate includes: the first transistor includes a first gate electrode, a first active portion, and a first gate insulating portion; a first gate insulating part disposed between the first gate electrode and the first active part and overlapping at least the first gate electrode in a direction perpendicular to the substrate; the second transistor includes a second gate electrode, a second active portion, and a second gate insulating portion; a second gate insulating portion disposed between the second gate electrode and the second active portion and overlapping at least the second gate electrode in a direction perpendicular to the substrate; the thickness of a portion of the first gate insulator of the first transistor overlapping the first gate in a direction perpendicular to the substrate is smaller than the thickness of a portion of the second gate insulator of the at least one second transistor overlapping the second gate in a direction perpendicular to the substrate.)

1. A display substrate, comprising a substrate; the display substrate further comprises a display area and a non-display area connected with the display area, wherein the non-display area comprises at least one first transistor, and the display area comprises at least one second transistor;

the first transistor includes a first gate electrode, a first active portion, and a first gate insulating portion; the first gate insulating part is disposed between the first gate electrode and the first active part and overlaps at least the first gate electrode in a direction perpendicular to the substrate;

the second transistor includes a second gate electrode, a second active portion, and a second gate insulating portion; the second gate insulating part is disposed between the second gate electrode and the second active part and overlaps at least the second gate electrode in a direction perpendicular to the substrate;

the thickness of a portion of the first gate insulating portion of the first transistor that overlaps the first gate electrode in a direction perpendicular to the substrate is smaller than the thickness of a portion of the second gate insulating portion of at least one of the second transistors that overlaps the second gate electrode in a direction perpendicular to the substrate.

2. The display substrate according to claim 1, wherein the first gate electrode and the second gate electrode are disposed in the same layer, and the first active portion and the second active portion are disposed in the same layer.

3. The display substrate of claim 1, wherein an orthographic projection of the first active portion on the substrate is located within an orthographic projection of the first gate insulating portion on the substrate.

4. The display substrate according to claim 3, wherein the first gate insulating portion has a uniform thickness.

5. The display substrate according to claim 4, wherein the first gate insulating portion further extends to an edge of the display region;

the second gate insulating portion of the second transistor also extends to an edge of the display region.

6. The display substrate according to claim 5, wherein the second gate insulating portion of the second transistor has a uniform thickness.

7. The display substrate according to claim 1, wherein a thickness of a portion of the first gate insulating portion of the first transistor which overlaps with the first gate electrode in a direction perpendicular to the substrate is in a range of 20 to 100 nm;

the thickness of the part, which is overlapped with the second gate electrode along the direction vertical to the substrate, in the second gate insulating part of the second transistor is in the range of 100-160 nm.

8. The display substrate according to claim 1, wherein the first gate is disposed on a side of the first active portion away from the substrate, and the second gate is disposed on a side of the second active portion away from the substrate;

or, the first gate is disposed on a side of the first active portion close to the substrate, and the second gate is disposed on a side of the second active portion close to the substrate.

9. A display device comprising the display substrate according to any one of claims 1 to 8.

10. The method for manufacturing a display substrate according to any one of claims 1 to 8, wherein the display substrate comprises a display region and a non-display region connected to the display region;

the manufacturing method comprises the following steps:

providing a substrate;

forming at least one first transistor and at least one second transistor on the substrate; wherein the at least one first transistor is disposed in the non-display region and the at least one second transistor is disposed in the display region; the first transistor includes a first gate electrode, a first active portion, and a first gate insulating portion; the first gate insulating part is disposed between the first gate electrode and the first active part and overlaps at least the first gate electrode in a direction perpendicular to the substrate; the second transistor includes a second gate electrode, a second active portion, and a second gate insulating portion; the second gate insulating part is disposed between the second gate electrode and the second active part and overlaps at least the second gate electrode in a direction perpendicular to the substrate; a thickness of a portion of the first gate insulating portion of the first transistor overlapping the first gate electrode in a direction perpendicular to the substrate is smaller than a thickness of a portion of the second gate insulating portion of the second transistor overlapping the second gate electrode in the direction perpendicular to the substrate;

the forming at least one first transistor and at least one second transistor on the substrate includes:

and forming a first gate insulating part and a second gate insulating part by adopting a one-step patterning process.

Technical Field

The invention relates to the technical field of display, in particular to a display substrate, a manufacturing method of the display substrate and a display device.

Background

The size of the GOA (Gate Driver on Array) area of the display device affects the frame of the device. The existing GOA region is generally composed of a large width-to-length ratioA large TFT (Thin Film Transistor) is formed, so that the display device is difficult to realize a narrow frame, and the user experience is poor.

Disclosure of Invention

The embodiment of the invention provides a display substrate, a manufacturing method thereof and a display device.

In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:

in one aspect, a display substrate, a method for manufacturing the same, and a display panel are provided, where the display substrate includes: a substrate; the display substrate further comprises a display area and a non-display area connected with the display area, wherein the non-display area comprises at least one first transistor, and the display area comprises at least one second transistor;

the first transistor includes a first gate electrode, a first active portion, and a first gate insulating portion; the first gate insulating part is disposed between the first gate electrode and the first active part and overlaps at least the first gate electrode in a direction perpendicular to the substrate;

the second transistor includes a second gate electrode, a second active portion, and a second gate insulating portion; the second gate insulating part is disposed between the second gate electrode and the second active part and overlaps at least the second gate electrode in a direction perpendicular to the substrate;

the thickness of a portion of the first gate insulating portion of the first transistor that overlaps the first gate electrode in a direction perpendicular to the substrate is smaller than the thickness of a portion of the second gate insulating portion of at least one of the second transistors that overlaps the second gate electrode in a direction perpendicular to the substrate.

Optionally, the first gate and the second gate are disposed in the same layer, and the first active portion and the second active portion are disposed in the same layer.

Optionally, an orthographic projection of the first active portion on the substrate is located within an orthographic projection of the first gate insulating portion on the substrate.

Optionally, the first gate insulating portion has a uniform thickness.

Optionally, the first gate insulating part further extends to an edge of the display region;

the second gate insulating portion of the second transistor also extends to an edge of the display region.

Optionally, the second gate insulating portion of the second transistor has a uniform thickness.

Optionally, a thickness of a portion of the first gate insulating portion of the first transistor overlapping the first gate in a direction perpendicular to the substrate is in a range of 20-100 nm;

the thickness of the part, which is overlapped with the second gate electrode along the direction vertical to the substrate, in the second gate insulating part of the second transistor is in the range of 100-160 nm.

Optionally, the first gate is disposed on a side of the first active portion away from the substrate, and the second gate is disposed on a side of the second active portion away from the substrate;

or, the first gate is disposed on a side of the first active portion close to the substrate, and the second gate is disposed on a side of the second active portion close to the substrate.

In another aspect, a display device is provided, which includes the display panel.

In another aspect, a method for manufacturing a display substrate is provided, where the display substrate includes a display area and a non-display area connected to the display area;

the manufacturing method comprises the following steps:

providing a substrate;

forming at least one first transistor and at least one second transistor on the substrate; wherein the at least one first transistor is disposed in the non-display region and the at least one second transistor is disposed in the display region; the first transistor includes a first gate electrode, a first active portion, and a first gate insulating portion; the first gate insulating part is disposed between the first gate electrode and the first active part and overlaps at least the first gate electrode in a direction perpendicular to the substrate; the second transistor includes a second gate electrode, a second active portion, and a second gate insulating portion; the second gate insulating part is disposed between the second gate electrode and the second active part and overlaps at least the second gate electrode in a direction perpendicular to the substrate; a thickness of a portion of the first gate insulating portion of the first transistor overlapping the first gate electrode in a direction perpendicular to the substrate is smaller than a thickness of a portion of the second gate insulating portion of at least one of the second transistors overlapping the second gate electrode in the direction perpendicular to the substrate;

the forming at least one first transistor and at least one second transistor on the substrate includes:

and forming a first gate insulating part and a second gate insulating part by adopting a one-step patterning process.

An embodiment of the present invention provides a display substrate, including: a substrate; the display substrate further comprises a display area and a non-display area connected with the display area, wherein the non-display area comprises at least one first transistor, and the display area comprises at least one second transistor; the first transistor includes a first gate electrode, a first active portion, and a first gate insulating portion; a first gate insulating part disposed between the first gate electrode and the first active part and overlapping at least the first gate electrode in a direction perpendicular to the substrate; the second transistor includes a second gate electrode, a second active portion, and a second gate insulating portion; a second gate insulating portion disposed between the second gate electrode and the second active portion and overlapping at least the second gate electrode in a direction perpendicular to the substrate; the thickness of a portion of the first gate insulator of the first transistor overlapping the first gate in a direction perpendicular to the substrate is smaller than the thickness of a portion of the second gate insulator of the at least one second transistor overlapping the second gate in a direction perpendicular to the substrate.

In the related art, the thickness of a portion of the second gate insulating portion of the second transistor disposed in the display region of the display substrate, which overlaps the second gate electrode in a direction perpendicular to the substrate, is the same as the thickness of a portion of the gate insulating portion of the reference transistor disposed in the non-display region, which overlaps the gate electrode in the direction perpendicular to the substrate. In contrast, in the present application, the thickness of the portion of the first gate insulator of the first transistor that overlaps the first gate in the direction perpendicular to the substrate is smaller than the thickness of the portion of the second gate insulator of the at least one second transistor that overlaps the second gate in the direction perpendicular to the substrate, that is, the thickness of the portion of the first gate insulator of the first transistor that overlaps the first gate in the direction perpendicular to the substrate is thinner than the thickness of the portion of the gate insulator of the reference transistor in the related art that overlaps the gate in the direction perpendicular to the substrate. Therefore, under the condition that the mobility and the conductance of the first transistor and the reference transistor are the same, the size of the first transistor is smaller than that of the reference transistor, so that the size of a non-display area can be reduced under the condition that the leakage level of the second transistor in the display area is ensured, and a narrow frame is realized.

The foregoing description is only an overview of the technical solutions of the present application, and the present application can be implemented according to the content of the description in order to make the technical means of the present application more clearly understood, and the following detailed description of the present application is given in order to make the above and other objects, features, and advantages of the present application more clearly understandable.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 to 12 are schematic views of a manufacturing process structure of a display substrate according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the embodiments of the present invention, the terms "first", "second", and the like are used for distinguishing identical items or similar items having substantially the same functions and actions, and are used only for clearly describing technical solutions of the embodiments of the present invention, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.

In the embodiments of the present invention, "at least one" means one or more unless specifically limited otherwise.

In the embodiments of the present invention, the terms "on" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

An embodiment of the present invention provides a display substrate, and as shown in fig. 12, the display substrate includes: a substrate 10; the display substrate further includes a display area AA and a non-display area BB connected to the display area AA, the non-display area BB including at least one first transistor 1, the display area AA including at least one second transistor 2.

The first transistor 1 includes a first gate electrode 11, a first active portion 12, and a first gate insulating portion 13; the first gate insulating part 13 is disposed between the first gate electrode 11 and the first active part 12, and overlaps at least the first gate electrode 11 in a direction perpendicular to the substrate 10. The second transistor 2 includes a second gate electrode 21, a second active portion 22, and a second gate insulating portion 23; the second gate insulating part 23 is disposed between the second gate electrode 21 and the second active part 22, and overlaps at least the second gate electrode 21 in a direction perpendicular to the substrate 10.

Referring to fig. 12, a thickness d1 of a portion of the first gate insulating portion 13 of the first transistor 1 overlapping the first gate 11 in a direction perpendicular to the substrate 10 is smaller than a thickness of a portion of the second gate insulating portion 23 of the at least one second transistor 2 overlapping the second gate 21 in the direction perpendicular to the substrate 10.

The display region is a region for realizing display, and the non-display region is generally used for setting a driving circuit, for example: a GOA driver circuit, etc.

The first transistor can be applied to a GOA driver circuit or other driver circuits, which is not limited herein.

Transistors can be classified into two types according to the positional relationship of electrodes. One is a thin film transistor of a bottom gate type in which a gate electrode is positioned below a source electrode and a drain electrode; one is a gate electrode on top of a source electrode and a drain electrode, and this is called a top gate type thin film transistor. The first transistor and the second transistor may be both top-gate transistors, or may also be both bottom-gate transistors; alternatively, one of the first transistor and the second transistor is a top gate transistor, and the other is a bottom gate transistor. Fig. 12 illustrates an example in which the first transistor and the second transistor are both top-gate transistors.

The types of the first transistor and the second transistor are not limited, and for example, the first transistor and the second transistor may be both low-temperature polysilicon transistors, or metal Oxide transistors such as IGZO (Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), and the like.

The first transistor and the second transistor may include a gate, a source, and a drain, respectively, and one of the source and the drain may be referred to as a first pole and the other may be referred to as a second pole.

The first gate insulating part overlapping at least the first gate electrode in a direction perpendicular to the substrate includes: the first gate insulating part only overlaps the first gate electrode along a direction perpendicular to the substrate, and at the moment, the orthographic projection of the first gate insulating part on the substrate is superposed with the orthographic projection of the first gate electrode on the substrate; alternatively, the first gate insulating part may overlap other film layers in a direction perpendicular to the substrate in addition to the first gate electrode, and for example, the first gate insulating part may overlap a portion of the first active part in a direction perpendicular to the substrate.

The second gate insulating part overlapping at least the second gate electrode in a direction perpendicular to the substrate includes: the second gate insulating part only overlaps the second gate electrode along a direction perpendicular to the substrate, and at the moment, the orthographic projection of the second gate insulating part on the substrate is superposed with the orthographic projection of the second gate electrode on the substrate; alternatively, the second gate insulating part may overlap other film layers in a direction perpendicular to the substrate in addition to the second gate electrode, and for example, the second gate insulating part may overlap a portion of the second active part in a direction perpendicular to the substrate.

The materials of the first gate insulating portion and the second gate insulating portion are not particularly limited. For example, the material of each of the first and second gate insulating portions may include silicon oxide or silicon oxynitride.

The material of the first active portion and the second active portion is not particularly limited. For example, the material of the first active portion and the second active portion may include metal oxide or polysilicon. The metal oxide may include IGZO or ITZO. The polysilicon may include LTPS (Low-temperature polysilicon).

The material of the above substrate is not particularly limited. By way of example, the substrate may comprise a rigid substrate, such as: glass; alternatively, a flexible substrate may be included, such as: PI (polyimide) film.

In the related art, the thickness of a portion of the second gate insulating portion of the second transistor disposed in the display region of the display substrate, which overlaps the second gate electrode in a direction perpendicular to the substrate, is the same as the thickness of a portion of the gate insulating portion of the transistor disposed in the non-display region, which overlaps the gate electrode in the direction perpendicular to the substrate. The non-display area is generally composed of a large width to length ratioLarger TFT (Thin Film Transistor) composition to obtain larger conductance, but this results inThe display substrate is difficult to realize narrow frames, and the user experience is poor.

The following explains a principle of the present application that enables a display substrate to realize a narrow bezel.

For convenience of explanation, a transistor in the related art in which a portion of the gate insulating portion overlapping with the gate electrode in a direction perpendicular to the substrate is located in the non-display region is referred to as a reference transistor.

In the display substrate provided by the present application, a thickness of a portion of the first gate insulator of the first transistor which overlaps the first gate electrode in a direction perpendicular to the substrate is smaller than a thickness of a portion of the second gate insulator of the at least one second transistor which overlaps the second gate electrode in the direction perpendicular to the substrate, that is, a thickness of a portion of the first gate insulator of the first transistor which overlaps the first gate electrode in the direction perpendicular to the substrate is thinner than a thickness of a portion of the gate insulator of the reference transistor in the related art which overlaps the gate electrode in the direction perpendicular to the substrate.

Mobility equation of transistorWhere μ represents the mobility of the transistor, L represents the channel length of the active portion of the transistor, W represents the channel width of the active portion of the transistor, g_mRepresenting the transconductance of the transistor, C_iRepresenting the area capacitance of the gate insulating layer in the transistor. For the first transistor and the reference transistor, when the mobility and transconductance of the first transistor and the reference transistor are the same, the capacitance C between the first gate and the first source/drain of the first transistor₁Larger than the capacitance C between the gate and the source/drain of the reference transistor₂And V of both_dsSame, of the first transistorSmaller than the reference transistorIf the mobility and transconductance of the first transistor and the reference transistor are the same, the first transistorOf reference transistorsOf large, opposite first transistorsOf reference transistorsSmall; i.e. in ensuring μ, g of the first transistor and the reference transistor_mUnder the same condition, the size of the first transistor is smaller than that of the reference transistor, so that the size of the non-display area can be reduced under the condition that the leakage level of the second transistor in the display area is guaranteed, and the narrow frame is further realized.

Optionally, the first gate and the second gate are disposed in the same layer, and the first active portion and the second active portion are disposed in the same layer, so that the manufacturing process can be simplified.

The same layer setting refers to manufacturing by adopting a one-time composition process. The one-step patterning process refers to a process of forming a desired layer structure through one exposure. The primary patterning process includes masking, exposing, developing, etching, and stripping processes.

Alternatively, referring to fig. 12, an orthogonal projection E1 of the first active portion 12 on the substrate 10 is located inside an orthogonal projection E2 of the first gate insulating portion 13 on the substrate 10. Therefore, the first gate insulating part can better protect the first active part and prevent the first active part from being influenced.

Optionally, the first gate insulating part has a uniform thickness for ease of fabrication. Fig. 12 illustrates an example in which the thickness of the first gate insulating portion d1 is uniform.

Alternatively, as shown in fig. 12, the first gate insulating part 13 also extends to the edge of the display area AA; the second gate insulating part 23 of the second transistor 2 also extends to the edge of the display area AA. Therefore, the first gate insulating part is located in the whole display area and can protect the first active part, the second gate insulating part is located in the whole non-display area and can protect the second active part, and meanwhile, the structure is simple and convenient to achieve.

Optionally, the second gate insulating portion of the second transistor has a uniform thickness. This makes it possible for the second gate insulating portion to better protect the second active portion, preventing the second active portion from being affected.

Alternatively, referring to fig. 12, the thickness d1 of the portion of the first gate insulating part 13 of the first transistor 1 that overlaps the first gate electrode 11 in the direction perpendicular to the substrate 10 is in the range of 20-100 nm. By way of example, the thickness of d1 may include: 20nm, 40nm, 60nm, 80nm or 100 nm.

The thickness d2 of the portion of the second gate insulating portion 23 of the second transistor 2 that overlaps the second gate electrode 21 in the direction perpendicular to the substrate 10 ranges from 100 to 160 nm. For example, the d2 may include: 100nm, 120nm, 140nm or 160 nm.

Alternatively, referring to fig. 12, the first gate 11 is disposed on a side of the first active portion 12 away from the substrate 10, and the second gate 21 is disposed on a side of the second active portion 22 away from the substrate 10. This makes it possible to form a top gate type transistor.

Or the first grid is arranged on one side of the first active part close to the substrate, and the second grid is arranged on one side of the second active part close to the substrate. This can form a bottom gate type transistor.

The embodiment of the invention also provides a display device which comprises the display substrate.

The display device may be a flexible display device (also referred to as a flexible screen) or a rigid display device (i.e., a display screen that cannot be bent), which is not limited herein. The Display device may be an OLED (Organic Light-Emitting Diode) Display device, an LCD (Liquid Crystal Display), or any product or component with a Display function, such as a large screen television, a digital camera, a mobile phone, a tablet computer, a notebook computer, and a vehicle-mounted instrument, which includes an OLED or an LCD. The display device has a narrow frame and has the advantages of good display effect, long service life, high stability, high contrast ratio and the like.

The embodiment of the invention also provides a manufacturing method of the display substrate.

The display substrate includes a display region and a non-display region connected to the display region.

The manufacturing method comprises the following steps:

and S1, providing a substrate.

S2, forming at least one first transistor and at least one second transistor on the substrate.

Wherein, at least one first transistor is arranged in the non-display area, and at least one second transistor is arranged in the display area; the first transistor includes a first gate electrode, a first active portion, and a first gate insulating portion; a first gate insulating part disposed between the first gate electrode and the first active part and overlapping at least the first gate electrode in a direction perpendicular to the substrate; the second transistor includes a second gate electrode, a second active portion, and a second gate insulating portion; a second gate insulating portion disposed between the second gate electrode and the second active portion and overlapping at least the second gate electrode in a direction perpendicular to the substrate; the thickness of a portion of the first gate insulator of the first transistor overlapping the first gate in a direction perpendicular to the substrate is smaller than the thickness of a portion of the second gate insulator of the at least one second transistor overlapping the second gate in a direction perpendicular to the substrate.

S2, forming at least one first transistor and at least one second transistor on the substrate includes:

and forming a first gate insulating part and a second gate insulating part by adopting a one-step patterning process.

Specifically, the first gate insulating part and the second gate insulating part with different thicknesses can be formed by adopting a half-tone mask, so that the first gate insulating part and the second gate insulating part are formed by a one-time composition process, the process is greatly simplified, and the production cost is reduced.

In the display substrate formed by performing steps S1 and S2, in the related art, the thickness of a portion of the second gate insulating portion of the second transistor disposed in the display region of the display substrate which overlaps the second gate electrode in the direction perpendicular to the substrate is the same as the thickness of a portion of the gate insulating portion of the reference transistor disposed in the non-display region which overlaps the gate electrode in the direction perpendicular to the substrate. In contrast, in the present application, the thickness of the portion of the first gate insulator of the first transistor that overlaps the first gate in the direction perpendicular to the substrate is smaller than the thickness of the portion of the second gate insulator of the at least one second transistor that overlaps the second gate in the direction perpendicular to the substrate, that is, the thickness of the portion of the first gate insulator of the first transistor that overlaps the first gate in the direction perpendicular to the substrate is thinner than the thickness of the portion of the gate insulator of the reference transistor in the related art that overlaps the gate in the direction perpendicular to the substrate. Therefore, under the condition that the mobility and the conductance of the first transistor and the reference transistor are the same, the size of the first transistor is smaller than that of the reference transistor, so that the size of a non-display area can be reduced under the condition that the leakage level of the second transistor in the display area is ensured, and a narrow frame is realized.

For the structural description of the relevant film layers in the display substrate, reference may be made to the description of the embodiments of the display substrate, which is not repeated herein.

Next, a method for manufacturing a display substrate will be specifically described by taking the structure shown in fig. 12 as an example.

The manufacturing method comprises the following steps:

s01, referring to fig. 1, a thin film is deposited on the substrate 10 and patterned to form the buffer layer 20.

Specifically, the material of the substrate may be glass or polyimide.

The patterning may include exposure, development, etching, and the like.

The buffer layer may be made of silicon oxide or silicon nitride.

S02, referring to fig. 2, a thin film is deposited on the buffer layer 20 and patterned to form the first active portion 12 and the second active portion 22.

Specifically, the method for depositing the thin film on the buffer layer may be CVD (Chemical Vapor Deposition).

The first active portion and the second active portion may be both made of LTPS, and the LTPS may be formed after a-silicon laser annealing.

S03, referring to fig. 3, a gate insulating layer 30 is formed after depositing a thin film on the first active portion 12 and the second active portion 22 and patterning the thin film.

Specifically, the method of depositing the thin film on the first active portion and the second active portion may be CVD.

S04, referring to fig. 4, the gate insulating layer 30 is subjected to half-tone mask lithography, and patterned to form a first gate insulating portion 13 having a thickness d1 and a second gate insulating portion 23 having a thickness d 2. The first gate insulating part 13 is positioned in the non-display area BB and the second gate insulating part 23 is positioned in the display area AA.

Specifically, the thickness d1 of the first gate insulating portion may be 70 nm.

The thickness d2 of the second gate insulating portion may be 150 nm.

S05, referring to fig. 5, thin films are deposited on the first gate insulating part 13 and the second gate insulating part 23, and the first gate electrode 11, the second gate electrode 21, and the first electrode 31 are formed after patterning.

Specifically, the materials of the first gate electrode, the second gate electrode, and the first electrode may be all molybdenum.

S06, referring to fig. 6, a second insulating layer 40 is formed after depositing a thin film on the first gate electrode 11, the second gate electrode 21, and the first electrode 31 and patterning the thin film.

Specifically, the material of the thin film deposited on the first gate electrode, the second gate electrode, and the first electrode may be silicon dioxide.

The method for depositing the thin film on the first gate electrode, the second gate electrode, and the first electrode may be CVD.

S07, referring to fig. 7, a film is deposited on the second insulating layer 40, and patterned to form the second electrode 32, and a storage capacitor is formed between the second electrode 32 and the first electrode 31.

Specifically, the material of the thin film deposited on the second insulating layer may be molybdenum.

S08, referring to fig. 8, a film is deposited on the second electrode 32 and patterned to form the interlayer dielectric layer 50.

Specifically, the material of the thin film deposited on the second electrode may be silicon dioxide.

The method for depositing the film on the second electrode may be CVD.

S09, referring to fig. 9, forming via holes after etching the interlayer dielectric layer 50, the second insulating layer 40, and the first insulating layer 30, depositing a thin film in the via holes, and forming the source 41 and the drain 42 after patterning.

Specifically, the method for depositing the thin film in the via hole may be sputtering.

The material of the thin film deposited in the via hole may be aluminum.

S10, referring to fig. 10, a thin film is deposited on the source electrode 41 and the drain electrode 42, and patterned to form the planarization layer 60.

Specifically, the method for depositing the thin film on the source electrode and the drain electrode may be spin coating or doctor blading.

S11, referring to fig. 11, a thin film is deposited on the planarization layer 60 and patterned to form the anode 70.

Specifically, the method for depositing the thin film on the flat layer may be sputtering.

The anode is made of ITO (Indium Tin Oxides) or silver.

S12, referring to fig. 12, a thin film is deposited on the anode 70 and patterned to form the encapsulation layer 80.

Specifically, the method for depositing the thin film on the anode can be spin coating or doctor blading.

The manufacturing method of the display substrate is simple and easy to implement, and the transistor performance of the display substrate formed by the method is good.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.