阅读说明：本技术 显示面板及显示装置 (Display panel and display device ) 是由 许玉萍 李杰良 于 2021-09-07 设计创作，主要内容包括：本申请提供了一种显示面板及显示装置,在第一边缘和第二边缘之间至少间隔一条信号线,在第一晶体管的第一极和数据写入晶体管的第一极之间产生横向电场之后,该信号线会对电场线进行阻隔,以减弱局部区域的电场,从而减小寄生电容,提高第一晶体管的第一极的电压稳定性,以增强驱动晶体管的栅极电压的稳定性。并且,为了避免第一边缘和第二边缘之间的信号线与第一晶体管的第一极和/或数据写入晶体管的第一极在同一层的情况下,之间再形成横向电场的情况发生,使第一边缘和第二边缘之间的信号线与第一金属层异层设置,以避免位于同一层对第一晶体管的第一极和/或数据写入晶体管的第一极造成不必要的干扰,提高驱动晶体管的栅极电压的稳定性。(The application provides a display panel and display device, at least one signal line of interval between first edge and second edge, after producing horizontal electric field between the first pole of first transistor and the first pole of data write-in transistor, this signal line can carry out the separation to the electric field line to weaken local area's electric field, thereby reduce parasitic capacitance, improve the voltage stability of the first pole of first transistor, with the stability of reinforcing drive transistor's grid voltage. In addition, in order to avoid the situation that a transverse electric field is formed between the signal line between the first edge and the second edge and the first pole of the first transistor and/or the first pole of the data writing transistor under the condition that the signal line and the first pole of the first transistor and/or the first pole of the data writing transistor are/is in the same layer, the signal line between the first edge and the second edge and the first metal layer are arranged in different layers, so that unnecessary interference on the first pole of the first transistor and/or the first pole of the data writing transistor caused by the signal line and the first metal layer in the same layer is avoided, and the stability of the grid voltage of the driving transistor is improved.)

1. A display panel, comprising:

the pixel circuit comprises a driving transistor, a data writing transistor and a first transistor, wherein the driving transistor is used for providing driving current for the light-emitting element, and the data writing transistor is used for providing a data signal for the driving transistor;

a signal line group including at least one signal line that supplies a control signal or an input signal to a transistor of the pixel circuit; wherein the content of the first and second substances,

the data writing transistor is connected between the first pole of the driving transistor and the data signal line, the first pole of the first transistor is connected to the grid electrode of the driving transistor, and the first pole of the first transistor and the first pole of the data writing transistor are located on the first metal layer; wherein the content of the first and second substances,

the side, facing the first pole of the data writing transistor, of the first pole of the first transistor is a first edge, and the side, facing the first pole of the first transistor, of the first pole of the data writing transistor is a second edge;

when orthographic projection is carried out on the plane parallel to the surface of the display panel, at least partial area of at least one signal line in the signal line group is located between the first edge and the second edge, and the at least partial area of the at least one signal line is arranged in a different layer with the first metal layer.

2. The display panel according to claim 1,

the grid electrode of the driving transistor is positioned on the second metal layer and is connected with the first pole of the first transistor through a through hole;

the data signal line is located on the third metal layer and connected to the first pole of the data writing transistor through a via hole, or the first pole of the data writing transistor is connected to the first pole of the driving transistor.

3. The display panel according to claim 1,

the pixel circuit includes a silicon transistor and an oxide semiconductor transistor;

the active layer of the silicon transistor comprises silicon, and the active layer of the oxide semiconductor transistor comprises an oxide semiconductor;

in a direction perpendicular to the surface of the display panel, the oxide semiconductor transistor comprises a top grid and a bottom grid which are positioned at two sides of an active layer, and the top grid is positioned at one side of the bottom grid facing the first metal layer;

the first transistor is one of oxide semiconductor transistors.

4. The display panel according to claim 3,

when orthographic projection is carried out on a plane parallel to the surface of the display panel, at least partial area of a first signal line in the signal line group is positioned between the first edge and the second edge, and at least partial area of a second signal line in the signal line group is also positioned between the first edge and the second edge; wherein the content of the first and second substances,

the first signal line is connected with the top gate of the first transistor and provides a control signal for the top gate of the first transistor;

the second signal line is connected with the bottom grid electrode of the first transistor and provides a control signal for the bottom grid electrode of the first transistor;

the first signal line and the second signal line extend in a first direction.

5. The display panel according to claim 4,

when orthographic projection is carried out on the plane parallel to the surface of the display panel, the first edge and the second edge are positioned on two sides formed after the first signal line extends along the first direction, and the first edge and the second edge are positioned on two sides formed after the second signal line extends along the first direction.

6. The display panel according to claim 4,

the first signal line includes a first convex portion extending in a second direction, the second signal line includes a second convex portion extending in the second direction, and the first direction and the second direction intersect;

the first edge and the second edge are located on two sides formed after the first protruding portion extends along the second direction, and the first edge and the second edge are located on two sides formed after the second protruding portion extends along the second direction.

7. The display panel according to claim 4,

when the display panel is orthographic projected to a plane parallel to the surface of the display panel, the distance between the first edge and the part of the first signal line spaced between the first edge and the second edge is D11, and the distance between the first edge and the part of the second signal line spaced between the first edge and the second edge is D12;

a spacing between a portion of the first signal line spaced between the first edge and the second edge is D21, and a spacing between a portion of the second signal line spaced between the first edge and the second edge is D22; wherein the content of the first and second substances,

d11 > D21, and/or D12 > D22.

8. The display panel according to claim 4,

a width of a portion of the first signal line spaced between the first edge and the second edge is W1, and a width of the second signal line spaced between the first edge and the second edge is W2, when orthographic projected to a plane parallel to the surface of the display panel;

the width of the overlapping portion between the first signal line and the second signal line is W0; wherein 0 ≦ W0 < Wx, which is the smaller of W1 and W2.

9. The display panel according to claim 4,

the width of the first signal line is greater than the width of the second signal line.

10. The display panel according to claim 4,

the signal line group further comprises a third signal line, when the third signal line is orthographically projected to a plane parallel to the surface of the display panel, the third signal line is positioned on one side of the first signal line and the second signal line, which is far away from the first edge, and at least part of area of the third signal line is also positioned between the first edge and the second edge.

11. The display panel according to claim 10,

the third signal line is located on the same layer as the first signal line, and the third signal line also extends in the first direction;

when the projection is performed to the plane parallel to the surface of the display panel, the distance between the third signal line and the first signal line is larger than the distance between the second signal line and the third signal line.

12. The display panel according to claim 4,

the signal line group comprises a sixth signal line, the sixth signal line is connected to the grid electrode of the data writing transistor and used for providing a control signal for the data writing transistor, and the sixth signal line is positioned between the first signal line and/or the second signal line and the grid electrode of the driving transistor;

the active layer of the first transistor includes a first region and a second region;

the first region and the sixth signal line are overlapped with each other to form a first capacitor;

the second region overlaps with the first signal line and the second signal line to form a channel region of the first transistor.

13. The display panel according to claim 12,

the first region extends along a third direction, the second region extends along the first direction, and the first direction and the third direction are perpendicular to each other;

there is no overlap between the first capacitor and the channel region of the first transistor.

14. The display panel according to claim 13,

the first region has a width in the first direction of H1 and a length in the third direction of K1, wherein H1 > K1;

the second region has a length along the first direction of K2 and a width along the third direction of H2, wherein K2 > H2.

15. The display panel according to claim 1,

when orthographic projection is carried out on the plane parallel to the surface of the display panel, at least partial area of a fourth signal line in the signal line group is positioned between the first edge and the second edge;

the fourth signal line is located on the fourth metal layer, and the fourth metal layer and the first metal layer are arranged in a different layer.

16. The display panel according to claim 15,

when the display panel is orthographically projected to a plane parallel to the surface of the display panel, the distance between the fourth signal line and the first edge is larger than the distance between the fourth signal line and the second edge.

17. The display panel according to claim 15,

when orthographic projection is carried out on the plane parallel to the surface of the display panel, at least partial area of a fifth signal line in the signal line group is also positioned between the first edge and the second edge;

the fifth signal line is located a fifth metal layer, and the fifth metal layer is arranged in a different layer with the first metal layer.

18. The display panel according to claim 17,

the fourth metal layer is located at one side of the first metal layer and faces the fifth metal layer

When the display panel is orthographically projected to a plane parallel to the surface of the display panel, the fourth signal line is positioned on one side of the fifth signal line towards the second edge.

19. A display device characterized by comprising the display panel according to any one of claims 1 to 18.

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

In a display panel, a pixel circuit supplies a driving current required for displaying to a light emitting element of the display panel and controls whether the light emitting element enters a light emitting stage, so that the pixel circuit becomes an indispensable element in most self-luminous display panels.

However, in the pixel circuit, a parasitic capacitance exists between the wiring connected to the gate of the driving transistor and the wiring located in the same layer, and the existence of the parasitic capacitance may cause a current flowing through the light emitting element to change, which causes a difference between actual display luminance and ideal luminance, thereby affecting the display effect of the display panel.

Disclosure of Invention

In view of the above, to solve the above problems, the present invention provides a display panel and a display device, and the technical solution is as follows:

in one aspect, the present application provides a display panel, comprising:

the pixel circuit comprises a driving transistor, a data writing transistor and a first transistor, wherein the driving transistor is used for providing driving current for the light-emitting element, and the data writing transistor is used for providing a data signal for the driving transistor;

a signal line group including at least one signal line that supplies a control signal or an input signal to a transistor of the pixel circuit; wherein the content of the first and second substances,

the data writing transistor is connected between the first pole of the driving transistor and the data signal line, the first pole of the first transistor is connected to the grid electrode of the driving transistor, and the first pole of the first transistor and the first pole of the data writing transistor are located on the first metal layer; wherein the content of the first and second substances,

the side, facing the first pole of the data writing transistor, of the first pole of the first transistor is a first edge, and the side, facing the first pole of the first transistor, of the first pole of the data writing transistor is a second edge;

when orthographic projection is carried out on the plane parallel to the surface of the display panel, at least partial area of at least one signal line in the signal line group is located between the first edge and the second edge, and the at least partial area of the at least one signal line is arranged in a different layer with the first metal layer.

In another aspect, the present application provides a display device including the display panel described above.

Compared with the prior art, the invention has the following beneficial effects:

the display panel provided by the invention has at least one signal line arranged between the first edge and the second edge, namely when the display panel is orthographically projected to a plane parallel to the surface of the display panel, at least part of the area of at least one signal line in the signal line group is positioned between the first edge and the second edge; then, after a lateral electric field is generated between the first pole of the first transistor and the first pole of the data writing transistor, the signal lines between the first edge and the second edge block the electric field lines to weaken the electric field in a local area, thereby reducing the parasitic capacitance, improving the voltage stability of the first pole of the first transistor, and thus enhancing the stability of the gate voltage of the driving transistor.

In addition, in order to avoid the situation that a transverse electric field is formed between the signal line between the first edge and the second edge and the first pole of the first transistor and/or the first pole of the data writing transistor under the condition that the signal line and the first pole of the first transistor and/or the first pole of the data writing transistor are/is in the same layer, the signal line between the first edge and the second edge is arranged in a different layer with the first metal layer, so that unnecessary interference on the first pole of the first transistor and/or the first pole of the data writing transistor caused by the signal line and the first metal layer which are positioned in the same layer is avoided, and the stability of the grid voltage of the driving transistor is further improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic circuit diagram of a pixel circuit in a display panel according to an embodiment of the present invention;

fig. 2 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present invention;

fig. 3 is a schematic circuit layout diagram of a pixel circuit in a display panel according to an embodiment of the present invention;

fig. 4 is a schematic circuit layout diagram of a pixel circuit in a display panel according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a circuit layout of a pixel circuit in a display panel according to an embodiment of the present invention;

fig. 6 is a schematic circuit layout diagram of a pixel circuit in a display panel according to an embodiment of the present invention;

fig. 7 is a schematic circuit layout diagram of a pixel circuit in a display panel according to an embodiment of the present invention;

fig. 8 is a schematic diagram of a further circuit layout of a pixel circuit in a display panel according to an embodiment of the present invention;

fig. 9 is a schematic diagram of a further circuit layout of a pixel circuit in a display panel according to an embodiment of the present invention;

fig. 10 is a schematic circuit diagram of a pixel circuit in a display panel according to an embodiment of the invention;

fig. 11 is a schematic circuit layout diagram of a pixel circuit in a display panel according to an embodiment of the present invention;

fig. 12 is a schematic circuit layout diagram of a pixel circuit in a display panel according to an embodiment of the present invention;

fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

Referring to fig. 1, fig. 1 is a schematic circuit structure diagram of a pixel circuit in a display panel according to an embodiment of the present invention, where the display panel includes: a pixel circuit 10 and a light emitting element Q, the pixel circuit 10 including a driving transistor T0, a data writing transistor T1, and a first transistor T2, the driving transistor T0 for supplying a driving current to the light emitting element Q, the data writing transistor T1 for supplying a data signal Vdata to the driving transistor T0.

The data writing transistor T1 is connected between the first electrode of the driving transistor T0 and the data signal line L1, and the first electrode of the first transistor T2 is connected to the gate of the driving transistor T0 to form a first node N1.

As shown in fig. 1, a first pole of the data writing transistor T1 is for receiving a data signal Vdata, a second pole of the data writing transistor T1 is connected to the first pole of the driving transistor T0 to form a second node N2, and a gate of the data writing transistor T1 is for receiving a control signal S1. In some embodiments, it may also be assumed that the first pole of the data writing transistor T1 may be connected to the first pole of the driving transistor T0 to form the second node N2, and the second pole of the data writing transistor T1 may be used for receiving the data signal Vdata. The control signal S1 received by the data writing transistor T1 is a pulse signal, and the active pulse of the control signal S1 controls the data writing transistor T1 to be in a conducting state, so as to provide the data signal Vdata to the driving transistor T0; the inactive pulse of the control signal S1 controls the data write transistor T1 to be in an off state. Accordingly, the data writing transistor T1 selectively supplies the data signal Vdata to the driving transistor T0 under the control of the control signal S1.

As shown in fig. 1, the second pole of the driving transistor T0 is coupled to the light emitting element Q to provide a driving current to the light emitting element Q after the driving transistor T0 and the light emission control transistors T3 and T4 are turned on.

As shown in fig. 1, in the embodiment of the present application, the first transistor T2 is exemplified by a compensation transistor for compensating the threshold voltage of the driving transistor T0; the first pole of the first transistor T2 is connected to the gate of the driving transistor T0, the second pole of the first transistor T2 is connected to the second pole of the driving transistor T0 to form a third node N3, and the gate of the first transistor T2 is used to receive the control signal S2. The control signal S2 received by the first transistor T2 is a pulse signal, and the active pulse of the control signal S2 controls the first transistor T2 to be in a conducting state to compensate the threshold voltage of the driving transistor T0; the inactive pulse of the control signal S2 controls the first transistor T2 to be in an off state. Accordingly, the first transistor T2 selectively compensates for the threshold voltage of the driving transistor T0 under the control of the control signal S2.

Optionally, as shown in fig. 1, the pixel circuit 10 further includes a second transistor T3 and a third transistor T4; the second transistor T3 is connected between the first power signal terminal PVDD and the first electrode of the driving transistor T0, and the third transistor T4 is connected between the second electrode of the driving transistor T0 and the light emitting element Q, for controlling whether the pixel circuit 10 is in the light emitting stage or the non-light emitting stage.

The gates of the second transistor T3 and the third transistor T4 receive the control signal EM at the same time, and the third transistor T4 is in an on state or an off state under the control of the control signal EM; the control signal EM received by the gate of the third transistor T4 is a pulse signal, and in the light emitting stage, the control signal EM outputs an active pulse to control the third transistor T4 to be in a conducting state, so that the driving current provided by the driving transistor T0 flows into the light emitting element Q to cause it to emit light; in the non-light emitting period, the control signal EM outputs an inactive pulse to control the third transistor T4 to be in an off state, and the light emitting element Q does not emit light.

Optionally, as shown in fig. 1, the pixel circuit 10 further includes a fourth transistor T5; a first pole of the fourth transistor T5 receives the reset signal DVINI, a second pole of the fourth transistor T5 is connected to the second pole of the driving transistor T0, and a gate of the fourth transistor T5 receives the control signal S3. The control signal S3 received by the fourth transistor T5 is a pulse signal, and the active pulse of the control signal S3 controls the fourth transistor T5 to be in a conducting state, so as to reset the gate of the driving transistor T0; the inactive pulse of the control signal S3 controls the fourth transistor T5 to be in an off state. In the reset phase of the pixel circuit 10, the first transistor T2 is turned on under the control of the control signal S2, and the fourth transistor T5 is turned on under the control of the control signal S3, so that the reset signal DVINI is written into the gate of the driving transistor T0 through the fourth transistor T5 and the first transistor T2 to reset the gate of the driving transistor T0.

Optionally, as shown in fig. 1, the pixel circuit 10 further includes a fifth transistor T6; a first pole of the fifth transistor T6 is for receiving the initialization signal VAR, a second pole of the fifth transistor T6 is connected to the anode of the light emitting element Q, and a gate of the fifth transistor T6 is for receiving the scan signal S4. The control signal S4 received by the fifth transistor T6 is a pulse signal, and the active pulse of the control signal S4 controls the fifth transistor T6 to be in an on state, so that the initialization signal VAR is written into the anode of the light emitting element Q through the fifth transistor T6 to initialize the light emitting element Q; the inactive pulse of the control signal S4 controls the fifth transistor T6 to be in an off state.

The cathode of the light emitting element Q is connected to the second power signal terminal PVEE.

Optionally, as shown in fig. 1, the pixel circuit further includes a storage capacitor C0, a first plate of the storage capacitor C0 is connected to the first power signal terminal PVDD, and a second plate of the storage capacitor C0 is connected to the first node N1.

Further, the display panel further includes a signal line group including at least one signal line for supplying a control signal or an input signal to the transistors of the pixel circuit 10, and illustratively, as shown in fig. 1, the signal lines that may be included in the signal line group include a signal line L1 for supplying a data signal Vdata, a signal line L2 for supplying a control signal S1, a signal line L3 for supplying a control signal S2, a signal line L4 for supplying a control signal S3, a signal line L5 for supplying a control signal S4, a signal line L6 for supplying a control signal EM, a signal line L7 for supplying a reset signal DVINI, a signal line L8 for supplying an initialization signal VAR, and the like.

Further, referring to fig. 2, fig. 2 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present invention.

As shown in fig. 2, the first pole of the first transistor T2 is located in the first metal layer M1, and the first pole of the data writing transistor T1 is located in the first metal layer M1, so that based on the current display panel structure, the first pole of the first transistor T2 and the first pole of the data writing transistor T1 are located in the same layer, i.e., on the first metal layer M1. Then, if the first pole of the first transistor T2 and the first pole of the data writing transistor T1 are close to each other, or there is no other structure between the two, a lateral electric field is generated between the first pole of the first transistor T2 and the first pole of the data writing transistor T1, and a parasitic capacitance is generated, so that the stability of the gate voltage of the driving transistor T0 is affected, and the display performance of the display panel is ultimately affected.

Specifically, in the data writing stage, the signal on the data signal line L1 is written into the gate of the driving transistor T0, and the gate voltage of the driving transistor T0 is an important factor for determining the driving current, so the requirement on the stability of the gate voltage of the driving transistor T0 is high; since the first electrode of the first transistor T2 is connected to the gate of the driving transistor T0, the voltage stability requirement indirectly for the first electrode of the first transistor T2 also needs to be high.

Then, when a lateral electric field is generated between the first electrode of the first transistor T2 and the first electrode of the data writing transistor T0 and a parasitic capacitance is generated, the voltage of the first electrode of the first transistor T2 is susceptible to change, and the gate voltage of the driving transistor T0 is changed accordingly, so that the stability of the gate voltage of the driving transistor T0 is affected, and the display performance of the display panel is affected finally.

Referring to fig. 3, fig. 3 is a circuit layout schematic diagram of a pixel circuit in a display panel according to an embodiment of the present invention.

In order to improve the stability of the gate voltage of the driving transistor T0, as shown in fig. 3, a side of the first pole of the first transistor T2 facing the first pole of the data writing transistor T1 is defined as a first edge a1, and a side of the first pole of the data writing transistor T1 facing the first pole of the first transistor T2 is defined as a second edge a 2.

When at least a partial region of at least one signal line is spaced between the first edge a1 and the second edge a2, that is, when the signal line is orthographically projected to a plane parallel to the surface of the display panel, the at least partial region of at least one signal line in the signal line group is located between the first edge a1 and the second edge a2, and the at least partial region of the at least one signal line is disposed in a different layer from the first metal layer, after a lateral electric field is generated between the first pole of the first transistor T2 and the first pole of the data write transistor T1, the signal line located between the first edge a1 and the second edge a2 blocks the electric field line to weaken the electric field of the partial region, thereby reducing parasitic capacitance, improving voltage stability of the first pole of the first transistor T2, and thus enhancing stability of the gate voltage of the driving transistor T0.

In order to avoid the situation that a lateral electric field is formed between the signal line between the first edge a1 and the second edge a2 and the first pole of the first transistor T2 and/or the first pole of the data writing transistor T1 in the same layer, the signal line between the first edge a1 and the second edge a2 is disposed in a different layer from the first metal layer M1, so as to avoid unnecessary interference on the first pole of the first transistor T2 and/or the first pole of the data writing transistor T1 in the same layer, and further improve the stability of the gate voltage of the driving transistor T0.

In the present embodiment, in order to better describe the relationship between the first edge a1, the second edge a2, and the electric field lines spaced therebetween, in the present application, the relationship between the structures on the plane is described by projecting the structures onto a plane parallel to the surface of the display panel, and the orthogonal projection may also be regarded as a perpendicular projection, that is, when the structures that are not originally located on the same film layer are perpendicularly projected onto the same plane, the relationship between the structures is described.

Optionally, in this embodiment, the gate of the driving transistor T0 is located in the second metal layer M1, the first pole of the first transistor T2 is located in the first metal layer M2, and the gate of the driving transistor T0 is connected to the first pole of the first transistor T2 through a via.

If the data signal line L1 is located in the third metal layer M3, then in order to connect the data signal line L1 to the data writing transistor T1, it is necessary to punch a hole to connect the data signal line L1 directly to the active layer of the data writing transistor T1, that is, it is necessary to punch a hole from the third metal layer M3 to the active layer of the data writing transistor T1, and if the active layer of the data writing transistor T1 is located at a relatively large distance from the third metal layer M3, for example, as shown in fig. 2, the active layer of the data writing transistor T1 is located closer to the substrate, and if the hole is punched from the third metal layer M3 to the active layer of the data writing transistor T1, the depth of the hole may be deep, which may affect the stability of connection between the data signal line L1 and the active layer. Therefore, as shown in fig. 2, in the present application, the third metal layer M3 is punched to the first metal layer M2, and then the first metal layer is punched to the active layer of the data writing transistor T1, that is, the first pole of the data writing transistor T1 is located on the first metal layer M1, and the data signal line L1 is connected to the first pole of the data writing transistor T1 through a via hole between the third metal layer M3 and the first metal layer M1. It can be seen that, based on the current display panel structure, the first electrode of the first transistor T2 and the first electrode of the data writing transistor T1 are located on the same layer, i.e., on the first metal layer M1.

Optionally, in another embodiment of the present invention, the pixel circuit 10 includes a silicon transistor and an oxide semiconductor transistor, the active layer of the silicon transistor includes silicon, the active layer of the oxide semiconductor transistor includes an oxide semiconductor, the oxide semiconductor transistor includes a top gate and a bottom gate on two sides of the active layer in a direction perpendicular to the surface of the display panel, the top gate is located on a side of the bottom gate facing the first metal layer M1, and the first transistor T2 is one of the oxide semiconductor transistors.

Alternatively, in the present application, the data writing transistor T2 may be one of the silicon transistors, the gate of the data writing transistor is located in the second metal layer M2, and the active layer includes low temperature polysilicon.

As shown in fig. 2, the first transistor T2 includes a top gate G1 and a bottom gate G2 on both sides of the active layer IGZO, between the second metal layer M2 and the first metal layer M1, i.e., as shown, the second metal layer M2 is located on the side of the bottom gate G2 facing the substrate base 11. In addition, the display panel further includes a plurality of dielectric layers in addition to the substrate base plate 11 and the buffer layer 12 to function as interlayer isolation insulation.

In this embodiment, the substrate 11 is a multi-film structure, may be a flexible substrate made of an insulating material, and has the characteristics of being stretchable, bendable, or bendable, and the material includes but is not limited to polyimide material (PI), polycarbonate material (PC), polyethylene terephthalate material (PET), and the like.

Optionally, the buffer layer 12 includes, but is not limited to, an inorganic material layer or an organic material layer, where the material of the inorganic material layer includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or aluminum nitride, and the material of the organic material layer includes, but is not limited to, acrylic, PI, or the like.

In the present application, the first transistor T2 is an oxide semiconductor transistor, because the first electrode of the first transistor T2 is connected to the gate of the driving transistor T0, and because the gate potential of the driving transistor T0 has an important influence on the driving current, the requirement for the stability of the gate potential of the driving transistor T0 during the light emitting period is very high, which requires that the leakage current of the first transistor T2 is sufficiently small when the first transistor T2 is in the off state, and the oxide semiconductor transistor has the characteristic that the leakage current is small, so that it is advantageous to set the first transistor T2 as an oxide semiconductor transistor to stabilize the gate potential of the driving transistor T0.

In addition, in this embodiment, the driving transistor may be an oxide semiconductor transistor, or may be a silicon transistor, that is, the active layer may be a silicon-based active layer poly as shown in fig. 2, or may be an oxide semiconductor active layer IGZO as in the first transistor T2.

In addition, it should be noted that the pixel circuit shown in fig. 1 is only one case of the pixel circuit included in the embodiment of the present application, and any pixel circuit layout structure that satisfies the features defined in the present application falls within the scope of the present application, in the present application, the first transistor T2 may be a compensation transistor shown in fig. 1, in other embodiments of the present application, the pixel circuit may further include a reset transistor connected to the gate of the driving transistor and the reset signal terminal, the reset transistor is used for providing the reset signal to the gate of the driving transistor, and the first transistor T2 may be a reset transistor.

Referring to fig. 4, fig. 4 is another schematic circuit layout diagram of a pixel circuit in a display panel according to an embodiment of the present invention, when the pixel circuit is projected to a plane parallel to a surface of the display panel, at least a partial region of a first signal line L3-1 in a signal line group is located between a first edge a1 and a second edge a2, and at least a partial region of a second signal line L3-2 in the signal line group is also located between the first edge a1 and a second edge a 2; the first signal line L3-1 is connected to the top gate G1 of the first transistor T2 for providing a control signal to the top gate G1 of the first transistor T2; the second signal line L3-2 is connected to the bottom gate G2 of the first transistor T2 for providing a control signal to the bottom gate G2 of the first transistor T2; the first signal line L3-1 and the second signal line L3-2 extend in the first direction X.

That is, referring to fig. 2, based on the structure in which the first transistor T2 is an oxide semiconductor transistor, the first transistor T2 has a top gate G1 and a bottom gate G2 at different layers, then a first signal line L3-1 for supplying a control signal to the top gate G1 of the first transistor T2, the second signal line L3-2 for supplying a control signal to the bottom gate G2 of the first transistor T2 is also located at a different layer, and since the top gate G1 and the bottom gate G2 are located at a different layer from the first metal layer M1, since the first signal line L3-1 is generally disposed at the same layer as the top gate G1, the second signal line L3-2 is generally disposed at the same layer as the bottom gate G2, therefore, the first signal line L3-1, the second signal line L3-2 and the first metal layer M1 are also located at different layers, namely, the first signal line L3-1, the second signal line L3-2 and the first metal layer M1 are disposed in different layers.

First, by using the first signal line L3-1 and the second signal line L3-2 of different layers to be spaced between the first edge a1 and the second edge a2, the adjustability limitation is small in the case of layout size limitation when adjusting the spacing between adjacent signal lines and the width of the signal lines themselves based on the characteristics of the different layers.

Secondly, the first transistor T2 has the top gate G1 and the bottom gate G2, so that the first signal line L3-1 and the second signal line L3-2 located in different layers are naturally generated, in this embodiment, the first signal line L3-1 and the second signal line L3-2 are spaced between the first edge a1 and the second edge a2, so that two signal lines located in different layers are spaced between the first edge a1 and the second edge a2 at the same time, and from the perspective of blocking electric field lines, the two signal lines located in different layers can block more electric field lines, so as to better weaken the electric field between the first edge a1 and the second edge a2, thereby reducing the parasitic capacitance and enhancing the stability of the gate voltage of the driving transistor T0.

Alternatively, in another embodiment of the present invention, as shown in fig. 4, when the front projection is performed on a plane parallel to the surface of the display panel, the first edge a1 and the second edge a2 are located at two sides formed by extending the first signal line L3-1 along the first direction X, and the first edge a1 and the second edge a2 are located at two sides formed by extending the second signal line L3-2 along the first direction X.

That is, the first signal line L3-1 and the second signal line L3-2 are themselves located directly between the first edge a1 and the second edge a2, which enables blocking of electric field lines between the first edge a1 and the second edge a2, which is one implementation in this application.

Optionally, in another embodiment of the present invention, referring to fig. 5, fig. 5 is a schematic circuit layout diagram of a pixel circuit in a display panel according to an embodiment of the present invention.

As shown in fig. 5, the first signal line L3-1 includes a first protrusion L3-1-a extending in the second direction Y, and the second signal line L3-2 includes a second protrusion L3-2-a extending in the second direction Y, the first direction X and the second direction Y intersecting, and particularly, the first direction X may be perpendicular to the second direction Y.

The first edge a1 and the second edge a2 are located at two sides formed after the first protrusion L3-1-a extends along the second direction Y, and the first edge a1 and the second edge a2 are located at two sides formed after the second protrusion L3-2-a extends along the second direction Y. In some other embodiments, the first protrusion L3-1-a may also be a broken line or a curved line, and first extends along the second direction Y, and then extends along the first direction X, as long as the first edge a1 and the second edge a2 are located at two sides formed after the first protrusion L3-1-a extends, which falls within the protection scope of the present application; similarly, the second protrusion L3-2-a may also be a broken line or a curve, which extends along the second direction Y first and then extends towards the first direction X, as long as the first edge a1 and the second edge a2 are located at two sides formed after the second protrusion L3-2-a extends, which is the protection scheme of the present application.

That is, in the case where the first signal line L3-1 and the second signal line L3-2 do not themselves lie between the first edge A1 and the second edge A2, when blocking of the electric field lines between the first edge a1 and the second edge a2 is not achieved, the wiring form of the first signal line L3-1 and the second signal line L3-2 may be modified such that the first signal line L3-1 has a first convex portion L3-1-a extending in the second direction Y, the second signal line L3-2 has a second convex portion L3-2-a extending in the second direction Y, and the first edge a1 and the second edge a2 are located at both sides formed after the first protrusion L3-1-a extends in the second direction Y, and the first edge a1 and the second edge a2 are located at both sides formed after the second protrusion L3-2-a extends in the second direction Y.

Since the first signal line L3-1 and the second signal line L3-2 are disposed in different layers and are also disposed in different layers from the first metal layer M1, that is, the first signal line L3-1, the second signal line L3-2 and the first metal layer M1 are disposed in different layers, the first protrusion L3-1-a and the second protrusion L3-2-a are also disposed in different layers and are also different from the first metal layer M1.

In the case where the first and second protrusions L3-1-a and L3-2-a are located between the first and second edges a1 and a2, blocking of electric field lines between the first and second edges a1 and a2 may also be achieved to weaken an electric field in a local area, thereby reducing parasitic capacitance and enhancing stability of a gate voltage of the driving transistor T0.

Optionally, in another embodiment of the present invention, referring to fig. 6, fig. 6 is a schematic circuit layout diagram of a pixel circuit in a display panel according to an embodiment of the present invention.

As shown in fig. 6, when the display panel is orthographically projected to a plane parallel to the surface of the display panel, a distance D11 is provided between a portion of the first signal line L3-1 spaced between the first edge a1 and the second edge a2 and the first edge a1, and a distance D12 is provided between a portion of the second signal line L3-2 spaced between the first edge a1 and the second edge a2 and the first edge a 1.

The first signal line L3-1 is spaced apart from the second edge A2 by a distance D21 between the portion spaced apart from the first edge A1 and the second edge A2, and the second signal line L3-2 is spaced apart from the second edge A2 by a distance D22 between the portion spaced apart from the first edge A1 and the second edge A2; wherein the content of the first and second substances,

d11 > D21, and/or D12 > D22.

That is, the first and second signal lines L3-1 and L3-2 further optimize the blocking effect of the electric field lines by the first and second signal lines L3-1 and L3-2 on the premise that blocking of the electric field lines between the first and second edges a1 and a2 can be achieved.

Since the first edge a1 is a side of the first pole of the first transistor T2 facing the first pole of the data write transistor T1, and the first pole of the first transistor T2 is connected to the gate of the driving transistor T0, it can be understood that the first edge a1 is connected to the gate of the driving transistor T0.

If the first signal line L3-1 and/or the second signal line L3-2 is closer to the first edge a1, the first edge a1 may be interfered by the first signal line L3-1 and/or the second signal line L3-2, which may affect the stability of the gate voltage of the driving transistor T0.

Because, in order to reduce the interference phenomenon suffered by the first edge a1 and sufficiently ensure the stability of the gate voltage of the driving transistor T0, the distance between the first signal line L3-1 and/or the second signal line L3-2 and the first edge a1 can be made sufficiently large, i.e., D11 > D21 and/or D12 > D22.

Note that, in the case of D11 > D21, and D12 > D22, the degree of disturbance to the first edge a1 is theoretically the lowest, and the stability of the gate voltage of the driving transistor T0 is optimal in this state.

In fig. 6, the lengths of the double-headed arrows indicating the distances between the first signal line L3-1, the second signal line L3-2, the first edge a1, and the second edge a2 do not indicate the numerical values of the distances, and the specific relationship between the distances is described in the specification.

Optionally, in another embodiment of the present invention, referring to fig. 7, fig. 7 is a schematic circuit layout diagram of a pixel circuit in a display panel according to an embodiment of the present invention.

When orthographically projected to a plane parallel to the surface of the display panel, the width of a portion of the first signal line L3-1 spaced between the first edge a1 and the second edge a2 is W1, and the width of a portion of the second signal line L3-2 spaced between the first edge a1 and the second edge a2 is W2.

The width of the overlapping portion between the first signal line L3-1 and the second signal line L3-2 is W0; wherein 0 ≦ W0 < Wx, which is the smaller of W1 and W2.

It should be noted that the width is worth mentioning the width of the first signal line L3-1 and the second signal line L3-2 in the direction parallel to the plane of the display panel surface and perpendicular to the extending direction thereof.

Specifically, when W0 is equal to 0, it indicates that the first signal line L3-1 and the second signal line L3-2 do not overlap at all; when 0 < W0 < Wx, it means that the first signal line L3-1 and the second signal line L3-2 overlap, but the first signal line L3-1 and the second signal line L3-2 do not completely overlap.

Due to the different layer arrangement of the first signal line L3-1 and the second signal line L3-2, if the first signal line L3-1 and the second signal line L3-2 completely overlap, electric field lines blocked by the first signal line L3-1 and the second signal line L3-2 together are minimal; if the overlapping area of the first signal line L3-1 and the second signal line L3-2 is reduced, that is, the non-overlapping area is increased, the electric field lines blocked by the first signal line L3-1 and the second signal line L3-2 are increased accordingly.

Therefore, in the embodiment of the present application, 0 ≦ W0 < Wx is set to block the electric field lines between the first edge a1 and the second edge a2 by the maximum amount, so as to weaken the electric field between the first edge a1 and the second edge a2 to the maximum extent, thereby reducing the parasitic capacitance and enhancing the stability of the gate voltage of the driving transistor T0.

Moreover, since the first signal line L3-1 and the second signal line L3-2 are disposed in different layers and are disposed in different layers with respect to the first metal layer M1, the first edge a1 and the second edge a2 are not greatly affected when the overlapping area of the first signal line L3-1 and the second signal line L3-2 is small or is not overlapped at all.

Optionally, in another embodiment of the present invention, the width W1 of the first signal line L3-1 is greater than the width W2 of the second signal line L3-2.

Specifically, the top gate G1 and the bottom gate G2 are located between the second metal layer M2 and the first metal layer M1, and the top gate G1 is located on the side of the bottom gate G2 facing the first metal layer M1; it is indirect to say that the distance between the first signal line L3-1 and the first metal layer M1 is smaller than the distance between the second signal line L3-2 and the first metal layer M1 in the direction perpendicular to the substrate base plate surface, i.e., the first signal line L3-1 is closer to the first metal layer M1 than the second signal line L3-2.

Based on the electric field characteristics, the electric field intensity in the region of the first signal line L3-1 is greater than the electric field intensity in the region of the second signal line L3-2, and the electric field line density in the region of the first signal line L3-1 is greater, i.e., the electric field lines in the region of the first signal line L3-1 are denser.

Therefore, the width of the first signal line L3-1 is set to be larger in the embodiment of the present application, so as to block more electric field lines to the greatest extent, thereby sufficiently weakening the electric field between the first edge a1 and the second edge a2, thereby reducing the parasitic capacitance and enhancing the stability of the gate voltage of the driving transistor T0.

Optionally, in another embodiment of the present invention, as shown in fig. 3 to 7, the signal line group in the display panel further includes a third signal line L8, when the signal line group is orthographically projected to a plane parallel to the surface of the display panel, the third signal line L8 is located on a side of the first signal line L3-1 and the second signal line L3-2 away from the first edge a1, and at least a partial region of the third signal line L8 is also located between the first edge a1 and the second edge a 2.

Specifically, in the embodiment of the present application, in combination with the circuit diagram shown in fig. 1, the third signal line L8 is used for transmitting the initialization signal VAR to the anode of the light-emitting element Q to initialize the light-emitting element Q.

Optionally, the third signal line L8 is disposed on the same layer as the first signal line L3-1, because the top gate G1 and the bottom gate G2 are located between the second metal layer M2 and the first metal layer M1, and the top gate G1 is located on a side of the bottom gate G2 facing the first metal layer M1; it is indirectly stated that the distance between the first signal line L3-1 and the first metal layer M1 is equal to the distance between the third signal line L8 and the first metal layer M1, and both are smaller than the distance between the second signal line L3-2 and the first metal layer M1, i.e., the first signal line L3-1 and the third signal line L8 are closer to the first metal layer M1 than the second signal line L3-2.

Based on the electric field characteristics, the first signal line L3-1 and the third signal line L8 are closer to the first metal layer M1, the electric field intensity in the region of the first signal line L3-1 and the third signal line L8 is greater than the electric field intensity in the region of the second signal line L3-2, the electric field line density in the region of the first signal line L3-1 and the third signal line L8 is greater, that is, the electric field lines in the region of the first signal line L3-1 and the third signal line L8 are denser.

Therefore, in the embodiment of the present application, more signal lines are disposed in the region with a greater density of electric field lines to block more electric field lines to the greatest extent, and three signal lines are spaced between the first edge a1 and the second edge a2 to block the electric field lines between the first edge a1 and the second edge a2, so as to sufficiently weaken the electric field between the first edge a1 and the second edge a2, thereby reducing the parasitic capacitance and enhancing the stability of the gate voltage of the driving transistor T0.

Optionally, in another embodiment of the present invention, referring to fig. 8, fig. 8 is a schematic circuit layout diagram of a pixel circuit in a display panel according to an embodiment of the present invention.

When orthographically projected to a plane parallel to the surface of the display panel, the distance D31 between the third signal line L8 and the first signal line L3-1 is greater than the distance D32 between the second signal line L3-2 and the third signal line L8.

Specifically, since the third signal line L8 is located at the same level as the first signal line L3-1 and the third signal line L8 also extends along the first direction X, the distance between the first signal line L3-1 and the third signal line L8 needs to be increased to avoid interference between the first signal line L3-1 and the third signal line L8.

In addition, in the case of increasing the distance between the first signal line L3-1 and the third signal line L8, more electric field lines can be blocked additionally, so as to sufficiently weaken the electric field between the first edge a1 and the second edge a2, thereby reducing the parasitic capacitance and enhancing the stability of the gate voltage of the driving transistor T0.

Note that, the length of the double-headed arrow indicating the pitch between the first signal line L3-1, the second signal line L3-2, and the third signal line L8 in fig. 8 does not indicate the magnitude of the pitch, and the relationship between the magnitudes of the pitches is described in the text of the specification.

Optionally, in another embodiment of the present invention, referring to fig. 9, fig. 9 is a schematic circuit layout diagram of a pixel circuit in a display panel according to an embodiment of the present invention.

The signal line group in the display panel comprises a sixth signal line L2, the sixth signal line L2 is connected to the gate of the data writing transistor T1 and is used for providing a control signal for the data writing transistor T1, and the sixth signal line L2 is positioned between the first signal line L3-1 and/or the second signal line L3-2 and the gate of the driving transistor T0.

The active layer of the first transistor T2 includes a first region B1 and a second region B2.

As shown in fig. 2, the first region B1 and the sixth signal line L2 overlap each other to form a first capacitor C1.

The second region B2 overlaps the first and second signal lines L3-1 and L3-2 to form a channel region of the first transistor T2.

In this embodiment, referring to fig. 10, fig. 10 is another schematic circuit structure diagram of the pixel circuit in the display panel according to the embodiment of the present invention, and as shown in fig. 10, a first capacitor C1 is formed between the gate of the driving transistor T0 and the gate trace sixth signal line L2 of the data writing transistor T1.

Since the first signal line L3-1 and the second signal line L3-2 need to be disposed between the first edge a1 and the second edge a2, so as to block the electric field lines between the first edge a1 and the second edge a2, in order to ensure that the pixel circuit 10 can operate normally and make the space of the circuit layout as compact as possible, and increase the resolution of the display panel (Pixels Per, abbreviated as PPI), in the embodiment of the present application, the active layer IGZO of the first transistor T2 is multiplexed to serve as a capacitor plate, on one hand, the first region B1 and the sixth signal line L2 overlap each other to form the first capacitor C1, and on the other hand, the second region B2 overlaps the first signal line L3-1 and the second signal line L3-2 to form a channel region of the first transistor T2; that is, the limited space of the circuit layout is fully utilized, and more structures are accommodated under the condition that the pixel circuit 10 can normally operate, so that the space of the circuit layout is as compact as possible.

Optionally, in another embodiment of the present invention, referring to fig. 11, fig. 11 is a schematic circuit layout diagram of a pixel circuit in a display panel according to an embodiment of the present invention.

The first region B1 of the active region of the first transistor T2 extends in the third direction Z, and the second region B2 of the active region of the first transistor T2 extends in the first direction X, which is perpendicular to the third direction Z.

There is no overlap between the first capacitor C1 and the channel region of the first transistor T2.

Specifically, in order to avoid that the distance between the second edge a2 and the gate of the driving transistor T0 is relatively long, which results in a relatively large space occupied by the pixel circuit and affects the resolution of the display panel, the first region B1 of the active region of the first transistor T2 is arranged to extend along the third direction Z, and the second region B2 of the active region of the first transistor T2 extends along the first direction X, that is, the number of structures arranged in the third direction Z is avoided too much, that is, in a case where a plurality of signal lines are spaced between the first edge a1 and the second edge a2, the distance between the first edge a1 and the second edge a2 is avoided from being too far, which results in a relatively large area of the entire pixel circuit.

Optionally, in another embodiment of the present invention, referring to fig. 12, fig. 12 is a schematic circuit layout diagram of a pixel circuit in a display panel according to an embodiment of the present invention.

The first region B1 of the active region of the first transistor T2 has a width H1 in the first direction X and a length K1 in the third direction Z, wherein H1 > K1.

The second region B2 of the active region of the first transistor T2 has a length K2 in the first direction X and a width H2 in the third direction Z, wherein K2 > H2.

Specifically, since the active layer of the first transistor T2 serves as a capacitor plate on one hand, and the first region B1 and the sixth signal line L2 are overlapped with each other to form the first capacitor C1, under the condition that the first capacitor C1 has a certain capacitance value, the width of the first region B1 of the active layer of the first transistor T2 in the first direction X needs to be as large as possible, and the length in the third direction Z needs to be as small as possible, so that the plate area of the first capacitor C1 is ensured to be large, and meanwhile, the first edge a1 and the second edge a2 in the third direction Z can be prevented from being too far apart.

Since the second region B2 of the active layer of the first transistor T2 overlaps the first signal line L3-1 and the second signal line L3-2 to form the channel region of the first transistor T2, the length of the channel region in the first direction X may be appropriately increased so as to be greater than the width in the third direction Z.

Alternatively, in another embodiment of the present invention, since the signal line group in the display panel includes at least one signal line for supplying a control signal or an input signal to the transistor of the pixel circuit, exemplary signal lines that may be included in the signal line group include a signal line L1 for supplying a data signal Vdata, a signal line L2 for supplying a control signal S1, a signal line L3 for supplying a control signal S2, a signal line L4 for supplying a control signal S3, a signal line L5 for supplying a control signal S4, a signal line L6 for supplying a control signal EM, a signal line L7 for supplying a reset signal DVINI, a signal line L8 for supplying an initialization signal VAR, and the like.

That is, the signal lines disposed between the first edge a1 and the second edge a2 are not only the first signal line L3-1, the second signal line L3-1, and the third signal line L8, but may be other signal lines.

That is, when orthographically projected onto a plane parallel to the surface of the display panel, the signal line group includes a fourth signal line, and at least a partial region of the fourth signal line is located between the first edge a1 and the second edge a 2.

The fourth signal line is located in a fourth metal layer, and the fourth metal layer is arranged in a different layer from the first metal layer M1.

Specifically, any signal line between the first edge a1 and the second edge a2 may be used as the fourth signal line to block the electric field lines between the first edge a1 and the second edge a2, and to weaken the electric field between the first edge a1 and the second edge a2, thereby reducing the parasitic capacitance and enhancing the stability of the gate voltage of the driving transistor T0.

In the embodiments of the present application, the specific function of the fourth signal line is not limited in the embodiments of the present application.

It should be noted that, in the embodiments of the present application, the fourth signal line is not shown in the drawings of the specification.

Optionally, in another embodiment of the present invention, the fourth metal layer is located between the second metal layer M2 and the first metal layer M1; and is

In the direction perpendicular to the surface of the display panel, the distance between the first metal layer M1 and the fourth metal layer is smaller than the distance between the second metal layer M2 and the fourth metal layer.

Specifically, the electric field strength is greater as the density of electric field lines between the first edge a1 and the second edge a2 is greater toward the region where the first metal layer M1 is located.

Then, in the direction perpendicular to the surface of the display panel, the distance between the first metal layer M1 and the fourth metal layer is smaller than the distance between the second metal layer M2 and the fourth metal layer, and since the fourth signal line is located on the fourth metal layer, the distance between the fourth signal line and the first metal layer M1 is also smaller than the distance between the fourth signal line and the second metal layer M2, that is, the fourth signal line is closer to the first metal layer M1, so as to block more electric field lines to the maximum extent, thereby sufficiently weakening the electric field between the first edge a1 and the second edge a2, thereby reducing the parasitic capacitance and enhancing the stability of the gate voltage of the driving transistor T0.

Optionally, in another embodiment of the present invention, when the display panel is orthographically projected to a plane parallel to the surface of the display panel, a distance between the fourth signal line and the first edge a1 is greater than a distance between the fourth signal line and the second edge a 2.

Specifically, on the premise that the fourth signal line can block the electric field lines between the first edge a1 and the second edge a2, the blocking effect of the fourth signal line on the electric field lines is further optimized.

Since the first edge a1 is a side of the first pole of the first transistor T2 facing the first pole of the data write transistor T1, and the first pole of the first transistor T2 is connected to the gate of the driving transistor T0, it can be understood that the first edge a1 is connected to the gate of the driving transistor T0.

If the fourth signal line is closer to the first edge a1, the fourth signal line may also interfere with the first edge a1, thereby affecting the stability of the gate voltage of the driving transistor T0.

Because, in order to reduce the interference phenomenon suffered by the first edge a1 and sufficiently ensure the stability of the gate voltage of the driving transistor T0, the distance between the fourth signal line and the first edge a1 may be made large enough, that is, the distance between the fourth signal line and the first edge a1 is larger than the distance between the fourth signal line and the second edge a 2.

Alternatively, in another embodiment of the present invention, since the signal line group in the display panel includes at least one signal line for providing a control signal or an input signal to the transistor of the pixel circuit 10, exemplary signal lines that may be included in the signal line group include a signal line L1 for providing a data signal Vdata, a signal line L2 for providing a control signal S1, a signal line L3 for providing a control signal S2, a signal line L4 for providing a control signal S3, a signal line L5 for providing a control signal S4, a signal line L6 for providing a control signal EM, a signal line L7 for providing a reset signal DVINI, a signal line L8 for providing an initialization signal VAR, and the like.

That is, the signal lines disposed between the first edge a1 and the second edge a2 are not only the first signal line L3-1, the second signal line L3-2, and the third signal line L8, but may be other signal lines.

That is, when orthographically projected onto a plane parallel to the surface of the display panel, a fifth signal line may be further included in the signal line group, and at least a partial region of the fifth signal line is also located between the first edge a1 and the second edge a 2.

The fifth signal line is located on a fifth metal layer, and the fifth metal layer is arranged in a different layer from the first metal layer M1.

Specifically, any signal line between the first edge a1 and the second edge a2 may be used as the fifth signal line to block the electric field lines between the first edge a1 and the second edge a2, and to weaken the electric field between the first edge a1 and the second edge a2, thereby reducing the parasitic capacitance and enhancing the stability of the gate voltage of the driving transistor T0.

In the embodiments of the present application, the specific function of the fifth signal line is not limited in the embodiments of the present application.

Further, in the embodiment of the present application, in the case that the fourth signal line and the fifth signal line are spaced between the first edge a1 and the second edge a2, the two signal lines are more favorable for blocking more electric field lines between the first edge a1 and the second edge a2, so as to sufficiently weaken the electric field between the first edge a1 and the second edge a2, thereby reducing the parasitic capacitance and enhancing the stability of the gate voltage of the driving transistor T0.

Note that, in the embodiments of the present application, the fifth signal line is not shown in the drawings of the specification.

Optionally, in another embodiment of the present invention, the fourth metal layer is located on a side of the fifth metal layer facing the first metal layer M1, and

the fourth signal line is located on a side of the fifth signal line facing the second edge a2 when orthographically projected to a plane parallel to the surface of the display panel.

Specifically, since the first edge a1 is a side of the first pole of the first transistor T2 facing the first pole of the data writing transistor T1, and the first pole of the first transistor T2 is connected to the gate of the driving transistor T0, it can be understood that the first edge a1 is connected to the gate of the driving transistor T0.

That is, the fourth metal layer is located on the side of the fifth metal layer facing the first metal layer M1, the fourth metal layer is closer to the first metal layer M1 than the fifth metal layer, and if the fourth signal line is closer to the first edge a1, the fourth signal line may also interfere with the first edge a1, and further affect the stability of the gate voltage of the driving transistor T0.

Therefore, the fourth signal line is disposed at a side close to the second edge a2, which is beneficial to reducing the influence of the fourth signal line on the first edge a1 and sufficiently ensuring the stability of the gate voltage of the driving transistor T0.

Optionally, based on all the above embodiments of the present invention, in another embodiment of the present invention, a display device is further provided, referring to fig. 13, and fig. 13 is a schematic structural diagram of the display device provided in the embodiment of the present invention.

The display device 13 includes any one of the display panels provided in the above embodiments.

Since the display panel 13 provided by the embodiment of the present invention includes any one of the display panels provided by the above embodiments, the same or corresponding technical effects as those of the display panel provided by the above embodiments are achieved.

The display device 13 may be a mobile phone, a computer, other electronic devices, and the like.

The display panel and the display device provided by the present invention are described in detail above, and the principle and the embodiment of the present invention are explained in detail herein by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include or include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.