阅读说明：本技术 输入电路 (Input circuit ) 是由 宇野治 于 2021-04-25 设计创作，主要内容包括：本发明公开了一种输入电路。输入电路(1)包括输入缓冲电路(12)、N型晶体管(N1)及上拉电路(21),该输入缓冲电路(12)将第一节点(a)作为输入,并将第二节点(b)作为输出,该N型晶体管(N1)的源极与输入端子(PAD)连接,漏极与第一节点(a)连接,栅极与电源(VDD)连接,该上拉电路(21)设置在第一节点(a)与电源(VDD)之间。上拉电路(21)在输入信号从低转变为高时,使电源(VDD)与第一节点(a)在规定期间内导通,另一方面,在输入信号从高转变为低时,不使电源(VDD)与第一节点(a)导通。在输入电路中,可缩短输入缓冲电路中的延迟时间,并可抑制输出信号的脉冲宽度的误差。(The invention discloses an input circuit. An input circuit (1) includes an input buffer circuit (12), an N-type transistor (N1) and a pull-up circuit (21), wherein the input buffer circuit (12) has a first node (a) as an input and a second node (b) as an output, the N-type transistor (N1) has a source connected to an input terminal (PAD), a drain connected to the first node (a), and a gate connected to a power source (VDD), and the pull-up circuit (21) is provided between the first node (a) and the power source (VDD). The pull-up circuit (21) conducts the power supply (VDD) and the first node (a) for a predetermined period when the input signal transitions from low to high, and does not conduct the power supply (VDD) and the first node (a) when the input signal transitions from high to low. In an input circuit, a delay time in an input buffer circuit can be shortened, and an error in a pulse width of an output signal can be suppressed.)

1. An input circuit that receives an input signal at an input terminal, comprising:

the input circuit comprises an input buffer circuit, an N-type transistor and a pull-up circuit,

the input buffer circuit having a first node as an input and a second node as an output,

a source of the N-type transistor is connected to the input terminal, a drain of the N-type transistor is connected to the first node, a gate of the N-type transistor is connected to a power supply,

the pull-up circuit is disposed between the first node and the power supply,

the pull-up circuit is configured to: the power supply and the first node are turned on for a predetermined period when the input signal transitions from low to high, and the power supply and the first node are not turned on when the input signal transitions from high to low.

2. The input circuit of claim 1, wherein:

the pull-up circuit includes a NAND circuit and a P-type transistor,

the NAND circuit has a signal of the first node as a first input and a signal of the second node as a second input when the input buffer circuit is an inverter and an inverted signal of the second node as a second input when the input buffer circuit is a buffer which does not invert the logic of the signal,

the source of the P-type transistor is connected to the power supply, the drain of the P-type transistor is connected to the first node, and the output of the NAND circuit is received at the gate of the P-type transistor.

3. The input circuit of claim 1, wherein:

the pull-up circuit includes a first P-type transistor and a second P-type transistor,

the first and second P-type transistors are connected in series between the power supply and the first node,

the first P-type transistor receives an inverted signal of the first node at a gate,

the second P-type transistor receives a signal of the second node at a gate when the input buffer circuit is a buffer that does not invert a logic of the signal, and receives an inverted signal of the second node at the gate when the input buffer circuit is an inverter.

4. The input circuit of claim 1, wherein:

the pull-up circuit includes a first P-type transistor and a second P-type transistor,

the first and second P-type transistors are connected in series between the power supply and the first node,

the first P-type transistor receives an inverted signal of the first node at a gate,

the second P-type transistor receives at a gate an inverse of the signal received by the gate of the first P-type transistor.

5. The input circuit of claim 1, wherein:

the input buffer circuit receives an enable signal, passes a signal of the first node when the enable signal is at a first logic level, and does not pass a signal of the first node when the enable signal is at a second logic level,

the pull-up circuit is configured to: when the enable signal is at the second logic level, the power supply is not conducted with the first node.

6. The input circuit of claim 1, wherein:

the input circuit includes a second N-type transistor having a drain connected to the power supply, a source connected to the first node, and a gate connected to the input terminal.

7. An input circuit that receives an input signal at an input terminal, comprising:

the input circuit comprises an input buffer circuit, an N-type transistor and a pull-up circuit,

the input buffer circuit having a first node as an input and a second node as an output,

a source of the N-type transistor is connected to the input terminal, a drain of the N-type transistor is connected to the first node, a gate of the N-type transistor is connected to a power supply,

the pull-up circuit is disposed between the first node and the power supply,

the pull-up circuit includes a first P-type transistor and a second P-type transistor,

the first and second P-type transistors are connected in series between the power supply and the first node,

the first P-type transistor receives an inverted signal of the first node at a gate,

the second P-type transistor receives a signal of the second node at a gate when the input buffer circuit is a buffer that does not invert a logic of the signal, and receives an inverted signal of the second node at the gate when the input buffer circuit is an inverter.

8. The input circuit of claim 7, wherein:

the input buffer circuit receives an enable signal, passes a signal of the first node when the enable signal is at a first logic level, and does not pass a signal of the first node when the enable signal is at a second logic level,

the pull-up circuit includes a third P-type transistor,

the third P-type transistor is connected in series with the first P-type transistor and the second P-type transistor,

the third P-type transistor receives a low signal at a gate when the enable signal is at the first logic level and receives a high signal at the gate when the enable signal is at the second logic level.

9. The input circuit of claim 7, wherein:

the input circuit includes a second N-type transistor having a drain connected to the power supply, a source connected to the first node, and a gate connected to the input terminal.

10. An input circuit that receives an input signal at an input terminal, comprising:

the input circuit comprises an input buffer circuit, an N-type transistor, a pull-up circuit and a voltage conversion circuit,

the input buffer circuit having a first node as an input and a second node as an output,

a source of the N-type transistor is connected to the input terminal, a drain of the N-type transistor is connected to the first node, a gate of the N-type transistor is connected to a third node,

the pull-up circuit is disposed between the first node and the third node,

the voltage conversion circuit is configured to: outputting a voltage of the power supply to the third node when the power supply is turned on, dividing a voltage of the input terminal and outputting the divided voltage to the third node when the power supply is turned off,

the pull-up circuit is configured to: when the input signal changes from low to high upon the power-on, the third node and the first node are turned on for a predetermined period, and when the input signal changes from high to low, the third node and the first node are not turned on.

11. The input circuit of claim 10, wherein:

the pull-up circuit includes a NAND circuit, a first P-type transistor, a second P-type transistor, and a pass-gate switch,

the NAND circuit has a signal of the first node as a first input and a signal of the second node as a second input when the input buffer circuit is an inverter and an inverted signal of the second node as a second input when the input buffer circuit is a buffer which does not invert the logic of the signal,

a source of the first P-type transistor is connected to the third node, a drain of the first P-type transistor is connected to the first node, an output of the NAND circuit is received at a gate of the first P-type transistor,

a source of the second P-type transistor is connected to a gate of the first P-type transistor, a drain of the second P-type transistor is connected to the first node, a gate of the second P-type transistor is connected to the power supply,

the transmission gate switch is composed of a P-type transistor and an N-type transistor connected in parallel, and is disposed between the gate of the first P-type transistor and the output node of the NAND circuit, the gate of the P-type transistor is connected to the first node, and the gate of the N-type transistor is connected to the power supply.

12. An input circuit that receives an input signal at an input terminal, comprising:

the input circuit comprises an input buffer circuit, an N-type transistor, a pull-up circuit and a voltage conversion circuit,

the input buffer circuit having a first node as an input and a second node as an output,

a source of the N-type transistor is connected to the input terminal, a drain of the N-type transistor is connected to the first node, a gate of the N-type transistor is connected to a third node,

the pull-up circuit is disposed between the first node and the third node,

the voltage conversion circuit is configured to: outputting a voltage of the power supply to the third node when the power supply is turned on, dividing a voltage of the input terminal and outputting the divided voltage to the third node when the power supply is turned off,

the pull-up circuit includes a first P-type transistor and a second P-type transistor,

the first and second P-type transistors are connected in series between the third node and the first node,

the first P-type transistor receives an inverted signal of the first node at a gate,

the second P-type transistor receives a signal of the second node at a gate when the input buffer circuit is a buffer that does not invert a logic of the signal, and receives an inverted signal of the second node at the gate when the input buffer circuit is an inverter.

13. The input circuit of claim 12, wherein:

the pull-up circuit includes a third P-type transistor and a pass-gate switch,

a source of the third P-type transistor is connected to a gate of the first P-type transistor or the second P-type transistor, a drain of the third P-type transistor is connected to the first node, a gate of the third P-type transistor is connected to the power supply,

the transmission gate switch is composed of a P-type transistor and an N-type transistor connected in parallel, and is disposed between a gate of the first P-type transistor or the second P-type transistor and a node that transmits a signal to the gate, the gate of the P-type transistor is connected to the first node, and the gate of the N-type transistor is connected to the power supply.

Technical Field

The present disclosure relates to an input circuit for a semiconductor integrated circuit device.

Background

In a semiconductor integrated circuit device, when the semiconductor integrated circuit device is connected to another electronic device, a signal having a voltage higher than a power supply voltage of the semiconductor integrated circuit device may be input. In such a case, in order to protect the internal circuit, a circuit for reducing the voltage of an input signal is provided in an input circuit of the semiconductor integrated circuit device. For example, in a commonly used input circuit, an N-type transistor for voltage reduction is provided in a stage preceding an input buffer circuit, and a gate of the N-type transistor is connected to a power supply. Thereby, the voltage of the input signal is reduced to a voltage corresponding to the difference between the power supply voltage and the threshold voltage of the N-type transistor. Therefore, the internal circuit of the semiconductor integrated circuit device can be protected.

Patent document 1 discloses the following configuration for an input circuit: the inverter includes an inverter as an input buffer circuit, an N-type transistor for voltage reduction provided at a preceding stage of the inverter, and a P-type transistor connected between an input node of the inverter and a power supply. The gate of the P-type transistor is connected to the output node of the inverter. When the input signal rises, if the output signal of the inverter is inverted from high to low, the P-type transistor is turned on, and the voltage of the input node of the inverter rises to the power supply voltage. This accelerates the inversion of the output signal, and therefore the delay time of the inverter can be kept short.

Patent document 1: japanese patent No. 3092636

Disclosure of Invention

Technical problems to be solved by the invention

However, in the input circuit disclosed in patent document 1, the following problems arise. That is, when the input signal starts to fall, the P-type transistor is in a conductive state. Therefore, the power source and the low-side driving element of the transmission-side output circuit are in a short-circuited state during a period until the output signal of the inverter is inverted to high and the P-type transistor is turned off. In this state, the transition of the input signal from high to low becomes slow, and the inversion of the output signal of the inverter is greatly delayed. Therefore, the delay time of the inverter may increase. As a result, a large difference occurs in delay time of the inverters in rising and falling of the input signal, and thus an error occurs in the pulse width of the output signal of the input circuit.

The purpose of the present disclosure is: in an input circuit, a delay time in an input buffer circuit is shortened, and an error in a pulse width of an output signal is suppressed.

Technical solution for solving technical problem

In a first aspect of the present disclosure, an input circuit that receives an input signal at an input terminal includes an input buffer circuit having a first node as an input and a second node as an output, an N-type transistor having a source connected to the input terminal, a drain connected to the first node, and a gate connected to a power supply, and a pull-up circuit (pull-up circuit) provided between the first node and the power supply, the pull-up circuit being configured to: the power supply and the first node are turned on for a predetermined period when the input signal transitions from low to high, and the power supply and the first node are not turned on when the input signal transitions from high to low.

According to this aspect, the input circuit includes an input buffer circuit having a first node as an input and a second node as an output, an N-type transistor having a source connected to the input terminal, a drain connected to the first node, and a gate connected to the power supply, and a pull-up circuit provided between the first node and the power supply. The pull-up circuit turns on the power supply and the first node for a predetermined period when the input signal transitions from low to high. Therefore, the voltage of the first node rises, the signal inversion of the second node is accelerated, and thus the delay time in the input buffer circuit becomes short. On the other hand, the pull-up circuit does not turn on the power supply from the first node when the input signal transitions from high to low. Therefore, no short circuit occurs between the power supply and the low-drive element of the transmission-side output circuit, and the input signal rapidly transitions from high to low, so that no delay is caused by the signal inversion at the second node. Therefore, the difference in delay time in the input buffer circuit can be suppressed between the rise and fall of the input signal, and thus the error occurring in the pulse width of the output signal can be suppressed.

In a second aspect of the present disclosure, an input circuit that receives an input signal at an input terminal includes an input buffer circuit that has a first node as an input and a second node as an output, an N-type transistor having a source connected to the input terminal, a drain connected to the first node and a gate connected to a power supply, and a pull-up circuit provided between the first node and the power supply, the pull-up circuit including a first P-type transistor and a second P-type transistor connected in series between the power supply and the first node, the first P-type transistor receiving an inversion signal of a signal of the first node at the gate, the second P-type transistor receiving a logic inversion signal of the signal when the input buffer circuit is a buffer that does not invert the logic of the signal, and receiving the signal of the second node at the gate, and receiving an inverted signal of the second node at the gate when the input buffer circuit is an inverter.

According to this aspect, the input circuit includes an input buffer circuit having a first node as an input and a second node as an output, an N-type transistor having a source connected to the input terminal, a drain connected to the first node, and a gate connected to the power supply, and a pull-up circuit provided between the first node and the power supply. The pull-up circuit includes a first P-type transistor and a second P-type transistor connected in series between a power supply and a first node. The first P-type transistor receives an inverted signal of a signal of the first node at a gate. The second P-type transistor receives a signal of the second node at the gate when the input buffer circuit is a buffer that does not invert the logic of the signal, and receives an inverted signal of the second node at the gate when the input buffer circuit is an inverter. When the input signal is a low signal, the second P-type transistor receives the low signal at the gate and is therefore in a conducting state. When the input signal changes from low to high, the first P-type transistor is turned on when the signal inverted from the signal at the first node is lower than a threshold value. Therefore, the voltage of the first node rises, the signal inversion of the second node is accelerated, and thus the delay time in the input buffer circuit becomes short. On the other hand, when the input signal is a high signal, the second P-type transistor receives a high signal at the gate and is thus in an off state. Therefore, when the input signal transitions from high to low, no short circuit occurs between the power supply and the low driving element of the transmission-side output circuit, the input signal rapidly transitions from high to low, and thus no delay is generated by the signal inversion of the second node. Therefore, the difference in delay time in the input buffer circuit can be suppressed in the rise and fall of the input signal, and thus the error generated in the pulse width of the output signal can be suppressed.

Effects of the invention

According to the present disclosure, in the input circuit, the delay time in the input buffer circuit can be shortened, and an error generated in the pulse width of the output signal can be suppressed.

Drawings

Fig. 1 is a diagram showing an example of a circuit configuration of an input circuit according to the first embodiment.

Fig. 2 is a signal waveform diagram showing an operation of the input circuit of fig. 1.

Fig. 3 is a diagram showing an example of the circuit configuration of the input circuit according to the second embodiment.

Fig. 4 is a signal waveform diagram showing an operation of the input circuit of fig. 3.

Fig. 5 is a diagram showing another circuit configuration example of the input circuit according to the second embodiment.

Fig. 6 is a diagram showing an example of the circuit configuration of the input circuit according to the third embodiment.

Fig. 7 is a diagram showing an example of the circuit configuration of the input circuit according to the fourth embodiment.

Fig. 8 is a signal waveform diagram showing an operation of the input circuit of fig. 7.

Fig. 9 is a diagram showing another circuit configuration example of the input circuit according to the fourth embodiment.

Fig. 10 is a diagram showing another circuit configuration example of the input circuit according to the fourth embodiment.

Fig. 11 is a diagram showing an example of the circuit configuration of an input circuit according to the fifth embodiment.

Fig. 12 is a diagram showing another circuit configuration example of the input circuit according to the fifth embodiment.

Fig. 13 is a diagram showing an example of the circuit configuration of the input circuit according to the sixth embodiment.

Fig. 14(a) is a diagram showing a circuit configuration example of the voltage conversion circuit in fig. 13, and fig. 14(b) shows an example of input/output voltages of the circuit in fig. 14 (a).

Fig. 15 is a diagram showing an example of the circuit configuration of the input circuit according to the seventh embodiment.

-description of symbols-

1. 2, 2A, 3, 4A, 4B, 5A, 6, 7-input circuit; 11-inverter (input buffer circuit); 12-buffers (input buffer circuits); 13-two-input NAND circuit (input buffer circuit); 14-two-input AND circuit (input buffer circuit); 21. 22, 22A, 23, 24A, 24B, 26, 27-pull-up circuitry; 31-a NAND circuit; 32. 33, 34-inverters; 61-a voltage conversion circuit; n1, N2-N type transistors; p1, P2, P5-P type transistors; a PAD-input terminal; SW-transmission gate switch; a-a first node; b-a second node; d-a third node; VDD-Power supply, Power supply Voltage.

Detailed Description

Hereinafter, embodiments will be described with reference to the drawings. In the circuit configuration diagram shown below, the components related to the present disclosure are mainly illustrated in a simplified manner. Thus, for example, there are the following cases: in an actual circuit configuration, components shown in the drawings as being directly connected are indirectly connected with each other with other components interposed therebetween.

In the following description, "VDD" is used as a symbol indicating both the power supply itself and the power supply voltage. The "high" and "low" of the signal mean the logic levels on the high side and the low side of the signal. The term "on" or "off" of a transistor means that the transistor is in a conductive state or a non-conductive state.

In the following embodiments, the power supply voltage VDD is set to 1.8V, and the voltage of the input signal is set to 3.3V or 1.8V. The description of the circuit operation is made for the case where the voltage of the input signal is 3.3V.

(first embodiment)

Fig. 1 shows a circuit configuration of an input circuit according to a first embodiment. An input circuit 1 shown in fig. 1 is provided in a semiconductor integrated circuit, and receives an input signal from another electronic device to the semiconductor integrated circuit through an input terminal PAD. When the voltage of the input signal is higher than the power supply voltage VDD, the input circuit 1 lowers the voltage of the input signal in order to protect the internal circuits of the semiconductor integrated circuit.

The input circuit 1 includes an inverter 11 as an example of an input buffer circuit, a step-down N-type transistor N1 provided between an input terminal PAD and the inverter 11, and a pull-up circuit 21. The inverter 11 receives the node a as an input, receives the node b as an output, inverts the signal at the node a, and outputs the inverted signal to the node b. The N-type transistor N1 has a source connected to the input terminal PAD, a drain connected to the node a, and a gate connected to the power supply VDD.

The pull-up circuit 21 includes a P-type transistor P1 and a two-input NAND circuit 31. The source of the P-type transistor P1 is connected to the power supply VDD, and the drain is connected to the node a. The two-input NAND circuit 31 has the signal of the node a and the signal of the node b as inputs, and the output node, i.e., the node c, is connected to the gate of the P-type transistor P1. That is, when the signals at nodes a and b are both high and the signal at node c is low, the P-type transistor P1 is turned on. Otherwise, the P-type transistor P1 is turned off.

The operation of the input circuit 1 of fig. 1 will be described with reference to signal waveforms of fig. 2.

(1) When a rising signal is input (the input signal changes from low to high)

When the input signal supplied to the input terminal PAD is low, the signal of the node a is low, and the signal of the node b is high. At this time, the signal at node c is high, and P-type transistor P1 is turned off.

When the input signal transitions from low to high, the voltage of node a rises as the voltage of the input signal rises. When the voltage of the node a exceeds the threshold of the NAND circuit 31, the signal of the node c becomes low, whereby the P-type transistor P1 is turned on. When the P-type transistor P1 is turned on, the voltage at the node a increases, and the signal at the node b is inverted more quickly. Therefore, the delay time in the inverter 11 becomes short (t 1).

Here, by designing the delay time in the NAND circuit 31 to be shorter than the delay time in the inverter 11, the P-type transistor P1 can be turned on faster than the example of patent document 1.

When the signal at the node b transitions from high to low, the signal at the node c becomes high, and the P-type transistor P1 becomes off again.

(2) When a falling signal is inputted (the input signal changes from high to low)

When the input signal transitions from high to low, the signal at node c remains high and the P-type transistor P1 remains off. Therefore, a short circuit does not occur between the power supply VDD and the low-drive element of the transmission-side output circuit, the input signal rapidly changes from high to low, and the signal waveform is not blunted. Therefore, the inversion of the signal of the node b is not delayed, and the delay time in the inverter 11 is not increased (t 2).

As a result of the above operation, no error occurs in the pulse width of the signal at the node b with respect to the pulse width of the input signal supplied to the input terminal PAD (tH _ b ═ tL _ PAD, tL _ b ═ tH _ PAD).

That is, in the present embodiment, the configuration is such that: the pull-up circuit 21 turns on the power supply VDD and the node a for a predetermined period when the input signal changes from low to high, and does not turn on the power supply VDD and the node a when the input signal changes from high to low.

As described above, according to the present embodiment, the input circuit 1 includes the inverter 11 having the node a as an input and the node b as an output, the N-type transistor N1 having the source of the N1 connected to the input terminal PAD, the drain connected to the node a, and the gate connected to the power supply VDD, and the pull-up circuit 21 provided between the node a and the power supply VDD. When the input signal changes from low to high, the output node c of the NAND circuit 31 becomes low for a predetermined period in the pull-up circuit 21, and the P-type transistor P1 turns on the power supply VDD and the node a. Therefore, the voltage of the node a rises, the signal inversion of the node b is accelerated, and therefore the delay time in the inverter 11 becomes short. On the other hand, when the input signal changes from high to low, the output node c of the NAND circuit 31 does not become low in the pull-up circuit 21, and the P-type transistor P1 does not turn on the power supply VDD and the node a. Therefore, a short circuit does not occur between the power supply VDD and the low driving element of the transmission side output circuit, the input signal rapidly transitions from high to low, and thus no delay is generated by the signal inversion of the node b. Therefore, the difference in delay time in the inverter 11 can be suppressed in the rise and fall of the input signal, and thus the error generated in the pulse width of the output signal can be suppressed.

Note that, as the input buffer circuit, a buffer that does not invert the logic of a signal may be used instead of the inverter 11. In this case, for example, an inverter may be provided between the node b and the NAND circuit 31. That is, the signal of the node a may be supplied as a first input to the NAND circuit 31, the signal of the node b may be supplied as a second input to the NAND circuit 31 when the input buffer circuit is an inverter, and the inverted signal of the node b may be supplied as a second input to the NAND circuit 31 when the input buffer circuit is a buffer that does not invert the logic of the signal.

(second embodiment)

Fig. 3 shows a circuit configuration of an input circuit according to a second embodiment. The basic configuration of the input circuit 2 shown in fig. 3 is the same as that of the input circuit 1 shown in fig. 1. As an example of the input buffer circuit, the input circuit 2 includes a buffer 12 that does not invert a signal, and a pull-up circuit 22 having a different configuration from the pull-up circuit 21 shown in fig. 1.

The pull-up circuit 22 includes P-type transistors P1, P2 connected in series between a power supply VDD and a node a, and an inverter 32. Inverter 32 receives the signal at node a and the output node, node c, is connected to the gate of P-type transistor P1. The P-type transistor P2 receives the signal at the output node of the buffer 12, i.e., the node b, at its gate.

The operation of the input circuit 2 of fig. 3 will be described with reference to signal waveforms of fig. 4.

(1) When a rising signal is input (the input signal changes from low to high)

When the input signal supplied to the input terminal PAD is low, the signal of the node a is low, and the signal of the node b is low. At this time, the signal at the node c becomes high, and the P-type transistor P1 is turned off. In addition, the P-type transistor P2 is turned on.

When the input signal transitions from low to high, the voltage of node a rises as the voltage of the input signal rises. When the voltage of the node a exceeds the threshold of the inverter 32, the signal of the node c becomes low, whereby the P-type transistor P1 is turned on. Since the P-type transistor P2 is turned on, the voltage at the node a is increased and the inversion of the signal at the node b is accelerated by turning on the P-type transistor P1. Therefore, the delay time in the buffer 12 is shortened (t 1).

Here, by designing the delay time in the inverter 32 to be shorter than the delay time in the buffer 12, the P-type transistor P1 can be turned on faster than the example of patent document 1.

When the signal at the node b transitions from low to high, the P-type transistor P2 becomes off.

(2) When a falling signal is inputted (the input signal changes from high to low)

When the input signal transitions from high to low, the signal at node b remains high and the P-type transistor P2 remains off. Therefore, a short circuit does not occur between the power supply VDD and the low-drive element of the transmission-side output circuit, the input signal rapidly changes from high to low, and the signal waveform is not blunted. Therefore, the inversion of the signal of the node b is not delayed, and the delay time in the buffer 12 is not increased (t 2).

Next, when the voltage of the node a falls below the threshold of the inverter 32, the signal of the node c becomes high, and the P-type transistor P1 becomes off again. After that, after the delay time in the buffer 12, the signal at the node b becomes low, and thus the P-type transistor P2 is turned on again. However, the P-type transistor P1 is turned off earlier than the P-type transistor P2 is turned on, and thus, when a falling signal is input, the power supply VDD and the node a are not turned on.

As a result of the above operation, no error occurs in the pulse width of the signal at the node b with respect to the pulse width of the input signal supplied to the input terminal PAD (tH _ b ═ tH _ PAD, tL _ b ═ tL _ PAD).

That is, the pull-up circuit 22 is configured to: when the input signal changes from low to high, the power supply VDD and the node a are turned on for a predetermined period, and when the input signal changes from high to low, the power supply VDD and the node a are not turned on.

As described above, according to the present embodiment, the input circuit 2 includes the buffer 12, the N-type transistor N1, and the pull-up circuit 22, the buffer 12 having the node a as an input and the node b as an output, the N-type transistor N1 having the source connected to the input terminal PAD, the drain connected to the node a, and the gate connected to the power supply VDD, and the pull-up circuit 22 provided between the node a and the power supply VDD. The pull-up circuit 22 includes P-type transistors P1, P2 connected in series between the power supply VDD and the node a. The P-type transistor P1 receives the inverted signal of the signal at the node a at its gate, and the P-type transistor P2 receives the signal at the node b at its gate. When the input signal is low, the P-type transistor P1 receives a high signal at the gate and is therefore off. When the input signal changes from low to high, the P-type transistor P1 is turned on when the signal inverted from the signal at the node a is lower than the threshold value. Therefore, the voltage of the node a rises, the signal inversion of the node b is accelerated, and thus the delay time in the buffer 12 becomes short. On the other hand, when the input signal is high, the P-type transistor P2 receives a high signal at the gate, and thus is in an off state. Therefore, when the input signal transitions from high to low, a short circuit does not occur between the power supply VDD and the low driving element of the transmission-side output circuit, the input signal rapidly transitions from high to low, and thus no delay is generated by the signal inversion of the node b. Therefore, the difference in delay time in the buffer 12 can be suppressed in the rise and fall of the input signal, and thus the error generated in the pulse width of the output signal can be suppressed.

Fig. 5 shows another circuit configuration example of the input circuit according to the present embodiment. As in the input circuit 2A shown in fig. 5, the inverter 11 may be used as an input buffer circuit. In this case, for example, in the pull-up circuit 22A, the inverter 33 may be provided between the node b and the gate of the P-type transistor P2, and the inverted signal of the node b may be supplied to the gate of the P-type transistor P2.

(third embodiment)

Fig. 6 shows a circuit configuration of an input circuit according to a third embodiment. The basic configuration of the input circuit 3 shown in fig. 6 is the same as that of the input circuit 2 shown in fig. 3. The input circuit 3 includes a pull-up circuit 23 having a different structure from the pull-up circuit 22 shown in fig. 3.

The pull-up circuit 23 includes P-type transistors P1, P2 and inverters 32, 34 connected in series between a power supply VDD and a node a. Inverter 32 receives the signal at node a and the output node, node c, is connected to the gate of P-type transistor P1. Inverter 34 receives the signal at node c and the output node is connected to the gate of P-type transistor P2.

That is, in the input circuit 2 shown in fig. 3, the signal of the node b is supplied to the gate of the P-type transistor P2, whereas in the input circuit 3 shown in fig. 6, the signal obtained by delaying the signal of the node a by the inverters 32 and 34 is supplied to the gate of the P-type transistor P2.

The operation of the input circuit 3 of fig. 6 is the same as the operation of the input circuit 2 of fig. 3. That is, the pull-up circuit 23 is configured to: when the input signal changes from low to high, the power supply VDD and the node a are turned on for a predetermined period, and when the input signal changes from high to low, the power supply VDD and the node a are not turned on. In the input circuit 3 of fig. 6, the P-type transistor P2 is controlled without depending on the characteristics of the buffer 12, which is an example of an input buffer circuit, and without affecting the characteristics of the buffer 12.

Therefore, according to the present embodiment, as in the second embodiment, the difference in delay time in the buffer 12 can be suppressed in the rise and fall of the input signal, and thus the error occurring in the pulse width of the output signal can be suppressed.

(fourth embodiment)

Fig. 7 shows a circuit configuration of an input circuit according to a fourth embodiment. The input circuit 4 shown in fig. 7 is configured to: the enable signal EN is received, and the pass/fail of the input signal can be controlled according to the enable signal EN. Here, the input circuit 4 is configured to: when the enable signal EN is "1" (high), the input signal is passed (enabled), and when the enable signal EN is "0" (low), the input signal is not passed (disabled).

As the input buffer circuit, the input circuit 4 includes a two-input NAND circuit 13. The two-input NAND circuit 13 has the signal of the node a and the enable signal EN as inputs, and has the node b as an output. When the enable signal EN is "1", an inverted signal of the node a is output to the node b, and when the enable signal EN is "0", the node b is fixed to be high. That is, the dual-input NAND circuit 13 functions as an inverter that passes a signal when the enable signal EN is "1", and does not pass a signal when the enable signal EN is "0".

The pull-up circuit 24 includes P-type transistors P1, P2 connected in series between the power supply VDD and the node a, and a NAND circuit 31. The NAND circuit 31 has the signal of the node a and the signal of the node b as inputs, and the output node, i.e., the node c, is connected to the gate of the P-type transistor P1. The gate of the P-type transistor P2 is connected to a node d that is the output node of the inverter 41 that receives the enable signal EN as an input. The pull-up circuit 24 has a structure in which a P-type transistor P2 is added to the pull-up circuit 21 of fig. 1.

When the enable signal EN is "1", the input circuit 4 of fig. 7 operates in the same manner as the input circuit 1 of fig. 1 according to the first embodiment because the dual-input NAND circuit 13 functions as an inverter and the P-type transistor P2 is turned on.

Fig. 8 is a signal waveform showing an operation when the enable signal EN is "0". As shown in fig. 8, when the enable signal EN is "0", the node b is fixed to high. Thus, the signal of the node c supplied to the gate of the P-type transistor P1 changes according to the transition of the input signal. However, since the signal of the node d supplied to the gate of the P-type transistor P2 is fixed to be high, the P-type transistor P2 is turned off. Therefore, short circuit does not occur between the power supply VDD and the low-drive element of the transmission-side output circuit, and the waveform of the input signal is not blunted.

Here, assuming that the P-type transistor P2 is not added to the pull-up circuit 24, the pull-up circuit 24 has the same structure as the pull-up circuit 21 of fig. 1. In this case, when the signal at the node c becomes low, a short circuit occurs between the power supply VDD and the low-driving element of the transmission-side output circuit, and the waveform of the input signal is blunted. In the present embodiment, this problem is solved. That is, according to this embodiment, the pass/fail of the input signal can be controlled by the enable signal EN, and when the enable signal EN is "0", the waveform of the input signal can be prevented from being blunted.

Fig. 9 shows another circuit configuration example of the input circuit according to the present embodiment. As the input buffer circuit, the input circuit 4A shown in fig. 9 includes a two-input AND circuit 14. The two-input AND circuit 14 has the signal of the node a AND the enable signal EN as inputs, AND the node b as an output. When the enable signal EN is "1", the signal of the node a is output to the node b, and when the enable signal EN is "0", the node b is fixed to be low. That is, the two-input AND circuit 14 functions as a buffer that allows a signal to pass when the enable signal EN is "1", AND does not allow a signal to pass when the enable signal EN is "0".

The pull-up circuit 24A includes P-type transistors P1, P2, P3 connected in series between the power supply VDD and the node a, and an inverter 32. Inverter 32 receives the signal at node a and the output node, node c, is connected to the gate of P-type transistor P1. The P-type transistor P2 receives a signal of the node b, which is the output of the two-input AND circuit 14, at the gate. The gate of the P-type transistor P3 is connected to a node d that is the output node of the inverter 41 that receives the enable signal EN as an input. The pull-up circuit 24A has a structure in which a P-type transistor P3 is added to the pull-up circuit 22 of fig. 3.

When the enable signal EN is "1", the input circuit 4A in fig. 9 operates in the same manner as the input circuit 2 in fig. 3 according to the second embodiment because the two-input AND circuit 14 functions as a buffer AND the P-type transistor P3 is turned on. On the other hand, when the enable signal EN is "0", the node b is fixed to low, and the P-type transistor P2 is turned on. However, since the signal of the node d supplied to the gate of the P-type transistor P3 is fixed to be high, the P-type transistor P3 is turned off. Therefore, short circuit does not occur between the power supply VDD and the low-drive element of the transmission-side output circuit, and the waveform of the input signal is not blunted. Therefore, the same action and effect as those of the input circuit 4 of fig. 7 are obtained.

Fig. 10 shows another circuit configuration example of the input circuit according to the present embodiment. As an input buffer circuit, the input circuit 4B shown in fig. 10 includes a two-input NAND circuit 13. The two-input NAND circuit 13 has a signal of the node a and the enable signal EN as inputs and a node b as an output, as in the input circuit 4 shown in fig. 7.

Pull-up circuit 24B includes P-type transistor P1 and three-input NAND circuit 35. The source of the P-type transistor P1 is connected to the power supply VDD, and the drain is connected to the node a. The three-input NAND circuit 35 has as inputs the signal of the node a, the signal of the node b, and the enable signal EN, and the output node, i.e., the node c, is connected to the gate of the P-type transistor P1.

When the enable signal EN is "1", the input circuit 4B in fig. 10 operates in the same manner as the input circuit 1 in fig. 1 according to the first embodiment because the two-input NAND circuit 13 functions as an inverter and the three-input NAND circuit 35 functions as a two-input NAND circuit. On the other hand, when the enable signal EN is "0", the node b is fixed to be high, but since the enable signal EN is included in the input of the three-input NAND circuit 35, the node c is fixed to be high. Therefore, the P-type transistor P1 is turned off. Therefore, short circuit does not occur between the power supply VDD and the low-drive element of the transmission-side output circuit, and the waveform of the input signal is not blunted. Therefore, the same action and effect as those of the input circuit 4 of fig. 7 can be obtained.

The structure of fig. 10 is such that only one stage of P-type transistors is arranged between the power supply VDD and the node a. This structure is effective in the case where a multistage structure of transistors is to be avoided from the viewpoint of area efficiency.

Note that this embodiment can be applied also to a case where the logic of the enable signal EN is opposite, that is, when the enable signal EN is "0", the input signal is passed (enabled) and when the enable signal EN is "1", the input signal is not passed (disabled). In this case, for example, in the configuration of fig. 7, the enable signal EN may be supplied to the gate of the P-type transistor P2, and the inverted signal of the enable signal EN may be supplied to the two-input NAND circuit 13.

(fifth embodiment)

Fig. 11 shows a circuit configuration of an input circuit according to a fifth embodiment. The input circuit 5 shown in fig. 11 includes an N-type transistor N2 provided between the power supply VDD and the node a, in addition to the configuration of the input circuit 1 shown in fig. 1 according to the first embodiment. That is, an N-type transistor N2 is provided in parallel with the P-type transistor P1 of the pull-up circuit 21. The N-type transistor N2 has a drain connected to the power supply VDD, a source connected to the node a, and a gate connected to the input terminal PAD.

The operation of the input circuit 5 of fig. 11 is the same as the operation of the input circuit 1 of fig. 1. However, when a rising signal having a voltage higher than the power supply voltage VDD is input to the input terminal PAD (when the input signal changes from low to high), the N-type transistor N2 is turned on. This assists the voltage at the node a to rise.

Fig. 12 shows another circuit configuration example of the input circuit according to the fifth embodiment. The input circuit 5A shown in fig. 12 includes an N-type transistor N2 provided between the power supply VDD and the node a, in addition to the configuration of the input circuit 4A shown in fig. 9 according to the fourth embodiment. That is, an N-type transistor N2 is provided in parallel with the P-type transistors P1, P2, and P3 of the pull-up circuit 24A. The N-type transistor N2 has a drain connected to the power supply VDD, a source connected to the node a, and a gate connected to the input terminal PAD.

The operation of the input circuit 5A of fig. 12 is the same as the operation of the input circuit 4A of fig. 9. However, when a rising signal having a voltage higher than the power supply voltage VDD is input to the input terminal PAD (when the input signal changes from low to high), the N-type transistor N2 is turned on. This assists the voltage at the node a to rise.

In the other configurations of the input circuit shown in the first to fourth embodiments, the N-type transistor N2 may be added in the same manner as in the configurations of fig. 11 and 12.

(sixth embodiment)

With recent power saving demands, a system of turning on/off the power of a semiconductor integrated circuit as needed is generally adopted. However, in the input circuit 1 shown in fig. 1, when the power supply is off, that is, VDD is 0V, it is not possible to allow a high-voltage signal to be received at the input terminal PAD. That is, if the drain-gate withstand voltage of the N-type transistor N1 is 1.8V, when the input terminal PAD receives an input signal of 3.3V when VDD is 0V, the drain-gate voltage of the N-type transistor N1 becomes 3.3V and exceeds the drain-gate withstand voltage.

In contrast, the present embodiment provides an input circuit that can turn off the power supply, that is, can set VDD to 0V, without depending on a signal received by the input terminal PAD.

Fig. 13 shows a circuit configuration of an input circuit according to a sixth embodiment. The basic configuration of the input circuit 6 shown in fig. 13 is the same as that of the input circuit 1 shown in fig. 1. However, the gate of the N-type transistor N1 and the drain of the P-type transistor P1 in the pull-up circuit 26 are not connected to the power supply VDD, but to the node d. The node d is connected to the input terminal PAD via the voltage conversion circuit 61. The voltage conversion circuit 61 outputs the power supply voltage VDD to the node d when the power supply VDD is turned on, and divides the voltage of the input terminal PAD and outputs the divided voltage to the node d when the power supply VDD is turned off.

Fig. 14(a) shows an example of the circuit configuration of the voltage conversion circuit 61, and fig. 14(b) shows the relationship between the input and output voltages of the voltage conversion circuit 61. In the voltage conversion circuit 61, when the power supply is turned on (VDD ═ 1.8V), the N-type transistor N61 is turned on, and thus the gate voltage of the P-type transistor P63 becomes 0V, whereby the P-type transistor P63 is turned on. As a result, the voltage VDD is output to the node d regardless of the signal received at the input terminal PAD. On the other hand, it is assumed that when the power supply is off (VDD ═ 0V), a high signal (3.3V) is supplied to the input terminal PAD. Since the gate voltage is 0V, both P-type transistors P61 and P62 are turned on. Therefore, 3.3/2V, which is a voltage divided by the resistors R connected in series, is output to the node d via the transistors P61 and P62. The configuration of the voltage conversion circuit 61 shown in fig. 14(a) is an example, and is not limited to this.

The input circuit 6 of fig. 13 operates as follows. When the power supply is turned on (VDD is 1.8V), the voltage conversion circuit 61 operates to output the power supply voltage VDD to the node d. Therefore, the input circuit 6 of fig. 13 operates in the same manner as the input circuit 1 of fig. 1.

On the other hand, when the power supply is turned off (VDD is 0V), if a high signal (3.3V) is supplied to the input terminal PAD, the voltage of the node d becomes 3.3/2V by the operation of the voltage conversion circuit 61. At this time, the N-type transistor N1 is turned on. The voltage of the node a drops from the voltage of the input terminal PAD of 3.3V due to the pinch-off characteristic of the N-type transistor N1, and does not exceed the voltage of the node d. When VDD is 0V, the voltage at the node c becomes almost 0V, the P-type transistor P1 is turned on, and the node a and the node d are turned on. As a result, the voltage at the node a becomes 3.3/2V.

In this way, since the gate of the N-type transistor N1 is not connected to the power supply VDD but connected to the node d, the drain-gate voltage of the N-type transistor N1 does not exceed the drain-gate withstand voltage even when a high signal is supplied to the input terminal PAD when the power supply is turned off.

In addition, since the drain of the P-type transistor P1 is not connected to VDD but to the node d, an unnecessary inflow current is not generated from the input terminal PAD even if a high signal is supplied to the input terminal PAD when the power supply is turned off. That is, if the drain of the P-type transistor P1 is connected to the power supply VDD, when a high signal is supplied to the input terminal PAD when the power supply is turned off, a current flows from the input terminal PAD along a path of the N-type transistor N1 → the node a → the P-type transistor P1 → VDD. In the present embodiment, this problem is avoided.

Further, since the reduced voltage is supplied to the node a, the voltage does not exceed the withstand voltage of the transistor.

Therefore, according to the present embodiment, in the input circuit 6, the power supply can be turned off without causing deterioration or damage of the transistor and without generating an unnecessary inflow current.

Here, the case where the present embodiment is applied to the first embodiment is described as an example, but the present embodiment can be applied to the other embodiments described above. That is, the gate of the N-type transistor N1 and the drain of the P-type transistor P1 in the pull-up circuit 22 and the like may be connected to a node d, which is connected to the input terminal PAD via the voltage conversion circuit 61. In the input circuit 5 shown in fig. 11 and the input circuit 5A shown in fig. 12, the drain of the N-type transistor N2 may be connected to the node d.

(seventh embodiment)

Fig. 15 shows a circuit configuration of an input circuit according to a seventh embodiment. The basic configuration of the input circuit 7 shown in fig. 15 is the same as that of the input circuit 6 shown in fig. 13. However, in the pull-up circuit 27, a P-type transistor P5 and a transmission gate switch SW including a P-type transistor and an N-type transistor connected in parallel are added.

The P-type transistor P5 is connected between a node c serving as the gate of the P-type transistor P1 and a node a serving as the source of the P-type transistor P1. The gate of the P-type transistor P5 is connected to the power supply VDD. The pass-gate switch SW is connected between the node c and the output node of the NAND gate 31. The gate of the N-type transistor constituting the transmission gate switch SW is connected to the power supply VDD, and the gate of the P-type transistor constituting the transmission gate switch SW is connected to the node a.

The input circuit 7 shown in fig. 15 operates as follows. When the power supply is turned on (VDD ═ 1.8V), the P-type transistor P5 is turned off, and the transmission gate switch SW is turned on because its N-type transistor is turned on. Therefore, the input circuit 7 of fig. 15 operates in the same manner as the input circuit 6 of fig. 13.

On the other hand, when the power supply is turned off (VDD ═ 0V), if a high signal (3.3V) is supplied to the input terminal PAD, the P-type transistor P5 is turned on, and thus conduction is established between the node a and the node c, and the voltages at the nodes a and c are the same as those at the node d. Therefore, the P-type transistor P1 is turned off. In the transmission gate switch SW, the N-type transistor is turned off by the gate voltage of 0V, and the P-type transistor is turned off by the voltage of the drain (node c) being equal to the voltage of the gate (node a), so that the transmission gate switch SW is turned off. As a result, the node c is cut off from the output node of the NAND gate 31, and thus unnecessary current flowing from the P-type transistor P5 through the NAND gate 31 can be prevented from occurring.

Therefore, according to the present embodiment, in the input circuit 7, the power supply can be turned off without causing deterioration or damage of the transistor and without generating an unnecessary inflow current.

Here, the case where the present embodiment is applied to the circuit configuration of the first embodiment is described as an example, but the present embodiment can be applied to the circuit configurations of the other embodiments described above. That is, in the pull-up circuit, the P-type transistor P5 may be connected between the node a and any one of the gates of the P-type transistors P1, P2, and P3, and the transmission gate switch SW may be provided between the gate and the node of the previous-stage circuit to which a signal is transmitted.

For example, in the input circuit 2 of fig. 3, the P-type transistor P5 may be connected between the gate of the P-type transistor P1 and the node a, and the transmission gate switch SW may be provided between the gate of the P-type transistor P1 and the output node of the inverter 32. Alternatively, the P-type transistor P5 may be connected between the gate of the P-type transistor P2 and the node a, and the transmission gate switch SW may be provided between the gate of the P-type transistor P2 and the input buffer 12.

The present disclosure is not limited to the configurations shown in the above embodiments, and those skilled in the art can make many modifications based on the technical idea of the present disclosure. In addition, the respective components in the plurality of embodiments may be arbitrarily combined without departing from the scope of the present disclosure.

Industrial applicability-

In the present disclosure, in the input circuit, the delay time in the input buffer circuit can be shortened, and the error generated in the pulse width of the output signal can be suppressed, and therefore, for example, it is effective in realizing high speed and performance improvement of the LSI.