阅读说明：本技术 存储器件及其操作方法 (Memory device and method of operating the same ) 是由 谢维哲 许育豪 张智皓 李政宏 于 2021-04-29 设计创作，主要内容包括：一种存储器件包括：多个存储器单元；字线,连接到多个存储器单元中的一个,字线被配置为提供第一WL脉冲,第一WL脉冲具有限定第一WL脉冲的脉冲宽度的上升沿和下降沿；第一跟踪WL,形成为与存储器单元相邻,第一跟踪WL被配置为通过物理地或可操作地耦合到被配置为将逻辑状态写入存储器单元的位线(BL)而提供具有上升沿的第二WL脉冲,上升沿具有减小的斜率；以及第一跟踪BL,被配置为模拟BL,第一跟踪BL耦合到第一跟踪WL,使得基于第二WL脉冲的上升沿的减小的斜率而增加第一WL脉冲的脉冲宽度。本发明的实施例还涉及操作存储器件的方法。(A memory device comprising: a plurality of memory cells; a word line connected to one of the plurality of memory cells, the word line configured to provide a first WL pulse having a rising edge and a falling edge defining a pulse width of the first WL pulse; a first tracking WL formed adjacent to the memory cell, the first tracking WL configured to provide a second WL pulse having a rising edge with a decreasing slope by being physically or operably coupled to a Bit Line (BL) configured to write a logic state to the memory cell; and a first tracking BL configured to simulate the BL, the first tracking BL coupled to the first tracking WL such that a pulse width of the first WL pulse is increased based on a decreasing slope of a rising edge of the second WL pulse. Embodiments of the present invention also relate to methods of operating memory devices.)

1. A memory device, comprising:

a memory cell;

a Word Line (WL) connected to the memory cell, the WL configured to present a first WL pulse to allow writing of the memory cell to a logic state within the first WL pulse, the first WL pulse having a rising edge and a falling edge;

a Bit Line (BL) connected to the memory cell, the BL configured to write the logic state to the memory cell;

a first tracking WL configured to emulate the WL to provide a second WL pulse having a rising edge with a disturbed slope; and

a first tracking BL configured to simulate the BL, the first tracking BL coupled to the first tracking WL such that the falling edge of the first WL pulse is extended based on the disturbed slope of the rising edge of the second WL pulse.

2. The memory device of claim 1, wherein a voltage of the first tracking BL is configured to transition to a low logic state in response to the rising edge of the second WL pulse, and wherein the falling edge of the first WL pulse occurs in response to the voltage of the tracking BL falling by a predetermined voltage.

3. The memory device of claim 2, wherein the disturbed slope of the rising edge of the second WL pulse causes the voltage of the first tracking BL to also assume a disturbed slope while transitioning to the low logic state.

4. The memory device of claim 1, wherein the first tracking WL comprises at least one tracking WL bit cell comprising a first transistor and a second transistor, respective gates of the first transistor and the second transistor being connected to the first tracking WL, respective sources of the first transistor and the second transistor being floated, one of the respective drains of the first transistor and the second transistor being directly connected to the BL.

5. The memory device of claim 1, wherein the first tracking WL comprises at least one tracking WL bit cell comprising a first transistor, a second transistor, a third transistor, and a fourth transistor, respective gates of the first and second transistors being connected to the first tracking WL, respective sources of the first and second transistors being floated by the third and fourth transistors, the third and fourth transistors being gate-connected and source-grounded, one of respective drains of the first and second transistors being directly connected to the BL.

6. The memory device of claim 1, further comprising:

a second tracking BL configured to simulate the BL; and

a transistor having a gate connected to the first tracking WL, a drain connected to the second tracking BL, and a source connected to ground, the transistor configured to reduce a voltage of the second tracking BL, thereby causing the second WL pulse to assume the rising edge with the disturbed slope.

7. The memory device of claim 6, further comprising:

a capacitor coupled between the second tracking BL and the first tracking WL.

8. The memory device of claim 1, further comprising:

a second tracking BL configured to simulate the BL; and

a second tracking WL connected to the second tracking BL and close-coupled to the first tracking WL, the second tracking WL configured to assume a logic state that is inverse to a logic state of the first tracking WL to cause the second WL pulse to assume the rising edge having the disturbed slope.

9. A memory device, comprising:

a memory array comprising a plurality of memory cells;

a Word Line (WL) connected to one of the plurality of memory cells, the WL configured to provide a first WL pulse having rising and falling edges defining a pulse width of the first WL pulse;

a first tracking WL formed adjacent to the memory array, the first tracking WL configured to provide a second WL pulse having a rising edge with a decreasing slope by being physically or operably coupled to a Bit Line (BL) configured to write a logic state to the memory cell; and

a first tracking BL configured to simulate the BL, the first tracking BL coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.

10. A method of operating a memory device, comprising:

transitioning a Word Line (WL) coupled to the memory cell from a first logic state to a second logic state;

transitioning a tracking WL, which simulates the WL, from the first logic state to the second logic state with a disturbed slope by at least one of: (i) coupling the tracking WL directly to a Bit Line (BL) of the memory cell, or (ii) coupling the tracking WL to a first tracking BL that emulates the BL; and

extending a timing of transitioning the WL from the second logic state to the first logic state by discharging a second tracking BL simulating the BL according to the disturbed slope.

Technical Field

Embodiments of the present invention relate to a memory device and a method of operating the same.

Background

Many modern electronic devices and systems include tremendous computing power for controlling and managing various functions and useful applications. The computational power of these modern devices and systems is typically provided by one or more processor "cores". These processor cores operate as digital computers, typically retrieving executable instructions from memory, performing arithmetic and logical operations on digital data retrieved from memory, and storing the results of those operations in memory. Other input and output functions for acquiring and outputting data processed by the processor core are performed as appropriate. Large-scale solid-state memory capacities are typically implemented in the electronic circuits used in these systems in view of the large amounts of digital data typically involved in performing the complex functions of these modern devices.

Static Random Access Memory (SRAM) has become the memory technology of choice for many of the solid state data storage requirements in these modern power efficient electronic systems. As is fundamental in the art, SRAM cells store content "statically" because the stored data state remains latched in each cell as long as power is applied to the memory.

Disclosure of Invention

According to an aspect of an embodiment of the present invention, there is provided a memory device including: a memory cell; a Word Line (WL) connected to the memory cell, the WL configured to present a first WL pulse to allow writing the memory cell to a logic state within the first WL pulse, the first WL pulse having a rising edge and a falling edge; a Bit Line (BL) connected to the memory cell, the BL configured to write a logic state to the memory cell; a first tracking WL configured to emulate a WL to provide a second WL pulse having a rising edge with a disturbed slope; and a first tracking BL configured to simulate the BL, the first tracking BL coupled to the first tracking WL such that a falling edge of the first WL pulse is extended based on a disturbed slope of a rising edge of the second WL pulse.

According to another aspect of an embodiment of the present invention, there is provided a memory device including: a memory array comprising a plurality of memory cells; a Word Line (WL) connected to one of the plurality of memory cells, the WL configured to provide a first WL pulse having a rising edge and a falling edge defining a pulse width of the first WL pulse; a first tracking WL formed adjacent to the memory array, the first tracking WL configured to provide a second WL pulse having a rising edge with a decreasing slope by being physically or operably coupled to a Bit Line (BL) configured to write a logic state to the memory cell; and a first tracking BL configured to simulate the BL, the first tracking BL coupled to the first tracking WL such that a pulse width of the first WL pulse is increased based on a decreasing slope of a rising edge of the second WL pulse.

According to still another aspect of an embodiment of the present invention, there is provided a method of operating a memory device, including: transitioning a Word Line (WL) coupled to the memory cell from a first logic state to a second logic state; transitioning a tracking WL of the simulated WL from the first logic state to the second logic state with the disturbed slope by at least one of: (i) coupling a tracking WL directly to a Bit Line (BL) of a memory cell, or (ii) coupling a tracking WL to a first tracking BL of a simulated BL; and extending the timing of the transition of the WL from the second logic state to the first logic state by discharging a second tracking BL simulating the BL according to the disturbed slope.

Drawings

Aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 illustrates a block diagram of an example of a large scale integrated circuit, in accordance with some embodiments.

FIG. 2 illustrates a block diagram of a memory device of the integrated circuit of FIG. 1 including a tracking Word Line (WL) circuit and a tracking Bit Line (BL) circuit, in accordance with some embodiments.

Fig. 3 illustrates an example circuit diagram of the tracking WL circuit and an example schematic diagram of the tracking BL circuit of fig. 2, in accordance with some embodiments.

Fig. 4 illustrates another example circuit diagram of the tracking WL circuit and another example schematic diagram of the tracking BL circuit of fig. 2 in accordance with some embodiments.

Fig. 5 illustrates yet another example circuit diagram of the tracking WL circuit and yet another example schematic diagram of the tracking BL circuit of fig. 2 in accordance with some embodiments.

Fig. 6 illustrates yet another example circuit diagram of the tracking WL circuit and yet another example schematic diagram of the tracking BL circuit of fig. 2 in accordance with some embodiments.

Fig. 7A illustrates yet another example circuit diagram of the tracking WL circuit and yet another example schematic diagram of the tracking BL circuit of fig. 2 according to some embodiments.

Fig. 7B illustrates yet another example circuit diagram of the tracking WL circuit and yet another example schematic diagram of the tracking BL circuit of fig. 2, in accordance with some embodiments.

Fig. 7C illustrates yet another example circuit diagram of the tracking WL circuit and yet another example schematic diagram of the tracking BL circuit of fig. 2, in accordance with some embodiments.

Fig. 8 illustrates an example circuit diagram of the tracking BL circuit of fig. 2 in accordance with some embodiments.

FIG. 9 illustrates example signals respectively present on a WL of a memory array, a BL/BBL of a memory array, a tracking WL of a tracking WL circuit, and a tracking BL of a tracking BL circuit, in accordance with some embodiments.

FIG. 10 illustrates a graph comparing respective write margins of different memory devices, in accordance with some embodiments.

Fig. 11 illustrates an example implementation of a capacitor coupled between two metal lines, according to some embodiments.

Fig. 12 illustrates an example implementation of a capacitor coupled between two metal lines, according to some embodiments.

FIG. 13 illustrates yet another example implementation of a capacitor coupled between two metal lines, according to some embodiments.

FIG. 14 illustrates yet another example implementation of a capacitor coupled between two metal lines according to some embodiments.

FIG. 15 illustrates yet another example implementation of a capacitor coupled between two metal lines according to some embodiments.

16A, 16B, and 16C illustrate yet another example implementation of a capacitor coupled between two metal lines according to some embodiments.

FIG. 17 illustrates a flow diagram of an example method of operating a memory device to restore wordline pulse widths, in accordance with various embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different components of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming the first component over or on the second component may include the following embodiments: embodiments in which the first and second components are formed in direct contact may also be included, and embodiments in which additional components are formed between the first and second components, such that the first and second components may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatial relational terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein to describe one element or component's relationship to another element or component as illustrated for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

A Static Random Access Memory (SRAM) is a volatile semiconductor memory that stores data bits using bi-stable circuits that do not require refreshing. SRAM devices typically include one or more memory arrays, where each array includes a plurality of SRAM cells. An SRAM cell is generally referred to as a memory cell (bitcell) because it stores one bit of information represented by the logic states of two cross-coupled inverters. Each memory array includes a plurality of bit cells arranged in rows and columns. Each bit cell in a memory array typically includes connections to a supply voltage and a reference voltage. Logic signals on the bit lines control reading and writing to the bit cells, and the word lines control the connection of the bit lines to the inverters, otherwise the inverters float. The word line may be coupled to a plurality of bit cells along a row of the memory array, providing different word lines for different rows.

Typically, when a bit cell is selected (e.g., to be read or written), a word line signal is provided to assert a corresponding word line of the bit cell. For example, a write operation may be performed on a bitcell during a period of time in which the wordline signal remains in a high logic state (commonly referred to as a "wordline pulse width") while the corresponding wordline is asserted. While writing the selected bit cell, other bit cells coupled to the asserted word line may also be activated. Even if a write operation is not performed on such unselected bit cells, a dummy read operation may still be performed on each of the unselected bit cells (e.g., reading the bit cells through one or more respective bit lines but not coupled to a sense amplifier). As such, the bit lines of the unselected bit cells may be capacitively coupled to the word line, which may degrade the word line signal. For example, such bitline-wordline capacitive coupling may reduce the slope of the rising edge of the wordline signal, which may shrink the wordline pulse width. Such reduced word line pulse widths may adversely affect the performance (e.g., write yield) of the memory device.

To address this problem, the prior art has proposed using one or more tracking schemes to simulate the write time (and/or read time) of a bit cell in order to recover (e.g., extend) the word line pulse width. However, when the respective sizes of the memory arrays of the memory device span a relatively wide range, using existing tracking schemes to solve the problem may not be entirely satisfactory. For example, in a memory device including a plurality of memory arrays, the problem of bit line-word line capacitive coupling may be exaggerated in memory arrays having a relatively large size (e.g., having a relatively large number of rows and/or a relatively large number of columns) and memory arrays having a relatively small size (e.g., having a relatively small number of rows). In this regard, two or more different tracking schemes are typically required to accommodate different sized memory arrays, which may disadvantageously increase design complexity and, in turn, cost/power consumption/area.

Various embodiments of a memory device are provided that include a tracking Word Line (WL) circuit and a tracking Bit Line (BL) circuit that directly emulate respective BL-WL capacitive couplings of each of one or more memory arrays of the memory device. In this manner, the memory device can use a tracking scheme to recover respective word line pulse widths for memory arrays of such different sizes, even though the respective sizes of the memory arrays may differ significantly from one another. In some embodiments, the tracking WL circuit may intentionally (and directly) simulate BL-WL capacitive coupling. For example, the track WL circuitry may simulate BL-WL capacitive coupling by coupling itself to the BL of each of the memory arrays. In another example, the tracking WL circuitry may simulate BL-WL capacitive coupling by coupling itself to the loaded replica BL of the BL simulating each of the memory arrays. In this way, the tracking WL circuit can accurately "track" the size of each of the memory arrays. By coupling the tracking WL circuit to the tracking BL circuit to reflect the tracked BL-WL capacitive coupling, the discharge time of the tracking BL circuit can be advantageously extended, which can automatically restore (e.g., extend) the WL pulse width. In this manner, even if a BL-WL capacitive coupling problem arises, the WL pulse width of each of the differently sized memory arrays may be accurately recovered according to the respective size.

Fig. 1 shows a block diagram of an example of a large scale integrated circuit 100 in the form of a so-called "system on a chip" ("SoC") as used in various electronic systems. Integrated circuit 100 may be a single-chip integrated circuit implementing an entire computer architecture. Thus, in this example, integrated circuit 100 includes a central processing unit connected to microprocessor 102 of system bus SBUS. Various memory resources, including Random Access Memory (RAM)104 and Read Only Memory (ROM)106, reside on the system bus SBUS and are therefore accessible to the microprocessor 102. ROM 106 may be implemented as mask-programmed ROM, electrically erasable programmable read-only memory (EEPROM) such as a "flash" EEPROM, or the like, and is typically used as a program memory to store program instructions that are executable by microprocessor 102, as well as RAM104 as data memory. In some cases, program instructions may reside in RAM104 for invocation and execution by microprocessor 102. The cache memory 108 (e.g., level 1, level 2, and level 3 caches, each typically implemented as SRAM) provides another source of memory and is itself resident in the microprocessor 102, and therefore does not require bus access. In a general sense, other system functions are shown in integrated circuit 100 through system control 110 and input/output interface 112.

It should be understood that integrated circuit 100 may include additional or alternative functionality to those shown in fig. 1, or may have its functionality arranged according to an architecture different from that shown in fig. 1. The architecture and functionality of integrated circuit 100 is thus provided by way of example only and is not intended to limit the scope of the present invention.

Fig. 2 shows a block diagram of a configuration of a RAM104 of an integrated circuit 100 (e.g., a memory device) including a tracking WL circuit and a tracking BL circuit as disclosed herein. Of course, other storage resources, such as cache 108, may be implemented using similar constructs. In some other embodiments, RAM104 may correspond to a stand-alone memory integrated circuit (i.e., rather than an embedded memory as shown in FIG. 1).

As shown in fig. 2, RAM104 includes a memory array 200, a tracking BL circuit 202, and a tracking WL circuit 204 operatively coupled to each other. Although memory array 200, tracking BL circuit 202, and tracking WL circuit 204 are shown as discrete elements (blocks) in the illustrated embodiment of fig. 1, at least two or more of memory array 200, tracking BL circuit 202, and tracking WL circuit 204 may be integrated into a single element while remaining within the scope of the present invention. It is believed that the illustrated embodiment of RAM104 in fig. 2 is simplified, and thus RAM104 may include one or more other blocks (or circuits) while remaining within the scope of the present invention. For example, the RAM104 may include a row (WL) decoder, a row (WL) driver, a column (BL) driver, one or more input/output circuits (sense amplifiers), and so forth.

In some embodiments, memory array 200 may comprise a Static Random Access Memory (SRAM) array. However, any of a variety of memory arrays (e.g., Resistive Random Access Memory (RRAM) arrays, Dynamic Random Access Memory (DRAM) arrays, Magnetoresistive Random Access Memory (MRAM) arrays, etc.) may be implemented as the memory array 200 while remaining within the scope of the present invention.

Memory array 200 includes a plurality of memory cells arranged in a column-row configuration. For example, the memory array 200 includes a plurality of memory cells (e.g., 200-1, 200-2, 200-3, 200-4, 200-5, 200-6, 200-7, 200-8, 200-9, etc.), where each column has a Bit Line (BL) and a Bit Bar Line (BBL), and each row has a Word Line (WL). The BL and BBL of each column are respectively coupled to a plurality of memory cells disposed in that column, and each memory cell in that column is arranged on a different row and coupled to a corresponding (different) WL. That is, each memory cell of memory array 200 is coupled to a BL of a column of memory array 200, a BBL of a column of memory array 200, and a WL of a row of memory array 200. In some embodiments, BL and BBL are arranged vertically in parallel, and WL is arranged horizontally (i.e., perpendicular to BL and BBL) in parallel.

Still referring to FIG. 2, in more detail, for purposes of illustration, nine memory cells (e.g., 200-1, 200-2, 200-3, 200-4, 200-5, 200-6, 200-7, 200-8, 200-9) are shown in memory array 200. Based on the above description, columns "A", "B", and "C" and rows "a", "B", and "C" are thus shown in memory array 200. Memory cells 200-1, 200-4, and 200-7 are arranged along column A; memory cells 200-2, 200-5, and 200-8 are arranged along column B; memory cells 200-3, 200-6, and 200-9 are arranged along column C; memory cells 200-1, 200-2, and 200-3 are arranged along row a; memory cells 200-4, 200-5, and 200-6 are arranged along row b; and memory cells 200-7, 200-8, and 200-9 are arranged along row c. Further, memory cells 200-1, 200-4, and 200-7 arranged along column A are coupled to a respective BL "BL _ A" of column A, and are each coupled to a WL of a respective row: WL _ a, WL _ b, and WL _ c; memory cells 200-2, 200-5, and 200-8 arranged along column B are all coupled to a respective BL "BL _ B" of column B, and are each coupled to a WL of a respective row: WL _ a, WL _ b, and WL _ c; memory cells 200-3, 200-6, and 200-9 arranged along column C are all coupled to a respective BL "BL _ C" of column C, and are each coupled to a WL of a respective row: WL _ a, WL _ b, and WL _ c.

Each memory cell of memory array 200 is configured to store/represent a data bit or data. Such a data bit may be repeatedly read (i.e., a read operation) from or written (i.e., a write operation) to each bitcell having a corresponding logic state (i.e., a logic 1 or a logic 0). Although the exemplary embodiment of FIG. 2 shows nine memory cells in memory array 200, any desired number of memory cells may be included in memory array 200 while remaining within the scope of the present invention. As such, the number of columns and the number of rows (and corresponding BL/BBL and WL) may be adjusted according to the number of memory cells in the memory array 200. Furthermore, for simplicity, only the BL is shown in fig. 2 along the corresponding column of the memory array 200, rather than both BL and BBL.

According to various embodiments of the invention, tracking WL circuit 204 may be directly coupled (e.g., physically connected) or operably coupled (e.g., non-physically connected but communicatively coupled) to memory array 200 (e.g., one or more of the BL/BBLs of memory array 200) in order to simulate the effect of capacitive coupling between WLs and BLs in memory array 200. By simulating the effects, tracking WL circuit 204 may generate a tracking WL signal that simulates the WL signal actually present on one or more of the WLs of memory array 200. In response, tracking BL circuit 202, which includes several tracking BL cells configured to simulate an electrical signal path propagating across memory array 200, may use such tracking WL signals to recover (e.g., lengthen) the pulse width of the actual WL.

Various embodiments of tracking WL circuit 204 and tracking BL circuit 202 will be discussed below with reference to fig. 3, 4, 5, 6, 7A, 7B, and 7C. It is contemplated that RAM104 may include a plurality of memory arrays, each of which is characterized by a respective size (e.g., a respective number of rows and/or a respective number of columns). In some embodiments, each of the memory arrays may correspond to a respective tracking WL circuit and a respective tracking BL circuit to accurately recover the respective WL signal. In some other embodiments, at least some of the memory arrays may correspond to common tracking WL circuitry and/or common tracking BL circuitry.

Referring to fig. 3, a circuit diagram of an example tracking WL circuit 300 and a circuit diagram of an example tracking BL circuit 350 are shown, respectively, in accordance with various embodiments. The tracking WL circuit 300 and the tracking BL circuit 350 may be respective examples of the tracking WL circuit 204 and the tracking BL circuit 202 of fig. 2.

As shown in fig. 3, tracking WL circuit 300 includes a tracking WL302 and several tracking WL cells (e.g., 304A, 304B, 304C, etc.). At least a portion of tracking WL302 may extend from one end of memory array 200 to the other end of the memory array to simulate a WL (e.g., WL _ a, WL _ b, WL _ c, etc.) of memory array 200. Tracking WL cells 304A-C are commonly coupled to tracking WL 302. Further, if desired, one or more delay elements (e.g., delay lines, inverters, etc.) may be coupled to tracking WL302 to create an RC delay on tracking WL 302. For example, one or more delay elements may be inserted into portion 302A of tracking WL302 and/or portion 302B of tracking WL 302.

Tracking WL cells 304A-C may correspond to columns of memory array 200, respectively. For example, tracking WL cell 304A corresponds to column a of memory array 200; tracking WL cell 304B corresponds to column B of memory array 200; and tracking WL cell 304C corresponds to column C of memory array 200. Specifically, each of the tracking WL cells 304A-C may be directly coupled to the BL (and BBL) of the corresponding column. For example, tracking WL cell 304A is directly coupled to BL _ a (and BBL _ a) of column a of memory array 200; tracking WL cell 304B is directly coupled to BL _ B (and BBL _ B) of column B of memory array 200; and tracking WL cell 304C is directly coupled to BL _ C (and BBL _ C) of column C of memory array 200. In this manner, the tracking WL circuit 300 may simulate the effects of BL-WL coupling that may occur in the memory array 200, which will be discussed in more detail below with reference to FIG. 9.

Each of the tracking WL cells 304A-C may include one or more transistors, the respective sources of which are floated. Using tracking WL cell 304A as a representative example, tracking WL cell 304A includes two transistors 306 and 308. In some embodiments, transistors 306 and 308 each include, but are not limited to, an n-type metal oxide semiconductor field effect transistor (nMOSFET). However, each of the transistors 306 and 308 may comprise any of various other types of transistors (e.g., p-type metal oxide semiconductor field effect transistors (pmosfets), Bipolar Junction Transistors (BJTs), High Electron Mobility Field Effect Transistors (HEMFETs), etc.) while remaining within the scope of the present invention. Specifically, in fig. 3, the respective gates of transistors 306 and 308 are connected to tracking WL 302; the drain of transistor 306 is connected to BL _ A; the drain of transistor 308 is connected to BBL _ A; and the respective sources of transistors 306 and 308 are floating. In this manner, transistors 306 and 308 may simulate capacitive coupling to tracking WL302 between BL (e.g., BL _ A, BBL _ a) and WL (e.g., WL _ a, WL _ b, WL _ c) by coupling their drains to their gates, respectively, to BL _ a and BBL _ a, which transistors (because their sources are floating) are commonly coupled to tracking WL302 while not affecting normal write operations performed in memory array 200.

The tracking BL circuit 350 includes a tracking BL 352 and several tracking BL units (e.g., 354a, 354b, 354c, etc.). At least a portion of tracking BL 352 may extend from one end of memory array 200 to another end of the memory array to simulate the BL/BBL of memory array 200 (e.g., BL _ A, BL _ B, BL _ C, etc.). Each of the tracking BL cells 354a-c is coupled to a tracking WL302, respectively. Tracking BL units 354a-c are commonly coupled to tracking BL 352. Tracking BL cells 354a-c may correspond to (e.g., be aligned with or coupled to) rows of memory array 200, respectively. For example, tracking BL cell 354a corresponds to row a of memory array 200; tracking BL cell 354b corresponds to row b of memory array 200; and tracking BL cell 354c corresponds to row c of memory array 200. Each of the tracking BL units 354a-c is substantially similar to a memory cell (e.g., 200-1, 200-2, etc.) of the memory array 200 and is configured to store a logic 0 to emulate the BL/BBL 200 of the memory array. For example, when the memory cells of the memory array 200 are implemented as 6-transistor SRAM memory cells, the tracking BL cells 354a-c may each be 6-transistor SRMA memory cells, but configured to permanently store a logic 0. However, it is contemplated that each of the tracking BL units 354a-c may be implemented differently from the memory cells of the memory array 200 while remaining within the scope of the present invention. Examples of tracking BL units 354a-c are discussed in more detail below with reference to fig. 8.

Referring to fig. 4, a circuit diagram of an example tracking WL circuit 400 and a circuit diagram of an example tracking BL circuit 450 are shown, respectively, in accordance with various embodiments. The tracking WL circuit 400 and the tracking BL circuit 450 may be respective examples of the tracking WL circuit 204 and the tracking BL circuit 202 of fig. 2.

As shown in fig. 4, the tracking WL circuit 400 includes a tracking WL 402 and several tracking WL cells (e.g., 404A, 404B, 404C, etc.). At least a portion of tracking WL 402 may extend from one end of memory array 200 to the other end of the memory array to simulate a WL (e.g., WL _ a, WL _ b, WL _ c, etc.) of memory array 200. Tracking WL cells 404A-C are commonly coupled to tracking WL 402. Further, if desired, one or more delay elements (e.g., delay lines, inverters, etc.) may be coupled to the tracking WL 402 to create an RC delay on the tracking WL 402. For example, one or more delay elements may be inserted into portion 402A of tracking WL 402 and/or portion 402B of tracking WL 402.

Tracking WL cells 404A-C may correspond to columns of memory array 200, respectively. For example, tracking WL cell 404A corresponds to column a of memory array 200; tracking WL cell 404B corresponds to column B of memory array 200; and tracking WL cell 404C corresponds to column C of memory array 200. Specifically, each of the tracking WL cells 404A-C may be directly coupled to the BL (and BBL) of the corresponding column. For example, tracking WL cell 404A is directly coupled to BL _ a (and BBL _ a) of column a of memory array 200; tracking WL cell 404B is directly coupled to BL _ B (and BBL _ B) of column B of memory array 200; and tracking WL cell 404C is directly coupled to BL _ C (and BBL _ C) of column C of memory array 200. In this manner, the tracking WL circuit 400 may simulate the effects of BL-WL coupling that may occur in the memory array 200, which will be discussed in more detail below with reference to FIG. 9.

Each of the tracking WL cells 404A-C may include one or more transistors, the respective sources of which are floated. Using tracking WL cell 404A as a representative example, tracking WL cell 404A includes four transistors 406, 408, 410 and 412. In some embodiments, transistors 406-412 each include, but are not limited to, an n-type metal oxide semiconductor field effect transistor (nMOSFET). However, each of the transistors 406-412 may comprise any of various other types of transistors (e.g., any of a p-type metal oxide semiconductor field effect transistor (pMOSFET), a Bipolar Junction Transistor (BJT), a High Electron Mobility Field Effect Transistor (HEMFET), etc.) while remaining within the scope of the present invention. Specifically, in fig. 4, the respective gates of transistors 406 and 408 are connected to tracking WL 402; the drain of transistor 406 is connected to BL _ A; the drain of transistor 408 is connected to BBL _ a; a source of transistor 406 is connected to a drain of transistor 410; a source of transistor 408 is connected to a drain of transistor 412; the respective gates of transistors 410 and 412 are grounded; and the respective sources of transistors 410 and 412 are also connected to ground. Effectively, transistors 406 and 408 may float at their respective sources. In this manner, transistors 406 and 408 can simulate capacitive coupling to tracking WL 402 between BL (e.g., BL _ A, BBL _ a) and WL (e.g., WL _ a, WL _ b, WL _ c) by coupling their drains to their gates, respectively, to BL _ a and BBL _ a, which transistors (because their sources are floating) are commonly coupled to tracking WL 402 while not affecting normal write operations performed in memory array 200.

The tracking BL circuit 450 includes a tracking BL 452 and several tracking BL units (e.g., 454a, 454b, 454c, etc.). Tracking BL 452 is similar to tracking BL 352 as shown in fig. 3; and each of the tracking BL units 454a-c is substantially similar to the tracking BL units 354 a-c. Accordingly, details of tracking BL 452 and tracking BL units 454a-c are discussed in further detail below with reference to FIG. 8.

Although tracking WL circuits 300 and 400 are shown in fig. 3 and 4 as separate components from memory array 200, in some other embodiments, tracking WL circuits 300 and 400 may be integrated into memory array 200, respectively. For example, each of the tracking WL circuits 300 and 400 may be formed as the memory array 200 on the same substrate (e.g., die), which may advantageously reduce the total area occupied by the ROM 104 and the length of the BL/BBL of the memory array 200.

Referring to fig. 5, a circuit diagram of an example tracking WL circuit 500 and a circuit diagram of an example tracking BL circuit 550 are shown, respectively, in accordance with various embodiments. The tracking WL circuit 500 and the tracking BL circuit 550 may be respective examples of the tracking WL circuit 204 and the tracking BL circuit 202 of fig. 2.

As shown in FIG. 5, the tracking WL circuit 500 includes a tracking WL 502, a transistor 504, a capacitor 506 and a transistor 508. Transistors 504 and 508 include, but are not limited to, pMOSFET and nMOSFET, respectively. However, transistors 504 and 508 may each comprise any of a variety of other types of transistors (e.g., pMOSFET, nMOSFET, Bipolar Junction Transistor (BJT), High Electron Mobility Field Effect Transistor (HEMFET), etc.), while remaining within the scope of the present invention. The capacitor 506 may include a Metal Oxide Semiconductor (MOS) capacitor, a Metal Insulator Metal (MIM) capacitor, or the like. Optionally, tracking WL circuit 500 may include several tracking WL cells (which may be substantially similar to tracking WL cells 304A-C and 404A-C shown in fig. 3 and 4, respectively) coupled to tracking WL 502. At least a portion of tracking WL 502 may extend from one end of memory array 200 to the other end of the memory array to simulate a WL (e.g., WL _ a, WL _ b, WL _ c, etc.) of memory array 200. Furthermore, if desired, one or more delay elements (e.g., delay lines, inverters, etc.) may be coupled to the tracking WL 502 to create an RC delay on the tracking WL 502. For example, one or more delay elements may be inserted into portion 502A of tracking WL 502 and/or portion 502B of tracking WL 502.

The tracking BL circuit 550 includes a tracking BL 552, a number of tracking BL units (e.g., 554a, 554b, 554c, etc.), and a replica tracking BL 556. Tracking BL 552 is similar to tracking BL 352 as shown in fig. 2; and each of tracking BL units 554a-c is substantially similar to tracking BL units 354 a-c. Accordingly, details of tracking BL 552 and tracking BL units 554a-c are discussed in further detail below with reference to FIG. 8. Unlike the example of fig. 3 and 4, the tracking BL circuit 550, as shown in fig. 5, additionally includes a replica tracking BL 556. According to some embodiments, replica tracking BL 556, without tracking BL cells coupled thereto, is configured to simulate one or more of the BL/BBLs of memory array 200 in order to allow tracking WL circuit 500 to simulate the effects of BL-WL coupling that may occur in memory array 200, which will be discussed in further detail below with reference to fig. 9.

Still referring to fig. 5, in more detail, one end (e.g., plate or terminal) of the capacitor 506 is connected to the replica track BL 556 at node X connected to the transistor 504, and the other end of the capacitor 506 is connected to the track WL 502 at node Y connected to the transistor 508. Specifically, the source of transistor 504 is connected to a power supply 505 (e.g., VDD), the gate of transistor 504 is controlled by a control signal 507, and the drain of transistor 504 is connected to a capacitor 506 at node X; and the drain of transistor 508 is connected to replica track BL 556, the gate of transistor 508 is connected to capacitor 506 at node Y, and the source of transistor 508 is connected to ground.

Referring to fig. 6, a circuit diagram of an example tracking WL circuit 600 and a circuit diagram of an example tracking BL circuit 650 are shown, respectively, in accordance with various embodiments. The tracking WL circuit 600 and the tracking BL circuit 650 may be respective examples of the tracking WL circuit 204 and the tracking BL circuit 202 of fig. 2.

As shown in fig. 6, tracking WL circuit 600 and tracking BL circuit 650 are substantially similar to tracking WL circuit 500 and tracking BL circuit 550, respectively, except that transistor 604, capacitor 606, and transistor 608 are coupled to tracking WL 602 at a further portion, e.g., 602C. Therefore, the tracking WL circuit 600 and the tracking BL circuit 650 are briefly described as follows. In the tracking WL circuit 600, one end (e.g., a plate or terminal) of a capacitor 606 is connected to a replica tracking BL 656 at a node X connected to a transistor 604, and the other end of the capacitor 606 is connected to a tracking WL 602 at a node Y connected to a transistor 608. Specifically, the source of transistor 604 is connected to a power supply 605 (e.g., VDD), the gate of transistor 604 is controlled by a control signal 607, and the drain of transistor 604 is connected to a capacitor 606 at node X; and the drain of transistor 608 is connected to replica track BL 656, the gate of transistor 608 is connected to capacitor 606 at node Y, and the source of transistor 608 is connected to ground. In the tracking BL circuit 650, the tracking BL circuit 650 includes a tracking BL 652, a number of tracking BL units (e.g., 654a, 654b, 654c, etc.), and a copy tracking BL 656. Copy tracking BL 656 is configured to emulate the BL/BBL of memory array 200, as will be discussed below.

Referring to fig. 7A, a circuit diagram of an example tracking WL circuit 700 and a circuit diagram of an example tracking BL circuit 750 are shown, respectively, in accordance with various embodiments. The tracking WL circuit 700 and the tracking BL circuit 750 may be respective examples of the tracking WL circuit 204 and the tracking BL circuit 202 of fig. 2.

As shown in FIG. 7A, the tracking WL circuit 700 includes a tracking WL 702, a tracking WL 704 and an inverter 706. According to various embodiments, tracking WL 702 and tracking WL 704 are configured to present signals that are logically inverted from each other by inverter 706. When tracking WL 702 and tracking WL 704 are manufactured, tracking WL 702 and tracking WL 704 are substantially adjacent to each other to intentionally induce capacitive coupling between the two tracking WLs. For example, at least a portion of tracking WL 702 is laterally close to at least a portion of tracking WL 704 by a distance. Various example implementations of tracking WLs 702 and 704 are discussed in further detail with reference to fig. 11-16C. By placing tracking WLs 702 and 704 exhibiting respective different logic states close to each other, the tracking WL 702 coupled to the replica tracking BL 756 may interfere with the tracking WL 704. As such, a degraded WL signal may be simulated on the tracking WL 702, which will be discussed in further detail below.

Alternatively or additionally, the tracking WL circuit 700 may include one or more capacitors 706 coupled between the tracking WL 702 and the tracking WL 704 to enhance the capacitive coupling caused therebetween. Such capacitors 706 may each include a Metal Oxide Semiconductor (MOS) capacitor, a metal-insulator-metal (MIM) capacitor, or the like. At least a portion of each of tracking WLs 702 and 704 can extend from one end of memory array 200 to another end of the memory array to emulate a WL (e.g., WL _ a, WL _ b, WL _ c, etc.) of memory array 200. Furthermore, if desired, one or more delay elements (e.g., delay lines, inverters, etc.) may be coupled to tracking WL 702 to create an RC delay on tracking WL 702. For example, one or more delay elements may be inserted into portion 702A of tracking WL 702 and/or portion 702B of tracking WL 702.

Fig. 7B and 7C each illustrate alternative configurations of the tracking WL circuit 700 according to various embodiments. For example, in FIG. 7B, in addition to connecting inverter 706 to tracking WL 702, tracking WLs 702 and 704 are still configured to present a logically inverted signal by inverter 706 as shown in FIG. 7A. In some embodiments, tracking WL circuit 700 may include any desired odd number of inverters connected to one of tracking WLs 702 and 704 to cause tracking WLs 702 and 704 to present logically inverted signals. For example, in fig. 7C, the tracking WL circuit 700 includes three inverters 706, 706', and 706 "connected to a tracking WL 704.

Referring to fig. 8, depicted is an example circuit diagram of a portion of a tracking BL circuit 850 coupled to a tracking WL 802, in accordance with various embodiments. As shown, the tracking BL circuit 800 includes a tracking BL 852 and several tracking BL units (e.g., 854a, 854b, 854c, etc.). Tracking WL 802 may be an example of tracking WLs 302, 402, 502, 602 and 702 and 704 as shown in fig. 3, 4, 5, 6 and 7A-7C, respectively; and tracking BL 852 and tracking BL units 854a-C may be respective instances of tracking BLs 352, 452, 552, 652, and 752 and tracking BL units 354a-C, 454a-C, 654a-C, 754a-C as shown in fig. 3, 4, 5, 6, and 7A-7C.

In some embodiments, each of tracking BL units 854a-c is substantially similar to a memory cell of memory array 200. In the example where the memory cells of memory array 200 comprise 6 transistor (6T) SRAM memory cells, each of tracking BL cells 854a-c may therefore comprise 6T SRAM memory cells. It is contemplated that the memory cells of memory array 200 may include any of a variety of other SRAM memory cell configurations or other memory cells, such as, for example, 2T-2R SRAM memory cells, 4T-SRAM memory cells, 8T-SRAM memory cells, 10T-SRAM memory cells, RRAM memory cells, MRAM memory cells, and the like. As such, each of tracking BL units 854a-c may include a conforming memory cell that is substantially similar to a memory cell of memory array 200.

To cause tracking BL circuit 850 to emulate the BL/BBL of memory array 200, tracking BL cells 854a-c may all be written to the same logic state, e.g., logic 0. As such, for example, as shown in FIG. 8, each of the tracking BL cells 854a-c configured as 6T SRAM memory cells may be effectively represented by two transistors (e.g., 856 and 858). As known to those of ordinary skill in the art, the transistor 856 may represent one of the access transistors of a 6T SRAM memory cell, and the transistor 858 may represent one of the pull-down transistors of the 6T SRAM memory cell. Specifically, the gate and drain of transistor 856 are connected to tracking WL 802 and tracking BL 852, respectively. As such a memory cell storing a logic 0, the gate of the transistor 858 is connected to a logic 1 (logically inverted to the logic 0), and the drain and source of the transistor 858 are connected to the source of the transistor 856 and ground, respectively. Thus, a logic high state present on tracking BL 852 may be pulled down to ground through transistors 856 and 858.

Fig. 9 illustrates an example signal respectively present on a WL of a memory array (hereinafter "WL signal 902"), an example signal on a BL/BBL of the memory array (hereinafter "BL signal 904"), an example signal on a tracking WL (hereinafter "TRKWL signal 906"), and an example signal on a tracking BL (hereinafter "TRKBL signal 908") in accordance with various embodiments. The WL signal 902, BL signal 904, TRKWL signal 906, and TRKBL signal 908 shown in fig. 9 may represent signals respectively present on the WL, BL/BBL, tracking WL, and tracking BL described above with reference to fig. 1 through 8.

Using FIGS. 3 and 8 as representative examples, when memory cell 200-1 is selected to be written, WL signal 90 present on WL _ a2 may be a pulse signal that includes a rising edge 902R and a falling edge 902F. WL _ a is asserted when WL signal 902 reaches a high logic state along rising edge 902R, thereby activating all memory cells (e.g., 200-1, 200-2, 200-3) arranged along row a. While performing a dummy read operation on all unselected memory cells, a write operation may be performed on the selected memory cell 200-1 by pulling up or pulling down BL _ A according to the logic state to be written to the memory cell 200-1. Ideally, the rising edge 902R of the WL signal 902 should exhibit a smooth slope, as shown by the dashed line in fig. 9. However, due to the WL-BL capacitive coupling (e.g., from BL _ B/BBL _ B to WL _ a, BL _ C/BBL _ C to WL _ a) primarily from unselected memory cells, the rising edge 902R may degrade to have a reduced slope as shown by the solid line of FIG. 9. As such, when compared to the original pulse width 902W defined by the original rising edge 902R (shown in phantom) and the original falling edge 902F (shown in phantom)₀When compared, the pulse width 902W of the WL signal 902, as defined by the degraded rising edge 902R (shown in solid lines) and the original falling edge 902F (shown in dashed lines), may be significantly reduced₁。

By directly coupling the BL/BBL of the memory array 200 to the tracking WL circuit 300, as shown in fig. 3, the tracking WL circuit 300 can simulate a degraded WL signal 902 to present a TRKWL signal 906 on the tracking WL302 with a slope that degrades on the rising edge of the WL signal. For example, by simulating the degraded WL signal 902, the TRKWL signal 906 may have a rising edge 906R with a degraded (e.g., reduced) slope. Referring now to fig. 8, each of the tracking BL cells 854a-c may be turned on based on the TRKWL signal 906 present on the tracking WL 802 (an example of the tracking WL302 of fig. 3). For example, when the TRKWL signal 906 transitions to a high logic state, each of the tracking BL cells 854a-c is turned on and the precharged tracking BL 852 may begin to be discharged to a low logic state. As shown in fig. 9, the TRKBL signal 908 transitions from a high logic state to a low logic state in response to being discharged. When the TRKBL signal 908 transitions to a sufficiently low voltage (e.g., drops by a predefined Δ V) (i.e., approximately at the time of the falling edge 902F or the timing of the falling edge 902F), the WL signal 902 is configured to transition to a low logic state along the falling edge 902F.

Due to the degraded slope of the rising edge 906R, the voltage across the gate and source (Vgs) of the access transistor (e.g., 856) of each of the tracking BL cells 854a-c is reduced, which causes the current I flowing through the tracking BL 852 to decrease. Thus, the TRKBL signal 908 is lowered by a time Δ T of Δ V (shown as a solid line)₁From time Δ T₀Extending until the TRKBL signal 908 falls by Δ V (as shown by the dashed line). In other words, the discharge rate of the TRKBL signal 908 is reduced. This is because I.times.DELTA.T₁(or I.times.DELTA.T)₀₎Is a constant value determined by the product of the capacitance value of tracking BL 852 and a predefined Δ V. Thus, the falling edge 902F of the WL signal 902 may also be extended, which may change the pulse width of the WL signal 902 from 902W₁Reverts to 902W₂. When the WL signal 902 is restored, the selected memory cell (e.g., memory cell 200-1 in the above example) can still have sufficient time to complete the write operation, despite the WL-BL capacitive coupling due to the unselected memory cells.

According to various embodiments, each of the combinations of tracking WL and tracking BL circuits described with reference to fig. 4 to 7C may follow the same principle to recover the pulse width of the degraded WL signal.

For example, in the example of any of fig. 5-6, by coupling a replica tracking BL 556 of tracking BL circuit 550 to tracking WL circuit 500, tracking WL circuit 500 may model degraded WL signal 902 to present a TRKWL signal 906 on tracking WL 502. Specifically, prior to the TRKWL signal 906 transitioning to a high logic state, a replica tracking BL 556 configured to simulate the BL/BBL of the memory array 200 is precharged to a high logic state by the transistor 504. Transistor 508 and transistor 504 can be turned on and off, respectively, while the TRKWL signal 906 transitions to a high logic state. As such, replica tracking BL 556 can begin to discharge through transistor 508 toward ground, which can cause TRKWL signal 906 to mimic degraded WL signal 902, thereby having a degraded slope on its rising edge. Based on the principles discussed above, the discharge rate of the TRKBL signal 908 (present on either the tracking BL 552 in fig. 5 or 852 in fig. 8) can be reduced, thereby restoring the pulse width of the WL signal 902.

For example, in the example of any of fig. 7A-7C, by coupling a replica tracking BL 756 of the tracking BL circuit 750 to the tracking WL circuit 700, the tracking WL circuit 700 may model the degraded WL signal 902 to present the TRKWL signal 906 on the tracking WL 702. Specifically, a replica tracking BL 756 configured to emulate the BL/BBL of memory array 200 is coupled to tracking WL 704, which presents a logically inverted signal relative to tracking WL 702. In some embodiments, tracking WL 704 may disturb tracking WL 702 by one or more capacitors formed (e.g., effectively inductively or physically disposed) therebetween. As such, the degraded WL signal 902 may be modeled as a TRKWL signal 906 (present on the tracking WL 702) that is also characterized by a slope of degradation on its rising edge. Based on the principles discussed above, the discharge rate of the TRKBL signal 908 (present on the tracking BL 752 in fig. 7A-7C or on 852 in fig. 8) may be reduced, thereby restoring the pulse width of the WL signal 902.

When writing a logic state to a memory cell, the reduced pulse width of the WL signal (e.g., due to its rising edge being degraded) may negatively impact the write operation. For example, if the pulse width is reduced too short, the write operation may fail. Generally, a figure of merit referred to as "write margin" is used to evaluate the write operation performance of the memory device. The write margin of a memory cell is typically defined as the duration from when the memory cell was successfully written to a logic state to when the falling edge of the corresponding WL signal occurs. As disclosed herein, by recovering the pulse width of the degraded WL signal using various tracking WL circuits and tracking BL circuits, the corresponding write margin can be significantly improved.

FIG. 10 shows a graph 1000 comparing write margins of different memory devices. For example, graph 1000 compares write margins (Y-axis) of a first memory device, a second memory device, and a third, different memory device under various operating conditions, e.g., power, VDD (X-axis). The first memory device represents a reference device without the WL-BL coupling effect. The trend of write margin versus operating condition for the first memory device is shown in graph 1002. The second memory device represents a device having a WL-BL coupling effect as described above and using at least one of a combination of tracking WL circuitry and tracking BL circuitry. The trend of the write margin versus operating conditions for the second memory device is shown in graph 1004. The third memory device represents a device having a WL-BL coupling effect as described above and not using any of the combinations of tracking WL circuit and tracking BL circuit. The trend of the write margin versus operating condition for the third memory device is shown in graph 1006. As shown, graph 1004 globally exhibits substantially larger writes than graph 1006 over a particular range of operating conditions.

Fig. 11 shows an exemplary implementation 1100 of a capacitor coupled between two metal lines, e.g., capacitor 506 coupled between replica track BL 556 and track WL 502 (fig. 5), capacitor 606 coupled between replica track BL 656 and track WL 602 (fig. 6), and capacitor 706 coupled between track WL 702 and track WL 704 (fig. 7A-7C). As shown in fig. 11, a capacitor coupled between two metal lines (e.g., metal line 1102 and metal line 1104) may be formed from at least one of: transistor 1110, transistor 1112, transistor 1114, or transistor 1116. In some embodiments, transistors 1110 and 1114 may each comprise a pMOSFET, and transistors 1112 and 1116 may each comprise an nMOSFET, while each of transistors 1110 and 1116 may comprise any of a variety of other transistors. Each of the transistors 1110-1116 has its gate connected to one of the metal lines 1102-1104 and its source and drain commonly connected to the other of the metal lines 1102-1104.

As a representative example, the transistor 1110 can function as the capacitor 506, where (i) the gate of the transistor 1110 is connected to the metal line 1102; and (ii) the source and drain of transistor 1110 are commonly connected to metal line 1104. In some embodiments, metal lines 1102 and 1104 may correspond to replica tracks BL 556 and track WL 502, respectively.

Fig. 12 shows another exemplary implementation 1200 of a capacitor coupled between two metal lines, for example, capacitor 506 coupled between replica track BL 556 and track WL 502 (fig. 5), capacitor 606 coupled between replica track BL 656 and track WL 602 (fig. 6), and capacitor 706 coupled between track WL 702 and track WL 704 (fig. 7A-7C). As shown in fig. 12, a capacitor coupled between two metal lines (e.g., metal line 1202 and metal line 1204) may be formed by a combination of (i) at least one of the following (transistor 1210, transistor 1212, transistor 1214, or transistor 1216) and (ii) one or more of metal lines 1220, 1222, 1224, and 1226. In some embodiments, transistors 1210 and 1214 may each comprise a pMOSFET, and transistors 1212 and 1216 may each comprise an nMOSFET, while each of transistors 1210-1216 may comprise any of a variety of other transistors. Each of the transistors 1210-1216 has a gate connected to one of the metal lines 1202-1204 and a source and a drain commonly connected to the other of the metal lines 1202-1204.

As a representative example, a combination of one or more of the transistors 1210 and the metal lines 1220-1226 may serve as the capacitor 506 having: (i) a gate of a transistor 1210 connected to the metal line 1202; (ii) a source and a drain of the transistor 1210 commonly connected to the metal line 1204; and (iii) at least one of: metal line 1220 connected to metal line 1202, metal line 1222 connected to metal line 1204, metal line 1224 connected to metal line 1202, or metal line 1226 connected to metal line 1204. In some embodiments, metal lines 1202 and 1204 may correspond to replica tracks BL 556 and track WL 502, respectively.

Typically, the first metal layer (also referred to as the metal 1(M1) layer) is typically the lowest metal layer in the integrated circuit. That is, the metal 1 layer is the metal layer closest to the substrate on which the metal layer is formed. The second metal layer, also referred to as the metal 2(M2) layer, is the metal layer formed over the metal 1 layer, without any other metal layers between the metal 1 and metal 2 layers. Likewise, the third metal layer (also referred to as the metal 3(M3) layer) is the next metal layer formed above the metal 2 layer, without any other metal layers between the metal 2 and metal 3 layers. Similarly, the fourth metal layer (also referred to as the metal 4(M4) layer) is the next metal layer formed above the metal 3 layer, without any other metal layers between the metal 3 and metal 4 layers. The progression of metal layers continues in this manner until a top metal layer is formed, such as an eighth metal layer (also referred to as a metal 8(M8) layer) formed over a seventh metal layer (also referred to as a metal 7 (M7)), without any other metal layers between the metal 7 layer and the metal 8 layer.

Fig. 13 shows yet another exemplary implementation 1300 of a capacitor coupled between two metal lines, e.g., capacitor 506 coupled between replica track BL 556 and track WL 502 (fig. 5), capacitor 606 coupled between replica track BL 656 and track WL 602 (fig. 6), and capacitor 706 coupled between track WL 702 and track WL 704 (fig. 7A-7C).

In example implementation 1300, a capacitor is formed using two substantially parallel metal plates in two metal layers separated by a dielectric material. A first metal plate of two substantially parallel metal plates is formed in the first metal layer. The second of the two substantially parallel metal plates is formed in a second metal layer different from the first metal layer of the first metal plate. The capacitance values in the example implementation 1300 are changed by changing the size of the metal plates.

For example, in fig. 13, a first metal plate 1302 and a second metal plate 1304 substantially parallel to the first metal plate 1302 are depicted. The first metal plate 1202 is formed in a metal 3(M3) layer, and the second metal plate 1304 is formed in a metal 4(M4) layer. The first metal plate 1302 is connected to a first metal line 1306 and the second metal plate 1304 is connected to a second metal line 1308 through a via 1310. Hereinafter, in the following drawings, the through-hole may be denoted by a symbol "X". A capacitor can be formed from such metal plates 1302 and 1304. By configuring the dimensions of the first metallic plate 1302 and the second metallic plate 1304, the capacitance values in the example implementation 1300 may be configured to a desired capacitance value. As a representative example, the capacitor 506 may be formed from metal plates 1302 and 1304. In some embodiments, metal lines 1306 and 1308 may correspond to replica tracks BL 556 and track WL 502, respectively.

A first metal line 1306 and a second metal line 1308 are also formed in the metal 3 layer. The second metal plate 1304 is substantially parallel to the first metal plate 1302, and is spaced apart from the first metal plate 1302 by a predetermined gap. In an example embodiment, the predetermined gap may be filled with a dielectric material. The dielectric material may include polymers such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), and the like; nitrides such as silicon nitride; oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG); etc., or combinations thereof. However, other types of dielectric materials are within the scope of the present invention.

Although the first metal plate 1302 is shown as being formed in a metal 3 layer and the second metal plate 1304 is shown as being formed in a metal 4 layer, other metal layers are within the scope of the invention for both the first metal plate 1302 and the second metal plate 1304. Further, although the first metal line 1306 and the second metal line 1308 are shown as being formed in the same metal layer (e.g., metal 3 layer) as the first metal plate 1302, in some other embodiments, the first metal line 1306 and the second metal line 1308 may be formed in the same metal layer (e.g., metal 4 layer) as the second metal plate 1304. The size and shape of each of the first metallic plate 1302 and the second metallic plate 1304 may be based on a desired capacitance value.

Fig. 14 shows yet another exemplary implementation 1400 of a capacitor coupled between two metal lines, e.g., capacitor 506 coupled between replica tracking BL 556 and tracking WL 502 (fig. 5), capacitor 606 coupled between replica tracking BL 656 and tracking WL 602 (fig. 6), and capacitor 706 coupled between tracking WL 702 and tracking WL 704 (fig. 7A-7C).

The example implementation 1400, also referred to as a buckle style, includes two sub-capacitors formed in parallel with each other, a first sub-capacitor and a second sub-capacitor. The two sub-capacitors are formed from two sets of metal strips. For example, a first sub-capacitor is formed from a first set of metal strips, and a second sub-capacitor is formed parallel to the first sub-capacitor, from a second set of metal strips. The first set of metal strips are placed parallel to each other so that a capacitor is formed between every two consecutive metal strips. Similarly, the second set of metal strips is also placed parallel to each other, so that a capacitor is formed between every two consecutive metal strips. The capacitance value of each of the two sub-capacitors depends on the number of metal strips and the size of the metal strips in each set of corresponding metal strips and the length of each metal strip. The total capacitance value in the example implementation 1400 is determined as the sum of two sub-capacitors formed by two sets of metal strips.

For example, in fig. 14, the example implementation 1400 includes a first sub-capacitor formed from a first set of metal strips 1402 and a second sub-capacitor formed from a second set of metal strips 1404. Each of the first set of metal strips 1402 and the second set of metal strips 1404 are formed in two different metal layers. For example, the first set of metal strips 1402 is formed in a metal 2(M2) layer, and the second set of metal strips 1404 is formed in a metal 4(M4) layer. However, other metal layers are within the scope of the invention. The first sub-capacitor is formed between a first pair of metal lines (e.g., first metal line 1406 and second metal line 1408). Each of the first and second metal lines 1406 and 1408 is formed in a metal 1(M1) layer. Each of the first set of metal strips 1402 is alternately connected to either a first metal line 1406 or a second metal line 1408 by a via. A second sub-capacitor is formed between a second pair of metal lines (e.g., third metal line 1410 and fourth metal line 1412). Each of the third and fourth metal lines 1410 and 1412 is formed in a metal 3(M3) layer. Each of the second set of metal strips 1404 is alternately connected to the third metal line 1410 or the fourth metal line 1412 through a via. As a representative example, the capacitor 506 may include at least one of a first sub-capacitor or a second sub-capacitor. In some embodiments, metal lines 1406 and 1410 may correspond to replica trace BL 556 and metal lines 1408 and 1412 may correspond to trace WL 502.

Each of the first set of metal strips 1402 and the second set of metal strips 1404 includes a predetermined number of metal strips disposed parallel to each other. A capacitor may be additionally formed between every two consecutive metal strips on top of the first and second sub-capacitors. In the above representative example, the capacitor 506 may include such additional capacitors in addition to the first sub-capacitor and/or the second sub-capacitor. Thus, the total capacitance value of each of the first set of metal strips 1402 and the second set of metal strips 1404 depends on the number of metal strips and the size of the metal strips in the corresponding set. For example, in fig. 14, the first set of metal strips 1402 includes three metal strips, and the second set of metal strips 1404 includes seven metal strips. However, the number of metal strips of each of the first and second sets of metal strips 1402, 1404 may vary based on the desired capacitance value of each of the first and second sub-capacitors. Accordingly, different numbers of metal strips for each of the first set of metal strips 1402 and the second set of metal strips 1404 are within the scope of the present invention. Further, the dimensions of each of the first set of metal strips 1402 and the second set of metal strips 1404 may also vary based on the desired capacitance values of the first sub-capacitors and the second sub-capacitors.

In an example implementation, each metal strip of the first set of metal strips 1402 is parallel to each other, with the gaps between the strips filled with a dielectric material. Similarly, each metal strip of the second set of metal strips 1404 is parallel to each other, with the gaps between the strips filled with a dielectric material. Example dielectric materials may include polymers such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), and the like; nitrides such as silicon nitride; oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG); etc., or combinations thereof. However, other dielectric materials are within the scope of the present invention.

Fig. 15 shows yet another exemplary implementation 1500 of a capacitor coupled between two metal lines, e.g., capacitor 506 coupled between replica track BL 556 and track WL 502 (fig. 5), capacitor 606 coupled between replica track BL 656 and track WL 602 (fig. 6), and capacitor 706 coupled between track WL 702 and track WL 704 (fig. 7A-7C).

The example implementation 1500, also referred to as a grid pattern, includes three sets of metal strips. Each of the three sets of metal strips forms three sub-capacitors. For example, a first sub-capacitor is formed by a first set of metal strips placed parallel to each other, a second sub-capacitor is formed by a second set of metal strips placed parallel to each other, and a third sub-capacitor is formed by a third set of metal strips placed parallel to each other. Each successive metal strip of each of the first and second sets of metal strips is alternately connected to a metal strip of the third set of metal strips, thereby forming a grid. The capacitance value of each of the three sub-capacitors depends on the number of metal strips in each set of corresponding metal strips and the size of each metal strip. The total capacitance value in example implementation 1500 is determined as the sum of three sub-capacitors formed by three sets of metal strips.

For example, in FIG. 15, implementation 1500 includes a first set of metal strips 1502, a second set of metal strips 1504, and a third set of metal strips 1506 (e.g., 1506-1, 1506-2, 1506-3, 1506-4, 1506-5, 1506-6). Third set of metal strips 1506 may be placed in the first direction and first set of metal strips 1502 and second set of metal strips 1504 may each be formed in the second direction. The second direction may be orthogonal to the first direction. Each metal strip in first set of metal strips 1502 and each metal strip in second set of metal strips 1504 is connected to each alternate metal strip of third set of metal strips 1506 by vias to form a grid. That is, the first metal strip of each of first set of metal strips 1502 and second set of metal strips 1504 is connected to the second, fourth, and sixth metal strips of third set of metal strips 1506 (1506-2, 1506-4, 1506-6). And, the second metal strip of each of first set of metal strips 1502 and second set of metal strips 1504 is connected to the first, third, and fifth metal strips of third set of metal strips 1506 (1506-1, 1506-3, 1506-5).

The first sub-capacitor is formed by one or more pairs of the first set of metal bars 1502; the second sub-capacitor is formed from one or more pairs of the second set of metal strips 1504; and the third sub-capacitor is formed by one or more pairs of a third set of metal strips 1506. The capacitance value of each of the first sub-capacitor formed by first set of metal strips 1502, the second sub-capacitor formed by second set of metal strips 1504, and the third sub-capacitor formed by third set of metal strips 1506 depends on the number of metal strips in each set and the size of each metal strip. Accordingly, each of first set of metal strips 1502, second set of metal strips 1504, and third set of metal strips 1506 includes a predetermined number of metal strips.

For example, in fig. 15, first set of metal strips 1502 includes three metal strips, second set of metal strips 1504 includes seven metal strips, and third set of metal strips 1506 includes six metal strips. However, the number of metal strips in each of the first set of metal strips 1502, the second set of metal strips 1504, and the third set of metal strips 1506 may vary based on the desired capacitance value. Accordingly, different numbers of metal strips for each of first set of metal strips 1502, second set of metal strips 1504, and third set of metal strips 1506 are within the scope of the present invention. Further, the dimensions of the metal strips in each of the first set of metal strips 1502, the second set of metal strips 1504, and the third set of metal strips 1506 may vary based on a desired capacitance value. As a representative example, the capacitor 506 may include at least one of a first sub-capacitor, a second sub-capacitor, or a third sub-capacitor. Thus, one of the third set of metal strips 1506 (e.g., 1506-5) may correspond to replica trace BL 556 and another of the third set of metal strips 1506 (e.g., 1506-6) may correspond to trace WL 502.

Each of the metal strips in the first set of metal strips 1502 is parallel to each other, and the gaps between the metal strips are filled with a dielectric material. Similarly, each metal strip of the second set of metal strips 1504 is parallel to each other, with the gaps between the strips filled with a dielectric material. In addition, each metal strip in the third set of metal strips 1506 is parallel to each other, and the gaps between the strips are filled with a dielectric material. Example dielectric materials may include polymers such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), and the like; nitrides such as silicon nitride; oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG); etc., or combinations thereof. However, other dielectric materials are within the scope of the present invention.

Further, each of first set of metal strips 1502, second set of metal strips 1504, and third set of metal strips 1506 may be disposed in a different metal layer. For example, first set of metal strips 1502 is in a metal 2(M2) layer, second set of metal strips 1504 is in a metal 4(M4) layer, and third set of metal strips 1506 is in a metal 3(M3) layer. However, other metal layers are within the scope of the invention. In some implementations, two of first set of metal strips 1502, second set of metal strips 1504, and third set of metal strips 1506 can be in the same metal layer, and the remaining metal strips are in different metal layers. For example, the metal strips of each of the first and second sets of metal strips 1502 and 1504 may be in a metal 2(M2) layer or a metal 4(M4) layer, and the third set of metal strips 1506 may be in a metal 3(M3) layer.

Fig. 16A, 16B, and 16C show yet another exemplary implementation 1600 of a capacitor coupled between two metal lines, e.g., capacitor 506 coupled between replica tracking BL 556 and tracking WL 502 (fig. 5), capacitor 606 coupled between replica tracking BL 656 and tracking WL 602 (fig. 6), and capacitor 706 coupled between tracking WL 702 and tracking WL 704 (fig. 7A-7C).

The example implementation 1600, also referred to as a via pattern, includes two sets of metal strips. Further, the example implementation 1600 includes a plurality of vias formed on the metal strip. Each of the two sets of metal strips forms two sub-capacitors. For example, a first sub-capacitor is formed by a first set of metal strips placed in parallel with each other, and a second sub-capacitor is formed by a second set of metal strips placed in parallel with each other. Further, additional capacitors are formed by the plurality of vias. For example, each of two adjacent vias forms a capacitor therebetween. The capacitance value of each of the two sub-capacitors depends on the number of metal strips in each set of corresponding metal strips, the size (e.g., length, width, and/or thickness) of the metal strips, the number of vias in each set of corresponding metal strips, and the size (e.g., length, width, and/or thickness) of each via. The total capacitance value in example implementation 1600 is determined as the sum of two sub-capacitors formed by two sets of metal strips.

For example, in fig. 16A, the example implementation 1600 includes a first set of metal strips 1602 and a second set of metal strips 1604. Each of the first set of metal strips 1602 and the second set of metal strips 1604 are in different metal layers. For example, the first set of metal strips 1602 is in a metal 2(M2) layer and the second set of metal strips 1604 is in a metal 4(M4) layer. However, other metal layers are within the scope of the invention. In some other embodiments, each of the first set of metal strips 1602 and the second set of metal strips 1604 may be in the same metal layer.

Each of the first set of metal strips 1602 and the second set of metal strips 1604 includes a predetermined number of metal strips. For example, in fig. 16A, the first set of metal strips 1602 includes three metal strips and the second set of metal strips 9604 includes seven metal strips. However, the number of metal strips may vary based on the desired capacitance value. Accordingly, different numbers of metal strips for each of the first set of metal strips 1602 and the second set of metal strips 1604 are within the scope of the present invention.

First set of metal strips 1602 includes a first plurality of vias 1606 and second set of metal strips 1604 includes a second plurality of vias 1608. Each pair of adjacent vias of first plurality of vias 1606 and second plurality of vias 1608 may additionally form a capacitor therebetween. Accordingly, the number of vias in each of first plurality of vias 1606 and second plurality of vias 1608 may be adjusted to change the capacitance value of example implementation 1600.

Each metal strip of first set 1602 and second set 1604 of metal strips is alternately connected to first metal line 1610 and second metal line 1612. First and second metal lines 1610, 1612 are formed in different metal layers than the metal layers in which first and second sets of metal strips 1602, 1604 are formed, respectively. For example, the first metal line 1610 and the second metal line 1612 are in a metal 3(M3) layer. However, other metal layers are within the scope of the invention.

Fig. 16B shows an example cross-sectional view of first metal strip 1602 cut along line a-a', which includes a first plurality of vias 1606. As shown in fig. 16B, a first plurality of vias 1606 are formed between the metal 2(M2) layer forming the first set of metal strips 1602 and the metal 3(M3) layer forming the first and second metal lines 1610, 1612. However, other metal layers are within the scope of the invention. Fig. 16C shows an example cross-sectional view of a second metal strip 1604 that includes a second plurality of vias 1608 cut along line a-a'. As shown in fig. 16C, a second plurality of vias 1608 are formed between the layer of metal 3(M3) that forms first metal line 1610 and second metal line 1612 and the layer of metal 4(M4) that forms second set of metal strips 1604. However, other metal layers are within the scope of the invention. Further, each of first plurality of metal strips 1602 and second plurality of metal strips 1604 are shown as including two rows of vias. However, different numbers of via rows are within the scope of the invention.

The first sub-capacitor is formed from one or more pairs of first set of metal strips 1602; and the second sub-capacitor is formed from one or more pairs of the second set of metal strips 1604. The capacitance value of each of the first sub-capacitor formed by the first set of metal strips 1602 and the second sub-capacitor formed by the second set of metal strips 1604 depends on the number of metal strips in each set and the size of each metal strip. Thus, each of the first set of metal strips 1602 and the second set of metal strips 1604 includes a predetermined number of metal strips. As a representative example, the capacitor 506 may include at least one of a first sub-capacitor or a second sub-capacitor. Thus, a first metal line 1610 may correspond to replica track BL 556 and a second metal line 1612 may correspond to track WL 502.

Further, the dimensions of each of the first set of metal strips 1602 and the second set of metal strips 1604 may also vary based on the desired capacitance value. In an example embodiment, each metal strip of the first set of metal strips 1602 is parallel to each other, and the gaps between the strips are filled with a dielectric material. Similarly, each metal strip of the second set of metal strips 1604 is parallel to each other, with the gaps between the strips filled with a dielectric material. Examples of the dielectric material may include polymers such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), and the like; nitrides such as silicon nitride; oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG); etc., or combinations thereof. However, other dielectric materials are within the scope of the present invention.

FIG. 17 illustrates a flow diagram of an example method 1700 of operating a memory device to restore wordline pulse widths in accordance with various embodiments. For example, as discussed with reference to fig. 1-16C, tracking WL circuit 204 and tracking BL circuit 202 may perform the operations of method 1700 to restore wordline pulse widths. As such, the following embodiments of method 1700 will be described in conjunction with fig. 1-16C. The illustrated embodiment of method 1700 is merely an example. Accordingly, it should be understood that any of the various operations of method 1700 may be omitted, reordered, and/or added while remaining within the scope of the present invention.

According to various embodiments, method 1700 begins with operation 1702 (transitioning a WL coupled to a memory cell from a low logic state to a high logic state). The memory cell may be selected to be written to a certain logic state. Referring again to FIG. 9, WL signal 902 (e.g., WL _ a of FIG. 2 when one of the memory cells 200-1-3 on row a is selected) may represent a signal present on a WL that transitions from a low logic state to a high logic state. The WL signal 902 may have a degraded slope on its rising edge 902R due to the effect of WL-BL coupling from the BL/BBL of the selected memory cell and/or the BL/BBL of one or more of the unselected memory cells arranged along the WL.

The method 1700 continues to operation 1704 (transitioning the tracking WL having the disturbed slope and simulating the WL from a low logic state to a high logic state by at least one of: according to various embodiments, (i) the tracking WL is coupled directly to the BL coupled with the memory cell, or (ii) the tracking WL is coupled to a first tracking BL simulating the BL. For example, in fig. 3-4, by respectively coupling tracking WL 302/402 (of tracking WL circuit 204 of fig. 2) to one or more of BL/BBLs (e.g., BL _ A, BBL _ A, BL _ B, BBL _ B, etc.) of memory array 200, tracking WL 302/402 may exhibit a TRKWL signal 906 (fig. 9) having an oxidizing or otherwise disturbed slope. For example, in fig. 5-7C, tracking WL 502/602/702 may also exhibit a TRKWL signal 906 (fig. 9) having a degraded or otherwise disturbed slope by coupling tracking WL 502/602/702 (of tracking WL circuit 204 of fig. 2) to replica tracking BL 556/656/756 (of tracking BL circuit 202 of fig. 2), respectively.

The method 1700 continues to operation 1706 (which, according to various embodiments, extends the timing of transitioning the WL from a high logic state to a low logic state by discharging the second tracking BL of the analog BL according to the disturbed slope). Referring again to fig. 8, the timing of the WL signal 902 transitioning back to the low logic state may be extended by discharging the tracking BL 852 (which may be an example of the tracking BLs 352, 452, 552, 652, 752 of fig. 3-7C) according to the disturbed slope of the TRKWL signal 906 (fig. 9). It should be noted that the tracking BL 852 is part of the tracking BL circuit 202. In some embodiments, the WL may transition from a high logic state to a low logic state in response to the voltage of the second tracking BL dropping by a predetermined voltage. For example, in fig. 9, when the TRKBL signal 908 falls by Δ V (is delayed from occurring), the WL signal 902 may transition from a high logic state to a low logic state, thereby lengthening the pulse width of the WL signal 902.

In one aspect of the invention, a memory device includes a memory cell. The memory device includes a Word Line (WL) connected to the memory cell configured to present a first WL pulse to allow writing the memory cell to a logic state within the first WL pulse. The first WL pulse has a rising edge and a falling edge. The memory device includes a Bit Line (BL), connected to the memory cell, configured to write a logic state to the memory cell. The memory device includes a first tracking WL configured to emulate a WL to provide a second WL pulse having a rising edge with a disturbed slope. The memory device includes a first tracking BL configured to emulate a BL coupled to the first tracking WL such that a falling edge of the first WL pulse is extended based on a disturbed slope of a rising edge of the second WL pulse.

In the above memory device, the voltage of the first tracking BL is configured to transition to a low logic state in response to a rising edge of the second WL pulse, and wherein a falling edge of the first WL pulse occurs in response to the voltage of the tracking BL falling by a predetermined voltage.

In the above memory device, the disturbed slope of the rising edge of the second WL pulse causes the voltage of the first tracking BL to assume the disturbed slope at the same time as the transition to the low logic state.

In the above memory device, the first tracking WL includes at least one tracking WL bit cell, the tracking WL bit cell includes a first transistor and a second transistor, respective gates of the first transistor and the second transistor are connected to the first tracking WL, respective sources of the first transistor and the second transistor are floated, and one of respective drains of the first transistor and the second transistor is directly connected to the BL.

In the above memory device, the first tracking WL includes at least one tracking WL bit cell including a first transistor, a second transistor, a third transistor, and a fourth transistor, respective gates of the first transistor and the second transistor are connected to the first tracking WL, respective sources of the first transistor and the second transistor are floated by the third transistor and the fourth transistor, the third transistor and the fourth transistor are connected by the gates and grounded by the sources, and one of respective drains of the first transistor and the second transistor is directly connected to the BL.

In the above memory device, further comprising: a second tracking BL configured to simulate the BL; and a transistor having a gate connected to the first tracking WL, a drain connected to the second tracking BL, and a source connected to ground, the transistor configured to reduce the voltage of the second tracking BL, thereby causing the second WL pulse to exhibit a rising edge with a disturbed slope.

In the above memory device, further comprising: and a capacitor coupled between the second tracking BL and the first tracking WL.

In the above memory device, further comprising: a second tracking BL configured to simulate the BL; and a second tracking WL connected to the second tracking BL and close-coupled to the first tracking WL, the second tracking WL configured to assume a logic state that is inverted from a logic state of the first tracking WL to cause the second WL pulse to assume a rising edge with a disturbed slope.

In the above memory device, further comprising: one or more capacitors coupled between the first tracking WL and the second tracking WL.

In another aspect of the invention, a memory device includes a memory array including a plurality of memory cells. The memory device includes a Word Line (WL), connected to one of the plurality of memory cells, configured to provide a first WL pulse having a rising edge and a falling edge defining a pulse width of the first WL pulse. The memory device includes a first tracking WL formed adjacent to the memory array configured to provide a second WL pulse having a rising edge with a decreasing slope by being physically or operably coupled to a Bit Line (BL) configured to write a logic state to the memory cell. The memory device includes a first tracking BL configured to emulate a BL coupled to the first tracking WL such that a pulse width of the first WL pulse increases based on a decreasing slope of a rising edge of the second WL pulse.

In the above memory device, the voltage of the first tracking BL is configured to transition to a low logic state in response to a rising edge of the second WL pulse, and wherein a falling edge of the first WL pulse occurs in response to the voltage of the tracking BL falling by a predetermined voltage.

In the above memory device, the decreasing slope of the rising edge of the second WL pulse causes the voltage of the first tracking BL to exhibit a decreasing slope while transitioning to a low logic state, thereby increasing the pulse width of the first WL pulse.

In the above memory device, further comprising: at least one tracking WL bit-cell coupled to the first tracking WL, wherein the tracking WL bit-cell comprises a first transistor and a second transistor, respective gates of the first transistor and the second transistor are connected to the first tracking WL, respective sources of the first transistor and the second transistor are floated, and one of respective drains of the first transistor and the second transistor is directly connected to the BL.

In the above memory device, the first tracking WL and the at least one tracking WL bit-cell are formed within a memory array.

In the above memory device, further comprising: at least one tracking WL bit-cell coupled to the first tracking WL, wherein the tracking WL bit-cell comprises a first transistor, a second transistor, a third transistor, and a fourth transistor, respective gates of the first and second transistors are connected to the first tracking WL, respective sources of the first and second transistors are floated through the third and fourth transistors, the third and fourth transistors are gate-connected and the sources are grounded, one of respective drains of the first and second transistors is directly connected to the BL.

In the above memory device, the first tracking WL and the at least one tracking WL bit-cell are formed within a memory array.

In the above memory device, further comprising: a second tracking BL formed adjacent to the memory array, the second tracking BL configured to simulate a BL; a transistor having a gate connected to the first tracking WL, a drain connected to the second tracking BL, and a source connected to ground, the transistor configured to reduce the voltage of the second tracking BL, thereby causing the second WL pulse to exhibit a rising edge with a falling slope; and a capacitor coupled between the second tracking BL and the first tracking WL, thereby also causing the second WL pulse to exhibit a rising edge with a reduced slope.

In the above memory device, further comprising: a second tracking BL configured to simulate the BL; and a second tracking WL connected to the second tracking BL and close-coupled to the first tracking WL, the second tracking WL configured to assume a logic state that is inverted from the logic state of the first tracking WL to cause the second WL pulse to assume a rising edge with a reduced slope.

In yet another aspect of the present invention, a method of operating a memory device includes: a Word Line (WL) coupled to the memory cell is transitioned from a first logic state to a second logic state. The method comprises the following steps: transitioning a tracking WL of the simulated WL from the first logic state to the second logic state with the disturbed slope by at least one of: (i) couple the tracking WL directly to a Bit Line (BL) coupled with the memory cell, or (ii) couple the tracking WL to a first tracking BL simulating the BL. The method includes extending a timing of transitioning the WL from the second logic state to the first logic state by discharging a second tracking BL simulating the BL according to the disturbed slope.

In the above method, further comprising: the WL is transitioned from the second logic state to the first logic state in response to the voltage of the second tracking BL dropping by a predetermined voltage.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.