阅读说明：本技术 像素阵列基板 (Pixel array substrate ) 是由 王睦凯 蔡艾茹 黄国有 锺岳宏 于 2021-07-07 设计创作，主要内容包括：一种像素阵列基板包括多条数据线、多条栅极线、多个像素结构及多条转接线。每一像素结构包括一薄膜晶体管、一像素电极及一桥接元件。多个像素结构排成多个像素列。每一数据线具有相对的第一侧与第二侧。一像素列的一像素结构的薄膜晶体管的源极与下一像素列的一像素结构的薄膜晶体管的源极电性连接至同一数据线。像素列的像素结构的薄膜晶体管的漏极与下一像素列的像素结构的薄膜晶体管的漏极位于同一数据线的第一侧。像素列的像素结构的像素电极与下一像素列的像素结构的像素电极分别位于同一数据线的第二侧及第一侧。像素列的像素结构的桥接元件跨越同一数据线及一转接线。(A pixel array substrate comprises a plurality of data lines, a plurality of gate lines, a plurality of pixel structures and a plurality of transfer lines. Each pixel structure comprises a thin film transistor, a pixel electrode and a bridging element. The plurality of pixel structures are arranged in a plurality of pixel columns. Each data line has a first side and a second side opposite to each other. The source electrode of the thin film transistor of one pixel structure of one pixel row and the source electrode of the thin film transistor of one pixel structure of the next pixel row are electrically connected to the same data line. The drain electrode of the thin film transistor of the pixel structure of the pixel column and the drain electrode of the thin film transistor of the pixel structure of the next pixel column are positioned on the first side of the same data line. The pixel electrode of the pixel structure of the pixel column and the pixel electrode of the pixel structure of the next pixel column are respectively positioned on the second side and the first side of the same data line. The bridging element of the pixel structure of the pixel column spans the same data line and a transfer line.)

1. A pixel array substrate, comprising:

a substrate;

a plurality of data lines disposed on the substrate and arranged in a first direction;

a plurality of gate lines disposed on the substrate and arranged in a second direction, wherein the first direction and the second direction are staggered;

a plurality of pixel structures disposed on the substrate, wherein each pixel structure includes a thin film transistor, a pixel electrode and a bridge element, a source and a gate of the thin film transistor are electrically connected to a corresponding data line and a corresponding gate line, respectively, the pixel electrode is disposed outside the drain of the thin film transistor, and the bridge element is electrically connected to a drain of the thin film transistor and the pixel electrode; and

a plurality of patch cords disposed on the substrate, arranged in the first direction, and electrically connected to the gate lines;

the pixel structures are arranged into a plurality of pixel rows, the pixel structures of each pixel row are arranged in the first direction, and the pixel rows are arranged in the second direction;

each data line is provided with a first side and a second side which are opposite;

the source electrode of the thin film transistor of the pixel structure of one pixel row and the source electrode of the thin film transistor of the pixel structure of the next pixel row are electrically connected to the same data line;

the drain electrode of the thin film transistor of the pixel structure of one pixel row and the drain electrode of the thin film transistor of the pixel structure of the next pixel row are positioned at the first side of the same data line;

the pixel electrode of the pixel structure of the pixel row and the pixel electrode of the pixel structure of the next pixel row are respectively positioned at the second side and the first side of the same data line;

the bridging element of the pixel structure of the pixel row spans the same data line and the same patch cord.

2. The pixel array substrate of claim 1, further comprising:

a first insulating layer disposed on the plurality of thin film transistors of the pixel structures;

a common electrode layer disposed on the first insulating layer; and

the second insulating layer is arranged on the common electrode layer, wherein the bridging element of the pixel structure of the pixel row is arranged on the second insulating layer, and the common electrode layer is arranged between the bridging element of the pixel structure of the pixel row and the transfer line.

3. The pixel array substrate of claim 2, wherein the pixel electrode of the pixel structure of the pixel row is disposed on the second insulating layer, and the common electrode layer is disposed between the pixel electrode of the pixel structure of the pixel row and the transfer line.

4. The pixel array substrate of claim 1, wherein the bridging element of the pixel structure of the pixel row is interlaced with the same data line, and the bridging element of the pixel structure of the next pixel row is disposed outside the same data line and does not overlap the same data line.

5. The pixel array substrate of claim 1, wherein the pixel electrodes of the pixel structures are arranged in a plurality of pixel electrode rows, the pixel electrodes of each pixel electrode row are arranged in the second direction, and the pixel electrode rows are arranged in the first direction; the pixel electrode rows comprise a first pixel electrode row and a second pixel electrode row which are respectively used for displaying red and blue; in a top view of the pixel array substrate, the patch cord is disposed between the first pixel electrode row and the second pixel electrode row.

6. The pixel array substrate of claim 1, wherein the pixel electrodes of the pixel structures are arranged in a plurality of pixel electrode rows, the pixel electrodes of each pixel electrode row are arranged in the second direction, and the pixel electrode rows are arranged in the first direction; the pixel electrode rows comprise a second electrode pixel row and a third electrode pixel row which are respectively used for displaying blue and green; in a top view of the pixel array substrate, the patch cord is disposed between the second pixel electrode row and the third pixel electrode row.

7. The pixel array substrate of claim 1, wherein the pixel structures are arranged in a plurality of pixel electrode rows, the pixel electrodes of each pixel electrode row are arranged in the second direction, and the pixel electrode rows are arranged in the first direction; the pixel electrode rows comprise a first pixel electrode row and a third pixel electrode row which are respectively used for displaying red and green; in a top view of the pixel array substrate, the patch cord is disposed between the first pixel electrode row and the third pixel electrode row.

8. The pixel array substrate of claim 1, wherein the thin film transistor further comprises a semiconductor pattern, two different regions of the semiconductor pattern are electrically connected to the source and the drain, respectively, and the semiconductor pattern is disposed between the gate and the substrate.

9. The pixel array substrate of claim 1, wherein the thin film transistor further comprises a semiconductor pattern, two different regions of the semiconductor pattern are electrically connected to the source and the drain, respectively, and the gate is disposed between the semiconductor pattern and the substrate.

Technical Field

The invention relates to a pixel array substrate.

Background

With the development of display technologies, the demands of people for display devices are no longer satisfied with optical characteristics such as high resolution, high contrast, and wide viewing angle, and people expect that display devices have elegant appearance. For example, it is desirable for a display device to have a narrow frame, even no frame.

Generally, a display device includes a pixel array disposed in a display region, a data driving circuit disposed below the display region, and a gate driving circuit disposed on the left, right, or left and right sides of the display region. In order to reduce the width of the left and right sides of the frame of the display device, the gate driving circuit and the data driving circuit may be disposed at the lower side of the display region. When the gate driving circuit is disposed at the lower side of the display region, the gate line extending in the horizontal direction should be electrically connected to the gate driving circuit via the transfer line extending in the vertical direction. However, when the patch cord is disposed in the active area, the patch cord is inevitably adjacent to the data line; the coupling effect between the patch cord and the data line can make the data signal on the data line deviate, thereby causing the problem of oblique lines.

Disclosure of Invention

The invention provides a pixel array substrate with good performance and high aperture ratio.

The pixel array substrate comprises a base, a plurality of data lines, a plurality of gate lines, a plurality of pixel structures and a plurality of transfer lines. The data lines are arranged on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction, wherein the first direction and the second direction are staggered. The pixel structures are arranged on the substrate, each pixel structure comprises a thin film transistor, a pixel electrode and a bridging element, a source electrode and a grid electrode of the thin film transistor are respectively and electrically connected to a corresponding data line and a corresponding grid line, the pixel electrode is arranged outside a drain electrode of the thin film transistor, and the bridging element is electrically connected with the drain electrode of the thin film transistor and the pixel electrode. The plurality of patch cords are disposed on the substrate, arranged in a first direction, and electrically connected to the plurality of gate lines. The plurality of pixel structures are arranged in a plurality of pixel columns. The plurality of pixel structures of each pixel column are arranged in a first direction, and the plurality of pixel columns are arranged in a second direction. Each data line has a first side and a second side opposite to each other. The source electrode of the thin film transistor of one pixel structure of one pixel row and the source electrode of the thin film transistor of one pixel structure of the next pixel row are electrically connected to the same data line. The drain electrode of the thin film transistor of the pixel structure of the pixel column and the drain electrode of the thin film transistor of the pixel structure of the next pixel column are positioned on the first side of the same data line. The pixel electrode of the pixel structure of the pixel column and the pixel electrode of the pixel structure of the next pixel column are respectively positioned on the second side and the first side of the same data line. The bridging element of the pixel structure of the pixel column spans the same data line and a transfer line.

In an embodiment of the invention, the pixel array substrate further includes a first insulating layer, a common electrode layer, and a second insulating layer. The first insulating layer is arranged on the thin film transistors of the pixel structures. The common electrode layer is disposed on the first insulating layer. The second insulating layer is disposed on the common electrode layer. The bridging element of the pixel structure of the pixel row is arranged on the second insulating layer, and the common electrode layer is arranged between the bridging element of the pixel structure of the pixel row and the transfer line.

In an embodiment of the invention, the pixel electrode of the pixel structure of the pixel row is disposed on the second insulating layer, and the common electrode layer is disposed between the pixel electrode of the pixel structure of the pixel row and the transfer line.

In an embodiment of the invention, the bridging elements of the pixel structures of the pixel rows are staggered with the same data line, and the bridging elements of the pixel structures of the next pixel row are disposed outside the same data line and are not overlapped with the same data line.

In an embodiment of the invention, the pixel electrodes of the pixel structures are arranged in a plurality of pixel electrode rows, the pixel electrodes of each pixel electrode row are arranged in the second direction, and the pixel electrode rows are arranged in the first direction; the pixel electrode rows comprise a first pixel electrode row and a second pixel electrode row which are used for displaying red and blue respectively; in a top view of the pixel array substrate, the patch cord is disposed between the first pixel electrode row and the second pixel electrode row.

In an embodiment of the invention, the pixel electrodes of the pixel structures are arranged in a plurality of pixel electrode rows, the pixel electrodes of each pixel electrode row are arranged in the second direction, and the pixel electrode rows are arranged in the first direction; the pixel electrode rows comprise a second electrode pixel row and a third electrode pixel row which are used for displaying blue and green respectively; in a top view of the pixel array substrate, the patch cord is disposed between the second electrode pixel row and the third pixel electrode row.

In an embodiment of the invention, the pixel structures are arranged in a plurality of pixel electrode rows, the pixel electrodes of each pixel electrode row are arranged in the second direction, and the pixel electrode rows are arranged in the first direction; the pixel electrode rows comprise a first pixel electrode row and a third pixel electrode row which are used for displaying red and green respectively; in a top view of the pixel array substrate, the patch cord is disposed between the first pixel electrode row and the third pixel electrode row.

In an embodiment of the invention, the thin film transistor further includes a semiconductor pattern, two different regions of the semiconductor pattern are electrically connected to the source and the drain, respectively, and the semiconductor pattern is disposed between the gate and the substrate.

In an embodiment of the invention, the thin film transistor further includes a semiconductor pattern, two different regions of the semiconductor pattern are electrically connected to the source and the drain, respectively, and the gate is disposed between the semiconductor pattern and the substrate.

Drawings

Fig. 1 is a schematic top view of a pixel array substrate 100 according to an embodiment of the invention.

Fig. 2 is a schematic cross-sectional view of a pixel array substrate 100 according to an embodiment of the invention.

Fig. 3 is a schematic cross-sectional view of a pixel array substrate 100 according to an embodiment of the invention.

Fig. 4 is a schematic top view of a pixel array substrate 100A according to an embodiment of the invention.

Fig. 5 is a schematic top view of a pixel array substrate 100B according to an embodiment of the invention.

Fig. 6 is a schematic cross-sectional view of a pixel array substrate 100B according to an embodiment of the invention.

Fig. 7 is a schematic cross-sectional view of a pixel array substrate 100B according to an embodiment of the invention.

Description of reference numerals:

100. 100A, 100B: pixel array substrate

110: substrate

120: buffer layer

130: gate insulating layer

132. 134, 142, 144: contact window

140: interlayer dielectric layer

150: a first insulating layer

160: common electrode layer

170: a second insulating layer

182: pixel electrode

182 a: slit

184: bridging element

190: a third insulating layer

C: pixel electrode row

Cr: a first pixel electrode row

Cb: second pixel electrode row

Cg: third pixel electrode row

DL: data line

GL: gate line

gl: adapter cable

PX: pixel structure

PXA: first type pixel structure

PXB: second type pixel structure

R, Rn + 1: pixel column

SM: shading pattern

T: thin film transistor

Ta: source electrode

Tb: drain electrode

Tc: grid electrode

Td: semiconductor pattern

x: a first direction

y: second direction

I-I ', II-II', III-III ', IV-IV': cutting line

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connections. Further, "electrically connected" or "coupled" may mean that there are additional elements between the elements.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 is a schematic top view of a pixel array substrate 100 according to an embodiment of the invention.

Fig. 2 is a schematic cross-sectional view of a pixel array substrate 100 according to an embodiment of the invention. Fig. 2 corresponds to the section line I-I' of fig. 1.

Fig. 3 is a schematic cross-sectional view of a pixel array substrate 100 according to an embodiment of the invention. Fig. 2 corresponds to the section line II-II' of fig. 1.

Referring to fig. 1, 2 and 3, the pixel array substrate 100 includes a substrate 110. In the present embodiment, the substrate 110 is made of glass, for example. However, the invention is not limited thereto, and according to other embodiments, the substrate 110 may be made of quartz, organic polymer, or opaque/reflective material (e.g., wafer, ceramic, etc.), or other suitable materials.

Referring to fig. 1 and 3, the pixel array substrate 100 further includes a plurality of data lines DL and a plurality of gate lines GL disposed on the substrate 110. Referring to fig. 1, a plurality of data lines DL are arranged in a first direction x, and a plurality of gate lines GL are arranged in a second direction y, wherein the first direction x and the second direction y are staggered. For example, in the embodiment, the first direction x and the second direction y may be perpendicular, but the invention is not limited thereto.

Referring to fig. 1, 2 and 3, the data line DL and the gate line GL belong to different film layers. For example, in the present embodiment, the gate line GL may selectively belong to a first metal layer, and the data line DL may selectively belong to a second metal layer, but the invention is not limited thereto.

In view of conductivity, in the present embodiment, a metal material is used for the data line DL and the gate line GL. However, the invention is not limited thereto, and according to other embodiments, other conductive materials may be used for the data line DL and the gate line GL, such as: an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or a stacked layer of a metal material and other conductive materials.

Referring to fig. 1, the pixel array substrate 100 further includes a plurality of pixel structures PX disposed on the substrate 110. The plurality of pixel structures PX may be arranged in a plurality of pixel columns R. The plurality of pixel structures PX of each pixel row R are arranged in the first direction x, and the plurality of pixel rows R are arranged in the second direction y.

Referring to fig. 1, each pixel structure PX includes a tft T, a pixel electrode 182, and a bridge element 184. Referring to fig. 1 and 2, the thin film transistor T includes a source electrode Ta, a drain electrode Tb, a gate electrode Tc, a semiconductor pattern Td and a gate insulating layer 130, the gate insulating layer 130 is disposed between the gate electrode Tc and the semiconductor pattern Td, two different regions of the semiconductor pattern Td are electrically connected to the source electrode Ta and the drain electrode Tb, respectively, and the source electrode Ta and the gate electrode Tc are electrically connected to a corresponding data line DL and a corresponding gate line GL, respectively. Referring to fig. 2, in the present embodiment, the thin film transistor T may further optionally include an interlayer dielectric layer 140, wherein the interlayer dielectric layer 140 is disposed on the gate insulating layer 130 and covers the gate Tc, and the source Ta and the drain Tb may be electrically connected to two different regions of the semiconductor pattern Td through the plurality of contact windows 142 of the interlayer dielectric layer 140 and the plurality of contact windows 132 of the gate insulating layer 130. Referring to fig. 1, the pixel electrode 182 is disposed outside the drain Tb of the tft T, and the bridging element 184 electrically connects the drain Tb of the tft T and the pixel electrode 182.

Referring to fig. 2, in the present embodiment, the semiconductor pattern Td of the thin film transistor T may be selectively disposed between the gate Tc and the substrate 110. In other words, the thin film transistor T of the present embodiment may be a top gate thin film transistor (top gate TFT), but the invention is not limited thereto.

In the embodiment, the gate Tc may be selectively belonging to the first metal layer, and the source Ta and the drain Tb may be selectively belonging to the second metal layer, but the invention is not limited thereto. In the present embodiment, the material of the semiconductor pattern Td is, for example, Low Temperature Polysilicon (LTPS). However, the present invention is not limited thereto, and in other embodiments, the material of the semiconductor pattern Td may also be amorphous silicon, microcrystalline silicon, monocrystalline silicon, an organic semiconductor material, an oxide semiconductor material (e.g., indium zinc oxide, indium gallium zinc oxide, or other suitable materials, or combinations thereof), or other suitable materials.

Referring to fig. 1 and 2, in the embodiment, the pixel array substrate 100 may further selectively include a light shielding pattern SM and a buffer layer 120, the light shielding pattern SM is disposed on the substrate 110, the buffer layer 120 covers the light shielding pattern SM, and the semiconductor pattern Td of the thin film transistor T may be selectively disposed on the buffer layer 120 and overlapped with the light shielding pattern SM, but the invention is not limited thereto.

Referring to fig. 2, in the present embodiment, the pixel array substrate 100 further includes a first insulating layer 150, a common electrode layer 160 and a second insulating layer 170. Referring to fig. 1 and fig. 2, the first insulating layer 150 is disposed on the thin film transistors T of the pixel structures PX, the common electrode layer 160 is disposed on the first insulating layer 150, the second insulating layer 170 is disposed on the common electrode layer 160, the pixel electrode 182 of each pixel structure PX is disposed on the second insulating layer 170 and has a plurality of slits 182a, and the plurality of slits 182a overlap the common electrode layer 160.

For example, in the present embodiment, the common electrode layer 160 may belong to a first transparent conductive layer, which includes metal oxides, such as: indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, other suitable oxides, or a stack of at least two of the foregoing, but the invention is not limited thereto; the pixel electrode 182 may belong to a second transparent conductive layer, which includes metal oxides, such as: indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, other suitable oxides, or a stack of at least two of the foregoing, but the invention is not limited thereto. In addition, in the embodiment, the bridging element 184 and the pixel electrode 182 may belong to the same layer and be directly connected, but the invention is not limited thereto.

Referring to fig. 1 and 3, the pixel array substrate 100 further includes a plurality of patch cords gl disposed on the substrate 110. Referring to fig. 1, a plurality of via lines GL are arranged in a first direction x and electrically connected to a plurality of gate lines GL arranged in a second direction y.

Referring to fig. 1, fig. 2 and fig. 3, for example, in the present embodiment, the plurality of gate lines GL may selectively belong to a first metal layer, the plurality of via lines GL may selectively belong to a second metal layer, an interlayer dielectric layer 140 is disposed between the first metal layer and the second metal layer, the interlayer dielectric layer 140 has a plurality of contact windows 144 (shown in fig. 1), and the plurality of via lines GL may be electrically connected to the plurality of gate lines GL through the plurality of contact windows 144 of the interlayer dielectric layer 140, but the invention is not limited thereto.

Referring to fig. 1, each data line DL has a first side (e.g., a right side) and a second side (e.g., a left side) opposite to each other, a source Ta of a tft T of a pixel structure PX of a pixel row Rn and a source Ta of a tft T of a pixel structure PX of a next pixel row Rn +1 are electrically connected to the same data line DL, a drain Tb of the tft T of the pixel structure PX of the pixel row Rn and a drain Tb of the tft T of the pixel structure PX of the next pixel row Rn are located on the first side (e.g., the right side) of the same data line DL, a pixel electrode 182 of the pixel structure PX of the pixel row Rn and a pixel electrode 182 of the pixel structure PX of the next pixel row Rn +1 are located on the second side (e.g., the left side) and the first side (e.g., the right side) of the same data line DL, and the bridge elements 184 of the pixel structures PX of the pixel rows Rn cross the same data line DL and a transfer line gl. In short, in the present embodiment, the pixel electrodes 182 of the pixel structures PX electrically connected to the same data line DL are arranged in a substantially zigzag (zigzag) manner. Therefore, the aperture ratio of the pixel array substrate 100 can be improved.

Referring to fig. 1 and fig. 3, in the present embodiment, the bridging element 184 of the pixel structure PX of the pixel row Rn is disposed on the second insulating layer 170, and the common electrode layer 160 is disposed between the bridging element 184 of the pixel structure PX of the pixel row Rn and the patch line gl. The common electrode layer 160 can be used as a shielding layer to reduce the coupling effect between the switching line gl and the bridging device 184, and prevent the gate driving signal of the switching line gl from excessively affecting the potential of the pixel electrode 182 electrically connected to the bridging device 184. Therefore, the pixel array substrate 100 not only has a high aperture ratio, but also improves the problem of the slanted pattern.

In the present embodiment, the pixel electrode 182 of the pixel structure PX of the pixel row Rn is disposed on the second insulating layer 170, and the common electrode layer 160 is disposed between the pixel electrode 182 of the pixel structure PX of the pixel row Rn and the patch line gl. In other words, the common electrode layer 160 can be a shielding layer between the pixel electrode 182 and the transfer line gl to reduce the influence of the gate driving signal of the transfer line gl on the potential of the pixel electrode 182.

Referring to fig. 1, in the present embodiment, the bridging element 184 of the pixel structure PX of the pixel row Rn is staggered with the data line DL, and the bridging element 184 of the pixel structure PX of the next pixel row Rn +1 is disposed outside the data line DL and does not overlap with the data line DL. In other words, in the present embodiment, the plurality of pixel structures PX can be divided into a plurality of first-type pixel structures PXA and a plurality of second-type pixel structures PXB, wherein the bridge element 184 of each first-type pixel structure PXA crosses the data line DL, and the bridge element 184 of each second-type pixel structure PXB does not cross the data line DL. For example, in the present embodiment, the pixel structures PX of the odd pixel rows R (e.g., Rn) may be the first type pixel structures PXA, and the pixel structures PX of the even pixel rows R (e.g., Rn +1) may be the second type pixel structures PXB. In other words, the first type pixel structures PXA and the second type pixel structures PXB are alternately arranged in the second direction y.

Referring to fig. 1, in the present embodiment, the pixel electrodes 182 of the pixel structures PX are arranged in a plurality of pixel electrode rows C, the pixel electrodes 182 of each pixel electrode row C are arranged in the second direction y, the pixel electrode rows C are arranged in the first direction x, and the pixel electrode rows C include a first pixel electrode row Cr, a second pixel electrode row Cb, and a third pixel electrode row Cg for displaying red, blue, and green, respectively. In the embodiment, in the top view of the pixel array substrate 100, the transfer line gl can be selectively disposed between the first pixel electrode row Cr and the second pixel electrode row Cb for displaying red and blue colors, but the invention is not limited thereto.

It should be noted that the following embodiments follow the reference numerals and parts of the contents of the foregoing embodiments, wherein the same reference numerals are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, which will not be repeated below.

Fig. 4 is a schematic top view of a pixel array substrate 100A according to an embodiment of the invention.

The pixel array substrate 100A of fig. 4 is similar to the pixel array substrate 100 of fig. 1, and the difference therebetween is: the arrangement positions of the transfer lines gl are different.

Referring to fig. 4, in the top view of the pixel array substrate 100A, in the present embodiment, the plurality of patch cords gl are disposed between the second pixel electrode row Cb and the third pixel electrode row Cg for displaying blue and green, and between the first pixel electrode row Cr and the third pixel electrode row Cg for displaying red and green, in addition to being disposed between the first pixel electrode row Cr and the second pixel electrode row Cb for displaying red and blue.

Fig. 5 is a schematic top view of a pixel array substrate 100B according to an embodiment of the invention.

Fig. 6 is a schematic cross-sectional view of a pixel array substrate 100B according to an embodiment of the invention. Fig. 6 corresponds to the section line III-III' of fig. 5.

Fig. 7 is a schematic cross-sectional view of a pixel array substrate 100B according to an embodiment of the invention. Fig. 7 corresponds to the section line IV-IV' of fig. 5.

The pixel array substrate 100B of fig. 5, 6 and 7 is similar to the pixel array substrate 100 of fig. 1, 2 and 3, and the difference therebetween is that: the thin film transistors T are different between the two.

Referring to fig. 5, 6 and 7, in the present embodiment, the gate Tc of the thin film transistor T is disposed between the semiconductor pattern Td of the thin film transistor T and the substrate 110. In other words, the thin film transistor T of the present embodiment may be a bottom gate Thin Film Transistor (TFT). In addition, in the present embodiment, the material of the semiconductor pattern Td of the thin film transistor T is, for example, Amorphous silicon (Amorphous silicon).

In addition, in the present embodiment, the pixel array substrate 100B may not include the light shielding pattern SM, the buffer layer 120 and the interlayer dielectric layer 140 of the pixel array substrate 100. In the present embodiment, the pixel array substrate 100B includes a third insulating layer 190 (shown in fig. 6 and 7) disposed between the first insulating layer 150 and the second metal layer to which the transfer line gl and the data line DL belong. In addition, in the present embodiment, the patch line GL of the pixel array substrate 100B is electrically connected to the gate line GL through the contact window 134 (shown in fig. 5 and 7) of the gate insulating layer 130.

The pixel array substrate 100B has similar technical effects and advantages as the pixel array substrate 100, and thus, will not be repeated.