阅读说明：本技术 可伸缩式基板 (Telescopic substrate ) 是由 林恭正 于 2021-08-30 设计创作，主要内容包括：本发明公开一种可伸缩式基板,其包括图案化基板、多个装置部以及多个线路部。装置部位于图案化基板上。各装置部包括主动区以及环绕主动区的周边区。各装置部包括设置于主动区中的第一主动元件以及第二主动元件。线路部位于图案化基板上,且连接对应的装置部。(The invention discloses a retractable substrate, which comprises a patterned substrate, a plurality of device parts and a plurality of circuit parts. The device portion is located on the patterned substrate. Each device portion includes an active region and a peripheral region surrounding the active region. Each device portion comprises a first active element and a second active element which are arranged in the active area. The circuit part is positioned on the patterned substrate and is connected with the corresponding device part.)

1. A retractable substrate, comprising:

patterning the substrate;

a plurality of device portions on the patterned substrate, wherein each device portion includes an active region and a peripheral region surrounding the active region, and each device portion includes a first active device and a second active device disposed in the active region; and

and the circuit parts are positioned on the patterned substrate and connected with the corresponding device parts.

2. The retractable substrate of claim 1, wherein the peripheral region has a width of about 10 microns to about 250 microns.

3. The retractable substrate of claim 1, wherein each of the device parts comprises:

a first sub-pixel including the first active device and a first light emitting diode directly electrically connected to the first active device;

a second sub-pixel including a second active device and a second light emitting diode directly electrically connected to the second active device; and

a third sub-pixel including a third active device and a third light emitting diode directly electrically connected to the third active device, wherein the second sub-pixel is located between the first sub-pixel and the third sub-pixel; and is

Each circuit portion comprises at least one signal wire which is electrically connected to the corresponding first sub-pixel, the corresponding second sub-pixel and/or the corresponding third sub-pixel.

4. The retractable substrate of claim 3, wherein the shape of the semiconductor layer of the second active device is different from the shape of the semiconductor layer of the first active device and the shape of the semiconductor layer of the third active device.

5. The retractable substrate of claim 3, wherein the position of the first active device relative to the first LED, the position of the second active device relative to the second LED, and the position of the third active device relative to the third LED are different from each other.

6. The retractable substrate as claimed in claim 1, wherein each of the device parts has a rectangular shape with a length L and a width W, wherein:

the peripheral area has a width of 16% W to 40% W in a width direction of each of the device portions

The peripheral area has a width of 16% L to 40% L in a direction of a length of each of the device portions.

7. The retractable substrate of claim 1, wherein the patterned substrate has a plurality of through holes.

8. The retractable substrate of claim 6, wherein one of the through holes is substantially surrounded by at least four device portions.

9. The collapsible substrate of claim 6, further comprising:

and the connecting parts are arranged on the patterned substrate and are adjacent to the corresponding circuit parts, and each connecting part comprises a plurality of reinforcing structures which are arranged in sequence.

10. The retractable base of claim 6, wherein each of the through holes has a dumbbell shape.

Technical Field

The present invention relates to a stretchable substrate, and more particularly, to a stretchable substrate suitable for a display device.

Background

With the high development of electronic technology, electronic products are continuously being developed. In order to apply electronic products to various fields, the characteristics of being stretchable, light, thin and unlimited in appearance are gradually emphasized. That is, electronic products are required to have different shapes according to different application modes and application environments, and therefore, the electronic products need to have stretchability.

However, when the electronic product is stretched, the electronic product may be subjected to stress to cause structural fracture, and even further cause disconnection of the internal circuit. Therefore, how to make stretchable electronic products have good manufacturing yield (yield) and product reliability (reliability) is a problem to be solved.

Disclosure of Invention

The invention provides a telescopic substrate which can solve the problem that an active element is damaged after the telescopic substrate is stretched.

At least one embodiment of the present invention provides a retractable substrate. The retractable substrate includes a patterned substrate, a plurality of device portions, and a plurality of circuit portions. The device portion is located on the patterned substrate. Each device portion includes an active region and a peripheral region surrounding the active region. Each device portion includes a first active (active) element and a second active element disposed in an active region. The circuit part is positioned on the patterned substrate and is connected with the corresponding device part.

Drawings

FIG. 1A is a schematic top view of a retractable substrate according to an embodiment of the present invention;

FIG. 1B is a schematic top view of the retractable base of FIG. 1A after stretching;

FIG. 2 is a schematic diagram of a strain simulation of the retractable substrate of FIG. 1B;

FIG. 3A is a schematic top view of a retractable substrate according to an embodiment of the present invention;

FIG. 3B is a schematic top view of the retractable substrate of FIG. 3A with some components omitted;

FIG. 3C is a schematic top view of the retractable base plate of FIG. 3A with some components omitted;

FIG. 3D is a schematic cross-sectional view of the retractable base plate of FIG. 3A;

FIG. 3E is an equivalent circuit diagram of a sub-pixel according to an embodiment of the invention;

FIG. 4 is a schematic top view of a retractable substrate according to an embodiment of the present invention;

fig. 5 is a schematic top view of a retractable substrate according to an embodiment of the present invention.

Description of the symbols

10. 20, 30, 40 retractable substrate

100 patterned substrate

200 device part

300 line part

310 signal line

400 connecting part

410 reinforcing structure

AR active region

BL buffer layer

Semiconductor layer of CHa, CHb, CHc, CHd, CHE, CHf

CL1 first conductive layer

CL2 second conductive layer

CL3 third conductive layer

Da. Db, Dc, Dd, De, Df drain

DL1 first data line

DL2 second data line

DL3 third data line

Ga. Gb, Gc, Gd, Ge, Gf gate

GI. ILD insulating layer

L is length

L1 first light emitting diode

L2 second light emitting diode

L3 third light-emitting diode

PD1, PD2, PD3, PD4, PD5 and PD6 contact pads

PL planar layer

PL1 first Power line

PL2 second Power line

PR peripheral zone

Sa, Sb, Sc, Sd, Se, Sf source

SE1 first switching element

SE2 second switching element

SE3 third switching element

SP1 first sub-pixel

SP2 second sub-pixel

SP3 third sub-pixel

SGL signal line

SL scanning line

TH a through hole

T1 first active element

T2 second active element

T3 third active element

V is a via hole

W, W1, W2 width

Detailed Description

Fig. 1A is a schematic top view of a retractable substrate 10 according to an embodiment of the present invention.

Referring to fig. 1A, the retractable substrate 10 includes a patterned substrate 100, a plurality of device portions 200, and a plurality of circuit portions 300. In this embodiment, the retractable substrate 10 further includes a connecting portion 400.

The patterned substrate 100 is made of a flexible material, for example, the material of the patterned substrate 100 may include Polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), Polycarbonate (PC), Polyethersulfone (PES), or polyarylate, other suitable materials, or a combination of at least two of the foregoing materials, but the invention is not limited thereto.

In the present embodiment, the patterned substrate 100 has a plurality of through holes TH. In this embodiment, each through hole TH has a dumbbell shape. In this embodiment, a portion of the through hole TH extends along the first direction E1, and another portion of the through hole TH extends along the second direction E2. The partial through holes TH extending along the first direction E1 and the other partial through holes TH extending along the second direction E2 are alternately arranged, thereby improving the flexibility of the retractable substrate 10.

The device portion 200, the line portion 300, and the connection portion 400 are located on the patterned substrate 100. The device portion 200, the circuit portion 300 and the connection portion 400 are connected together, and one of the through holes TH is substantially surrounded by at least four device portions 200. In the present embodiment, one through hole TH is substantially surrounded by four device parts 200, two circuit parts 300, and two connection parts 400. For example, in fig. 1A, the through hole TH at the center is surrounded by two circuit portions 300 at the left and right, two connecting portions 400 at the upper and lower, and the device portions 200 at four corners.

Each device portion 200 includes an active region AR and a peripheral region PR surrounding the active region AR. Each device section 200 includes a first active device T1 and a second active device T2 disposed in the active region AR. In the present embodiment, each device portion 200 further includes a third active element T3. In some embodiments, each device portion 200 is rectangular with a length L and a width W, the width W1 of the peripheral region PR in the direction of the width W of each device portion 200 is 16% W to 40% W, and the width W2 of the peripheral region PR in the direction of the length L of each device portion 200 is 16% L to 40% L. The width W1 and the width W2 of the peripheral region PR are 10 to 250 μm.

In the present embodiment, each device section 200 includes a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3, wherein the second sub-pixel SP2 is located between the first sub-pixel SP1 and the third sub-pixel SP 3. The first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 respectively include a first active device T1, a second active device T2 and a third active device T3, and the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 respectively include a first light emitting diode (not shown in fig. 1A), a second light emitting diode (not shown in fig. 1A) and a third light emitting diode (not shown in fig. 1A). The first active device T1, the second active device T2, and the third active device T3 are respectively adapted to drive the first light emitting diode, the second light emitting diode, and the third light emitting diode.

In the present embodiment, the retractable substrate 10 is suitable for a display device, but the invention is not limited thereto. In other embodiments, the retractable substrate 10 is not a display device, and the device portion 200 does not include sub-pixels.

The line unit 300 is connected to the corresponding device unit 200. In the present embodiment, each line unit 300 connects two corresponding device units 200. Each circuit portion 300 includes at least one signal line 310. The signal line 310 is electrically connected to the corresponding first sub-pixel SP1, the corresponding second sub-pixel SP2, and/or the corresponding third sub-pixel SP 3. Although fig. 1A shows that the signal line 310 extends to the edge of the device part 200, in practice, many other conductive lines (not shown in fig. 1A) are included in the device part 200, thereby electrically connecting the signal line 310 to the corresponding first sub-pixel SP1, the corresponding second sub-pixel SP2, and/or the corresponding third sub-pixel SP 3.

The connection portions 400 are adjacent to the corresponding line portions 300. In the present embodiment, each connection portion 400 connects two corresponding device portions 200 and is located on one side of a corresponding one of the line portions 300. Each of the connection portions 400 includes a plurality of reinforcing structures 410 arranged in sequence. The reinforcing structure 410 is spaced apart from the signal line 310. In some embodiments, the reinforcing structure 410 can adjust the neutral axis position of the connecting portion 400 and the circuit portion 300, and reduce the risk of the signal wire 310 breaking due to stretching. In addition, since the reinforcing structure 410 is spaced apart from the signal line 310, even if the reinforcing structure 410 is cracked, the crack is not easily extended to the signal line 310, which may cause the signal line 310 to be broken. In some embodiments, the reinforcing structure 410 is a spare wire. In some embodiments, the reinforcing structure 410 is an insulating pattern.

Fig. 1B is a schematic top view of the retractable substrate 10 of fig. 1A after stretching. Fig. 2 is a diagram showing a strain amount simulation of the retractable substrate of fig. 1B, wherein the numerical values on the left side in fig. 2 represent strain amounts.

Referring to fig. 1B and fig. 2, the retractable substrate 10 is stretched and deformed. In this embodiment, the retractable substrate 10 is subjected to different directions of pulling forces F, which change the shape of the retractable substrate 10. As can be seen from the simulation diagram of fig. 2, in the device portion 200, the peripheral region PR near the periphery is more likely to have larger strain than the central active region AR, so that the first active device T1, the second active device T2 and the third active device T3 are disposed in the active region AR instead of the peripheral region PR, thereby avoiding the failure problem of the first active device T1, the second active device T2 and the third active device T3 after the retractable substrate 10 is stretched.

In some embodiments, the first active device T1, the second active device T2, and the third active device T3 are directly electrically connected to the driving device of the light emitting diode, i.e., there is no other thin film transistor between the first active device T1, the second active device T2, and the third active device T3 and the corresponding light emitting diode, so the quality of the first active device T1, the second active device T2, and the third active device T3 has a larger effect on the display than other thin film transistors (e.g., switching devices) in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP 3. Therefore, the problem of Mura after stretching of the retractable substrate 10 can be better improved by disposing the first active device T1, the second active device T2, and the third active device T3 in the active area AR than by disposing other tfts not directly electrically connected to the leds in the active area AR.

Fig. 3A is a schematic top view of a retractable substrate 20 according to an embodiment of the present invention, wherein in order to more clearly illustrate the retractable substrate 20 of fig. 3A, some components of the retractable substrate 20 are omitted and are shown in fig. 3B and fig. 3C, in fig. 3A to fig. 3D, the conductive layers of different layers (i.e., the conductive layers formed by the same patterning process) are shown with the same oblique lines or dots, and the conductive layers of different layers are electrically connected through via holes V penetrating through the insulating layer (e.g., the insulating layer GI and/or the insulating layer ILD). Fig. 3D is a schematic cross-sectional view of line a-a' of fig. 3A. Fig. 3E is an equivalent circuit diagram of a sub-pixel according to an embodiment of the invention, in the embodiment, the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 have similar equivalent circuits, and fig. 3E takes the equivalent circuit of the first sub-pixel SP1 as an example.

It should be noted that the embodiment of fig. 3A to 3E uses the element numbers and part of the contents of the embodiment of fig. 1A and 1B, wherein the same or similar elements are denoted by the same or similar reference numbers, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.

Referring to fig. 3A to 3E, the device portion 200 and the circuit portion 300 are disposed on the patterned substrate 100. In some embodiments, the surface of the patterned substrate 100 is provided with a buffer layer BL, and the device portion 200 and the circuit portion 300 are located on the buffer layer BL.

Each line section 300 includes a plurality of signal lines SGL. The signal line SGL is a scan line SL, a first data line DL1, a second data line DL2, a third data line DL3, a first power line PL1, and/or a second power line PL 2.

Each device section 200 includes a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP 3.

The first sub-pixel SP1 includes a first switching element SE1, a first active element T1, and a first light emitting diode L1. The first switching element SE1 includes a semiconductor layer CHa, a gate Ga, a source Sa, and a drain Da. The gate Ga is electrically connected to the scan line SL. The gate Ga overlaps the channel layer CHa with the insulating layer GI interposed therebetween. An insulating layer ILD covers the gate Ga. The source Sa and the drain Da are on the insulation layer ILD and electrically connected to the channel layer CHa. The source Sa is electrically connected to the first data line DL 1.

The first active device T1 includes a semiconductor layer CHb, a gate Gb, a source Sb and a drain Db. The gate Gb is electrically connected to the drain Da of the first switching element SE 1. The gate electrode Gb overlaps the channel layer CHb with the insulating layer GI interposed therebetween. The insulating layer ILD covers the gate electrode Gb. The source Sb and the drain Db are on the insulating layer ILD and electrically connected to the channel layer CHb. Source Sb is electrically connected to first power supply line PL 1.

The planarization layer PL is disposed on the source electrode Sa, the drain electrode Da, the source electrode Sb, and the drain electrode Db, and the first light emitting diode L1 is disposed on the planarization layer PL. In some embodiments, the first light emitting diode L1 is electrically connected to the source Sb and the second power line PL2 through the pad PD1 and the pad PD2, respectively.

The second sub-pixel SP2 includes a second switching element SE2, a second active element T2, and a second light emitting diode L2. The second switching element SE2 includes a semiconductor layer CHc, a gate Gc, a source Sc, and a drain Dc. The gate Gc is electrically connected to the scan line SL. The gate Gc overlaps the channel layer CHc with the insulating layer GI interposed therebetween. The insulating layer ILD covers the gate Gc. The source Sc and the drain Dc are on the insulating layer ILD and electrically connected to the channel layer CHc. The source Sc is electrically connected to the second data line DL 2.

The second active device T2 includes a semiconductor layer CHd, a gate Gd, a source Sd and a drain Dd. The gate Gd is electrically connected to the drain Dc of the second switching element SE 2. The gate Gd overlaps the channel layer CHd with the insulating layer GI interposed therebetween. An insulating layer ILD covers the gate Gd. The source Sd and the drain Dd are on the insulating layer ILD and electrically connected to the channel layer CHd. The source Sd is electrically connected to the first power supply line PL 1.

The second light emitting diode L2 is located on the planarization layer PL. In some embodiments, the second light emitting diode L2 is electrically connected to the source Sd and the second power line PL2 through the pad PD3 and the pad PD4, respectively.

The third sub-pixel SP3 includes a third switching element SE3, a third active element T3, and a third light emitting diode L3. The third switching element SE3 includes a semiconductor layer CHe, a gate Ge, a source SE, and a drain De. The gate Ge is electrically connected to the scan line SL. The gate Ge overlaps the channel layer CHe with the insulating layer GI therebetween. An insulating layer ILD covers the gate Ge. The source Se and the drain De are on the insulating layer ILD and electrically connected to the channel layer CHe. The source Se is electrically connected to the second data line DL 3.

The third active device T3 includes a semiconductor layer CHf, a gate Gf, a source S and a drain Df. The gate Gf is electrically connected to the drain De of the third switching element SE 3. The gate Gf overlaps the channel layer CHf with the insulating layer GI interposed therebetween. An insulating layer ILD covers the gate Gf. The source Sf and the drain Df are on the insulating layer ILD and are electrically connected to the channel layer CHf. The source Sf is electrically connected to the first power line PL 1.

The third light emitting diode L3 is located on the planarization layer PL. In some embodiments, the third light emitting diode L3 is electrically connected to the source Sf and the second power line PL2 through the pad PD5 and the pad PD6, respectively. In the present embodiment, the position of the first active device T1 relative to the first led L1, the position of the second active device T2 relative to the second led L2, and the position of the third active device T3 relative to the third led L3 are different from each other, so that the first led L1, the second active device T2, and the third active device T3 can be more easily disposed in the active region AR.

In some embodiments, the pads PD1 through PD6 have a multi-layer structure, for example, each of the pads PD1 through PD6 includes a first pad layer CL1, a second conductive layer CL2, and a third conductive layer CL 3. In some embodiments, the first conductive layer CL1 is a metal oxide (e.g., indium tin oxide), the second conductive layer CL2 is a metal (e.g., indium), and the third conductive layer CL3 is a metal (e.g., gold), but the invention is not limited thereto. In the present embodiment, the first light emitting diode L1, the second light emitting diode L2, and the third light emitting diode L3 are inorganic light emitting diodes (such as micro-LEDs), but the invention is not limited thereto. In other embodiments, the first led L1, the second led L2, and the third led L3 are organic leds, electroluminescent devices, or other self-emitting devices.

In the present embodiment, in order to prevent the signal lines transmitting different signals from being short-circuited, each signal line selectively includes different conductive layers, and the different conductive layers are electrically connected to each other through the via hole V.

In this embodiment, the semiconductor layer CHb of the first active device T1, the semiconductor layer CHd of the second active device T2, and the semiconductor layer CHf of the third active device T3 are disposed in the active region AR but not in the peripheral region PR around the active region AR, thereby avoiding the problem of the failure of the retractable substrate 20 after stretching and resulting in the Mura.

In this embodiment, the first active device T1, the second active device T2, and the third active device T3 are directly electrically connected to the first light emitting diode L1, the second light emitting diode L2, and the third light emitting diode L3, respectively, so the quality of the first active device T1, the second active device T2, and the third active device T3 has a larger effect on the display than the first switch device SE1, the second switch device SE2, and the third switch device SE 3. In some embodiments, based on the limitation of the wiring space, the first active device T1, the second active device T2, the third active device T3, the first switch device SE1, the second switch device SE2, and the third switch device SE3 may not be all disposed in the active area AR, and the disposing of the first active device T1, the second active device T2, and the third active device T3 in the active area AR may preferably improve the problem of the frame Mura occurring after the retractable substrate 20 is stretched, but the invention is not limited thereto. In other embodiments, if the wiring space is sufficient, the first active device T1, the second active device T2, the third active device T3, the first switching element SE1, the second switching element SE2, and the third switching element SE3 are disposed in the active region AR.

Fig. 4 is a schematic top view illustrating a retractable substrate according to an embodiment of the present invention, wherein fig. 4 illustrates a semiconductor layer of a first active device T1 in a first sub-pixel SP1, a semiconductor layer of a second active device T2 in a second sub-pixel SP2, and a semiconductor layer of a third active device T3 in a third sub-pixel SP3, and other components in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are omitted.

It should be noted that the embodiment of fig. 4 follows the element numbers and partial contents of the embodiment of fig. 3A to 3E, wherein the same or similar elements are denoted by the same or similar reference numbers, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.

Referring to fig. 4, in the present embodiment, the shape of the second active device T2 of the retractable substrate 30 is different from the shape of the first active device T1 and the shape of the third active device T3. For example, the shape of the semiconductor layer of the second active device T2 is different from the shape of the semiconductor layer of the first active device T1 and the shape of the semiconductor layer of the third active device T3. In the present embodiment, the semiconductor layer of the second active device T2 is substantially straight, and the semiconductor layer of the first active device T1 and the semiconductor layer of the third active device T3 are substantially L-shaped. The L-shaped or bent semiconductor layer can disperse the stress, thereby reducing the adverse electrical effect of the semiconductor layer caused by strain or stress.

In some embodiments, each device portion 200 is rectangular with a length L and a width W, the width W1 of the peripheral region PR in the direction of the width W of each device portion 200 is 16% W to 40% W, and the width W2 of the peripheral region PR in the direction of the length L of each device portion 200 is 16% L to 40% L.

Based on the above, the semiconductor layer of the first active device T1, the semiconductor layer of the second active device T2, and the semiconductor layer of the third active device T3 are disposed in the active region AR but not in the peripheral region PR around the active region AR, thereby avoiding the problem of the frame Mura caused by the failure of the retractable substrate 30 after stretching.

Fig. 5 is a schematic top view illustrating a retractable substrate according to an embodiment of the present invention, wherein fig. 5 illustrates a semiconductor layer of a first active device T1 in a first sub-pixel SP1, a semiconductor layer of a second active device T2 in a second sub-pixel SP2, and a semiconductor layer of a third active device T3 in a third sub-pixel SP3, and other components in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are omitted.

It should be noted that the embodiment of fig. 5 follows the element numbers and partial contents of the embodiment of fig. 3A to 3E, wherein the same or similar elements are denoted by the same or similar reference numbers, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.

Referring to fig. 5, in the present embodiment, the shape of the second active device T2 of the retractable substrate 40 is different from the shape of the first active device T1 and the shape of the third active device T3. For example, the shape of the semiconductor layer of the second active device T2 is different from the shape of the semiconductor layer of the first active device T1 and the shape of the semiconductor layer of the third active device T3. In the present embodiment, the semiconductor layer of the first active device T1 and the semiconductor layer of the third active device T3 are substantially straight strips, and the semiconductor layer of the second active device T2 is substantially S-shaped.

The S-shaped or bent semiconductor layer can disperse the stress, thereby reducing the adverse electrical effect of the semiconductor layer caused by strain or stress.

The current of the semiconductor layer with longer length is smaller under the same voltage difference. In the present embodiment, the length of the semiconductor layer of the second active device T2 is longer and can be configured corresponding to the blue sub-pixel. The semiconductor layers of the first active device T1 and the third active device T3 are shorter in length and are disposed corresponding to the red sub-pixel and the green sub-pixel, respectively.

In some embodiments, each device portion 200 is rectangular with a length L and a width W, the width W1 of the peripheral region PR in the direction of the width W of each device portion 200 is 16% W to 40% W, and the width W2 of the peripheral region PR in the direction of the length L of each device portion 200 is 16% L to 40% L.

Based on the above, the semiconductor layer of the first active device T1, the semiconductor layer of the second active device T2, and the semiconductor layer of the third active device T3 are disposed in the active region AR but not in the peripheral region PR around the active region AR, thereby avoiding the problem of the frame Mura caused by the failure of the retractable substrate 40 after stretching.