阅读说明：本技术 显示基板及其制备方法、显示装置 (Display substrate, preparation method thereof and display device ) 是由 陈腾 史大为 王文涛 赵天龙 王玲玲 刘珂 方飞 于 2021-09-13 设计创作，主要内容包括：一种显示基板,包括：衬底基板。衬底基板包括第一显示区,第一显示区包括透光区以及至少一个子显示区。在垂直于显示基板的平面内,子显示区的显示基板至少包括：设置在衬底基板上的半导体层、第一导电层、第二导电层、第三导电层以及透明导电层。透明导电层与第三导电层直接接触,且透明导电层覆盖第三导电层。(A display substrate, comprising: a base substrate. The substrate base plate comprises a first display area, and the first display area comprises a light-transmitting area and at least one sub-display area. In a plane perpendicular to the display substrate, the display substrate of the sub-display area includes at least: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a transparent conductive layer disposed on the base substrate. The transparent conductive layer is in direct contact with the third conductive layer, and the transparent conductive layer covers the third conductive layer.)

1. A display substrate, comprising:

the substrate comprises a first display area, a second display area and a third display area, wherein the first display area comprises a light-transmitting area and at least one sub-display area;

in a plane perpendicular to the display substrate, the display substrate of the sub-display area includes at least: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a transparent conductive layer which are arranged on the substrate;

the transparent conductive layer is in direct contact with the third conductive layer, and the transparent conductive layer covers the third conductive layer.

2. The display substrate according to claim 1, wherein a first insulating layer is provided between the semiconductor layer and a first conductive layer, a second insulating layer is provided between the first conductive layer and a second conductive layer, and a third insulating layer is provided between the second conductive layer and a third conductive layer;

in a plane perpendicular to the display substrate, the display substrate of the light-transmitting region includes: the first insulating layer, the second insulating layer, the third insulating layer, and the transparent conductive layer are disposed on the substrate base plate.

3. The display substrate of claim 1, wherein the display substrate of the sub-display region further comprises: the anode layer is positioned on one side of the transparent conducting layer, which is far away from the substrate; at least a first inorganic insulating layer is arranged between the transparent conducting layer and the anode layer;

at least one organic insulating layer is arranged between the first inorganic insulating layer and the anode layer of the sub-display area, and the orthographic projection of the organic insulating layer on the substrate does not overlap with the light-transmitting area.

4. The display substrate according to any one of claims 1 to 3, wherein the first display region is provided with a plurality of first sub-pixels, a plurality of first signal lines extending in a first direction, and a plurality of second signal lines extending in a second direction; the first direction intersects with a second direction;

the plurality of first sub-pixels are located in the at least one sub-display region, at least one of the plurality of first sub-pixels includes a light emitting element and a pixel circuit connected to the light emitting element, and the pixel circuit is electrically connected to at least one of the plurality of first signal lines and at least one of the plurality of second signal lines;

the first signal line and the second signal line are located on the transparent conductive layer.

5. The display substrate according to claim 4, wherein the at least one first signal line comprises a plurality of first sub-signal lines, and adjacent first sub-signal lines are electrically connected through the pixel circuit.

6. The display substrate according to claim 4, wherein the plurality of first signal lines comprise at least one of: the display device comprises a scanning line, a reset signal line, an initial voltage line, a light-emitting control line and a first connecting line;

the plurality of second signal lines include at least one of: data line, first power cord.

7. The display substrate of claim 6, wherein the first connection line and the first power line are connected to the pixel circuit, and the first connection line and the first power line form a mesh-type routing structure for transmitting a first voltage signal in the first display area.

8. The display substrate of claim 4, wherein the substrate base further comprises: a second display area located on at least one side of the first display area, and a peripheral area at least partially surrounding the first display area and the second display area;

the second display area is provided with a plurality of third signal lines extending along the first direction and a plurality of fourth signal lines extending along the second direction;

at least one of the first signal lines is connected to at least one of the third signal lines, and at least one of the second signal lines is connected to at least one of the fourth signal lines;

the at least one third signal line is positioned on one side of the connected first signal line close to the substrate base plate, and the at least one fourth signal line is positioned on one side of the connected second signal line close to the substrate base plate.

9. The display substrate according to claim 8, wherein the at least one third signal line is located in the first conductive layer or the second conductive layer, and wherein the at least one fourth signal line is located in the third conductive layer.

10. The display substrate according to claim 8, wherein the second display region is further provided with a plurality of second sub-pixels; the pixel circuit of at least one of the plurality of second sub-pixels is connected to at least one third signal line and at least one fourth signal line.

11. A display device comprising the display substrate according to any one of claims 1 to 10.

12. A method for preparing a display substrate is characterized by comprising the following steps:

sequentially forming a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer and a transparent conductive layer on the substrate base plate of the sub-display area of the first display area of the substrate base plate; wherein the transparent conductive layer is in direct contact with a third conductive layer, and the transparent conductive layer covers the third conductive layer.

13. The method of manufacturing according to claim 12, further comprising: and sequentially forming a first insulating layer, a second insulating layer, a third insulating layer and a transparent conducting layer on the substrate base plate of the light transmitting area of the first display area of the substrate base plate.

14. The method of manufacturing according to claim 12, further comprising: forming a first inorganic insulating layer on one side, far away from the substrate, of the transparent conductive layer of the first display area;

and forming at least one organic insulating layer on one side of the first inorganic insulating layer of the first display area, which is far away from the substrate base plate, and removing the organic insulating layer of the light transmission area of the first display area.

Technical Field

The present disclosure relates to but not limited to the field of display technologies, and in particular, to a display substrate, a method for manufacturing the same, and a display device.

Background

Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting diodes (QLEDs) are active Light Emitting display devices, and have the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high reaction speed, lightness, thinness, flexibility, low cost, and the like. With the continuous development of display technology, a camera is usually installed on a display device to meet the shooting requirement.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the disclosure provides a display substrate, a preparation method thereof and a display device.

In one aspect, an embodiment of the present disclosure provides a display substrate, including: a base substrate. The substrate base plate comprises a first display area, and the first display area comprises a light-transmitting area and at least one sub-display area. In a plane perpendicular to the display substrate, the display substrate of the sub-display area includes at least: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a transparent conductive layer disposed on the base substrate. The transparent conductive layer is in direct contact with the third conductive layer, and the transparent conductive layer covers the third conductive layer.

In some exemplary embodiments, a first insulating layer is disposed between the semiconductor layer and the first conductive layer, a second insulating layer is disposed between the first conductive layer and the second conductive layer, and a third insulating layer is disposed between the second conductive layer and the third conductive layer. In a plane perpendicular to the display substrate, the display substrate of the light-transmitting region includes: the first insulating layer, the second insulating layer, the third insulating layer and the transparent conducting layer are arranged on the substrate base plate.

In some exemplary embodiments, the display substrate of the sub-display region further includes: and the anode layer is positioned on one side of the transparent conducting layer, which is far away from the substrate. At least a first inorganic insulating layer is disposed between the transparent conductive layer and the anode layer. At least one organic insulating layer is arranged between the first inorganic insulating layer and the anode layer of the sub-display area, and the orthographic projection of the organic insulating layer on the substrate does not overlap with the light-transmitting area.

In some exemplary embodiments, the first display region is provided with a plurality of first sub-pixels, a plurality of first signal lines extending in a first direction, and a plurality of second signal lines extending in a second direction; the first direction intersects the second direction. The plurality of first sub-pixels are located in the at least one sub-display region, at least one of the plurality of first sub-pixels includes a light emitting element and a pixel circuit connected to the light emitting element, and the pixel circuit is electrically connected to at least one of the plurality of first signal lines and at least one of the plurality of second signal lines. The first signal line and the second signal line are located on the transparent conductive layer.

In some exemplary embodiments, the at least one first signal line includes a plurality of first sub-signal lines, and adjacent first sub-signal lines are electrically connected through the pixel circuit.

In some exemplary embodiments, the plurality of first signal lines includes at least one of: scanning line, reset signal line, initial voltage line, luminous control line, first connecting wire. The plurality of second signal lines include at least one of: data line, first power cord.

In some exemplary embodiments, the first connection line and the first power line are both connected to the pixel circuit, and the first connection line and the first power line form a mesh routing structure for transmitting a first voltage signal in the first display area.

In some exemplary embodiments, the substrate base plate further includes: the display device comprises a first display area, a second display area and a peripheral area, wherein the first display area is positioned on at least one side of the first display area, and the peripheral area at least partially surrounds the first display area and the second display area. The second display area is provided with a plurality of third signal lines extending in the first direction and a plurality of fourth signal lines extending in the second direction. At least one of the first signal lines is connected to at least one of the third signal lines, and at least one of the second signal lines is connected to at least one of the fourth signal lines. The at least one third signal line is positioned on one side of the connected first signal line close to the substrate base plate, and the at least one fourth signal line is positioned on one side of the connected second signal line close to the substrate base plate.

In some exemplary embodiments, the at least one third signal line is located at the first conductive layer or the second conductive layer, and the at least one fourth signal line is located at the third conductive layer.

In some exemplary embodiments, the second display region is further provided with a plurality of second sub-pixels; the pixel circuit of at least one of the plurality of second sub-pixels is connected to at least one third signal line and at least one fourth signal line.

In another aspect, an embodiment of the present disclosure provides a display device including the display substrate as described above.

On the other hand, the embodiment of the present disclosure further provides a method for manufacturing a display substrate, including: sequentially forming a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer and a transparent conductive layer on the substrate base plate of the sub-display area of the first display area of the substrate base plate; wherein the transparent conductive layer is in direct contact with a third conductive layer, and the transparent conductive layer covers the third conductive layer.

In some exemplary embodiments, the preparation method further comprises: and sequentially forming a first insulating layer, a second insulating layer, a third insulating layer and a transparent conducting layer on the substrate base plate of the light transmitting area of the first display area of the substrate base plate.

In some exemplary embodiments, the preparation method further comprises: forming a first inorganic insulating layer on one side, far away from the substrate, of the transparent conductive layer of the first display area; and forming at least one organic insulating layer on one side of the first inorganic insulating layer of the first display area, which is far away from the substrate base plate, and removing the organic insulating layer of the light transmission area of the first display area.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the example serve to explain the principles of the disclosure and not to limit the disclosure. The shapes and sizes of one or more of the elements in the drawings are not to be considered as true scale, but rather are merely intended to illustrate the present disclosure.

Fig. 1 is a schematic view of a display substrate according to at least one embodiment of the present disclosure;

fig. 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

FIG. 3 is a timing diagram illustrating operation of the pixel circuit shown in FIG. 2;

FIG. 4 is a schematic view of a portion of a display substrate according to at least one embodiment of the present disclosure;

fig. 5 is a partial schematic plan view of a first display area according to at least one embodiment of the present disclosure;

FIG. 6 is a schematic partial cross-sectional view taken along line O-O' of FIG. 5;

FIG. 7 is a schematic partial cross-sectional view taken along line Q-Q' of FIG. 5;

fig. 8 is a schematic partial plan view of a first display region after a semiconductor layer is formed in accordance with at least one embodiment of the present disclosure;

fig. 9 is a schematic partial plan view of a first display region after a first conductive layer is formed according to at least one embodiment of the disclosure;

fig. 10 is a schematic partial plan view of a first display region after a second conductive layer is formed in accordance with at least one embodiment of the present disclosure;

fig. 11 is a partial schematic plan view of the first display region after forming the third insulating layer according to at least one embodiment of the disclosure;

fig. 12 is a schematic partial plan view of the first display region after forming the third conductive layer according to at least one embodiment of the disclosure;

fig. 13 is a schematic partial plan view of a first display region after a transparent conductive layer is formed according to at least one embodiment of the disclosure;

fig. 14 is a partial schematic plan view of the first display region after forming a fourth insulating layer according to at least one embodiment of the disclosure;

fig. 15 is a partial schematic plan view of a first display region after forming a first planarization layer according to at least one embodiment of the present disclosure;

fig. 16 is a schematic partial plan view of a first display region after an anode layer is formed according to at least one embodiment of the disclosure;

fig. 17 is a schematic view of a process for preparing a transparent conductive layer, a fourth insulating layer, a first planarization layer, and an anode layer according to at least one embodiment of the present disclosure;

fig. 18 is a schematic view of a display device according to at least one embodiment of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments may be embodied in many different forms. One of ordinary skill in the art can readily appreciate the fact that the manner and content can be modified into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be arbitrarily combined with each other without conflict.

In the drawings, the size of one or more constituent elements, the thickness of layers, or regions may be exaggerated for clarity. Accordingly, one aspect of the disclosure is not necessarily limited to the dimensions, and the shapes and sizes of one or more components in the drawings are not intended to reflect actual proportions. Further, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

The ordinal numbers such as "first", "second", "third", and the like in the present specification are provided for avoiding confusion among the constituent elements, and are not limited in number. The "plurality" in the present disclosure means two or more numbers.

In this specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating orientations or positional relationships are used to explain positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the described directions of the constituent elements. Therefore, the words described in the specification are not limited to the words described in the specification, and may be replaced as appropriate.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically indicated and limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; may be a mechanical connection, or a connection; either directly or indirectly through intervening components, or both may be interconnected. The meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having some kind of electrical action" is not particularly limited as long as it can transmit an electrical signal between connected components. Examples of the "element having a certain electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having a plurality of functions, and the like.

In this specification, a transistor refers to an element including at least three terminals, i.e., a gate, a drain, and a source. The transistor has a channel region between a drain (a drain electrode terminal, a drain region, or a drain electrode) and a source (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to a region through which current mainly flows.

In this specification, the first pole may be a drain and the second pole may be a source, or the first pole may be a source and the second pole may be a drain. In the case where transistors of opposite polarities are used, or in the case where the direction of current flow during circuit operation changes, the functions of the "source" and the "drain" may be interchanged. Therefore, in this specification, "source" and "drain" may be interchanged with each other.

In the present specification, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and therefore, includes a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which the angle is 85 ° or more and 95 ° or less.

"light transmission" in this disclosure refers to the ability of light to transmit through a medium and is the percentage of the amount of light transmitted through a transparent or translucent body as compared to the amount of light incident upon it.

"about" and "approximately" in this disclosure refer to the situation where the limits are not strictly defined, allowing for process and measurement tolerances. In the present disclosure, "substantially the same" means that the numerical values are within 10% of each other.

At least one embodiment of the present disclosure provides a display substrate, including: a base substrate. The substrate base plate comprises a first display area, and the first display area comprises a light-transmitting area and at least one sub-display area. In a plane perpendicular to the display substrate, the display substrate of the sub-display area includes at least: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a transparent conductive layer disposed on the base substrate. The transparent conductive layer is in direct contact with the third conductive layer, and the transparent conductive layer covers the third conductive layer.

The display substrate that this embodiment provided, through setting up transparent conducting layer and third conducting layer direct contact, and transparent conducting layer covers the third conducting layer, can utilize transparent conducting layer to arrange the signal line to improve the light transmissivity in first display area, and prevent light diffraction.

In some exemplary embodiments, a first insulating layer is disposed between the semiconductor layer and the first conductive layer, a second insulating layer is disposed between the first conductive layer and the second conductive layer, and a third insulating layer is disposed between the second conductive layer and the third conductive layer. The display substrate of the light transmission region includes, in a plane perpendicular to the display substrate: the first insulating layer, the second insulating layer, the third insulating layer and the transparent conducting layer are arranged on the substrate base plate. In this example, the light-transmitting region is not provided with the non-light-transmitting conductive layer, and the light transmittance of the light-transmitting region can be improved.

In some exemplary embodiments, the display substrate of the sub-display region further includes: and the anode layer is positioned on one side of the transparent conducting layer, which is far away from the substrate. At least a first inorganic insulating layer is disposed between the transparent conductive layer and the anode layer. At least one organic insulating layer is arranged between the first inorganic insulating layer and the anode layer of the sub-display area, and the orthographic projection of the organic insulating layer on the substrate does not overlap with the light-transmitting area. In this example, the first inorganic insulating layer covers the transparent conductive layer, so that corrosion of the transparent conductive layer in the preparation process of the anode layer can be avoided; moreover, the organic insulating layer in the light transmitting area is removed, so that the light transmittance of the light transmitting area can be improved, and the yellow of transmitted light can be reduced.

In some exemplary embodiments, the first display region is provided with a plurality of first sub-pixels, a plurality of first signal lines extending in a first direction, and a plurality of second signal lines extending in a second direction. The first direction intersects the second direction. For example, the first direction is perpendicular to the second direction. The plurality of first sub-pixels are located in the sub-display area, at least one first sub-pixel comprises a light emitting element and a pixel circuit connected with the light emitting element, and the pixel circuit is electrically connected with at least one first signal line and at least one second signal line. The first signal line and the second signal line are located on the transparent conductive layer. In this example, by arranging the first signal lines and the second signal lines of the first display region in the transparent conductive layer, the light transmittance of the first display region can be improved and light diffraction can be prevented.

In some exemplary embodiments, the at least one first signal line includes a plurality of first sub-signal lines, and adjacent first sub-signal lines are electrically connected through the pixel circuit. In some examples, the first signal line includes a first sub-signal line located in the light transmissive region and extending to the sub-display region to be electrically connected to the pixel circuit. However, this embodiment is not limited to this.

In some exemplary embodiments, the plurality of first signal lines includes at least one of: scanning line, reset signal line, initial voltage line, luminous control line, first connecting wire. The plurality of second signal lines include at least one of: data line, first power cord. Wherein the first power line is configured to provide a first voltage signal (e.g., a high potential signal). The first connecting line can be electrically connected with the first power line to realize the transmission of the first voltage signal.

In some exemplary embodiments, the first connection line and the first power supply line are both connected to the pixel circuit. The first connecting line and the first power line form a mesh-shaped wiring structure for transmitting a first voltage signal in the first display area. In this example, the first voltage signal may be transmitted in the first display region through the mesh routing structure, and an IR Drop (Drop) may be prevented from being generated.

In some exemplary embodiments, the substrate base plate further includes: the display device comprises a first display area, a second display area and a peripheral area, wherein the first display area is positioned on at least one side of the first display area, and the peripheral area at least partially surrounds the first display area and the second display area. The second display area is provided with a plurality of third signal lines extending in the first direction and a plurality of fourth signal lines extending in the second direction. The at least one first signal line is connected with the at least one third signal line, and the at least one second signal line is connected with the at least one fourth signal line. The third signal line is positioned at one side of the connected first signal line close to the substrate base plate, and the fourth signal line is positioned at one side of the connected second signal line close to the substrate base plate. For example, the third signal line may be located in the first conductive layer or the second conductive layer, and the fourth signal line may be located in the third conductive layer. However, this embodiment is not limited to this.

The scheme of the present embodiment is illustrated by some examples below.

Fig. 1 is a schematic view of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in fig. 1, the display substrate includes a display area AA and a peripheral area BB surrounding the display area AA. The display area AA of the display substrate may include: a first display region a1 and a second display region a2 positioned at least one side of the first display region a 1. In some examples, the first Display area a1 may be referred to as an Under Display Camera (UDC) area, and the second Display area a2 may be referred to as a normal Display area. For example, an orthographic projection of hardware such as a light-sensitive sensor (e.g., a camera) on a display substrate may be located within the first display area a1 of the display substrate. In some examples, as shown in fig. 1, the first display area a1 may be circular, and the size of the orthographic projection of the photosensor on the display substrate may be less than or equal to the size of the first display area a 1. However, this embodiment is not limited to this. In other examples, the first display area may be rectangular, and the size of the orthographic projection of the photosensor on the display substrate may be less than or equal to the size of the inscribed circle of the first display area.

In some exemplary embodiments, as shown in fig. 1, the first display area a1 may be located at the top right middle position of the display area AA. However, this embodiment is not limited to this. For example, the first display area may be located at other positions such as the upper left corner or the upper right corner of the display area.

In some exemplary embodiments, as shown in fig. 1, the display area AA may be a rectangle, for example, a rounded rectangle. The first display area a1 may be circular or oval. However, this embodiment is not limited to this. For example, the first display area may be rectangular, pentagonal, or other shapes.

In some exemplary embodiments, the display area is provided with a plurality of sub-pixels. At least one of the sub-pixels includes a pixel circuit and a light emitting element. The pixel circuit is configured to drive the connected light emitting element. For example, the pixel circuit is configured to supply a driving current to drive the light emitting element to emit light. In some examples, the light emitting elements may be Organic Light Emitting Diodes (OLEDs), and the light emitting elements emit red light, green light, blue light, white light, or the like under the driving of their corresponding pixel circuits. The color of the light emitted by the light-emitting element can be determined according to the requirement.

In some exemplary embodiments, one pixel unit of the display region may include three sub-pixels, which may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. However, this embodiment is not limited to this. In some examples, one pixel unit may include four sub-pixels, which may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, respectively.

In some exemplary embodiments, the shape of the sub-pixel may be a rectangle, a diamond, a pentagon, or a hexagon. When one pixel unit comprises three sub-pixels, the three sub-pixels can be arranged in a horizontal parallel mode, a vertical parallel mode or a delta-shaped mode; when a pixel unit comprises four sub-pixels, the four sub-pixels can be arranged in a horizontal parallel manner, a vertical parallel manner or a square manner. However, this embodiment is not limited to this.

In some exemplary embodiments, the sub-pixel may include: a pixel circuit and a light emitting element electrically connected to the pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor, and for example, the pixel circuit may be a 3T1C (3 transistors and 1 capacitor) structure, a 7T1C (7 transistors and 1 capacitor) structure, or a 5T1C (5 transistors and 1 capacitor) structure. In some examples, the light emitting element may be an OLED device. The light emitting element may include: an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The anode of the light emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

Fig. 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the disclosure. Fig. 3 is a timing diagram illustrating the operation of the pixel circuit shown in fig. 2.

In some exemplary embodiments, as shown in fig. 2, the pixel circuit of the present exemplary embodiment may include: six switching transistors (T1, T2, T4 to T7), one driving transistor T3, and one storage capacitor Cst. The six switching transistors are a data writing transistor T4, a threshold compensation transistor T2, a first light emission control transistor T5, a second light emission control transistor T6, a first reset transistor T1, and a second reset transistor T7, respectively. The light emitting element EL includes an anode, a cathode, and an organic light emitting layer between the anode and the cathode.

In some exemplary embodiments, the driving transistor and the six switching transistors may be P-type transistors, or may be N-type transistors. The same type of transistors are adopted in the pixel circuit, so that the process flow can be simplified, the process difficulty of the display substrate is reduced, and the yield of products is improved. In some possible implementations, the driving transistor and the six switching transistors may include a P-type transistor and an N-type transistor.

In some exemplary embodiments, the driving transistor and the six switching transistors may employ a low temperature polysilicon thin film transistor, or may employ an oxide thin film transistor, or may employ a low temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the Low Temperature polysilicon thin film transistor adopts Low Temperature Polysilicon (LTPS), and the active layer of the Oxide thin film transistor adopts Oxide semiconductor (Oxide). The Low-Temperature Polycrystalline silicon thin film transistor has the advantages of high mobility, quick charging and the like, the Oxide thin film transistor has the advantages of Low leakage current and the like, the Low-Temperature Polycrystalline silicon thin film transistor and the Oxide thin film transistor are integrated on one display substrate to form a Low-Temperature Polycrystalline Oxide (LTPO) display substrate, the advantages of the LTPO and the LTPO can be utilized, Low-frequency driving can be realized, power consumption can be reduced, and display quality can be improved.

In some exemplary embodiments, as shown in fig. 2, the pixel circuit is electrically connected to the scan line GL, the data line DL, the first power line PL1, the second power line PL2, the light emission control line EML, the initial signal line INIT, the first reset control line RST1, and the second reset control line RST 2. In some examples, the first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel circuit, the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel circuit, and the first voltage signal VDD is greater than the second voltage signal VSS. The SCAN line GL is configured to supply a SCAN signal SCAN to the pixel circuit, the DATA line DL is configured to supply a DATA signal DATA to the pixel circuit, the light emission control line EML is configured to supply a light emission control signal EM to the pixel circuit, the first RESET control line RST1 is configured to supply a first RESET control signal RESET1 to the pixel circuit, and the second RESET control line RST2 is configured to supply a second RESET signal RESET2 to the pixel circuit. In some examples, in a row of pixel circuits, the second reset control line RST2 may be connected to the SCAN line GL to be input with the SCAN signal SCAN. That is, the second RESET signal RESET2(n) received by the pixel circuit of the nth row is the scan signal scan (n) received by the pixel circuit of the nth row. However, this embodiment is not limited to this. For example, the second RESET control signal line RST2 may be input with a second RESET control signal RESET2 different from the SCAN signal SCAN. In some examples, in the n-th row of pixel circuits, the first RESET control line RST1 may be connected to the SCAN line GL of the n-1 th row of pixel circuits to be input with the SCAN signal SCAN (n-1), i.e., the first RESET control signal RESET1(n) is the same as the SCAN signal SCAN (n-1). Therefore, signal lines of the display substrate can be reduced, and the narrow frame of the display substrate is realized.

In some exemplary embodiments, as shown in fig. 2, the driving transistor T3 is electrically connected to the light emitting element EL and outputs a driving current to drive the light emitting element EL to emit light under the control of the SCAN signal SCAN, the DATA signal DATA, the first voltage signal VDD, the second voltage signal VSS, and the like. The gate of the data writing transistor T4 is electrically connected to the scan line GL, the first pole of the data writing transistor T4 is electrically connected to the data line DL, and the second pole of the data writing transistor T4 is electrically connected to the first pole of the driving transistor T3. The gate of the threshold compensation transistor T2 is electrically connected to the scan line GL, the first pole of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the second pole of the threshold compensation transistor T2 is electrically connected to the second pole of the driving transistor T3. A gate of the first light emission controlling transistor T5 is electrically connected to the light emission control line EML, a first pole of the first light emission controlling transistor T5 is electrically connected to the first power line PL1, and a second pole of the first light emission controlling transistor T5 is electrically connected to the first pole of the driving transistor T3. The gate of the second light emission controlling transistor T6 is electrically connected to the light emission control line EML, the first pole of the second light emission controlling transistor T6 is electrically connected to the second pole of the driving transistor T3, and the second pole of the second light emission controlling transistor T6 is electrically connected to the anode of the light emitting element EL. The first reset transistor T1 is electrically connected to the gate of the driving transistor T3 and configured to reset the gate of the driving transistor T3, and the second reset transistor T7 is electrically connected to the anode of the light emitting element EL and configured to reset the anode of the light emitting element EL. The gate of the first reset transistor T1 is electrically connected to a first reset control line RST1, a first pole of the first reset transistor T1 is electrically connected to the initialization signal line INIT, and a second pole of the first reset transistor T1 is electrically connected to the gate of the driving transistor T3. A gate of the second reset transistor T7 is electrically connected to a second reset control line RST2, a first pole of the second reset transistor T7 is electrically connected to the initialization signal line INIT, and a second pole of the second reset transistor T7 is electrically connected to the anode of the light emitting element EL. A first electrode of the storage capacitor Cst is electrically connected to the gate electrode of the driving transistor T3, and a second electrode of the storage capacitor Cst is electrically connected to the first power line PL 1. In this example, the first node N1 is a connection point of the storage capacitor Cst, the first reset transistor T1, the driving transistor T3, and the threshold compensation transistor T2, the second node N2 is a connection point of the first light emission control transistor T5, the data writing transistor T4, and the driving transistor T3, the third node N3 is a connection point of the driving transistor T3, the threshold compensation transistor T2, and the second light emission control transistor T6, and the fourth node N4 is a connection point of the second light emission control transistor T6, the second reset transistor T7, and the light emitting element EL.

The operation of the pixel circuit shown in fig. 2 will be described with reference to fig. 3. The pixel circuit shown in fig. 2 is described by taking a case where a plurality of transistors are P-type transistors.

In some exemplary embodiments, as shown in fig. 2 and 3, during a display period of one frame, the operation process of the pixel circuit may include: a first stage S1, a second stage S2, and a third stage S3.

The first stage S1 is referred to as a reset stage. The first RESET control signal RESET1 provided by the first RESET control line RST1 is a low level signal, which turns on the first RESET transistor T1, and the initialization signal Vinit provided by the initialization signal line INIT is provided to the first node N1, so as to initialize the first node N1 and clear the storage capacitor Cst from the original data voltage. The SCAN signal SCAN supplied from the SCAN line GL is a high level signal, and the emission control signal EM supplied from the emission control line EML is a high level signal, turning off the data writing transistor T4, the threshold compensation transistor T2, the first emission control transistor T5, the second emission control transistor T6, and the second reset transistor T7. At this stage, the light emitting element EL does not emit light.

The second phase S2 is referred to as a data write phase or a threshold compensation phase. The SCAN signal SCAN supplied from the SCAN line GL is a low level signal, the first RESET control signal RESET1 supplied from the first RESET control line RST1 and the emission control signal EM supplied from the emission control line EML are both high level signals, and the DATA signal DATA is output from the DATA line DL. At this stage, the second electrode of the storage capacitor Cst is at a low level, so the driving transistor T3 is turned on. The SCAN signal SCAN is a low level signal, turning on the threshold compensation transistor T2, the data write transistor T4, and the second reset transistor T7. The threshold compensation transistor T2 and the data write transistor T4 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N2 through the second node N2, the turned-on driving transistor T3, the third node N3, and the turned-on threshold compensation transistor T2, and a difference between the data voltage Vdata output by the data line DL and the threshold voltage of the driving transistor T3 is charged into the storage capacitor Cst, and the voltage of the second electrode (i.e., the first node N1) of the storage capacitor Cst is Vdata- | Vth |, where Vdata is the data voltage output by the data line DL and Vth is the threshold voltage of the driving transistor T3. The second reset transistor T7 is turned on, so that the initialization signal Vinit provided by the initialization signal line INIT is provided to the anode of the light emitting element EL, the anode of the light emitting element EL is initialized (reset), the pre-stored voltage therein is cleared, the initialization is completed, and the light emitting element EL is ensured not to emit light. The first RESET control signal RESET1 provided by the first RESET control line RST1 is a high level signal, turning off the first RESET transistor T1. The emission control signal EM supplied from the emission control signal line EML is a high level signal, turning off the first emission control transistor T5 and the second emission control transistor T6.

The third stage S3 is referred to as a lighting stage. The emission control signal EM supplied from the emission control signal line EML is a low-level signal, and the SCAN signal SCAN supplied from the SCAN line GL and the first RESET control signal RESET1 supplied from the first RESET control line RST1 are high-level signals. The light emission control signal EM supplied from the light emission control signal line EML is a low-level signal, and turns on the first light emission control transistor T5 and the second light emission control transistor T6, and the first voltage signal VDD output from the first power line PL1 supplies a drive voltage to the anode of the light emitting element EL through the turned-on first light emission control transistor T5, the drive transistor T3, and the second light emission control transistor T6, thereby driving the light emitting element EL to emit light.

During driving of the pixel circuit, the driving current flowing through the driving transistor T3 is determined by a voltage difference between the gate and the first electrode thereof. Since the voltage of the first node N1 is Vdata- | Vth |, the driving current of the driving transistor T3 is:

I＝K×(Vgs-Vth)²＝K×[(VDD-Vdata+|Vth|)-Vth]²＝K×[(VDD-Vdata)]²；

where I is a driving current flowing through the driving transistor T3, that is, a driving current driving the light emitting element EL, K is a constant, Vgs is a voltage difference between the gate and the first electrode of the driving transistor T3, Vth is a threshold voltage of the driving transistor T3, Vdata is a data voltage output from the data line DL, and VDD is a first voltage signal output from the first power line PL 1.

It can be seen from the above equation that the current flowing through the light emitting element EL is independent of the threshold voltage of the driving transistor T3. Therefore, the pixel circuit of the present embodiment can compensate the threshold voltage of the driving transistor T3 well.

Fig. 4 is a partial schematic view of a display substrate according to at least one embodiment of the disclosure. In some exemplary embodiments, as shown in fig. 4, the first display area a1 includes: a light-transmitting region a12 and a plurality of sub-display regions a 11. The sub-display area a11 is surrounded by the light transmitting area a 12. The first display area a1 is provided with a plurality of first sub-pixels PX1, a plurality of first signal lines L1 extending in the first direction X, and a plurality of second signal lines L2 extending in the second direction Y. The second display area a2 is provided with a plurality of second sub-pixels PX2, a plurality of third signal lines L3 extending in the first direction X, and a plurality of fourth signal lines L4 extending in the second direction Y. The first direction X intersects the second direction Y, for example, the first direction X is perpendicular to the second direction Y.

In some exemplary embodiments, as shown in fig. 4, a plurality of first sub-pixels PX1 are disposed in a plurality of sub-display regions a11 of the first display region a 1. For example, one sub display area a11 sets one first sub pixel PX 1. A light-transmitting area a12 is located between adjacent first sub-pixels PX 1. However, this embodiment is not limited to this. This example can improve the light transmittance of the first display region by setting the first sub-pixel in the sub-display region and setting the adjacent region of the sub-display region as the light-transmitting region.

In some exemplary embodiments, as shown in fig. 4, in the first display area a1, a plurality of first signal lines L1 extend in the first direction X and are sequentially arranged in the second direction Y. The first signal line L1 is electrically connected to the pixel circuits of the plurality of first sub-pixels arranged in the first direction X. The plurality of second signal lines L2 extend in the second direction Y and are arranged in order in the first direction X. The second signal line L2 is electrically connected to the pixel circuits of the plurality of first sub-pixels PX1 arranged in the second direction Y. In the second display area a2, a plurality of third signal lines L3 extend in the first direction X and are sequentially arranged in the second direction Y. The third signal line L3 is electrically connected to the pixel circuits of the plurality of second sub-pixels PX2 arranged in the first direction X. The plurality of fourth signal lines L4 extend in the second direction Y and are sequentially arranged in the first direction X. The fourth signal line L4 is electrically connected to the pixel circuits of the plurality of second sub-pixels PX2 arranged in the second direction Y.

In some exemplary embodiments, as shown in fig. 4, the plurality of first signal lines L1 of the first display area a1 are connected with the plurality of third signal lines L3 of the second display area a 2. The plurality of second signal lines L2 of the first display area a1 are connected to the plurality of fourth signal lines L4 of the second display area a 2. In some examples, the first signal line L1 of the first display region a1 may include a plurality of first sub signal lines extending in the first direction X. The plurality of first sub-signal lines may be positioned at the light transmitting area a12 in sequence along the first direction X, and adjacent first sub-signal lines may be electrically connected through the pixel circuit of the first sub-pixel positioned at the sub-display area a 11. The at least one third signal line L3 of the second display area a2 may include two third sub-signal lines extending in the first direction X. The two third sub-signal lines may be electrically connected through one first signal line L1 of the first display area a 1. The at least one fourth signal line L4 of the second display area a2 may include two fourth sub signal lines extending in the second direction Y. The two fourth sub-signal lines may be electrically connected through one second signal line L2 of the first display area a 1. In some examples, the first and second signal lines L1 and L2 may be located at a side of the third and fourth signal lines L3 and L4 away from the substrate. However, this embodiment is not limited to this.

In some exemplary embodiments, the plurality of first signal lines L1 may include: the scanning line GL, the initialization signal line INIT, the first reset control line RST1, the emission control signal line EML, and the first connection line 404. The plurality of second signal lines L2 may include: data line DL, first power line PL 1. However, this embodiment is not limited to this.

Fig. 5 is a partial schematic plan view of a first display area according to at least one embodiment of the disclosure. Fig. 5 illustrates a sub-display region where a first sub-pixel is disposed, and a peripheral part of the transmissive region. Fig. 6 is a partial cross-sectional view taken along the direction O-O' in fig. 5. Fig. 7 is a partial cross-sectional view taken along the line Q-Q' in fig. 5. In the present example of the present invention,

in some exemplary embodiments, as shown in fig. 5 to 7, the display substrate of the sub-display area a11 of the first display area may include, in a plane perpendicular to the display substrate: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a transparent conductive layer, and an anode layer are sequentially provided on a base substrate 10. A first insulating layer 11 is arranged between the semiconductor layer and the first conductive layer, a second insulating layer 12 is arranged between the first conductive layer and the second conductive layer, a third insulating layer 13 is arranged between the second conductive layer and the third conductive layer, and a fourth insulating layer 14 and a first flat layer 15 are arranged between the transparent conductive layer and the anode layer. On the side of the anode layer remote from the substrate 10, a pixel defining layer 16, an organic light emitting layer, a cathode layer and an encapsulation layer are provided. In some examples, the first to fourth insulating layers 11 to 14 may be inorganic insulating layers, and the first planarization layer 15 may be an organic insulating layer. For example, the first and second insulating layers 11 and 12 may also be referred to as a Gate Insulating (GI) layer, the third insulating layer 13 may also be referred to as an interlayer Insulating Layer (ILD), and the fourth insulating layer 14 may also be referred to as a Passivation (PVX) layer. However, this embodiment is not limited to this.

In this example, the fourth insulating layer 14 is the first inorganic insulating layer, and the first planarization layer 15 is the organic insulating layer.

In some exemplary embodiments, as shown in fig. 5 to 7, the display substrate of the light transmission region a12 of the first display region may include, in a plane perpendicular to the display substrate: a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, a transparent conductive layer, and a fourth insulating layer 14 are provided in this order on the base substrate 10. In this example, the transparent region is only provided with the transparent conductive layer to realize signal transmission, and the rest of the conductive layers are removed, so that the light transmittance of the transparent region can be improved, and the light scattering can be reduced. Moreover, the first flat layer of the light-transmitting area is removed, so that the light transmittance can be greatly improved, and the yellowness of transmitted light is reduced.

Fig. 8 is a partial schematic plan view of a first display region after a semiconductor layer is formed according to at least one embodiment of the disclosure. Fig. 9 is a partial schematic plan view of the first display region after the first conductive layer is formed according to at least one embodiment of the disclosure. Fig. 10 is a partial schematic plan view of the first display region after the second conductive layer is formed according to at least one embodiment of the disclosure. Fig. 11 is a partial schematic plan view of the first display region after forming the third insulating layer according to at least one embodiment of the disclosure. Fig. 12 is a partial schematic plan view of the first display region after the third conductive layer is formed according to at least one embodiment of the disclosure. Fig. 13 is a partial schematic plan view of the first display region after the transparent conductive layer is formed according to at least one embodiment of the disclosure. Fig. 14 is a partial plan view of the first display region after forming the fourth insulating layer according to at least one embodiment of the disclosure. Fig. 15 is a partial schematic plan view of the first display region after the first planarization layer is formed according to at least one embodiment of the disclosure. Fig. 16 is a partial schematic plan view of a first display region after an anode layer is formed according to at least one embodiment of the disclosure. In this example, a description will be given taking as an example a configuration in which the pixel circuit of the first sub-pixel is 7T1C shown in fig. 2.

In some exemplary embodiments, as shown in fig. 8, the semiconductor layer of the sub-display region of the first display region may include: active layers of a plurality of transistors of the pixel circuit of the first sub-pixel, for example, a first active layer T10 of the first reset transistor T1, a second active layer T20 of the threshold compensation transistor T2, a third active layer T30 of the driving transistor T3, a fourth active layer T40 of the data write transistor T4, a fifth active layer T50 of the first light emission control transistor T5, a sixth active layer T60 of the second light emission control transistor T6, and a seventh active layer T70 of the second reset transistor T7. The seventh active layer T70 shown in fig. 8 is an active layer of the second reset transistor T7 of the pixel circuit of the previous row. Among them, the first to sixth active layers T10 to T60 of one pixel circuit and the seventh active layer T70 of the second reset transistor of the pixel circuit of the previous row may be an integral structure connected to each other.

In some exemplary embodiments, the material of the semiconductor layer may include, for example, polysilicon. The active layer may include at least one channel region and a plurality of doped regions. The channel region may be undoped with impurities and have semiconductor characteristics. The plurality of doped regions may be on both sides of the channel region and doped with impurities and thus have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. A portion of the active layer between the transistors may be interpreted as a wiring doped with impurities, which may be used to electrically connect the transistors.

In some exemplary embodiments, as shown in fig. 9, the first conductive layer of the sub display region of the first display region may include: gates of a plurality of transistors of the pixel circuit of the first sub-pixel (e.g., a gate T13 of the first reset transistor T1, a gate T23 of the threshold compensation transistor T2, a gate T33 of the driving transistor T3, a gate T43 of the data write transistor T4, a gate T53 of the first emission control transistor T5, a gate T63 of the second emission control transistor T6, a gate T73 of the second reset transistor T7), and a first electrode Cst-1 of the storage capacitor Cst of the pixel circuit.

In some exemplary embodiments, the first electrode Cst-1 of the storage capacitor Cst and the gate electrode T33 of the driving transistor T3 may be a unitary structure. The gate electrode T53 of the first light emission controlling transistor T5 and the gate electrode T63 of the second light emission controlling transistor T6 may be a unitary structure. The gate T43 of the data writing transistor T4 and the gate T23 of the threshold compensating transistor T2 may be a unitary structure. The gate T13 of the first reset transistor T1 and the gate T73 of the second reset transistor T7 of the previous pixel circuit may be a unitary structure.

In some exemplary embodiments, as shown in fig. 10, the second conductive layer of the sub display region of the first display region may include: a second electrode Cst-2 of the storage capacitor Cst of the pixel circuit of the first sub-pixel, and an initial connection line 21. An overlapping region exists between an orthographic projection of the second electrode Cst-2 of the storage capacitor Cst on the substrate and an orthographic projection of the first electrode Cst-1 on the substrate. The second electrode Cst-2 is provided with a first opening 201, the first opening 201 exposes the second insulating layer covering the first electrode Cst-1, and an orthographic projection of the first electrode Cst-1 on the substrate includes an orthographic projection of the first opening 201 on the substrate. In some examples, the first opening 201 is configured to receive a subsequently formed second via H7, and the second via H7 is located within the first opening 201 and exposes the first electrode Cst-1, such that the first electrode T21 of the subsequently formed threshold compensation transistor T2 is electrically connected to the first electrode Cst-1.

In some exemplary embodiments, as shown in fig. 11, the opening of the third insulating layer of the sub-display area of the first display area may include: the plurality of first vias K1 to K6, the plurality of second vias H1 to H7, and the plurality of third vias V1 to V6. The third insulating layer 13 in the plurality of third vias V1 to V6 is etched away, exposing the surface of the second conductive layer; the third insulating layer 13 and the second insulating layer 12 in the plurality of second vias H1 to H7 are etched away, exposing the surface of the first conductive layer; the third insulating layer 13, the second insulating layer 12, and the first insulating layer 11 in the plurality of first vias K1 through K6 are etched away to expose the surface of the semiconductor layer.

In some exemplary embodiments, as shown in fig. 12, the third conductive layer of the sub display region of the first display region may include: first and second poles of a plurality of transistors of a pixel circuit of the first sub-pixel (for example, a first pole T11 of a first reset transistor T1, a first pole T21 of a threshold compensation transistor T2, a first pole T41 of a data write transistor T4, a first pole T51 of a first emission control transistor T5, a second pole T62 of a second emission control transistor T6, a first pole T71 of a second reset transistor T7), a first connection electrode 301a, a second connection electrode 301b, a third connection electrode 302a, a fourth connection electrode 302b, a fifth connection electrode 303a, a sixth connection electrode 303b, a seventh connection electrode 304a, an eighth connection electrode 304b, a ninth connection electrode 305a, a tenth connection electrode 305b, a data connection line 306, and a second connection line 307. In some examples, the data connection line 306 and the second connection line 307 both extend along the second direction Y. The data link line 306 and the second link line 307 are adjacent in the first direction X.

In some exemplary embodiments, as shown in fig. 12, the first pole T41 of the data writing transistor T4 and the data link line 306 may be a unitary structure. The first electrode T51 of the first light emitting control transistor T5 and the second connection line 307 may be an integral structure.

In some exemplary embodiments, as shown in fig. 12, the first pole T11 of the first reset transistor T1 is electrically connected to the initial connection line 21 through the third via V2 and is also electrically connected to the first doped region of the first active layer T10 of the first reset transistor T1 through the first via K2. The first electrode T21 of the threshold compensation transistor T2 is electrically connected to the first doped region of the second active layer T20 of the threshold compensation transistor T2 through the first via K3, and is also electrically connected to the first electrode Cst-1 of the storage capacitor Cst through the second via H7. The first pole T41 of the data write transistor T4 is electrically connected to the first doped region of the fourth active layer T40 of the data write transistor T4 through the first via K4. The first pole T51 of the first light emitting control transistor T5 is electrically connected to the first doping region of the fifth active layer T50 of the first light emitting control transistor T5 through the first via hole K6. The second diode T62 of the second light emission controlling transistor T6 is electrically connected to the second doping region of the sixth active layer T60 of the second light emission controlling transistor T6 through the first via hole K5. The first pole T71 of the second reset transistor T7 is electrically connected to the first doping region of the seventh active layer T70 of the second reset transistor T7 through the first via K1. The second connection line 307 is electrically connected to the second electrode Cst-2 of the storage capacitor Cst through two vertically arranged third vias V5. In the present example, "vertically arranged" means that they are arranged in order in the second direction Y.

In some exemplary embodiments, as shown in fig. 12, the first connection electrode 301a is electrically connected to one end of the initial connection line 21 through the third via V3, and the second connection electrode 301b is electrically connected to the other end of the initial connection line 21 through the third via V1. The third connection electrode 302a is electrically connected to the gate T13 of the first reset transistor T1 through the second via H2, and the fourth connection electrode 302b is electrically connected to the gate T73 of the seventh reset transistor T7 of the previous pixel circuit through the second via H1. Since the gate T13 of the first reset transistor T1 and the gate T73 of the seventh reset transistor T7 of the previous pixel circuit are of an integral structure, the third connection electrode 302a and the fourth connection electrode 302b are electrically connected through the gate T13 of the first reset transistor T1 and the gate T73 of the seventh reset transistor T7 of the previous pixel circuit. The fifth connection electrode 303a is electrically connected to the gate T43 of the data write transistor T4 through the second via H4, and the sixth connection electrode 303b is electrically connected to the gate T23 of the threshold compensation transistor T2 through the second via H3. Since the gate T43 of the data writing transistor T4 and the gate T23 of the threshold compensating transistor T2 are of an integral structure, the fifth connection electrode 303a and the sixth connection electrode 303b may be electrically connected through the gate T43 of the data writing transistor T4 and the gate T23 of the threshold compensating transistor T2. The seventh connection electrode 304a is electrically connected to one end of the second electrode Cst-2 of the storage capacitor Cst through the third via hole V4, and the eighth connection electrode 304b is electrically connected to the other end of the second electrode Cst-2 of the storage capacitor Cst through the third via hole V6. The ninth connection electrode 305a is electrically connected to the gate T53 of the first light emission control transistor T5 through the second via H6, and the tenth connection electrode 305b is electrically connected to the gate T63 of the second light emission control transistor T6 through the second via H5. Since the gate T53 of the first light emission controlling transistor T5 and the gate T63 of the second light emission controlling transistor T6 are of an integral structure, the ninth connection electrode 305a and the tenth connection electrode 305b may be electrically connected through the gate T53 of the first light emission controlling transistor T5 and the gate T63 of the second light emission controlling transistor T6.

In some exemplary embodiments, as shown in fig. 13, in the sub-display region of the first display region, an orthogonal projection of the transparent conductive layer on the substrate base plate overlaps an orthogonal projection of the third conductive layer on the substrate base plate. The transparent conductive layer and the third conductive layer are in direct contact. The transparent conductive layer of the sub-display region of the first display region may include: a plurality of first sub-signal lines (e.g., initial sub-signal lines 401a and 401b, first reset control sub-signal lines 402a and 402b, scanning sub-signal lines 403a and 404b, first power supply sub-connection lines 404a and 404b, light emission control sub-signal lines 405a and 405b), a data line DL, a first power supply line PL1, a first protective electrode 406, a second protective electrode 407, a third protective electrode 408, and a fourth protective electrode 409.

In some exemplary embodiments, as shown in fig. 13, the initial sub-signal line 401a is in direct contact with the first connection electrode 301a, and an orthogonal projection of the initial sub-signal line 401a on the substrate base overlaps an orthogonal projection of the first connection electrode 301a on the substrate base. The initial sub-signal line 401b is in direct contact with the second connection electrode 301b, and an orthogonal projection of the initial sub-signal line 401b on the substrate covers an orthogonal projection of the second connection electrode 301b on the substrate. The initial sub-signal lines 401a and 401b extend in the first direction X, and the initial sub-signal lines 401a and 401b may electrically connect the initial connection lines 21 of the adjacent pixel circuits.

In some exemplary embodiments, as shown in fig. 13, the first reset control sub-signal line 402a is in direct contact with the third connection electrode 302a, and an orthogonal projection of the first reset control sub-signal line 402a on the substrate covers an orthogonal projection of the third connection electrode 302a on the substrate. The first reset control sub-signal line 402b is in direct contact with the fourth connection electrode 302b, and an orthogonal projection of the first reset control sub-signal line 402b on the substrate overlaps an orthogonal projection of the fourth connection electrode 302b on the substrate. The first reset control sub-signal lines 402a and 402b extend in the first direction X, and the first reset control sub-signal lines 402a and 402b may electrically connect gates of first reset transistors of adjacent pixel circuits.

In some exemplary embodiments, as shown in fig. 13, the scan sub-signal line 403a is in direct contact with the fifth connection electrode 303a, and an orthogonal projection of the scan sub-signal line 403a on the substrate covers an orthogonal projection of the fifth connection electrode 303a on the substrate. The scanning sub-signal line 403b is in direct contact with the sixth connection electrode 303b, and an orthogonal projection of the scanning sub-signal line 403b on the base substrate covers an orthogonal projection of the sixth connection electrode 303b on the base substrate. The scan sub-signal lines 403a and 403b extend in the first direction X, and the scan sub-signal lines 403a and 403b may electrically connect the gates of the data writing transistors T4 and the gates of the threshold compensating transistors T2 of the adjacent pixel circuits.

In some exemplary embodiments, as shown in fig. 13, the first connection line 404 may include a plurality of first power sub-connection lines 404a and 404 b. The first power supply sub-connecting line 404a is in direct contact with the seventh connecting electrode 304a, and an orthographic projection of the first power supply sub-connecting line 404a on the substrate covers an orthographic projection of the seventh connecting electrode 304a on the substrate. The first power supply sub-connecting line 404b is in direct contact with the eighth connecting electrode 304b, and an orthographic projection of the first power supply sub-connecting line 404b on the substrate covers an orthographic projection of the eighth connecting electrode 304b on the substrate. The first power supply sub-connection lines 404a and 404b extend in the first direction X, and the first power supply sub-connection lines 404a and 404b may electrically connect the second electrodes of the storage capacitors Cst of the adjacent pixel circuits.

In some exemplary embodiments, as shown in fig. 13, the light emission control sub-signal line 405a is in direct contact with the ninth connection electrode 305a, and an orthogonal projection of the light emission control sub-signal line 405a on the substrate covers an orthogonal projection of the ninth connection electrode 305a on the substrate. The light emission control sub-signal line 405b is in direct contact with the tenth connection electrode 305b, and an orthogonal projection of the light emission control sub-signal line 405b on the substrate covers an orthogonal projection of the tenth connection electrode 305b on the substrate. The light emission control sub-signal lines 405a and 405b extend in the first direction X, and the light emission control sub-signal lines 405a and 405b may electrically connect the gates of the first and second light emission control transistors of the adjacent pixel circuits.

In some exemplary embodiments, as shown in fig. 13, the data lines DL are in direct contact with the data link lines 306, and an orthographic projection of the data lines DL on the substrate covers an orthographic projection of the data link lines 306 on the substrate. The first power supply line PL1 is in direct contact with the second connection line 307, and an orthographic projection of the first power supply line PL1 on the substrate covers an orthographic projection of the second connection line 307 on the substrate. The first protective electrode 406 is in direct contact with the first pole T11 of the first reset transistor, and an orthographic projection of the first protective electrode 406 on the substrate covers an orthographic projection of the first pole T11 of the first reset transistor on the substrate. The second guard electrode 407 is in direct contact with the first electrode T21 of the threshold compensation transistor, and an orthogonal projection of the second guard electrode 407 on the substrate base overlaps an orthogonal projection of the first electrode T21 of the threshold compensation transistor on the substrate base. The third guard electrode 408 is in direct contact with the second diode T62 of the second emission control transistor, and an orthogonal projection of the third guard electrode 408 on the substrate overlaps an orthogonal projection of the second diode T62 of the second emission control transistor on the substrate. The fourth guard electrode 409 is in direct contact with the first electrode T71 of the second reset transistor, and an orthogonal projection of the fourth guard electrode 409 on the substrate overlaps an orthogonal projection of the first electrode T71 of the second reset transistor on the substrate.

In some exemplary embodiments, as shown in fig. 6, 7 and 13, the transparent conductive layer of the light transmission region of the first display region may include: a plurality of first sub-signal lines (e.g., initial sub-signal lines 401a and 401b, first reset control sub-signal lines 402a and 402b, scanning sub-signal lines 403a and 404b, first power supply sub-connection lines 404a and 404b, light emission control sub-signal lines 405a and 405b), a data line DL, a first power supply line PL1, and a third protective electrode 408. In some examples, the third guard electrode 408 of the sub display region may extend to the light transmission region in the second direction Y and be connected to the fourth guard electrode 409 of the adjacent sub display region. For example, the third and fourth guard electrodes 408 and 409 of the adjacent sub-display regions in the second direction Y may be an integral structure.

In some exemplary embodiments, as shown in fig. 14, at least one via hole is opened on the fourth insulating layer of the sub-display area of the first display area, for example, a fourth via hole M1 may be included. The fourth insulating layer 14 within the fourth via M1 is etched away, exposing the surface of the transparent conductive layer.

In some exemplary embodiments, as shown in fig. 15, the first planarization layer 15 of the sub-display area of the first display area is opened with at least one via hole, for example, a fifth via hole M2 may be included. The first planarization layer 15 in the fifth via M2 is removed. The fifth via M2 and the fourth via M1 are in communication, exposing the surface of the transparent conductive layer. The first planarization layer 15 of the light-transmitting area of the first display area is removed. In other words, the first planarization layer 15 is disposed only in the sub-display region and the second display region of the first display region, and the first planarization layer 15 is not disposed in the light-transmitting region of the first display region.

In some exemplary embodiments, as shown in fig. 16, the anode layer of the sub display region of the first display region may include: the anode 501 of the light emitting element of the first sub-pixel. The anode 501 may be electrically connected to the third protective electrode 408 through the fifth and fourth vias M2 and M1. Since the third protective electrode 408 is electrically connected to the second electrode T62 of the second light emission controlling transistor, the anode 501 can be electrically connected to the pixel circuit through the third protective electrode 408.

In some exemplary embodiments, as shown in fig. 5, a side of the anode layer of the sub-display region of the first display region, which is away from the substrate, is further provided with a pixel defining layer 16. The pixel defining layer 16 has a pixel opening OP exposing a surface of the anode layer. In this example, the orthographic projection of the pixel opening OP on the substrate is located within the orthographic projection of the anode 501 on the substrate. The pixel defining layer 16 of the light transmitting region of the first display region is removed. In other words, the pixel defining layer 16 is disposed only in the sub display region and the second display region of the first display region, and the pixel defining layer 16 is not disposed in the light transmitting region of the first display region.

In some exemplary embodiments, the light emitting element of the first sub-pixel may include: an anode, a pixel defining layer, an organic light emitting layer, and a cathode. The pixel defining layer has a pixel opening exposing the anode, and the organic light emitting layer is formed in the pixel opening. The organic light emitting layer of the light emitting element is connected with the anode, the cathode is connected with the organic light emitting layer, and the organic light emitting layer emits light rays with corresponding colors under the driving of the anode and the cathode. An encapsulation layer may be provided on the side of the cathode remote from the substrate base plate. The packaging layer can be including the first packaging layer, second packaging layer and the third packaging layer of establishing of folding, and first packaging layer and third packaging layer can adopt inorganic material, and the second packaging layer can adopt organic material, and the second packaging layer setting can guarantee that external steam can't get into light emitting component between first packaging layer and third packaging layer.

In some exemplary embodiments, the organic light Emitting Layer may include a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron blocking Layer (EBL, Electron Block Layer), a light Emitting Layer (EML, Emitting Layer), a Hole blocking Layer (HBL, Hole Block Layer), an Electron Transport Layer (ETL, Electron Transport Layer), and an Electron Injection Layer (EIL, Electron Injection Layer) stacked one on another. However, this embodiment is not limited to this.

In some exemplary embodiments, the pixel defining layer may employ an organic material such as polyimide, acryl, or polyethylene terephthalate. In some examples, the anode of the light emitting element may use a transparent conductive material such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), and the cathode may use any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above metals. However, this embodiment is not limited to this. The anode of the light-emitting element may be made of a reflective material such as metal, and the cathode may be made of a transflective material.

In some exemplary embodiments, the substrate base plate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked. The material of the first flexible material layer and the second flexible material layer can adopt Polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film and the like. The first inorganic material layer and the second inorganic material layer may be made of silicon nitride (SiNx), silicon oxide (SiOx), or the like, and are used to improve the water and oxygen resistance of the substrate. The first layer of inorganic material and the second layer of inorganic material are also referred to as Barrier (Barrier) layers. However, this embodiment is not limited to this.

In some exemplary embodiments, the first conductive layer, the second conductive layer, and the third conductive layer may employ a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo, and the like. The transparent conductive layer may be made of a transparent conductive material such as ITO or IZO. The first, second, third, and fourth insulating layers 11, 12, 13, and 14 may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first planarization layer 15 may be made of polyimide, acryl, or polyethylene terephthalate. However, this embodiment is not limited to this.

In some exemplary embodiments, the first flat layer and the pixel defining layer are made of organic materials, that is, the first flat layer and the pixel defining layer may be organic layers, and the thickness of the organic layers has a significant influence on the transmittance. For example, when the total thickness of the organic layers of the display substrate is about 4.5um (e.g., the pixel defining layer is about 1.5um, and the first and second planarization layers are about 1.5um), the light Transmittance (TR) of the display substrate is about 61.5%, and the Yellowness (YI) is about 63.4; when the total thickness of the organic layers of the display substrate is about 4.0um (for example, the pixel defining layer is about 1.0um, and the first and second planarization layers are about 1.5um), the light transmittance of the display substrate is about 67.9%, and the yellowness is about 59.4; when the total thickness of the organic layers of the display substrate is about 2.5um (e.g., the pixel defining layer is about 1.0um, and the first flat layer is 1.5um), the light transmittance of the display substrate is about 71.3%, and the yellowness is about 41.2. It can be seen that the thinner the organic layer thickness is, the higher the light transmittance is, and the thinner the organic material layer thickness is, the lower the yellowness is, indicating that the transmitted light is closer to white light. Generally, light rays having a yellowness of less than 10 can be approximated as white light. In the present exemplary embodiment, the organic layers (i.e., the planarization layer and the pixel defining layer) of the light transmitting region of the first display region are all cut out, thereby increasing the light transmittance of the light transmitting region and reducing the yellowness of the transmitted light.

In the present exemplary embodiment, in the first display region, the first signal line extending in the first direction X may include: the display device comprises a scanning line, an initial signal line, a first reset control line, a light-emitting control signal line and a first connecting line. The scan line includes a plurality of scan sub-signal lines extending in the first direction X, the initialization signal line includes a plurality of initialization sub-signal lines extending in the first direction X, the first reset control line includes a plurality of first reset control sub-signal lines extending in the first direction X, and the light emission control signal line includes a plurality of light emission control sub-signal lines extending in the first direction X. The first connection line includes a plurality of first power supply sub-connection lines extending in the first direction X. The first signal line is located on the transparent conductive layer and electrically connected to the pixel circuit through a connection electrode of the third conductive layer of the sub display region, thereby providing various signals (e.g., a scan signal, a light emission control signal, an initial signal, a first reset control signal, and a first voltage signal) to the pixel circuit.

In the present exemplary embodiment, the second signal lines extending in the second direction Y may include a data line and a first power line in the first display region. The data line and the first power line are located on the transparent conductive layer. The data line is electrically connected with the pixel circuit through the data connecting line of the third conductive layer of the sub-display area to provide a data signal for the pixel circuit. The first power line is electrically connected with the pixel circuit through a second connecting line of the third conductive layer of the sub-display area, and provides a first voltage signal for the pixel circuit.

In the exemplary embodiment, the first signal lines extending in the first direction and the second signal lines extending in the second direction of the first display region are both located in the transparent conductive layer, so that the light transmittance of the first display region can be improved, and light diffraction can be prevented. Moreover, the first voltage signal may be transmitted through the first power line and the second connection line extending along the second direction Y, and may also be transmitted through the first connection line extending along the first direction X, so that a mesh routing structure for transmitting the first voltage signal is formed in the first display region, and the IR Drop (Drop) may be prevented from being generated.

In the present exemplary embodiment, the transparent conductive layer and the third conductive layer are in direct contact, and the transparent conductive layer covers the third conductive layer. An insulating layer is not arranged between the transparent conducting layer and the third conducting layer, and the process of opening holes in the insulating layer is not needed. The overlapping of the transparent conducting layer and the third conducting layer does not need to consider the positions of the openings in the third insulating layer and the fourth insulating layer, and the pattern area of the third conducting layer can be reduced, so that the pixel circuit area can be compressed.

Fig. 17 is a schematic view of a process for preparing a transparent conductive layer, a fourth insulating layer, a first planarization layer, and an anode layer according to at least one embodiment of the disclosure. The "patterning process" according to the embodiments of the present disclosure includes processes of coating a photoresist, mask exposure, development, etching, and stripping a photoresist for a metal material, an inorganic material, or a transparent conductive material, and processes of coating an organic material, mask exposure, and development for an organic material. The deposition can be any one or more of sputtering, evaporation and chemical vapor deposition, the coating can be any one or more of spraying, spin coating and ink-jet printing, and the etching can be any one or more of dry etching and wet etching, and the disclosure is not limited. "thin film" refers to a layer of a material deposited, coated, or otherwise formed on a substrate. The "thin film" may also be referred to as a "layer" if it does not require a patterning process throughout the fabrication process. If the "thin film" requires a patterning process during the entire fabrication process, it is referred to as "thin film" before the patterning process and "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern".

In some exemplary embodiments, the third conductive layer 31 may be a three-layered metal structure of titanium (Ti), Al, Ti. After forming the third conductive layer 31 on the third insulating layer 13, the first transparent conductive film 40 is deposited on the base substrate, the first transparent conductive film 40 is patterned using a patterning process, the transparent conductive layer 411 covering the third conductive layer 31 is formed at the sub-display area a11, and the transparent conductive layer 412 is formed at the light transmission area a 12. Subsequently, an inorganic insulating film is deposited on the base substrate, and the fourth insulating layer 14 is formed through a patterning process. The fourth insulating layer 14 covers the transparent conductive layers 411 and 412. Subsequently, an organic insulating film 150 is coated on the base substrate, and the organic insulating film 150 is patterned through a patterning process to form the first planarization layer 15. The first planarization layer 15 of the light-transmitting area a12 is removed, and the orthographic projection of the first planarization layer 15 of the sub-display area a11 on the substrate covers the orthographic projection of the transparent conductive layer 411 on the substrate. Subsequently, a second transparent conductive film 50 is deposited on the base substrate, and the second transparent conductive film 50 is patterned using a patterning process to form an anode layer (e.g., including the anode 501) in the sub-display area a 11.

In the present exemplary embodiment, the transparent conductive layer covers the third conductive layer to protect the third conductive layer. When the first transparent conductive film is etched, the etching liquid of the first transparent conductive film contains strong acid, the third conductive layer adopts a three-layer metal structure of Ti, AL and Ti, the etching liquid of the first transparent conductive film can corrode the Al, the third conductive layer is covered by the transparent conductive layer to carry out edge covering treatment on the third conductive layer, and the third conductive layer can be protected. Further, the transparent conductive layer is covered with a fourth insulating layer. Therefore, when the second transparent conductive film is etched, the fourth insulating layer can protect the transparent conductive layer and prevent the transparent conductive layer from being etched by the etching liquid of the second transparent conductive film. Moreover, the transparent conductive layer is protected by the fourth insulating layer, so that the first flat layer of the light-transmitting area can be removed, the light transmittance of the light-transmitting area is improved, and the yellowness of light-transmitting light is reduced.

In some exemplary embodiments, the structure of the second sub-pixels of the second display region may be substantially the same as the structure of the first sub-pixels of the sub-display region of the first display region. For example, the display substrate of the second display region may include: the organic light emitting diode comprises a semiconductor layer, a first insulating layer, a first conducting layer, a second insulating layer, a second conducting layer, a third insulating layer, a third conducting layer, a transparent conducting layer, a fourth insulating layer, a first flat layer, an anode layer, a pixel defining layer, an organic light emitting layer and a cathode which are sequentially arranged on a substrate. The semiconductor layer may include: an active layer of the pixel circuit of the second sub-pixel. The first conductive layer may include at least: the gate electrodes of the plurality of transistors of the pixel circuit of the second sub-pixel and the first electrode of the storage capacitor. The second conductive layer may include: a second electrode of the storage capacitor of the pixel circuit of the second sub-pixel. The third conductive layer may include: a first pole and a second pole of a plurality of transistors of a pixel circuit of the second sub-pixel. The transparent conductive layer may include a plurality of guard electrodes, and the transparent conductive layer may cover the third conductive layer. The anode layer may comprise an anode of the light emitting element. The second electrodes of the storage capacitors of the plurality of pixel circuits adjacent to each other in the first direction in the second display region may be integrated to realize transmission of the first voltage signal. In some examples, the scan line of the second display region may be located at the first conductive layer, and the gate electrodes of the data writing transistor and the threshold compensation transistor of the pixel circuit of the second sub-pixel may be a unitary structure. The first reset control line of the second display region may be located at the first conductive layer, and may be integrated with gates of the first reset transistor of the pixel circuit of the second sub-pixel and the second reset transistor of the pixel circuit of the previous row. The light emission control signal line of the second display region may be located on the first conductive layer, and may be integrally structured with gates of the first and second light emission control transistors of the pixel circuit of the second sub-pixel. The initial signal line of the second display region may be located at the second conductive layer. The data line and the first power line of the second display region may be located at the third conductive layer. However, this embodiment is not limited to this.

In some examples, the third signal line of the second display region may include: the scan line, the initialization signal line, the first reset control line, and the emission control signal line, and the fourth signal line of the second display region may include: a data line and a first power line. The third signal line may be located in the first conductive layer or the second conductive layer. The fourth signal line may be a third conductive layer. The third signal line of the second display region may be electrically connected to the first signal line of the first display region, and the fourth signal line of the second display region may be electrically connected to the second signal line of the first display region. However, this embodiment is not limited to this.

The structure of the display substrate of the present embodiment and the process of manufacturing the same are merely exemplary illustrations. In some exemplary embodiments, the corresponding structure may be changed and the patterning process may be added or reduced according to actual needs. For example, a light-shielding layer may be provided on a side of the semiconductor layer close to the base substrate to shield the semiconductor layer from bottom light. The light-shielding layer may be made of a metal material. For another example, a fourth conductive layer and a second planarization layer may be sequentially disposed on a side of the transparent conductive layer away from the substrate, the fourth conductive layer may include an anode connection electrode, and the anode of the light emitting element and the transparent conductive layer may be electrically connected through the anode connection electrode. The second planarization layer may be between the fourth conductive layer and the anode layer, and the first planarization layer may be between the fourth insulating layer and the fourth conductive layer. The first and second planarization layers of the light-transmitting region may be removed. For another example, the transparent conductive layer may not be disposed in the second display region, and the transparent conductive layer may be disposed only in the first display region. However, this embodiment is not limited to this.

At least one embodiment of the present disclosure further provides a display device including the display substrate as described above.

Fig. 18 is a schematic view of a display device according to at least one embodiment of the present disclosure. As shown in fig. 18, the present embodiment provides a display device including: a display substrate 91 and a photosensitive sensor 92 located on the light-emitting side of the display structure layer far from the display substrate 91. The orthographic projection of the photosensor 92 on the display substrate 91 overlaps the first display area a 1.

In some examples, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be: the OLED display, the mobile phone, the tablet computer, the television, the display, the notebook computer, the digital photo frame, the navigator and other products or components with display functions, which is not limited in the embodiments of the present disclosure.

The drawings in this disclosure relate only to the structures to which this disclosure relates and other structures may be referred to in the general design. Without conflict, features of embodiments of the present disclosure, i.e., embodiments, may be combined with each other to arrive at new embodiments.

It will be understood by those skilled in the art that various modifications and equivalent arrangements may be made in the present disclosure without departing from the spirit and scope of the present disclosure, and the scope of the appended claims should be accorded the full scope of the disclosure.