阅读说明：本技术 高性能双栅ltpo面板结构及制备工艺 (High-performance double-gate LTPO panel structure and preparation process ) 是由 陈宇怀 黄志杰 陈伟 于 2021-10-08 设计创作，主要内容包括：本发明公开了高性能双栅LTPO面板结构及制备工艺,基板上端设置有缓冲层,缓冲层上端设置有多晶硅层,缓冲层上端设置有第一栅极绝缘层,且第一栅极绝缘层成膜导电层上设置有第一栅极和驱动电路走线,第一栅极上端设置有第一中间绝缘层,第一中间绝缘层上端设置有Oxide有源层,Oxide有源层上端设置有第三栅极绝缘层,第三栅极绝缘层之上成膜导电层并图案化形成第二栅极、桥接区和栅极驱动线路,第二栅极之上成膜第二中间绝缘层,第二中间绝缘层上端设置有第三金属层,第三金属层外部设置有钝化层。在Oxide-TFT中引入Dual-Gate结构,可提高器件开态电流以及stress稳定性；IGZO/有效提高Oxide-TFT电子迁移率；通过采用W/Mo叠层结构,可以使Mo金属电阻降低30%,实现低功耗。(The invention discloses a high-performance double-gate LTPO panel structure and a preparation process, wherein a buffer layer is arranged at the upper end of a substrate, a polycrystalline silicon layer is arranged at the upper end of the buffer layer, a first grid insulation layer is arranged at the upper end of the buffer layer, a first grid and a driving circuit wire are arranged on a film forming conducting layer of the first grid insulation layer, a first middle insulation layer is arranged at the upper end of the first middle insulation layer, an Oxide active layer is arranged at the upper end of the Oxide active layer, a third grid insulation layer is arranged at the upper end of the Oxide active layer, a film forming conducting layer is arranged on the third grid insulation layer and is patterned to form a second grid, a bridging area and a grid driving circuit, a second middle insulation layer is formed on the second grid, a third metal layer is arranged at the upper end of the second middle insulation layer, and a passivation layer is arranged outside the third metal layer. The Dual-Gate structure is introduced into the Oxide-TFT, so that the on-state current and stress stability of the device can be improved; IGZO/effectively improves the electron mobility of Oxide-TFT; by adopting the W/Mo laminated structure, the Mo metal resistance can be reduced by 30 percent, and low power consumption is realized.)

1. High performance double gate LTPO panel structure, including base plate (1), its characterized in that: the upper end of the substrate (1) is provided with a buffer layer (2), the upper end of the buffer layer (2) is provided with a polysilicon layer (3), the upper end of the buffer layer (2) is provided with a first grid insulation layer (4), a film-forming conductive layer of the first grid insulation layer (4) is provided with a first grid electrode (5) and a drive circuit routing, the upper end of the first grid electrode (5) is provided with a first intermediate insulation layer (6), the upper end of the first intermediate insulation layer (6) is provided with an Oxide active layer (7), the upper end of the Oxide active layer (7) is provided with a third grid insulation layer (8), the film-forming conductive layer is arranged on the third grid insulation layer (8) and is patterned to form a second grid electrode (9), a bridging area (10) and a grid drive circuit, the film-forming second intermediate insulation layer (11) is arranged on the second grid electrode (9), the upper end of the second intermediate insulation layer (11) is provided with a third metal layer (12), and a passivation layer (13) is arranged outside the third metal layer (12).

2. The high performance dual gate LTPO panel structure of claim 1, wherein: buffer layer (2) are inorganic oxide or insulating property's compound, and the thick scope of buffer layer (2) membrane is 100um ~ 500nm, the thick scope of polycrystalline silicon layer (3) membrane is 20 ~ 200um, first grid insulation layer (4) are inorganic oxide or insulating property's compound, and the thick scope of membrane is 100um ~ 400 um.

3. The high performance dual gate LTPO panel structure of claim 1, wherein: the film-forming conducting layer can be one or a plurality of stacked layers of metal with excellent conductivity, the film thickness ranges from 100um to 400um, and B is adopted on the first grid insulating layer (4)₂H₆P + doping is carried out on a source drain contact area of the LTPS-TFT device by gas, the first intermediate insulating layer (6) is used as an LTPS intermediate dielectric layer and an Oxide-TFT gate insulating layer, the film thickness range is 100-400 um, and the first intermediate insulating layer (6) and the first gate insulating layer (4) are made of the same material.

4. The high performance dual gate LTPO panel structure of claim 1, wherein: the Oxide active layer (7) is any one of IGZO, IGZTO, IGTO, Pr-IZO and InO, the third grid insulating layer (8) is the same as the first grid insulating layer (4), the third grid insulating layer (8) is patterned through a photomask, the surface of a source and drain contact region of the Oxide-TFT device is exposed by etching, and the second middle insulating layer (11) is the same as the first grid insulating layer (4) in material and is etched to form a through hole.

5. The high performance dual gate LTPO panel structure of claim 1, wherein: the first grid (5) and the second grid (9) are connected through a bridge region (10) through a third metal layer (12), and the passivation layer (13) is any one of an inorganic insulating oxide and a compound with insulating property.

6. The high performance dual gate LTPO panel structure of claim 1, wherein: all be provided with substrate (14) in first grid (5) and second grid (9), substrate (14) upper end has metal seed crystal layer (15) through physical sputtering deposition, and metal seed crystal layer (15) can be W and MoW alloy, and thickness is 2 ~ 30nm, and metal Mo layer (16) have been deposited to metal seed crystal layer (15) upper end, and thickness is 100 ~ 400 nm.

7. A process for making a high performance double gate LTPO panel structure as claimed in claims 1-6 wherein: the method specifically comprises the following steps:

s1, preparing a buffer layer: a first insulating layer is manufactured on a substrate to be used as a buffer layer (2), and the material can be inorganic oxide or compound with insulating property, such as SiOx, SiNx, titanium oxide and aluminum oxide material, and is subjected to single-layer coating or multi-layer coating with the thickness of 100 um-500 nm, preferably SiOx 300 um;

s2, p-Si preparation: forming an amorphous silicon layer, storing for 2H at 450 ℃ and in an N2 environment, removing H +, performing blue-laser-annealing process treatment on the amorphous silicon layer to crystallize the amorphous silicon layer to form a polysilicon layer (3) p-Si, and patterning, wherein the film thickness is 20-200 um, preferably 45 um;

s3, preparing a first gate insulation layer: a first grid insulation layer (4) is manufactured on the polycrystalline silicon layer (3), the material can be inorganic insulation oxide or compound with insulation property, such as SiOx, SiNx, titanium oxide and aluminum oxide, the SiOx is preferred, and the film thickness ranges from 100um to 400um, and is preferred to be 100 um;

s4, preparing a first grid: forming a conductive layer on the first grid insulation layer (4) to manufacture a thin film transistor grid and related drive circuit wiring, wherein the thin film transistor grid is a first grid (5), the conductive film layer can be one or more stacked layers of metal with excellent conductivity such as aluminum, tungsten, molybdenum, titanium, nickel, copper, silver and niobium chromium, such as Mo/Al/Mo, Mo/Cu, Ti/Al/Ti and alloys such as MoTi/Cu, MoNb/Al and MoAlTi/Al, the film thickness ranges from 100um to 400um, preferably a W/Mo stacked structure metal film layer is used as a device grid, in the first grid (5), a metal seed crystal layer (15) is deposited on a substrate (14) through physical sputtering, W and MoW alloys can be selected, the thickness is 2-30 nm, preferably 10nm, a metal Mo layer (16) is continuously deposited on the metal seed crystal layer (15), the thickness is 100-400 nm, preferably 300 nm;

s5, P + doping process: by using B₂H₆P + doping is carried out on a source drain contact area of the LTPS-TFT device by using the gases to enable the source drain contact area to be conductive, the source drain contact area is taken out to be dug before doping, the upper surface of P-Si is exposed, and then ion doping is carried out;

s6, preparing a first intermediate insulating layer: forming an insulating layer on the first grid (5) to serve as an LTPS (low temperature poly-silicon) intermediate dielectric layer and an Oxide-TFT (thin film transistor) grid insulating layer, wherein the first intermediate insulating layer (6) is also called as a second grid insulating layer, performing high temperature annealing treatment after film forming at the temperature range of 350-490 ℃ for 10 s-2 h, and selecting the material to be the same as that of the first grid insulating layer (4), preferably SiOx, and the film thickness range is 100-400 um, preferably 200 um;

s7, Oxide active layer preparation: an oxide active layer is manufactured on the first intermediate insulating layer (6), annealing is carried out at the speed of 350 ℃/1h, the materials of IGZO, IGZTO, IGTO, Pr-IZO and InO can be selected, IGZO is preferred, the active layer is manufactured In an IGZO/InO lamination mode, the thickness of the film ranges from 20um to 80um, 50um is preferred, In the IGZO/InO manufacturing process, the thickness of IGZO is 10-60 nm, 20nm is preferred, In is In₂O₃The thickness is 10-60 nm, preferably 50 nm;

s8, preparing a third gate insulation layer: manufacturing a third gate insulating layer (8) on the Oxide active layer (7), wherein the material is selected from the buffer layer (2);

s9, preparing a second grid: forming a conducting layer on the third gate insulating layer (8), wherein the conducting layer is made of the same material as the first gate (5), patterning is carried out to form a second gate (9), a bridging region (10) and a gate drive circuit, the third gate insulating layer (8) is patterned again through the same photomask, the surface of a source and drain contact region of the Oxide-TFT device is exposed through etching, optionally, N + doping is carried out on the source and drain contact region, in the second gate (9), a metal seed crystal layer (15) is deposited on the substrate (14) through physical sputtering, the seed crystal layer is made of W and MoW alloy, the thickness is 2-30 nm, preferably 10nm, a metal Mo layer (16) is continuously deposited on the metal seed crystal layer (15), and the thickness is 100-400 nm, preferably 300 nm;

s10, preparing a second intermediate insulating layer: forming a second intermediate insulating layer (11) on the second grid electrode (9), selecting a material and a buffer layer (2), etching a through hole to expose the upper surface of a source/drain contact region p-Si of the LTPS-TFT device, the upper surface of an Oxide active layer of the source/drain contact region of the Oxide-TFT, and the upper surfaces of the first grid electrode (5) and the second grid electrode (9) of the bridging region (10);

s11, preparing a third metal layer: forming a film source drain electrode metal layer on the second intermediate insulating layer (11) and patterning the film source drain electrode metal layer, wherein the material is selected to be the same as the grid electrode metal layer, and the first grid electrode (5) is connected with the second grid electrode (9) through the third metal layer (12) through the bridging region (10) so that upper and lower gate signals of Oxide-TFT are consistent;

s12, preparing a passivation layer: a passivation layer (13) is formed on the source and drain electrodes, and the material can be inorganic insulating oxide or compound with insulating property, such as SiOx, SiNx, titanium oxide and aluminum oxide, and SiOx/SiNx double layers are preferable.

Technical Field

The invention belongs to the technical field of display back plates, and particularly relates to a high-performance double-gate LTPO panel structure and a preparation process thereof.

Background

In recent years, a low-temperature polysilicon oxide LTPO thin film transistor is widely concerned in the active matrix organic light emitting diode display back panel technology, among metal oxide TFTs, amorphous indium gallium zinc oxide a-IGZOTFT is most popular at present, the oxide thin film transistor has ultralow off-leakage current smaller than 10-14A and higher mobility exceeding 10cm2/V.s, can realize low-frequency driving and reduce power consumption, and can be manufactured at low temperature with lower manufacturing cost; on the other hand, the LTPS TFT has high mobility and excellent stability, and is easy to realize the manufacture of an ultrahigh-resolution display panel, but the off-state current of the LTPS TFT is high and is between 10 and 12A, low-frequency driving cannot be realized, so that the power consumption of the panel is high, two-side profit can be realized by mixing the two TFT technologies, the panel with high resolution and capable of realizing low-frequency driving is produced, and the high-quality display effect and the low power consumption can be realized.

In general, LTPS-TFT and metal oxide TFT backplane processes are incompatible, LTPS-TFT requires a large number of hydrogen atoms to passivate dangling bonds and defects inside the poly-Si and at the interface of the poly-Si and the gate insulator, however, excessive hydrogen gas can cause an imbalance between oxygen vacancies and metal oxygen bonds, resulting in an oxide TFT device threshold voltage Vth shift; this Vth shift phenomenon will be more pronounced at low display drive frequencies due to the increased negative bias applied to the metal oxide switching TFT; the metal oxide switching TFT needs to be robust enough to exhibit a minimum threshold voltage Vth shift to reduce image degradation.

Researches find that the double-gate driven a-IGZO TFT not only obviously improves the stability of the device, but also obtains higher drain current and stronger subthreshold slope while keeping lower turn-off current, and is superior to a single-gate driven device; in order to improve the stability of the oxide transistor in the LTPO thin film transistor and further improve the electron mobility of the oxide transistor, the on-state current Ion of the device and the like.

Therefore, we propose a high performance dual gate LTPO panel structure and fabrication process to solve the above mentioned problems in the background art.

Disclosure of Invention

The present invention is directed to a high performance dual gate LTPO panel structure and a manufacturing process thereof, which solves the above problems.

In order to achieve the purpose, the invention provides the following technical scheme: high performance double gate LTPO panel structure, including the base plate, the base plate upper end is provided with the buffer layer, and the buffer layer upper end is provided with the polycrystalline silicon layer, and the buffer layer upper end is provided with first grid insulating layer, and is provided with first grid and drive circuit on the first grid insulating layer film-forming conducting layer and walks the line, first grid upper end is provided with first intermediate insulation layer, and first intermediate insulation layer upper end is provided with Oxide active layer, Oxide active layer upper end is provided with third grid insulating layer, form film-forming conducting layer and patterning formation second grid, bridging district and gate drive circuit on the third grid insulating layer, film-forming second intermediate insulation layer on the second grid, second intermediate insulation layer upper end is provided with the third metal level, and third metal level outside is provided with the passivation layer.

Preferably, the buffer layer is inorganic oxide or insulating property's compound, and the thick scope of buffer layer membrane is 100um ~ 500nm, the thick scope of polycrystalline silicon layer membrane is 20 ~ 200um, first grid insulation layer is inorganic oxide or insulating property's compound, and the thick scope of membrane is 100um ~ 400 um.

Preferably, the film-forming conductive layer can be one or more stacked layers of metal with excellent conductivity, the film thickness ranges from 100um to 400um, and the first gate insulating layer is provided with B₂H₆P + doping is carried out on a source drain contact area of the LTPS-TFT device by gas, the first intermediate insulating layer is used as an LTPS intermediate dielectric layer and an Oxide-TFT gate insulating layer, the thickness range of the film is 100-400 um, the first intermediate insulating layer is made of the same material as the first gate insulating layer, the Oxide active layer is any one of IGZO, IGZTO, IGTO, Pr-IZO and InO, the third gate insulating layer is the same as the first gate insulating layer, the third gate insulating layer is patterned through a photomask, the surface of the source drain contact area of the Oxide-TFT device is exposed by etching, and the second intermediate insulating layer and the first intermediate insulating layer are exposed through etchingThe gate insulating layer is made of the same material, and a through hole is etched.

Preferably, the first grid electrode and the second grid electrode are connected through a third metal layer through a bridging area, the passivation layer is any one of inorganic insulating oxide and insulating compounds, substrates are arranged in the first grid electrode and the second grid electrode, a metal seed crystal layer is deposited at the upper end of the substrate through physical sputtering, the metal seed crystal layer can be W and MoW alloy, the thickness of the metal seed crystal layer is 2-30 nm, a metal Mo layer is deposited at the upper end of the metal seed crystal layer, and the thickness of the metal Mo layer is 100-400 nm.

The preparation process of the high-performance double-gate LTPO panel structure specifically comprises the following steps:

s1, preparing a buffer layer: a first insulating layer is manufactured on a substrate to be used as a buffer layer, and the material can be inorganic oxide or compound with insulating property, such as SiOx, SiNx, titanium oxide and aluminum oxide material, and is subjected to single-layer coating or multi-layer coating with the thickness of 100 um-500 nm, preferably SiOx 300 um;

s2, p-Si preparation: forming an amorphous silicon layer, storing for 2H at 450 ℃ and in an N2 environment, performing H + removal treatment, and performing blue-laser-annealing process treatment on the amorphous silicon layer to crystallize the amorphous silicon layer to form a polysilicon layer p-Si and pattern the polysilicon layer p-Si, wherein the film thickness is 20-200 um, and preferably 45 um;

s3, preparing a first gate insulation layer: a first grid insulating layer is manufactured on the polycrystalline silicon layer, the material can be inorganic insulating oxide or compound with insulating property, such as SiOx, SiNx, titanium oxide and aluminum oxide, the SiOx is preferred, and the film thickness ranges from 100um to 400um, and is preferred to be 100 um;

s4, preparing a first grid: forming a conductive layer on the first gate insulating layer to manufacture a thin film transistor gate and related drive circuit wiring, wherein the thin film transistor gate is a first gate, the conductive film layer can be one or more stacked layers of metals with excellent conductivity such as aluminum, tungsten, molybdenum, titanium, nickel, copper, silver and niobium chromium, such as Mo/Al/Mo, Mo/Cu, Ti/Al/Ti and alloys such as MoTi/Cu, MoNb/Al and MoAlTi/Al, the film thickness range is 100-400 um, preferably, a W/Mo stacked structure metal film layer is used as a device gate, in the first gate, a metal seed crystal layer is deposited on a substrate through physical sputtering, a W and MoW alloy can be selected, the thickness is 2-30 nm, preferably 10nm, a metal Mo layer is continuously deposited on the metal seed crystal layer, and the thickness is 100-400 nm, preferably 300 nm;

s5, P + doping process: by using B₂H₆P + doping is carried out on a source drain contact area of the LTPS-TFT device by using the gases to enable the source drain contact area to be conductive, the source drain contact area is taken out to be dug before doping, the upper surface of P-Si is exposed, and then ion doping is carried out;

s6, preparing a first intermediate insulating layer: forming an insulating layer on the first grid electrode to serve as an LTPS (low temperature poly-silicon) intermediate dielectric layer and an Oxide-TFT (thin film transistor) grid electrode insulating layer, wherein the first intermediate insulating layer is also called a second grid electrode insulating layer, performing high-temperature annealing treatment at the temperature of 350-490 ℃ for 10 s-2 h after film forming, and selecting the material to be the same as the first grid electrode insulating layer, preferably SiOx, and the film thickness range is 100-400 um, preferably 200 um;

s7, Oxide active layer preparation: an oxide active layer is manufactured on the first middle insulating layer, annealing is carried out at 350 ℃/1h, the materials of IGZO, IGZTO, IGTO, Pr-IZO and InO can be selected, IGZO is preferred, the active layer is manufactured In an IGZO/InO laminated mode, the film thickness ranges from 20um to 80um, 50um is preferred, In the IGZO/InO manufacturing process, the thickness of IGZO ranges from 10nm to 60nm, 20nm is preferred, In is In₂O₃The thickness is 10-60 nm, preferably 50 nm;

s8, preparing a third gate insulation layer: manufacturing a third gate insulating layer on the Oxide active layer, wherein the material is selected from the same buffer layer;

s9, preparing a second grid: forming a conducting layer on the third gate insulating layer, wherein the conducting layer is made of the same material as the first gate, patterning is carried out to form a second gate, a bridging region and a gate drive circuit, the third gate insulating layer is patterned again through the same photomask, the surface of a source and drain contact region of the Oxide-TFT device is exposed through etching, optionally, N + doping is carried out on the source and drain contact region, in the second gate, a metal seed crystal layer is deposited on the substrate through physical sputtering, W and MoW alloy are selected, the thickness is 2-30 nm, preferably 10nm, a metal Mo layer is continuously deposited on the metal seed crystal layer, and the thickness is 100-400 nm, preferably 300 nm;

s10, preparing a second intermediate insulating layer: forming a second intermediate insulating layer on the second grid electrode, selecting a material and a buffer layer, etching a through hole, and exposing the upper surface of a source/drain contact region p-Si of the LTPS-TFT device, the upper surface of an Oxide active layer of the source/drain contact region of the Oxide-TFT, and the upper surfaces of a first grid electrode and a second grid electrode of a bridging region;

s11, preparing a third metal layer: forming a film source drain electrode metal layer on the second intermediate insulating layer and patterning the film source drain electrode metal layer, wherein the material is selected to be the same as the grid electrode metal layer, and the first grid electrode is connected with the second grid electrode through the third metal layer through the bridging area, so that upper and lower gate signals of the Oxide-TFT are consistent;

s12, preparing a passivation layer: and a passivation layer is formed on the source and drain electrodes, and the material can be inorganic insulating oxide or compound with insulating property, such as SiOx, SiNx, titanium oxide and aluminum oxide, and SiOx/SiNx double layers are preferred.

Compared with the prior art, the invention has the beneficial effects that: according to the high-performance double-Gate LTPO panel structure and the preparation process, the double-Gate structure is introduced into the Oxide-TFT, so that the extremely low off-state current of the Oxide TFT is maintained, and the on-state current and stress stability of a device can be improved; in an Oxide-TFT device, when one of the Oxide-TFT devices uses an IGZO material, H2 and N2 code processes are introduced, so that the electron mobility of the device can be effectively improved, and the preparation of the high-performance Oxide-TFT is realized; in Oxide-TFT devices, a dual Oxide active layer structure such as IGZO/In is included₂O₃The structure can effectively improve the electron mobility of Oxide-TFT; in one metal material used by LTPS-Top-Gate and Oxide-Top/Bottom-Gate, by adopting W/Mo laminated structure, the Mo metal resistance can be reduced by 30%, and low power consumption can be realized.

Drawings

FIG. 1 is a schematic left-view diagram of a dual gate LTPO panel structure of the present invention;

FIG. 2 is a gate metal process of the present invention;

FIG. 3 is an Oxide active layer optimization process _ N/H-coding;

FIG. 4 shows an Oxide active layer optimization process of Bilayer-stack of IGZO/In₂O₃；

FIG. 5 is a schematic structural view of example 1 of the present invention;

FIG. 6 is a schematic structural view of example 2 of the present invention;

FIG. 7 is a schematic structural view of example 3 of the present invention;

FIG. 8 is a schematic structural view of example 4 of the present invention;

fig. 9 is a schematic structural diagram of embodiment 5 of the present invention.

In the figure: 1. a substrate; 2. a buffer layer; 3. a polysilicon layer; 4. a first gate insulating layer; 5. a first gate electrode; 6. a first intermediate insulating layer; 7. an Oxide active layer; 8. a third gate insulating layer; 9. a second gate electrode; 10. a bridging area; 11. a second intermediate insulating layer; 12. a third metal layer; 13. a passivation layer; 14. a substrate; 15. a metal seed layer; 16. a metal Mo layer.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example 1

The present invention provides a high performance dual gate LTPO panel structure as shown in fig. 1-5, comprising a substrate 1, a buffer layer 2 is arranged at the upper end of the substrate 1, a polysilicon layer 3 is arranged at the upper end of the buffer layer 2, a first grid insulation layer 4 is arranged at the upper end of the buffer layer 2, and the first gate insulating layer 4 is formed on the conductive layer and provided with a first gate 5 and a driving circuit trace, a first intermediate insulating layer 6 is arranged at the upper end of the first grid electrode 5, an Oxide active layer 7 is arranged at the upper end of the first intermediate insulating layer 6, a third gate insulation layer 8 is arranged at the upper end of the Oxide active layer 7, a conductive layer is formed on the third gate insulation layer 8 and patterned to form a second gate 9, a bridge region 10 and a gate driving circuit, a second intermediate insulating layer 11 is formed on the second gate 9, a third metal layer 12 is disposed on the upper end of the second intermediate insulating layer 11, and a passivation layer 13 is disposed outside the third metal layer 12.

Buffer layer 2 is inorganic oxide or insulating property's compound, and the thick scope of buffer layer 2 membrane is 100um ~ 500nm, the thick scope of 3 membrane of polycrystalline silicon layer is 20 ~ 200um, first gate insulation layer 4 is inorganic oxide or insulating property's compound, and the thick scope of membrane is 100um ~ 400 um.

The film-forming conductive layer can be one or a plurality of stacked layers of metal with excellent conductivity, the film thickness ranges from 100um to 400um, and the first grid insulating layer 4 is provided with B₂H₆P + doping is carried out on a source drain contact area of the LTPS-TFT device by gas, the first intermediate insulating layer 6 is used as an LTPS intermediate dielectric layer and an Oxide-TFT gate insulating layer, the thickness range of the film is 100-400 um, and the first intermediate insulating layer 6 is made of the same material as the first gate insulating layer 4.

The Oxide active layer 7 is any one of IGZO, IGZTO, IGTO, Pr-IZO and InO, the third gate insulating layer 8 is the same as the first gate insulating layer 4, the third gate insulating layer 8 is patterned through a photomask, the surface of a source-drain contact region of the Oxide-TFT device is exposed by etching, and the second intermediate insulating layer 11 is the same as the first gate insulating layer 4 in material and is etched to form a through hole.

The first gate electrode 5 and the second gate electrode 9 are connected via a bridge region 10 via a third metal layer 12, and the passivation layer 13 is any one of an inorganic insulating oxide and a compound having insulating properties.

The substrate 14 is arranged in each of the first grid 5 and the second grid 9, the metal seed crystal layer 15 is deposited at the upper end of the substrate 14 through physical sputtering, the metal seed crystal layer 15 can be W and MoW alloy, the thickness is 2-30 nm, the metal Mo layer 16 is deposited at the upper end of the metal seed crystal layer 15, and the thickness is 100-400 nm.

Molybdenum Mo is generally used as a gate metal material for various thin film transistors due to its good reliability and conductivity.

The preparation process of the high-performance double-gate LTPO panel structure specifically comprises the following steps:

s1, preparing a buffer layer: a first insulating layer is made on the substrate as a buffer layer 2, and the material can be inorganic oxide or compound with insulating property, such as SiOx, SiNx, titanium oxide, and aluminum oxide material, and is subjected to single-layer coating or multi-layer coating with a thickness of 100 um-500 nm, preferably SiOx 300 um;

s2, p-Si preparation: forming an amorphous silicon layer, storing for 2H at 450 ℃ and in an N2 environment, performing H + removal treatment, and performing blue-laser-annealing process treatment on the amorphous silicon layer to crystallize the amorphous silicon layer to form a polycrystalline silicon layer 3p-Si and pattern the polycrystalline silicon layer, wherein the film thickness is 20-200 um, and preferably 45 um;

s3, preparing a first gate insulation layer: a first gate insulating layer 4 is formed on the polysilicon layer 3, and the material can be selected from inorganic insulating oxide or insulating compound, such as SiOx, SiNx, titanium oxide, and aluminum oxide, preferably SiOx, with a film thickness ranging from 100um to 400um, preferably 100 um;

s4, preparing a first grid: forming a conductive layer on the first gate insulating layer 4 to manufacture a thin film transistor gate and related drive circuit wiring, wherein the thin film transistor gate is a first gate 5, the conductive film layer can be one or more stacked layers of metals with excellent conductivity such as aluminum, tungsten, molybdenum, titanium, nickel, copper, silver and niobium chromium, such as Mo/Al/Mo, Mo/Cu, Ti/Al/Ti and alloys such as MoTi/Cu, MoNb/Al and MoAlTi/Al, the film thickness range is 100-400 um, preferably, a W/Mo stacked structure metal film layer is used as a device gate, in the first gate 5, a metal seed crystal layer 15 is deposited on a substrate 14 through physical sputtering, W and MoW alloys can be selected, the thickness is 2-30 nm, preferably 10nm, a metal Mo layer 16 is continuously deposited on the metal seed crystal layer 15, the thickness is 100-400 nm, preferably 300 nm;

s5, P + doping process: by using B₂H₆P + doping is carried out on a source drain contact area of the LTPS-TFT device by using the gases to enable the source drain contact area to be conductive, the source drain contact area is taken out to be dug before doping, the upper surface of P-Si is exposed, and then ion doping is carried out;

s6, preparing a first intermediate insulating layer: forming an insulating layer on the first grid 5 to serve as an LTPS (low temperature poly-silicon) intermediate dielectric layer and an Oxide-TFT (thin film transistor) grid insulating layer, wherein the first intermediate insulating layer 6 is also called a second grid insulating layer, performing high-temperature annealing treatment at the temperature of 350-490 ℃ for 10 s-2 h after film forming, and selecting the material to be the same as the first grid insulating layer 4, preferably SiOx, and the film thickness range is 100-400 um, preferably 200 um;

s7, Oxide active layer preparation: in thatAn oxide active layer is manufactured on the first middle insulation layer 6, annealing is carried out at 350 ℃/1h, the materials of IGZO, IGZTO, IGTO, Pr-IZO and InO can be selected, IGZO is preferred, the active layer is manufactured In an IGZO/InO laminated mode, the film thickness ranges from 20um to 80um, 50um is preferred, In the IGZO/InO manufacturing process, the thickness of IGZO ranges from 10nm to 60nm, 20nm is preferred, In is In the IGZO/InO manufacturing process₂O₃The thickness is 10-60 nm, preferably 50 nm;

s8, preparing a third gate insulation layer: a third gate insulating layer 8 is manufactured on the Oxide active layer 7, and the material is selected from the buffer layer 2;

s9, preparing a second grid: forming a conductive layer on the third gate insulation layer 8, wherein the conductive layer is made of the same material as the first gate 5 and is patterned to form a second gate 9, a bridging region 10 and a gate drive circuit, patterning the third gate insulation layer 8 again through the same photomask, etching to expose the surface of a source-drain contact region of an Oxide-TFT device, optionally performing N + doping on the source-drain contact region, depositing a metal seed crystal layer 15, optionally W and MoW alloy, with the thickness of 2-30 nm, preferably 10nm, on the substrate 14 in the second gate 9 through physical sputtering, and continuously depositing a metal Mo layer 16 with the thickness of 100-400 nm, preferably 300nm on the metal seed crystal layer 15;

s10, preparing a second intermediate insulating layer: forming a second intermediate insulating layer 11 on the second grid 9, selecting a material and a buffer layer 2, etching a through hole to expose the upper surface of a source/drain contact region p-Si of the LTPS-TFT device, the upper surface of an Oxide active layer of the source/drain contact region of the Oxide-TFT, and the upper surfaces of the first grid 5 and the second grid 9 of the bridging region 10;

s11, preparing a third metal layer: forming a source drain electrode metal layer on the second intermediate insulating layer 11 and patterning the source drain electrode metal layer, wherein the material is selected to be the same as the grid electrode metal layer, and the first grid electrode 5 is connected with the second grid electrode 9 through a bridging area 10 via a third metal layer 12, so that upper and lower gate signals of Oxide-TFT are consistent;

s12, preparing a passivation layer: a passivation layer 13 is formed on the source and drain electrodes, and the material may be selected from inorganic insulating oxide or insulating compound, such as SiOx, SiNx, titanium oxide, and aluminum oxide, and preferably a SiOx/SiNx double layer.

Example 2

The invention provides a high-performance double-gate LTPO panel structure as shown in figure 2, figure 3, figure 4 and figure 6, compared with the double-gate LTPO panel structure in the embodiment 1, a metal layer is formed on a third gate insulating layer 8 and is patterned to form a second gate 9, a lap joint region and a gate driving circuit, the third insulating layer is patterned again by the same photomask, the surface of a source and drain contact region of an Oxide-TFT device is exposed by etching, a through hole is arranged on the third gate insulating layer 8 in the lap joint region to expose the upper surface of a first gate 5, a second intermediate insulating layer 11 is formed on the second gate 9, the material is selected from the same buffer layer 2, the through hole is etched to expose the upper surface of a source and drain contact region p-Si of the LTPS TFT device and the upper surface of an Oxide active source and drain layer of the Oxide-TFT contact region, the difference between the embodiment 1 and the embodiment 2 lies in that the lap joint region 10 is different, embodiment 2 the second gate 9 is directly connected to the first gate 5 through an insulating layer via;

example 3

The invention provides a high-performance double-gate LTPO panel structure as shown in a figure 2, a figure 3, a figure 4 and a figure 7, compared with the double-gate LTPO panel structure in an embodiment 1, a film forming conducting layer is formed on an insulating layer of a first grid 5 to manufacture a thin film transistor grid and related drive circuit routing, the material selection is the same as that in the embodiment 1, and P + doping is carried out on a source drain contact area of an LTPS-TFT device to enable the source drain contact area to be conductive, in one process, the insulating layer is patterned by using a photomask the same as the first grid 5 before doping, the upper surface of P-Si is exposed by etching, and then ion doping is carried out;

a third Gate insulating layer 8 is manufactured on an Oxide active layer 7, a material is selected from the same buffer layer 2, a source and drain metal layer is formed on a second intermediate insulating layer 11 and is patterned, a material is selected from the same Gate metal layer, a passivation layer is manufactured on a source and drain electrode, the material can be selected from inorganic insulating Oxide or a compound with insulating property, such as SiOx, SiNx, titanium Oxide and aluminum Oxide, preferably SiOx/SiNx double layers, meanwhile, metal is reserved above an Oxide-TFT-channel to be used as Top-Gate, the upper surface of the active layer of the source and drain electrode contact region of the LPTS-TFT is exposed by etching, the upper surface of the active layer of the source and drain electrode contact region of the Oxide-TFT, the upper surface of the first Gate 5 of the lap joint region, and the main difference between the embodiment 3 and the embodiment 1 is that the Oxide-TFT-Top-Gate and the source and drain electrode share one metal layer, so that the process is simplified;

example 4

The invention provides a high-performance double-gate LTPO panel structure as shown in a figure 2, a figure 3, a figure 4 and a figure 8, compared with the double-gate LTPO panel structure in an embodiment 3, a film forming conducting layer is formed on an insulating layer of a first grid 5 to manufacture a thin film transistor grid and related drive circuit routing, the material selection is the same as that in the embodiment 1, and P + doping is carried out on a source drain contact region of an LTPS-TFT device to enable the source drain contact region to be conductive, in one process, the insulating layer is patterned by using the same photomask as the first grid 5 before doping, the upper surface of P-Si is exposed by etching, then ion doping is carried out, a film forming source drain metal layer is formed on a second middle insulating layer 11 and is patterned, and the material selection is the same as the grid metal layer;

meanwhile, metal is reserved above the Oxide-TFT-channel to be used as Top-Gate, a film forming insulating layer is formed on a source drain electrode to be used as an Oxide intermediate dielectric layer, the material is selected to be the same as the first grid insulating layer 4, SiOx/SiNx double layers are preferred, the film thickness range is 100-400 um, 200um is preferred, through holes are manufactured through photoresist exposure and etching processes to expose the upper surface of the first grid 5, metal is reserved above the Oxide-TFT-channel to be used as Top-Gate, and a bridging area 10 is connected with the first grid 5 through a through hole of a second intermediate insulating layer 11, the main difference between the embodiment 4 and the embodiment 3 is that another layer of metal used as Oxide-TFT-Top-Gate in the device design in the actual process in the embodiment 3, the film layer matching structure is large in adjustable space, the optimization of the device is facilitated, and the yield is improved;

example 5

The invention provides a high-performance dual-gate LTPO panel structure as shown in FIG. 2, FIG. 3, FIG. 4 and FIG. 9, compared with the dual-gate LTPO panel structure in embodiment 4, a source drain metal layer is formed and patterned on an Oxide active layer 7, a material is selected to be the same as a gate metal layer, a third gate insulating layer 8 is formed on the Oxide active layer, and a material is selected to be the same as a buffer layer 2; through holes are manufactured through etching to expose the upper surface of the first grid 5 in the overlapping area, metal is reserved above the Oxide-TFT-channel to serve as Top-Gate, and the bridging area 10 is connected with the first grid 5 through the second middle insulating layer 11 through holes, the main difference between the embodiment 5 and the embodiment 4 is that the Oxide-TFT device in the embodiment 5 simplifies a film layer structure between the Top-Gate and the Oxide active layer 7, only one layer of the third grid insulating layer 8 can meet the requirement of device design, the device design in the embodiment 4 is reserved, the advantage that the adjustable space of a film layer matching structure is large is achieved, the cost is further reduced, and the yield is improved.

In summary, compared with the prior art, the LTPO panel structure of the invention is characterized in that a Dual-Gate structure is introduced into the Oxide-TFT, so that the on-state current and stress stability of the device can be improved while the extremely low off-state current of the Oxide TFT is maintained;

in the Oxide-TFT device, when one of the IGZO materials is used, H2 and N2 code processes are introduced, so that the electron mobility of the device can be effectively improved, and the preparation of the high-performance Oxide-TFT is realized;

the Oxide-TFT device comprises a double-layer Oxide active layer structure such as IGZO/In₂O₃The structure can effectively improve the electron mobility of Oxide-TFT;

in one metal material used by the LTPS-Top-Gate and Oxide-Top/Bottom-Gate of the invention, the W/Mo laminated structure is adopted, so that the Mo metal resistance can be reduced by 30%, and low power consumption is realized.

Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments or portions thereof without departing from the spirit and scope of the invention.