阅读说明：本技术 存储器阵列以及用于形成存储器阵列和导电阵列通孔(tav)的方法 (Memory array and method for forming memory array and conductive array via (TAV) ) 是由 I·V·恰雷 C·E·卡特 A·查杜鲁 J·B·德胡特 房骏 M·J·金 B·D·洛 于 2020-04-07 设计创作，主要内容包括：一种用于形成存储器阵列和导电阵列通孔(TAV)的方法包括形成包括竖直交替的绝缘层和字线层的堆叠。在所述堆叠上方形成包括水平伸长的沟槽开口和操作性TAV开口的掩模。通过所述掩模中的所述沟槽开口和所述操作性TAV开口对所述堆叠的未掩蔽部分进行蚀刻以在所述堆叠中形成水平伸长的沟槽开口且在所述堆叠中形成操作性TAV开口。在所述堆叠中的所述操作性TAV开口中形成导电材料以在所述堆叠中的所述操作性TAV开口中的个别者中形成个别操作性TAV。在所述堆叠中的所述沟槽开口中的个别者中形成字线介入结构。(A method for forming a memory array and a conductive array via (TAV) includes forming a stack including vertically alternating layers of insulating layers and word lines. A mask including a horizontally elongated trench opening and an operative TAV opening is formed over the stack. An unmasked portion of the stack is etched through the trench opening and the operative TAV opening in the mask to form a horizontally elongated trench opening in the stack and an operative TAV opening in the stack. Forming conductive material in the operative TAV openings in the stack to form individual operative TAVs in individual ones of the operative TAV openings in the stack. Word line intervening structures are formed in individual ones of the trench openings in the stack.)

1. A method for forming a memory array and a conductive array via (TAV), comprising:

forming a stack comprising vertically alternating layers of insulating layers and word lines;

forming a mask comprising a horizontally elongated trench opening and an operative TAV opening over the stack;

etching an unmasked portion of the stack through the trench opening and the operative TAV opening in the mask to form a horizontally elongated trench opening in the stack and an operative TAV opening in the stack;

forming conductive material in the operative TAV openings in the stack to form individual operative TAVs in individual ones of the operative TAV openings in the stack; and

word line intervening structures are formed in individual ones of the trench openings in the stack.

2. The method of claim 1, comprising forming a string of channel material through the insulating layer and the word line layer prior to the etching.

3. The method of claim 1, comprising forming a string of channel material through the insulating layer and the word line layer after the etching.

4. The method of claim 1, comprising forming the conductive material in the individual operative TAV openings in the stack prior to forming the word line intervening structures in the stack.

5. The method of claim 1, comprising forming the wordline intervening structure in the stack prior to forming the conductive material in the individual operative TAV openings in the stack.

6. The method of claim 1, comprising:

forming the mask to include a dummy TAV opening;

the etching also forms a dummy TAV opening in the stack; and

forming dummy material in individual ones of the dummy TAV openings in the stack.

7. The method of claim 6, wherein,

the dummy material comprises the conductive material; and

forming the conductive material in the individual operative TAV openings in the stack and in the individual dummy TAV openings in the stack occurs simultaneously.

8. The method of claim 6, wherein,

the dummy material does not include the conductive material; and

forming the conductive material in the individual operative TAV openings in the stack and forming the dummy material in the individual dummy TAV openings in the stack occur at time periods of different time intervals.

9. The method of claim 8, comprising forming the conductive material in the individual operative TAV openings in the stack prior to forming the dummy material in the individual dummy TAV openings in the stack.

10. The method of claim 1, comprising forming and removing sacrificial plugs in the individual operative TAV openings in the stack and in the individual trench openings in the stack before forming the conductive material in the individual operative TAV openings in the stack and before forming the word line intervening structures in the stack.

11. The method of claim 10, wherein the sacrificial plugs in the individual operative TAV openings in the stack and in the individual trench openings in the stack are insufficient to fill the individual operative TAV openings in the stack and are insufficient to fill the individual trench openings in the stack, thereby comprising void space below individual ones of the individual operative TAV openings in the stack and the sacrificial plugs in the individual trench openings.

12. The method of claim 10, wherein the sacrificial plugs in the individual operative TAV openings in the stack and in the individual trench openings in the stack completely fill the individual operative TAV openings in the stack and completely fill the individual trench openings in the stack.

13. The method of claim 10, wherein the sacrificial plugs in the individual operative TAV openings in the stack and in the individual trench openings in the stack are formed simultaneously and removed at time periods of different time intervals.

14. The method of claim 10, comprising removing the sacrificial plug from the individual operative TAV opening in the stack prior to removing the sacrificial plug in the individual trench opening in the stack, the forming the conductive material in the individual operative TAV opening in the stack occurring prior to removing the sacrificial plug in the individual trench opening in the stack.

15. The method of claim 1, wherein the stack comprises an uppermost conductor layer, and further comprising:

a step is formed atop or over an uppermost portion of the insulating layer on at least one side of an individual wordline, the wordline intervening structure being atop the step.

16. The method of claim 1, wherein the stack comprises an uppermost conductor layer, and further comprising:

forming the wordline intervening structure to include opposing laterally outer longitudinal edges, at least some of each of the opposing laterally outer longitudinal edges above the uppermost conductor layer having a lesser overall steepness than the opposing laterally outer longitudinal edges below the uppermost conductor layer.

17. The method of claim 1, wherein the etching is performed in a single etching step.

18. A method for forming a memory array and a conductive array via (TAV), comprising:

forming a stack comprising an uppermost conductor layer and vertically alternating insulation layers and word line layers, the uppermost conductor layer and word line layers comprising a first material, the insulation layers comprising a second material having a different composition than the first material;

forming a string of channel material through the insulating layer and the word line layer;

forming a mask comprising a horizontally elongated trench opening and an operative TAV opening over the stack;

etching an unmasked portion of the stack through the trench opening and the operative TAV opening in the mask to form a horizontally elongated trench opening in the stack and an operative TAV opening in the stack;

forming conductive material in the operative TAV openings in the stack to form individual operative TAVs in individual ones of the operative TAV openings in the stack;

removing the first material after forming the conductive material in the operative TAV opening in the stack to form a wordline layer void and an uppermost conductor layer void;

Forming conductive material in the word line layer voids to comprise individual word lines and forming conductive material in the uppermost conductor layer voids; and

after forming the conductive material, word line intervening structures are formed in individual ones of the trench openings in the stack.

19. The method of claim 18, wherein forming the conductive material in the individual operative TAV openings in the stack occurs when at least all lower halves of individual ones of the trench openings in the stack are completely occluded.

20. The method of claim 19, wherein forming the conductive material in the individual operative TAV openings in the stack occurs when all individual ones of the trench openings in the stack are fully occluded.

21. The method of claim 20, wherein forming the conductive material in the individual operative TAV openings in the stack occurs when less than all of the individual trench openings in the stack are completely filled with sacrificial material, thereby including void space under the sacrificial material in the individual trench openings in the stack.

22. The method of claim 20, wherein forming the conductive material in the individual operative TAV openings in the stack occurs when all of the individual trench openings in the stack are completely filled with a sacrificial material.

23. A memory array, comprising:

a vertical stack comprising an uppermost insulating layer, an uppermost conductor layer below the insulating layer, and alternating insulating and word line layers below the uppermost conductor layer, the word line layers comprising gate regions of individual memory cells, the gate regions individually comprising portions of word lines in individual ones of the word line layers;

a string of channel material extending vertically through the insulating layer and the word line layer;

individual memory cells comprising memory structures laterally between individual ones of the gate regions and channel material of the string of channel material;

word line intervening structures extending through the stack between immediately adjacent ones of the word lines; and

a staircase on or over an uppermost top of the insulating layers of the alternating insulating layers and word line layers on at least one side of individual ones of the word lines, the word line intervening structure being located atop the staircase.

24. The memory array of claim 23, wherein the staircase is located atop the uppermost insulating layer of the alternating insulating layers and word line layers and comprises insulating material of the uppermost insulating layer of the alternating insulating layers and word line layers.

25. The memory array of claim 24, wherein the step comprises an uppermost surface of the insulative material.

26. The memory array of claim 23, wherein the staircase is located above the uppermost insulating layer of the alternating insulating and word line layers.

27. The memory array of claim 26, wherein the staircase is located above the uppermost conductor layer.

28. The memory array of claim 27, wherein the staircase is located within an insulating material of the uppermost insulating layer.

29. The memory array of claim 26, wherein the staircase is located atop the uppermost conductor layer and comprises conductive material of the conductor layer.

30. The memory array of claim 29, wherein the staircase comprises an uppermost surface of the conductive material.

31. The memory array of claim 23, wherein the staircase is located on only one side of the individual of the word lines.

32. The memory array of claim 23, wherein the staircase is located on both sides of the individual word line.

33. The memory array of claim 23, wherein the staircase is horizontal.

34. The memory array of claim 23, comprising forming under-array CMOS circuitry.

35. A memory array, comprising:

a vertical stack comprising an uppermost insulating layer, an uppermost conductor layer below the insulating layer, and alternating insulating and word line layers below the uppermost conductor layer, the word line layers comprising gate regions of individual memory cells, the gate regions individually comprising portions of word lines in individual ones of the word line layers;

a string of channel material extending vertically through the insulating layer and the word line layer;

individual memory cells comprising memory structures laterally between individual ones of the gate regions and channel material of the string of channel material;

word line intervening structures extending through the stack between immediately adjacent ones of the word lines; and

the wordline intervening structure includes opposing lateral outer longitudinal edges, at least some of each of the opposing lateral outer longitudinal edges above the uppermost conductor layer having a lesser overall steepness than the opposing lateral outer longitudinal edges below the uppermost conductor layer.

36. The memory array of claim 35, wherein the at least some have a constant slope above the uppermost conductor layer.

37. The memory array of claim 36, wherein all of the opposing lateral outer longitudinal edges above the uppermost conductor layer each have a constant slope.

38. The memory array of claim 35, wherein the at least some do not have a constant slope above the uppermost conductor layer.

39. The memory array of claim 38, wherein the at least some are curved.

40. The memory array of claim 35, wherein each of the opposing laterally outer longitudinal edges on each side has a respective lowest position, wherein steepness varies to a different and constant steepness below the lowest position, the lowest positions on each side being at the same height relative to each other.

41. The memory array of claim 35, wherein each of the opposing laterally outer longitudinal edges on each side has a respective lowest position, wherein steepness changes to a different and constant steepness below the lowest position, the lowest positions on each side being at different heights relative to each other.

42. The memory array of claim 35, comprising forming under-array CMOS circuitry.

Technical Field

Embodiments disclosed herein relate to memory arrays and methods for forming memory arrays and conductive array vias (TAVs).

Background

Memory is one type of integrated circuit system and is used in computer systems to store data. The memory may be fabricated as one or more arrays of individual memory cells. The digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines) may be used to write to or read from the memory cells. Sense lines can conductively interconnect memory cells along columns of the array, and access lines can conductively interconnect memory cells along rows of the array. Each memory cell is uniquely addressable by a combination of a sense line and an access line.

The memory cells may be volatile, semi-volatile, or nonvolatile. Non-volatile memory cells can store data for long periods of time without power. Non-volatile memory is typically designated as memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of a few milliseconds or less. Regardless, the memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the state is considered to be either "0" or "1". In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

A field effect transistor is one type of electronic component that may be used in a memory cell. These transistors include a pair of conductive source/drain regions with a semiconductive channel region therebetween. A conductive gate is adjacent to and separated from the channel region by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. The field effect transistor may also include additional structures, such as a reversibly programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate.

Flash memory is one type of memory and is used in large numbers in modern computers and devices. For example, modern personal computers may store the BIOS on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in solid state drives instead of conventional hard disk drives. As yet another example, flash memory is popular in wireless electronic devices because flash memory enables manufacturers to support new communication protocols as they become standardized and enables manufacturers to provide the ability to remotely upgrade devices for enhanced features.

NAND can be the basic architecture for integrated flash memory. A NAND cell unit includes at least one select device coupled in series to a series combination of memory cells (the series combination is commonly referred to as a NAND string). The NAND architecture can be configured in a three-dimensional arrangement that includes vertically stacked memory cells that individually include reversibly programmable vertical transistors. Control circuitry or other circuitry may be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells that individually include transistors.

Drawings

FIG. 1 is a diagrammatic, cross-sectional view of a portion of a substrate in process in accordance with an embodiment of the invention and is taken through line 1-1 in FIG. 2.

Fig. 2 is a diagrammatic cross-sectional view taken through line 2-2 in fig. 1.

Fig. 3 through 33 are diagrammatic sequential cross-sectional and/or enlarged views of the construction of fig. 1 in process according to some embodiments of the invention.

20A, 20B, 20C, 33A, 33B, 33C, and 34 through 42 are diagrammatic cross-sectional views of a portion of a substrate in process in accordance with an embodiment of the invention.

Detailed Description

Embodiments of the invention encompass methods for forming memory arrays and conductive array vias (TAVs), such as NAND arrays or arrays of other memory cells with array-down peripheral control circuitry, such as array-down CMOS. Embodiments of the present invention encompass so-called "gate last" or "replacement gate" processes, so-called "gate first" processes, and other processes, whether now existing or developed in the future, that are independent of when the transistor gates are formed. Embodiments of the present invention also encompass memory arrays (e.g., NAND architectures) that are independent of the method of fabrication. A first example method embodiment is described with reference to fig. 1-33, which may be considered a "gate last" or "replacement gate" process.

Fig. 1 and 2 show a construction 10 having an array or array region 12 in which vertically extending strings of transistors and/or memory cells are to be formed. Construction 10 includes a base substrate 11 having any one or more of conductive/conductor/conductive, semi-conductive/semiconductor/semi-conductive or insulating (insulating)/insulator/insulating (i.e., electrically insulating herein) materials. Various materials have been formed vertically above the base substrate 11. The material may be alongside, vertically inward of, or vertically outward of the material depicted in fig. 1 and 2. For example, other partially or fully fabricated components of the integrated circuit system may be disposed over, around, or somewhere within the base substrate 11. Control circuitry and/or other peripheral circuitry for operating components within a vertically-extending array of strings of memory cells (e.g., array 12) may also be fabricated, and may or may not be entirely or partially within the array or sub-array. Furthermore, multiple sub-arrays may also be fabricated and operated independently, sequentially, or otherwise with respect to each other. Herein, a "sub-array" may also be considered an array.

The example construction 10 includes a conductive layer 16 that has been formed over a substrate 11. Example conductive layer 16 is shown to include a metallic material 19 (e.g., WSi) _x) An overlying conductive material 17 (e.g., conductively doped semiconductive material such as conductively doped polysilicon). Etch stop region 21 may be within conductive material 17. Region 21 may be conductive, insulating or semiconductive, for example, elemental tungsten, and may be sacrificial. Conductive layer 16 may comprise part of control circuitry (e.g., peripheral array lower circuitry and/or common source line or plate) for controlling read and write access to transistors and/or memory cells to be formed within array 12.

A stack 18 has been formed over the conductive layer 16. In some embodiments, the stack 18 includes an uppermost insulating layer 13, an uppermost conductor layer 15 below the uppermost insulating layer 13, and alternating insulating layers 20 and word line layers 22 below the uppermost conductor layer 15. An example thickness for each of such layers is 25 to 60 nanometers. Only a small number of layers 20 and 22 are shown, with the stack 18 more likely including tens, a hundred, or more, etc. of layers 20 and 22. Other circuitry, which may or may not be part of the peripheral and/or control circuitry, may be located between conductive layer 16 and stack 18. For example, multiple vertically alternating layers of conductive material and insulative material of such circuitry may be located below a lowermost portion of word line layer 22 and/or above an uppermost portion of word line layer 22. For example, one or more select gate layers (not shown) may be located between conductive layer 16 and lowermost word line layer 22, and one or more select gate layers may be located above the uppermost portion of word line layer 22. In any event, the uppermost conductor layer 15 may or may not be a word line layer. Regardless, the word line layer 22 and the uppermost conductor layer 15 may not include conductive material when processed in conjunction with the example method embodiments initially described herein, which are "back gates" or "replacement gates. Further, the insulating layer 20 and the uppermost insulating layer 13 may not include an insulating material or be insulating at the time of processing. The example word line layer 22 and the uppermost conductor layer 15 include a first material 26 (e.g., silicon nitride) that may be fully or partially sacrificial. The example insulating layer 20 and the uppermost insulating layer 13 include a second material 24 (e.g., silicon dioxide) that is different in composition from the first material 26 and may be fully or partially sacrificial.

Referring to fig. 3 and 4, and in one embodiment, channel opening 25 has been etched through insulating layer 20 and word line layer 22 (and layers 13 and 15) to material 17 of conductive layer 16. Channel opening 25 may partially enter material 17 as shown, may stop on top of material 17 (not shown), or completely through material 17 (not shown), or stop on material 19 or at least partially enter material 19. Alternatively, the trench opening 25 may stop on top of or inside the lowermost insulating layer 20, as an example. The reason for extending channel opening 25 at least to material 17 is to ensure that subsequently formed channel material (not shown) is directly electrically coupled with conductive layer 16 when such connection is desired, without the use of alternative processes and structures to accomplish this. An etch stop material (not shown) may be within conductive material 17 to facilitate stopping the etching of channel opening 25 atop conductive layer 16 when desired. Such etch-resistant materials may be sacrificial or non-sacrificial. By way of example only and for the sake of brevity, the channel openings 25 are shown arranged in groups or columns of staggered rows of four openings 25 per row. Any alternative existing or future developed arrangements and configurations may be used.

Transistor channel material may be formed vertically along the insulating and word line layers in individual channel openings, thus comprising individual strings of channel material that are directly electrically coupled with conductive material in the conductive layers. The individual memory cells of the example memory array formed may include a gate region (e.g., a control gate region) and a memory structure laterally between the gate region and the channel material. In one such embodiment, a memory structure is formed that includes a charge blocking region, a storage material (e.g., a charge storage material), an insulating charge transport material. The storage material (e.g., floating gate material, such as doped or undoped silicon, or charge trapping material, such as silicon nitride, metal dots, etc.) of individual memory cells is vertically along individual ones of the charge blocking regions. An insulating charge transport material (e.g., a band gap engineered structure having a nitrogen-containing material [ e.g., silicon nitride ] sandwiched between two insulator oxides [ e.g., silicon dioxide ]) is located laterally between the channel material and the memory material.

Fig. 5 and 6 show one embodiment in which charge blocking material 30, storage material 32, and charge transport material 34 have been formed vertically along insulating layer 20 and word line layer 22 in individual channel openings 25. Transistor materials 30, 32, and 34 (e.g., memory cell materials) may be formed by, for example, depositing respective thin layers thereof over stack 18 and within individual channel openings 25, followed by planarizing such transistor materials back to at least the uppermost surface of stack 18. Channel material 36 has been formed in channel opening 25 vertically along insulating layer 20 and word line layer 22, thereby including individual strings of channel material 53. Example channel material 36 includes appropriately doped crystalline semiconductor material such as one or more of silicon, germanium, and so-called group III/group V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). An example thickness for each of materials 30, 32, 34, and 36 is 25 to 100 angstroms. A punch etch may be performed as shown to remove materials 30, 32, and 34 from the base of the channel opening 25 to expose the conductive layer 16 such that the channel material 36 is directly against the conductive material 17 of the conductive layer 16. Alternatively and by way of example only, no punch etch may be performed, and channel material 36 may be directly electrically coupled to material 17/19 through separate conductive interconnects (not shown). The channel opening 25 is shown as including a radially central solid dielectric material 38 (e.g., spin-on dielectric, silicon dioxide, and/or silicon nitride). Alternatively, and by way of example only, the radially central portion within the channel opening 25 may include void space (not shown) and/or be free of solid material (not shown).

Referring to fig. 7-9, a mask 23 comprising a masking material 27 (e.g., photoresist) has been formed over the stack 18. The mask 23 includes a horizontally elongated trench opening 28 and a operative array via (TAV) opening 31. In the context of this document, an "operative TAV opening" is an opening in which conductive material is or will be formed in the stack, and which is an operative conductive interconnect between electronic components at different heights in the finished construction of an integrated circuit system that has been or is being manufactured. The immediately adjacent horizontally elongated trench openings 28 in the mask 23 may comprise a longitudinal shape of the longitudinal profile of the individual word lines to be formed in the individual word line layer 22. An example operative TAV opening 31 is shown between trench openings 28 and thereby within the longitudinal profile of the individual word lines and at the end of the grouping of channel openings 25. Alternative placements of the operative TAV opening 31 may be used. For example, one or more operational TAV openings may be placed outside of the immediately adjacent trench openings 28 within a grouping of channel openings 25 and/or outside of any wordline profile.

Referring to fig. 10-12, mask 23 has been used (e.g., as an etch mask) while the unmasked portions of stack 18 are etched through trench openings 28 and operative TAV openings 31 in mask 23 to form horizontally elongated trench openings 40 in stack 18 and operative TAV openings 33 in stack 18. Ideally, at least the TAV opening 33 extends at least to the conductive layer 16. In one embodiment and as shown, the channel opening and the string of channel material are formed through the insulating layer and the word line layer prior to the etching illustrated by figures 10-12. Alternatively, such channel material openings and/or strings of channel material may be formed after such etching (not shown). In any event, the openings 40 and 33 may taper inwardly or outwardly, with slight inward tapering being illustrated. Alternatively, for example, all of the sidewalls of openings 40 and 33 may be vertical.

In some embodiments, sacrificial plugs are formed in and removed from the individual operative TAV openings 33 in the stack 18 and the individual trench openings 40 in the stack 18. An example such process is described below with reference to fig. 13-19.

Referring to fig. 13, mask 23 (not shown) has been removed. Sacrificial plugs 35 comprising material 37 have been formed in openings 33 and 40. Material 37 may be any of insulating, conducting, and/or semiconducting, with an example being Al₂O₃. Material 26 in layers 15 and 22 may be recessed laterally prior to forming plugs 35 (not shown). Regardless, and in one embodiment, and as shown, such sacrificial plugs are insufficient to fill openings 33 and 40, thereby leaving or including void spaces 39 in such openings beneath such plugs. Alternatively, and by way of example only, such sacrificial plugs may completely fill (not shown) the respective openings.

Referring to fig. 14, a sacrificial masking material 41 (e.g., carbon) has been formed atop the stack 18 and includes an opening 42 through which the sacrificial plug 35 in the operative TAV opening 33 is reached, while leaving the sacrificial plug 35 in the covered trench opening 40.

Referring to fig. 15, the exposed sacrificial plug 35 in the operative TAV opening 33 (not shown) has been removed, followed by removal of the sacrificial masking material 41 (not shown), leaving the sacrificial plug 35 in the trench opening 40.

Referring to fig. 16, an insulating liner 43 (e.g., silicon dioxide) has been formed within the operative TAV opening 33.

Referring to fig. 17, the insulating liner 43 is punch etched to expose the conductive material 17 of the conductive layer 16, followed by forming a conductive material 44 therein and planarizing it back to at least the vertically outermost surface of the uppermost insulating layer 13, forming operative TAVs 45 in the individual operative TAV openings 33 in the stack 18. In one embodiment and as shown, forming the conductive material 44 in the individual operative TAV openings 33 in the stack 18 occurs when at least all of the lower half of the individual trench openings 40 in the stack 18 are fully occluded, and in one embodiment as shown, when all of the individual trench openings 40 in the stack 18 are fully occluded.

Referring to fig. 18, an insulator material 51 (e.g., silicon dioxide) has been formed atop the stack 18 and, thus, comprises a portion of the uppermost insulating layer 13. Masking material 46 (e.g., carbon) has been formed thereover. This has been formed to have a mask opening 47 therein, which mask opening 47 has a corresponding profile of the trench opening 40 in the stack 18. The opening 47 may have the same lateral width as the trench opening 40 (not shown) or may be wider than the trench opening 40 (as shown). Regardless and typically, the opening 47 may be misaligned with at least one side (shown misaligned with the right side) relative to the underlying trench opening 40.

Referring to fig. 19 and 20, and in one embodiment, masking material 46 (not shown) has been used as a mask while insulator material 51 is etched through openings 47 (not shown), and in one embodiment into the uppermost insulating layer 13, and masking material 46 (not shown) has subsequently been removed from trench openings 40 with sacrificial plugs 35 (not shown). In one example, the etching may proceed completely through the uppermost insulating layer 13 to the material 26 of the uppermost conductor layer 15.

20A, 20B, and 20C show alternative example constructions 10A, 10B, 10C, respectively. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffixes "a", "b", "c", respectively. Construction 10A in fig. 20A is similar to that in fig. 20, except for the unlikely perfect left and right mask alignment to show masking material openings 47 (not shown) relative to trench openings 40. Fig. 20B shows a construction 10B with the same right side mask misalignment as shown in fig. 18, but with the subsequent etching occurring only partially in the uppermost insulating layer 13. Fig. 20C shows another alternative example construction 10C similar to that of fig. 20A, in which perfect left and right side mask alignment of masking material openings 47 (not shown) has occurred, and in which, similar to that shown in fig. 20B, only a subsequent partial etch is performed in the uppermost insulating layer 13.

Referring to fig. 21 and 22, this is done, for example, by selectively etching (e.g., using liquid or vapor H) relative to materials 24, 30, 32, 34, 36, and 38₃PO₄As the primary etchant, where material 26 is silicon nitride and material 24 is silicon dioxide), material 26 (not shown) of word line layer 22 and the uppermost conductor layer 15 has been removed. This has formed word line layer voids 90 and uppermost conductor layer voids 92.

Referring to fig. 23-25, conductive material 48 has been formed through trenches 40 into the word line layer voids in word line layer 22 and into the uppermost conductor layer voids in the uppermost conductor layer 15. A thin insulating material liner (e.g., Al) may be formed prior to forming conductive material 48₂O₃And HfO_xAnd not shown). In any event, any suitable conductive material 48 may be used, such as one or both of a metallic material and a conductively doped semiconductive material. In but one example embodiment, conductive material 48 comprises a first deposition of a conformal titanium nitride liner (not shown), followed by a deposition of another component metallic material (e.g., elemental tungsten).

Referring to fig. 26-29, conductive material 48 has been removed from the individual trenches 40. This has resulted in the formation of vertically extending strings 49 of word lines 29 and individual transistors and/or memory cells 56. The approximate locations of transistors and/or memory cells 56 are indicated in parenthesis in fig. 29, and some are indicated in dashed outline in fig. 26 and 28, where transistors and/or memory cells 56 are substantially ring-shaped or ring-shaped in the depicted example. Conductive material 48 may be laterally recessed relative to sidewalls of material 24 within trench openings 40 (not shown). Conductive material 48 can be considered to have ends 50 corresponding to control gate regions 52 of individual transistors and/or memory cells 56 (fig. 29). In the depicted embodiment, the control gate regions 52 comprise individual portions of individual word lines 29. Materials 30, 32, and 34 may be considered memory structure 65 located laterally between control gate region 52 and channel material 36.

A charge blocking region, such as charge blocking material 30, is between the storage material 32 and the respective control gate region 52. The charge barrier may have the following functions in the memory cell: in a program mode, the charge blocking member may prevent charge carriers from passing from the storage material (e.g., floating gate material, charge trapping material, etc.) to the control gate, and in an erase mode, the charge blocking member may prevent charge carriers from flowing from the control gate into the storage material. Thus, the charge barriers may be used to block charge migration between the control gate region and the storage material of the individual memory cell. The example charge blocking region as shown includes an insulator material 30. By way of further example, the charge blocking region may comprise a laterally (e.g., radially) outer portion of a memory material (e.g., material 32), wherein such memory material is insulative (e.g., in the absence of any different composition material between the insulative memory material 32 and the conductive material 48). Regardless, as an additional example, the interface of the storage material and the conductive material of the control gate may be sufficient to act as a charge blocking region in the absence of any separate constituent insulator material 30. Furthermore, the interface of conductive material 48 and material 30 (if present) in combination with insulator material 30 may together act as a charge blocking region and, alternatively or additionally, may act as a laterally outer region of an insulating memory material, such as silicon nitride material 32. Example material 30 is one or more of hafnium silicon oxide and silicon dioxide.

Referring to fig. 30-33, material 57 (dielectric and/or silicon-containing, such as undoped polysilicon) has been formed in the respective trenches 40, thus forming word line intervening structures 55 (structures immediately between word lines) in the respective trench openings 40 in the stack 18.

Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used with respect to the embodiments described above.

The above process is but one example, and wherein the conductive material 44 in the individual operative TAV openings 33 in the stack 18 is formed prior to forming the word line intervening structures 55 in the stack 18. Alternatively, this may be reversed (not shown). The above process is also only an example, wherein the sacrificial plugs 35 are formed in the respective operative TAV openings 33 and in the respective trench openings 40 at the same time, and are still removed at time periods of different time intervals. Such depicted processing is also just one example embodiment of removing the sacrificial plug 35 from the individual operative TAV openings 33 prior to removing the sacrificial plug 35 in the individual trench openings 40, wherein the formation of the conductive material 44 in the individual operative TAV openings 33 occurs prior to removing the sacrificial plug 55 in the trench openings 40. Alternatively, this may be reversed (not shown). Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

In one embodiment, a mask (e.g., 23) including horizontally elongated trench openings (e.g., 28) and operative TAV openings (e.g., 31) may be formed to include dummy TAV openings. In the context of this document, a "dummy TAV opening" is an opening in which a dummy TAV is or will be formed in the stack, where a "dummy TAV" is a TAV in which no current flows all the way through it in the finished circuit construction, and which may be a circuit inoperable blind end that is not part of the current flow path of the circuit even if extending to or from an electronic component. As an example, one or more of the TAV openings 31 depicted in fig. 7 and 8 may be dummy TAV openings. Alternatively, the dummy TAV openings may be formed elsewhere among the operative TAV openings and/or laterally outside of any word line. Regardless, in such embodiments, such etching of the unmasked portion of stack 18 would also then proceed through the dummy TAV opening, forming a dummy TAV opening in stack 18. Some time thereafter, dummy material is formed in individual ones of the dummy TAV openings in the stack. In this document, a "dummy material" is a material through which no current flows all the way in the finished circuitry construction, regardless of whether the dummy material is conductive, semiconductive, and/or insulative. In one embodiment, such dummy material may comprise conductive material 44, which conductive material 44 is formed in individual dummy TAV openings at the same time that conductive material 44 is formed in the operative TAV openings in the stack. Alternatively, and as an example, the dummy material may not include such conductive material 44, with the formation of the conductive material 44 in the operative TAV opening 33 and the formation of the dummy material in individual dummy TAV openings in the stack occurring at time periods of different time intervals. Either may be formed before the other, and in one embodiment, conductive material 44 is formed in the individual operative TAV openings in stack 18 before the dummy material is formed in the individual dummy TAV openings in the stack.

In one embodiment, memory array 12 is formed to include under-array CMOS circuitry.

Some embodiments of the invention include forming a step on top of or over an uppermost portion of alternating insulating layers on at least one side of individual ones of the word lines and insulating layers in the word line layer, with a word line intervening structure on top of such step. See, e.g., fig. 31-33 processed according to the example embodiments described above. This shows that a step 59 (designated only in fig. 33 due to space constraints in fig. 31 and 32) is formed atop the uppermost insulating layer 20 in the stack 18, wherein the step 59 comprises the insulating material 24 of such uppermost insulating layer 20. The step 59 may be recessed vertically into such insulation (not shown), or may comprise an uppermost surface of such insulation as shown. Regardless, the word line intervening structure 55 is atop the step 59.

Fig. 33A, 33B and 33C show structures that may result from processing alternative constructions 10A, 10B and 10C as shown in fig. 20A, 20B and 20C, respectively, and have one or more corresponding steps 59, respectively. Thus, in some embodiments, the step 59 is over the uppermost insulating layer 20, and in some such embodiments over the uppermost conductor layer 15. In some such embodiments, the step is within the insulating material of the uppermost insulating layer 13. In one embodiment, the staircase is located on only one side of the individual word line 29 and in another embodiment on both sides of the individual word line 29. In some embodiments, the step is horizontal. Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

In some embodiments, the step is atop the uppermost conductor layer (not shown) and comprises conductive material of the conductor layer (not shown), such as may occur in a gate-first process in which the sacrificial material 26 is not first deposited. In such example embodiments, the step may comprise, or may be recessed vertically into, an uppermost surface of the conductive material of the conductor layer. Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

Some embodiments of the invention include forming the wordline intervening structures to include opposing laterally outer longitudinal edges, at least some of each of the opposing laterally outer longitudinal edges above the uppermost conductor layer having a lesser overall steepness than opposing laterally outer longitudinal edges below the uppermost conductor layer. A first example of such an embodiment is described with respect to configuration 10d with reference to fig. 34 and 35. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix "d" or with different numerals.

Referring to fig. 34, this shows the structure in the same processing order as the processing sequence shown by fig. 20 in the first described embodiment. The tapered/sloped sidewalls of the materials 51 and 24 of the uppermost insulating layer 13 have been formed with less overall steepness than beneath the uppermost conductor layer 15. This may be due to the use of a wider mask opening 47 (in fig. 18), right side misalignment, and as an article of manufacture that is etched to form the opening 40. Alternatively, this may result from varying the etch power and/or etch chemistry to introduce a degree of isotropy into the action of the etch, regardless of whether a wider mask opening is used than shown in fig. 18.

Fig. 35 shows subsequent processing by and in accordance with the example that has occurred as shown by fig. 33 in the first described embodiment, with a word line intervening structure 55d also being formed. This includes opposing laterally outer longitudinal edges 70. The overall steepness of at least some of each of the opposing laterally outer longitudinal edges 70 above the uppermost conductor layer 15 is less than the opposing laterally outer longitudinal edges 70 below the uppermost conductor layer 15. Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

In one embodiment and as shown, at least some (e.g., all as shown) of each of the opposing lateral outer longitudinal edges 70 above the uppermost conductor layer 15 has a constant slope (rising with operation) above the uppermost conductor layer 15. Alternatively, for example, at least some of each of the opposing lateral outer longitudinal edges 70 above the uppermost conductor layer 15 may not have a constant slope, e.g., as shown in fig. 42 with respect to alternative embodiment construction 10 h. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix "h". This shows an example in which each of the opposing lateral outer longitudinal edges 70 above the uppermost conductor layer 15 is convexly curved relative to the opening 40. Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

Fig. 35 also shows an example embodiment in which each of the opposing laterally outer longitudinal edges 70 on each side has a respective lowest position 75, with the steepness varying to a different and constant steepness below the lowest position 75, with the lowest positions 75 on each side being at different heights relative to each other (e.g., left position 75 being higher than right position 75). This may be caused by mask misalignment to the left or right of the mask opening 47 in the masking material 46 as illustrated in fig. 18. Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

Fig. 36 and 37 show an alternative example construction 10 e. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix "e". Fig. 36 and 37 show perfect left and right side mask alignment, whereby, for example, the lowest locations 75e on each side of the word line intervening structure 55e are at the same height relative to each other. Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

Fig. 38, 39 and 40, 41 show similar alternative embodiment constructions 10f and 10g, respectively. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffixes "f" and "g", respectively. Fig. 38 and 39 show example embodiments in which a slight mask misalignment to the right occurs and the lowest locations 75f of the structures 55f are within the uppermost insulating layer 13 and at different heights relative to each other. Fig. 40 and 41 show an alternative example embodiment in which perfect mask alignment has occurred, with the lowest locations 75g of structures 55g being within the uppermost insulating layer 13 and at the same height relative to each other. Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

Embodiments of the present invention encompass memory arrays regardless of method of manufacture. Nonetheless, such memory arrays may have any of the attributes as described herein in method embodiments. Similarly, the method embodiments described above may incorporate and form any of the attributes described with respect to the device embodiments. The memory array embodiments may be produced from an article of manufacture and, in any event, may or may not have changes (e.g., improvements) in operation as compared to predecessor constructions not in accordance with the present disclosure.

Embodiments of the invention include a memory array (e.g., 12) comprising a vertical stack (e.g., 18) comprising an uppermost insulating layer (e.g., 13), an uppermost conductor layer (e.g., 15) below the insulating layer, and alternating insulating layers (e.g., 20) and word line layers (e.g., 22) below the uppermost conductor layer. The word line layer includes the gate regions (e.g., 52) of the individual memory cells (e.g., 56). The gate regions individually include portions of word lines (e.g., 29) in individual ones of the word line layers. A string of channel material (e.g., 53) extends vertically through the insulating layer and the word line layer. The individual memory cells include a memory structure (e.g., 65) laterally between an individual one of the gate regions and a channel material (e.g., 36) of the string of channel material. Word line intervening structures (e.g., 55a, 55b, 55c) extend through the stack between immediately adjacent word lines. A step (e.g., 59) is on top of or over an uppermost portion of the insulating layer on at least one side of the individual word line. A word line intervening structure is atop the step. Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

In some embodiments, a memory array (e.g., 12) includes a vertical stack (e.g., 18) including an uppermost insulating layer (e.g., 13), an uppermost conductor layer (e.g., 15) below the insulating layer, and alternating insulating layers (e.g., 20) and word line layers (e.g., 22) below the uppermost conductor layer. The word line layer includes the gate regions (e.g., 52) of the individual memory cells (e.g., 56). The gate regions individually include portions of word lines (e.g., 29) in individual ones of the word line layers. A string of channel material (e.g., 53) extends vertically through the insulating layer and the word line layer. The individual memory cells include a memory structure (e.g., 65) laterally between an individual one of the gate regions and a channel material (e.g., 36) of the string of channel material. Word line intervening structures (e.g., 55d, 55e, 55f, 55g, 55h) extend through the stack between immediately adjacent word lines. The wordline intervening structure includes opposing laterally outer longitudinal edges (e.g., 70). At least some of each of the opposing laterally outer longitudinal edges above the uppermost conductor layer have a less overall steepness than the opposing laterally outer longitudinal edges below the uppermost conductor layer. Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

The above-described processes or configurations may be viewed as being relative to an array of components formed into or within a single stack or stack of such components over or as part of an underlying base substrate (although a single stack/stack may have multiple layers). Control and/or other peripheral circuitry for operating or accessing such components within the array may also be formed anywhere as part of the finished construction, and in some embodiments may be underneath the array (e.g., CMOS under the array). Regardless, one or more additional such stacks/stacks may be provided or fabricated above and/or below the stacks/stacks shown in the figures or described above. Further, the arrays of components may be the same or different relative to each other in different stacks/stackups. Intervening structures may be disposed between vertically adjacent stacks (e.g., additional circuitry and/or dielectric layers). Further, different stacks may be electrically coupled with respect to each other. Multiple stacks/stacks may be manufactured separately and sequentially (e.g., one on top of the other), or two or more stacks/stacks may be manufactured substantially simultaneously.

The assemblies and structures discussed above may be used in integrated circuits/circuitry and may be incorporated in electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic system may be any of a wide range of systems: such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular telephones, personal computers, automobiles, industrial control systems, aircraft, and so forth.

In this document, unless otherwise indicated, "vertical," "higher," "upper," "lower," "top," "bottom," "above," "below," "under …," "under …," "up," and "down" generally refer to a vertical direction. "horizontal" refers to a general direction along the main substrate surface (i.e., within 10 degrees) and may be relative to the substrate being processed during fabrication, and vertical is a direction generally orthogonal thereto. Reference to "exactly horizontal" refers to a direction along the main substrate surface (i.e., not forming degrees with the surface) and to which the processing substrate may refer during fabrication. Further, "vertical" and "horizontal" as used herein are generally vertical directions relative to each other and are independent of the orientation of the substrate in three-dimensional space. In addition, "vertically extending" and "vertically extending" refer to directions inclined at least 45 ° from exactly horizontal. Furthermore, with respect to the orientation of the field effect transistor "vertically extending", "horizontally extending" and so on, which is referred to as the channel length of the transistor, current flows between the source/drain regions in operation. For a bipolar junction transistor, "vertically extending," "horizontally extending," and so forth are orientations with reference to the length of the substrate along which, in operation, current flows between the emitter and collector. In some embodiments, any component, feature, and/or region that extends vertically or within 10 ° of vertical.

Further, "directly above," "directly below," and "directly under" require at least some lateral overlap (i.e., horizontally) of the two recited regions/materials/components with respect to each other. Also, the use of "over" without "right before merely requires that some portion of the stated region/material/component above another stated region/material/component be vertically outside of the other stated region/material/component (i.e., independent of whether there is any lateral overlap of the two stated regions/material/components). Similarly, the use of "under" and "under" without "positive" above merely requires that some portion of the stated region/material/component under/under another stated region/material/component be vertically inboard of the other stated region/material/component (i.e., independent of whether there is any lateral overlap of the two stated regions/material/components).

Any of the materials, regions, and structures described herein may be uniform or non-uniform, and may be continuous or discontinuous over any material it overlies in any way. When one or more example ingredients are provided for any material, the material can comprise, consist essentially of, or consist of such one or more ingredients. Additionally, unless otherwise stated, each material may be formed using any suitable existing or future-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

Additionally, "thickness" (the preceding non-directional adjectives), used alone, is defined as the average straight-line distance perpendicularly through a given material or region from the nearest surface of the immediately adjacent material or region having a different composition. In addition, the various materials or regions described herein can have a substantially constant thickness or have a variable thickness. If having a variable thickness, the thickness refers to an average thickness unless otherwise indicated, and such materials or regions will have some minimum thickness and some maximum thickness due to the variable thickness. As used herein, "different compositions" only requires that those portions of two recited materials or regions that may be directly against each other be chemically and/or physically different, such as where the materials or regions are non-uniform. If two recited materials or regions are not directly against each other, then "different compositions" merely requires that those portions of the two recited materials or regions that are closest to each other be chemically and/or physically different where such materials or regions are not homogeneous. In this document, a material, region or structure is "directly against" another material, region or structure when the stated materials, regions or structures are in at least some physical contact with respect to each other. In contrast, the absence of "positive" above … …, "on … …," "adjacent," "along," and "against" preceding encompasses "directly against," as well as configurations in which intervening materials, regions, or structures render the recited materials, regions, or structures physically untouchable relative to one another.

Herein, zone-material-components are "electrically coupled" with respect to each other if, in normal operation, an electrical current can flow continuously from one zone-material-component to another zone-material-component, and the flow is predominantly by movement of the subatomic positive and/or negative charge when it is sufficiently generated. Another electronic component may be between and electrically coupled to the zone-material-component. In contrast, when a region-material-component is referred to as "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-component.

The composition of any of the conductive/conductor/conductive materials herein can be a metallic material and/or a conductively doped semiconductive/semiconductive material. A "metallic material" is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

Herein, "selectivity" with respect to etching, removing, depositing, forming, and/or forming is such an effect that one stated material acts at a ratio of at least 2:1 by volume relative to another stated material. Further, selectively depositing, selectively growing, or selectively forming is depositing, growing, or forming one material relative to another or more stated materials by a ratio of at least 2:1 by volume for at least a first 75 angstroms.

The use of "or" herein encompasses either and both unless otherwise indicated.

Conclusion

In some embodiments, a method for forming a memory array and a conductive array via (TAV) includes forming a stack including vertically alternating layers of insulating layers and word lines. A mask including a horizontally elongated trench opening and an operative TAV opening is formed over the stack. The unmasked portion of the stack is etched through the trench opening in the mask and the operative TAV opening to form a horizontally elongated trench opening in the stack and an operative TAV opening in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual ones of the operative TAV openings in the stack. Word line intervening structures are formed in individual ones of the trench openings in the stack.

In some embodiments, a method for forming a memory array and a conductive array via (TAV) includes forming a stack including an uppermost conductor layer and vertically alternating layers of insulation and word lines. The uppermost conductor layer and the word line layer include a first material, and the insulating layer includes a second material having a different composition from the first material. A string of channel material is formed through the insulating layer and the word line layer. A mask including a horizontally elongated trench opening and an operative TAV opening is formed over the stack. The unmasked portion of the stack is etched through the trench opening in the mask and the operative TAV opening to form a horizontally elongated trench opening in the stack and an operative TAV opening in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual ones of the operative TAV openings in the stack. The first material is removed after forming the conductive material in the operative TAV opening in the stack to form a wordline void and an uppermost conductor layer void. Conductive material is formed in the word line layer voids to include the individual word lines and in the uppermost conductor layer voids. After forming the conductive material, word line intervening structures are formed in individual ones of the trench openings in the stack.

In some embodiments, a memory array includes a vertical stack including an uppermost insulating layer, an uppermost conductor layer below the insulating layer, and alternating insulating layers and word line layers below the uppermost conductor layer. The word line layers include gate regions of the individual memory cells, and the gate regions individually include portions of the word lines in individual ones of the word line layers. The string of channel material extends vertically through the insulating layer and the word line layer. The individual memory cells include a memory structure laterally between an individual one of the gate regions and the channel material of the string of channel material. The word line intervening structures extend through the stack between immediately adjacent word lines. The staircase is on top of or above the uppermost portion of the alternating insulating layers on at least one side of individual ones of the word lines and the insulating layers of the word line layer. The word line intervening structures are on top of the steps.

In some embodiments, a memory array includes a vertical stack including an uppermost insulating layer, an uppermost conductor layer below the insulating layer, and alternating insulating layers and word line layers below the uppermost conductor layer. The word line layers include gate regions of the individual memory cells, and the gate regions individually include portions of the word lines in individual ones of the word line layers. The string of channel material extends vertically through the insulating layer and the word line layer. The individual memory cells include a memory structure laterally between an individual one of the gate regions and the channel material of the string of channel material. The word line intervening structures extend through the stack between immediately adjacent word lines. The wordline intervening structure includes opposing laterally outer longitudinal edges, and at least some of each of the opposing laterally outer longitudinal edges is above an uppermost conductor layer and has an overall steepness that is less than opposing laterally outer longitudinal edges below the uppermost conductor layer.