阅读说明：本技术 静态存储器及其显示驱动方法 (Static memory and display driving method thereof ) 是由 金宗洙 吴水兵 于 2021-08-17 设计创作，主要内容包括：本申请公开一种静态存储器及其显示驱动方法。该静态存储器包括静态存储阵列、锁存器、多路复用器和输出电路,锁存器与存储单元的位线连接,并锁存静态图像中第一帧画面的数据,以及维持于读取第一帧画面的数据时的电平状态；多路复用器与锁存器连接,并选定存储该第一帧画面的数据的存储单元；输出电路与多路复用器连接,按照时序输出第一帧画面的数据作为剩余各帧画面的数据。本申请在读取除第一帧画面之外的数据时,无需位线再次预充电,能够降低功耗。(The application discloses a static memory and a display driving method thereof. The static memory comprises a static memory array, a latch, a multiplexer and an output circuit, wherein the latch is connected with a bit line of a memory unit and latches data of a first frame of picture in a static image and maintains a level state when the data of the first frame of picture is read; the multiplexer is connected with the latch and selects a storage unit for storing the data of the first frame picture; the output circuit is connected with the multiplexer and outputs the data of the first frame picture as the data of the rest frames according to time sequence. When reading data except the first frame picture, the method and the device do not need to precharge the bit lines again, and can reduce power consumption.)

1. A static memory, comprising:

the static storage array comprises a plurality of storage units;

a latch connected to bit lines of the plurality of memory cells connected to the same word line, and latching data of a first frame in a still image, and maintaining an output terminal thereof in a level state when the data of the first frame is read, wherein the data of all frames of the still image are stored in the plurality of memory cells connected to the same word line;

a multiplexer connected to the latch and selecting a storage unit for storing data of a first frame of picture in the still image;

and the output circuit is connected with the multiplexer and outputs the data of the rest frame pictures in the static image according to time sequence, wherein the latched data of the first frame picture in the static image are all output.

2. The static memory of claim 1, further comprising a sense amplifier connected to two bit lines of each memory cell, wherein the sense amplifier is configured to amplify a differential input voltage of the two bit lines to an output voltage, and wherein the latch maintains the two bit lines in a level state at which the output voltage is output.

3. The static memory of claim 2, wherein the sense amplifier and the latch are integrated as a latching-type sense amplifier.

4. The static memory of claim 1, wherein bit lines of a plurality of memory cells connected to a same word line are connected to one of said latches.

5. The static memory of claim 1, wherein the number of latches is set according to a duration of latched data of the latches.

6. The static memory according to claim 1, wherein the data of any two frames in the static image are the same or the data variation is smaller than a preset threshold.

7. A display driving method, comprising:

selecting a storage unit for storing data of a first frame picture in a static image, wherein the data of all the frame pictures of the static image are stored in a plurality of storage units connected to the same word line;

applying an enabling signal to a word line of the static memory array, charging a bit line of a selected memory cell, and reading data of a first frame of picture in a static image;

the latch latches the data of a first frame of picture in the static image and maintains the output end of the latch at the level state when the data of the first frame of picture is read;

and outputting the data of the rest frames in the static image according to the time sequence, wherein the latched data of the first frame in the static image are all output.

8. The method of claim 7, wherein said latching data for a first frame in said still image comprises:

amplifying the differential input voltage of the two bit lines to an output voltage;

and latching the data of the first frame of picture in the static image, and maintaining the output end of the latch in a level state when the output voltage is output.

9. The method of claim 7, wherein the bit lines of the plurality of memory cells connected to the same word line are connected to a latch, and the data of the first frame in the still image is latched by the latch.

Technical Field

The application relates to the field of static storage, in particular to a static memory and a display driving method thereof.

Background

An SRAM (Static Random-Access Memory) is one of the indispensable important components in an electronic system. The SRAM is used for temporarily storing data or instructions, and has the advantages of high speed, low power consumption, easy embedded integration, and the like, and thus is a preferred device for caching in a Central Processing Unit (CPU).

In modern high-performance processors, the area of a chip occupied by the SRAM is becoming larger and larger, and in the coming years, with the explosive growth of mobile internet, internet of things and wearable electronic devices, the power consumption of the chip will be subject to strict requirements and severe challenges, and the SRAM is the first to rush. Therefore, how to reduce the power consumption of the SRAM is an urgent problem to be solved in the field of static storage.

In a display, a static memory Array (SRAM Cell Array)11 is built in a driver IC (also called a driver chip) and is mainly used for storing image data. Each row of the SRAM is provided with a Word Line (WL), and each column is provided with two Bit lines, which are a Bit Line (BL) and a Bit line not (BLB), and are collectively referred to as Bit line below. In reading data of each row of memory cells, referring to fig. 1 and 2, a word line WL receives an enable signal EN-WL to turn on each row of memory cells, a multiplexer (MUX Switch)12 selects a memory cell to which data is to be read each time, a Sense Amplifier (SA) receives the enable signal EN-SA, precharges a bit line BL of the selected memory cell to a high level V-BL, and then outputs data of the selected memory cell. For the memory cells connected to the same word line WL (i.e. in the same row), before reading the data of the selected memory cell each time, the word line WL receives the enable signal EN-WL, and correspondingly, the sense amplifier SA receives the enable signal EM-SA and precharges the bit line BL of the selected memory cell to the high level V-BL each time. The number of times of reading data by the driving IC is large, and the electric quantity consumed by multiple times of pre-charging is large, so that the power consumption of the SRAM is not reduced.

Disclosure of Invention

In view of the above, the present application provides a static memory and a display driving method thereof to solve the problem of large power consumption of the SRAM.

The application provides a static memory, including:

the static storage array comprises a plurality of storage units;

a latch connected to bit lines of the plurality of memory cells connected to the same word line, and latching data of a first frame in a still image, and maintaining an output terminal thereof in a level state when the data of the first frame is read, wherein the data of all frames of the still image are stored in the plurality of memory cells connected to the same word line;

a multiplexer connected to the latch and selecting a storage unit for storing data of a first frame of picture in the still image;

and the output circuit is connected with the multiplexer and outputs the data of the rest frame pictures in the static image according to time sequence, wherein the latched data of the first frame picture in the static image are all output.

Optionally, the static memory further comprises a sense amplifier connected to the two bit lines of each memory cell, the sense amplifier is configured to amplify a differential input voltage of the two bit lines to an output voltage, and the latch maintains the two bit lines in a level state when the output voltage is output.

Alternatively, the sense amplifier and the latch are integrated as a latch type sense amplifier.

Alternatively, bit lines of a plurality of memory cells connected to the same word line are connected to one latch.

Alternatively, the number of latches is set according to the duration of the latch data of the latches.

Optionally, the data of any two frames of pictures in the still image are the same, or the data variation is smaller than a preset threshold.

The application provides a display driving method, which comprises the following steps:

selecting a storage unit for storing data of a first frame picture in a static image, wherein the data of all the frame pictures of the static image are stored in a plurality of storage units connected to the same word line;

applying an enabling signal to a word line of the static memory array, charging a bit line of a selected memory cell, and reading data of a first frame of picture in a static image;

the latch latches the data of a first frame of picture in the static image and maintains the output end of the latch at the level state when the data of the first frame of picture is read;

and outputting the data of the rest frames in the static image according to the time sequence, wherein the latched data of the first frame in the static image are all output.

Optionally, latching data of a first frame picture in the still image includes:

amplifying the differential input voltage of the two bit lines into an output voltage;

the latch latches data of a first frame of picture in a static image, and maintains an output end of the latch in a level state when the output voltage is output.

Alternatively, bit lines of a plurality of memory cells connected to the same word line are connected to one latch, and data of a first frame in the still image is latched by one latch.

As described above, in the static memory and the display driving method thereof according to the present invention, after reading data of a first frame in a static image, the latch latches the data of the first frame and maintains a level state at the time of reading the data (of the first frame), and when reading data of the remaining frames, the bit lines do not need to be precharged again, so that power consumption can be reduced.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application. To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of an SRAM structure of a conventional display;

FIG. 2 is a timing diagram of the image data in the SRAM read by the prior art display;

FIG. 3 is a schematic structural diagram of a static memory according to an embodiment of the present application;

FIG. 4 is an equivalent circuit schematic of the static memory shown in FIG. 3;

FIG. 5 is a timing diagram of the image data read from the SRAM according to the present application;

fig. 6 is a flowchart illustrating a display driving method according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application clearer, the following description of the present application will clearly and completely describe the technical solutions of the present application with reference to the specific embodiments and the accompanying drawings. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the application. Based on the following description, the various embodiments and their technical features may be combined with each other without conflict.

Considering that in the current process of reading image data of the SRAM, each time the driver IC reads data of one frame of picture, two bit lines connected to the memory cell need to be precharged (to a high level), the more the driver IC reads data, the more the number of precharging, the larger the consumed electric quantity, which is not beneficial to reducing the power consumption of the SRAM. In contrast, in the embodiment of the present application, after the data of the first frame in the still image is read, the data of the first frame is latched by the latch, and the output terminal of the latch is maintained in the level state when the data of the first frame is read.

Fig. 3 is a schematic structural diagram of a static memory according to an embodiment of the present application, and fig. 4 is a schematic equivalent circuit diagram of the static memory shown in fig. 3. Referring to fig. 3 and 4, the static memory 20 includes a static memory Array (SRAM Cell Array)21, a Latch (Latch)22, a multiplexer (MUX Switch)23, and an output circuit (Data output) 24.

The static memory array 21 may be an SRAM for storing data of each frame of an image, or related instructions of the display during the image display process. The static memory array 21 includes a plurality of memory cells 21a, the memory cells 21a may be arranged in an array, the memory cells 21a in each row are connected to a same word line WL, and any memory cell 21a in each column is connected to two bit lines, which are a bit line (bit line) BL and a bit line not (bit line) BLB. For convenience of description, the present application is hereinafter described as two bit lines BL.

For the memory cells 21a connected to the same word line WL, the latch 22 is connected to the two bit lines BL of each memory cell 21 a. As shown in FIG. 4, the two bit lines BL of each row of memory cells 21a are connected to the same latch 22.

The latch 22 has two main functions:

firstly, data of a first frame in a static image is latched. The latch 22 has a buffering function, and after the word line WL is turned on, the memory cell 21a outputs the stored data of the first frame through the two bit lines BL, and the latch 22 buffers the data.

Second, the output terminal of the latch 22 is maintained at the level state when the data of the first frame is read. The output terminal of the latch 22 does not change with the change of the level state of the input terminal, so that when the data of the first frame picture is read, the output terminal of the latch 22 maintains a certain level state, and when the data of the remaining frame pictures are output subsequently, the level state is maintained, and herein, all the bit lines BL connected to the output terminal of the latch 22 can maintain the level state without charging.

In one implementation, the static memory 20 may further include a Sense amplifier (Sense amplifier)25 connected to the two bit lines BL of each memory cell 21 a. The sense amplifier 25 is used to amplify the differential input voltage of the two bit lines BL into an output voltage, and when reading data of a first frame picture, for example, the output voltage of the two bit lines BL of a certain memory cell 21a is V1, and the output terminal of the latch 22 is maintained in the current level state.

Alternatively, the sense amplifier 25 and the latch 22 may be integrated as a latch type sense amplifier.

The multiplexer 23 is connected to the latch 22 for selecting a memory cell for storing data of the first frame picture in the still image. That is, the multiplexer 23 is used for selecting the storage unit 21a storing the first frame of picture data and communicating the reading channel of the storage unit 21 a. The multiplexer 23 functions as a switch to connect the memory cell 21a of the data to be read with the output circuit 24 to transmit the data to be read to the output circuit 24.

The output circuit 24 is connected to the multiplexer 23, and outputs data of the remaining frames in the still image in time series, wherein the latched data of the first frame in the still image are each output.

In a scene such as a single picture or a news reading, the picture change of the image is small, so that the change between the remaining frames and the first frame is very small, and the data of the first frame is taken as the data of the remaining frames and displayed according to the time sequence, so that the frame frequency of the static image can be reduced, for example, the driving IC refreshes the picture according to a frequency frame of 50Hz to 60Hz during normal display, while the embodiment of the present invention reduces the frequency frame from 50Hz to 60Hz to 10Hz, even within 10Hz, reduces the frequency of the driving IC refreshing the picture, and reduces the current consumption.

Referring to fig. 5, a word line driving unit (WL Driver)27 applies an enable signal EN-WL to a word line WL, the word line WL receives the enable signal EN-WL to control the memory cells 21a of a certain row to be turned on at a stage of reading data of a first frame of a still image, a sense amplifier 25 (or a latch type sense amplifier) receives an enable signal EN-SA to amplify a differential input voltage of two bit lines BL into an output voltage, two bit lines BL of one memory cell 21a of the row are precharged until reaching a high level V-BL, data of the first frame is output, and then a latch 22 (or a latch type sense amplifier) receives the enable signal EN-LA, latches the data of the first frame, and maintains a level state when the data of the first frame is read.

In a stage of reading data of the second frame in the still image, the latch 22 (or latch-type sense amplifier) receives the enable signal EN-LA, and the latch 22 outputs the latched data of the first frame as the data of the second frame to the output circuit 24, and the data is output from the output circuit 24 to the Control Block (Control Block)26 of the static memory 20, and is displayed under the Control of the Control Block 26. Similarly, at the stage of reading the data of each frame remaining in the still image, the latch 22 (or latch-type sense amplifier) receives the enable signal EN-LA and outputs the data of the first frame as the data of the corresponding frame.

As a result, after the data of the first frame in the still image is read, the latch 22 latches the data of the first frame and maintains the level state at the time of reading the data (of the first frame), and when the data of the remaining frames in the still image is read, the bit lines BL do not need to be precharged again, so that power consumption can be reduced.

The latch period of the latches 22 (period of latching data) is limited, and the number of the latches 22 may be set according to the latch period of a single latch 22, for example, for a scenario in which the same row of memory cells 21a is connected to one latch 22, the latch period of the latch 22 is longer than the period of reading data of all frames in a still image.

Referring to fig. 6, the display driving method may include the following steps S11 to S14.

S11: and selecting a storage unit for storing the data of the first frame in the static image, wherein the data of all the frames in the static image are stored in a plurality of storage units connected with the same word line.

S12: and applying an enabling signal to a word line of the static memory array, charging a bit line of the selected memory cell, and reading data of a first frame in the static image.

S13: the latch latches data of a first frame of picture in the still image, and maintains an output terminal of the latch in a level state when the data of the first frame of picture is read.

S14: and outputting the data of the rest frames in the static image according to the time sequence, wherein the latched data of the first frame in the static image are all output.

After reading the data of the first frame in the still image, the latch latches the data of the first frame and maintains the latch in a level state at the time of reading the data (of the first frame), and when reading the data of the remaining frames, the bit lines do not need to be precharged again, so that power consumption can be reduced.

In the display driving method, the main body of each step may be the corresponding component in the static memory 20, for example, the multiplexer 23 may select a memory cell for storing data of a first frame in a static image, the word line driving unit 27 may apply the enable signal EN-WL to the word line WL, and the latch 22 may output the latched data of the first frame as data of the remaining frames to the output circuit 24, and then the latched data of the first frame is output to the control module 26 of the static memory 20 by the output circuit 24 for final display.

The above description is only a part of the embodiments of the present application, and not intended to limit the scope of the present application, and all equivalent structural changes made by using the contents of the specification and the drawings are included in the scope of the present application.

Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element, and that elements, features, or elements having the same designation in different embodiments may or may not have the same meaning as that of the other elements, and that the particular meaning will be determined by its interpretation in the particular embodiment or by its context in further embodiments.

In addition, although the terms "first, second, third, etc. are used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well. The terms "or" and/or "are to be construed as inclusive or meaning any one or any combination. An exception to this definition will occur only when a combination of elements, functions, steps or operations are inherently mutually exclusive in some way.