阅读说明：本技术 电容器和半导体芯片 (Capacitor and semiconductor chip ) 是由 夏文彬 于 2019-04-15 设计创作，主要内容包括：一种电容器,被内置于半导体芯片中,包括两个极板,这两个极板分别分布于该半导体芯片中的两个金属层上。在这两个金属层之间还分布有多个金属层,每个金属层上分布有多个金属块。所述多个金属块包括多个第一金属块和多个第二金属块,所述多个第一金属块通过多个第一通孔耦合至一个极板,所述多个第二金属块通过多个第二通孔耦合至另一极板。每两个相邻的金属层被介质层所隔离。每个极板上可包括一个或多个槽隙。该电容器可以有效降低天线效应。(A capacitor is built in a semiconductor chip and comprises two polar plates which are respectively distributed on two metal layers in the semiconductor chip. A plurality of metal layers are distributed between the two metal layers, and a plurality of metal blocks are distributed on each metal layer. The plurality of metal blocks includes a plurality of first metal blocks coupled to one plate through a plurality of first vias and a plurality of second metal blocks coupled to another plate through a plurality of second vias. Every two adjacent metal layers are separated by a dielectric layer. Each plate may include one or more slots therein. The capacitor can effectively reduce the antenna effect.)

A capacitor, comprising:

a first electrode plate arranged at the first conductor layer;

a second electrode plate disposed at the second conductor layer; wherein the content of the first and second substances,

the first conductor layer and the second conductor layer are separated by at least one dielectric layer, and at least one of the first plate and the second plate comprises at least one slot.

The capacitor of claim 1, further comprising: a plurality of conductor tiles disposed on at least one third conductor layer between the first conductor layer and the second conductor layer, the first conductor layer, the second conductor layer, and the at least one third conductor layer being separated by the at least one dielectric layer; wherein the plurality of conductor blocks includes at least one first conductor block coupled to the first plate through at least one first via and at least one second conductor block coupled to the second plate through at least one second via.

The capacitor of claim 2, wherein each first conductor block in any third conductor layer is adjacent to one or more second conductor blocks in said any third conductor layer.

The capacitor of claim 3 wherein all of the plurality of adjacent blocks of each first conductor block are second conductor blocks.

The capacitor of claim 4 wherein all of said plurality of adjacent blocks are four second conductor blocks.

The capacitor of claim 5 wherein, in any of said third conductor layers, said four second conductor tiles are left-adjacent, right-adjacent, upper-adjacent and lower-adjacent tiles of each of said first conductor tiles.

The capacitor of any one of claims 2 to 6, wherein the at least one third conductor layer is a plurality of third conductor layers; any one of the first conductor blocks in any one of the third conductor layers is coupled to one of the first conductor blocks in another one of the third conductor layers through a first via, any one of the second conductor blocks in any one of the third conductor layers is coupled to one of the second conductor blocks in another one of the third conductor layers through a second via, and the another one of the third conductor layers is vertically adjacent to the any one of the third conductor layers.

The capacitor of any one of claims 2 to 7, wherein at least one of the first, second and at least one third conductor layers is a metal layer.

The capacitor of any one of claims 2 to 8, wherein projections of the first plate, the second plate, and the plurality of conductor blocks in a vertical direction overlap.

The capacitor of any one of claims 1 to 8, wherein projections of the first plate and the second plate in a vertical direction overlap.

The capacitor of any one of claims 1-10, wherein said at least one dielectric layer comprises an oxide.

The capacitor of any one of claims 1 to 11, wherein the capacitor comprises a metal-oxide-metal (MOM) capacitor.

The capacitor of any one of claims 1-12, wherein the first plate or the second plate is coupled to a power line or a ground line.

A semiconductor chip comprising the capacitor as claimed in any one of claims 1 to 13.