阅读说明：本技术 一种具有隔离结构的氮化镓集成电路 (Gallium nitride integrated circuit with isolation structure ) 是由 孙瑞泽 罗攀 刘超 陈万军 于 2021-09-03 设计创作，主要内容包括：本发明属于功率半导体技术,特别涉及一种具有隔离结构的氮化镓集成电路,相对于传统的凹槽隔离,本发明在凹槽隔离结构内填充有p型半导体材料,填充的p型半导体材料与缓冲层形成耗尽区,实现对氮化镓集成电路模块的电学隔离；同时通过改变凹槽结构和填充物的形状、大小以及填充材料的掺杂浓度,可以与缓冲层形成不同大小和形状的耗尽区域,达到理想的隔离效应。本发明的效应效果：通过对缓冲层的耗尽可以达到良好的隔离效果；制备简单,实用性强,不引入额外的电流源或电压源。(The invention belongs to the power semiconductor technology, in particular to a gallium nitride integrated circuit with an isolation structure, and compared with the traditional groove isolation, the invention fills p-type semiconductor material in the groove isolation structure, and the filled p-type semiconductor material and a buffer layer form a depletion region to realize the electrical isolation of a gallium nitride integrated circuit module; meanwhile, by changing the shape and size of the groove structure and the filler and the doping concentration of the filler, depletion regions with different sizes and shapes can be formed with the buffer layer, and an ideal isolation effect is achieved. The effect and effect of the invention are as follows: a good isolation effect can be achieved by depletion of the buffer layer; the preparation is simple, the practicability is strong, and no additional current source or voltage source is introduced.)

1. A gallium nitride integrated circuit with an isolation structure is formed by integrating a first device (09) and a second device (10) on the same substrate (01), wherein the first device (09) and the second device (10) have the same structure and respectively comprise the substrate (01), a buffer layer (02), a channel layer (03) and a barrier layer (04) which are sequentially arranged from bottom to top, and the channel layer (04) and the barrier layer (04) form a heterojunction structure; first metals (05) are arranged at two ends of the upper surface of the barrier layer (04), an insulating layer (07) is arranged on the upper surface of the barrier layer (04) between the first metals (05), and second metals (06) are arranged on the upper surface of the insulating layer (07); an isolation structure is arranged between the first device (09) and the second device (10), the isolation structure is formed by the groove (11) and the filling material (08) in the groove (11), and the isolation structure extends into the buffer layer (02) from the upper surface of the integrated circuit along the vertical direction.

2. The isolation structure of claim 1, wherein the recess is one of rectangular, trapezoidal and T-shaped.

3. An isolation structure applied to a GaN integrated circuit according to claim 1 or 2, wherein the filling material (08) is a p-type semiconductor material, and the semiconductor material is one of Polysilicon, NiO, ZnO and GaN.

Technical Field

The invention belongs to the technical field of semiconductor power integrated circuits, and particularly relates to a gallium nitride integrated circuit with an isolation structure.

Background

Gallium nitride (GaN) has a wide bandgap (3.4eV), a high thermal conductivity (2.0W/(cm. K)), and a high electron saturation velocity (2.7X 10) as a wide bandgap semiconductor material⁷cm/s), high critical breakdown field (-3.5 x 10)⁶V/cm), high electron mobility (2000 cm)²V.s), and a Heterojunction Field Effect Transistor (HFET) prepared by utilizing the spontaneous polarization effect of gallium nitride and the piezoelectric polarization effect of an AlGaN/GaN heterojunction structure can form a two-dimensional electron gas channel with high electron density (the density of the two-dimensional electron gas surface of the channel under the condition of non-artificial doping is as high as 10)¹³cm^-2Magnitude). By means of the excellent material characteristics of the gallium nitride, electronic power devices and circuits prepared on the basis of the GaN material have stronger high-temperature working and irradiation resistance than silicon and gallium arsenide devices, have extremely low conduction loss and high current density, and have wide application prospects in high-frequency, small-volume, high-power and other scenes such as radio frequency, consumer electronics, aerospace, rail transit and the like.

Although the GaN-based device has outstanding physical, chemical and electrical characteristics, the volume of elements such as capacitance and inductance in a circuit can be effectively reduced, the miniaturization of equipment is promoted, the cost of the product is further reduced, and the reliability of the product is improved. However, in the application of the high frequency domain, the influence of the parasitic parameters gradually becomes prominent, and most of the circuits of the GaN power devices are still driven by silicon-based circuits, which limits the great advantage of the GaN circuits in terms of frequency characteristics. Therefore, it is desired to fully develop the performance of GaN-based devices, and GaN-based monolithic integrated circuits are a necessary trend in the development of GaN power devices. Through the full GaN integration of all modules of driving, protection, power, logic and the like on a single GaN-on-Si chip, the parasitic capacitance in the circuit is effectively reduced, and the characteristics of high frequency, small volume, low cost and high integration degree of a GaN-based device are exerted.

The GaN monolithic integration can reduce circuit parasitic parameters and fully realize GaN high-frequency characteristics, but in the integration, a plurality of modules are integrated on the same wafer, crosstalk caused by leakage current between different modules is not negligible, and interference between a digital module and an analog module can cause false opening of devices and even damage of circuits; therefore, proper isolation measures are adopted, and the method is an important basis for ensuring the stable work of the GaN integrated circuit; at present, most of the commonly adopted materials are isolated by a table top, an isolation groove far larger than the depth of a channel is formed by etching a non-active area, and electrical isolation between different devices and circuits is realized. Another common isolation method is ion implantation isolation, in which a high resistance region is formed by implanting ions such as He ions, but the depth of ion implantation is limited; in addition, based on the isolation of the SOI principle, the device is semi-wrapped by growing an oxide layer on the substrate, but the problems of heat dissipation and stability exist; meanwhile, a reverse coupling electric field isolation mode exists for reducing current-voltage signal crosstalk between devices by forming a reverse coupling electric field between the devices, but an additional negative voltage source is required for forming the reverse coupling electric field.

Disclosure of Invention

The invention aims to solve the isolation problem of a single-chip GaN integrated circuit, and provides an isolation mode based on p-type semiconductor material filling.

The invention has the following characteristics:

1) and a depletion region is formed in the GaN buffer layer for isolation, so that the isolation effect is better.

2) Simple preparation, strong practicability, no introduction of extra current source or voltage source

3) Without drastically increasing the thermal resistance of the device or circuit

4) The surface is flat and does not influence the subsequent process

The invention provides an isolation structure, which is structurally shown in figure 1, a depletion region is formed between a p-type filling material and a buffer layer, the GaN integrated electrical isolation is effectively realized, meanwhile, the influence of current signals and voltage signals among devices, circuits and functional modules in a GaN integrated circuit is further inhibited through the depletion of a semi-insulating buffer layer, the leakage current of the circuit is reduced, and the device is prevented from being turned on mistakenly due to crosstalk. Meanwhile, the invention can adjust the shape and size of the groove and the filling so as to achieve better depletion effect on the buffer layer and optimize the isolation effect.

The technical scheme of the invention is as follows:

a gallium nitride integrated circuit with an isolation structure is formed by integrating a first device 09 and a second device 10 on the same substrate 01, wherein the first device 09 and the second device 10 have the same structure and respectively comprise the substrate 01, a buffer layer 02, a channel layer 03 and a barrier layer 04 which are sequentially arranged from bottom to top, and the channel layer 04 and the barrier layer 04 form a heterojunction structure; first metals 05 are arranged at two ends of the upper surface of the barrier layer 04, an insulating layer 07 is arranged on the upper surface of the barrier layer 04 between the first metals 05, and a second metal 06 is arranged on the upper surface of the insulating layer 07; an isolation structure is arranged between the first device 09 and the second device 10, the isolation structure is formed by the groove 11 and the filling material 08 filled in the groove 11, and the isolation structure extends from the upper surface of the integrated circuit to the buffer layer 02 along the vertical direction;

further, the groove 11 may be one of a rectangle, a trapezoid, a V-shape and a T-shape, and a depletion region is formed by depletion of the p-type filling material 08 and the buffer layer, so as to isolate different devices and reduce interference between the devices caused by current leakage.

The filling material 08 is a p-type semiconductor material, and the semiconductor material is one of Polysilicon, NiO, ZnO, and GaN.

Furthermore, the doping concentration of the p-type semiconductor material is 1 multiplied by 10¹⁶～1×10¹⁸cm^-2。

The invention has the beneficial effects that:

relative to conventional mesa isolationThe invention has good surface flatness, which is beneficial to the subsequent process. Meanwhile, in general, the GaN material has a 1 × 10 structure under the condition of non-artificial doping¹⁴cm^-2The n-type background is doped, so that a GaN buffer layer of a general GaN-based High Electron Mobility Transistor (HEMT) is n-type, certain buffer layer leakage current can be generated, a depletion region is formed through the depletion effect between a p-type filling material and the buffer layer, and the good isolation effect is achieved; compared with the GaN-on-SOI technology, the method has the advantages that the substrate is not wrapped and the like, so that the problems of thermal resistance increase and the like are avoided. And isolation modes such as reverse electric field coupling and the like are adopted, a negative voltage power supply is not required to be additionally introduced, and the preparation and the use are relatively simpler.

Drawings

FIG. 1 is a schematic view of an isolation structure applied to a GaN integrated circuit according to the present invention

FIG. 2 is a schematic view of a ladder isolation structure applied to a GaN integrated circuit according to the present invention

FIG. 3 is a schematic diagram of an isolation structure applied to a T-shaped structure of a GaN integrated circuit according to the present invention

FIG. 4 is a schematic structural diagram of an embodiment of the present invention

FIG. 5 is a simulation structure diagram of an embodiment based on TCAD software according to the present invention

FIG. 6 shows the variation of leakage current at different isolation fill depths according to the present invention

FIG. 7 is a graph comparing leakage current of the electric field coupling isolation structure of the present invention

Detailed Description

The technical scheme of the invention is described in detail in the following with the accompanying drawings:

fig. 4 is a schematic view of an isolation structure applied to a GaN integrated circuit according to an embodiment of the present invention, which is an exemplary application of a GaN-based high electron mobility transistor, and the isolation structure is a main structure of the present invention.

An isolation structure applied to a gallium nitride integrated circuit comprises a substrate 01, a buffer layer 02, a channel layer 03 and a barrier layer 04 which are sequentially arranged from bottom to top, wherein the channel layer 04 and the barrier layer 04 form a heterojunction structure;

further, in the embodiment, the substrate 01 is silicon, the buffer layer 02 is GaN, the channel layer 03 is GaN, and the barrier layer 04 is AlGaN.

Specifically, the AlGaN barrier layer and the GaN buffer layer form a heterojunction structure, and a two-dimensional electron gas channel is formed at an AlGaN/GaN heterojunction interface under the polarization action.

The barrier layer 04 is provided with a first metal 05, an insulating layer 07 and a pGaN layer 101 on the upper surface, and the pGaN layer 101 is provided with a second metal 06.

Specifically, the first metal 05 is a low work function metal and forms ohmic contact with the channel layer to serve as a source or a drain of the device, and the second metal 06 is a high work function metal and forms schottky contact with the pGaN layer 101 to serve as a gate of the device.

The integrated circuit is formed by integrating a first device 09 and a second device 10 on the same substrate, wherein the first device 09 and the second device 10 are formed by integrating a pGaN layer 101, a buffer layer 02, a channel layer 03, a barrier layer 04, a first metal 05, a first metal 06 and an insulating layer 07 on a substrate 01;

furthermore, the first device and the second device are all pGaN enhancement type GaN-based high electron mobility transistors.

The isolation structure is located between the first device 09 and the second device 10, the isolation structure is formed by the groove 11 and the filling material 08 filled in the groove 11, and the isolation structure extends into the buffer layer 02 from the upper surface of the integrated circuit along the vertical direction.

Through the structure, the filling material 08 and the GaN buffer layer in the groove 11 form a depletion region to isolate the first device 09 from the second device 10, so that the current leakage of the devices between each other during working is avoided, meanwhile, the signal crosstalk between different devices is effectively inhibited, and the working stability and reliability of the devices are improved.

In this embodiment, the isolation structure is located between the first device 09 and the second device 10, and the isolation structure may be located between a circuit and a circuit, and the isolation between the circuit and the device may be implemented by different modules. As long as the depletion region can be formed by filling the corresponding semiconductor material and other materials to achieve effective electrical isolation in the gallium nitride integrated circuit, corresponding effects can be obtained by the technology of the present invention.

Further, in this embodiment, the groove 11 is rectangular, and the shape of the groove may be different shapes such as trapezoid, V-shape, T-shape, and the like, referring to fig. 1, 2, and 3, and different groove-shaped filling materials have different boundaries of the depletion region, so that the groove can be adjusted according to actual use requirements.

Specifically, in the present embodiment, the groove width is 1.5um, wherein the gate-source distance of the first device 09 is 14 μm, and the gate-source distance of the second device is 3 μm. I.e. the first device 09 is a high voltage device and the second device 10 is a low voltage device.

Further, in this embodiment, the filling material 08 is p-type semiconductor material GaN, and the doping concentration is 1 × 10¹⁸cm^-2The semiconductor material can be one of Polysilicon, NiO, ZnO and GaN, and the doping concentration can be 1 × 10¹⁶cm^-2～1×10¹⁸cm^-2。

Specifically, the doping concentration determines the width of the depletion region, and can be adjusted according to the background doping concentration of the GaN buffer layer, the thickness of the GaN buffer layer, the device and circuit spacing distance and the shape in practical application.

The structure is simulated through TCAD software, a simulation structure diagram of the device is shown in figure 5, a first device is arranged on the left side, a second device is arranged on the right side, and when the first device works at high voltage, the source leakage current of the second device is measured, and the isolation effect of the isolation structure is verified. The current leakage curve of the device is obtained, see fig. 6. As is apparent from fig. 6, with the proposed structure, the drain voltage of the first device is 700V, and the second device has only 10 on one side^-15Magnitude leakage current plays a good role in isolation. Meanwhile, the larger the depth of the isolation structure is, the better the current inhibition effect is.

Through simulation, the isolation effect of the reverse electric field coupling isolation and the isolation structure of the invention is compared, and referring to fig. 7, it can be seen that when the reverse coupling voltage is-10V, the leakage current of the invention is still 2-3 orders of magnitude smaller than that of the reverse electric field coupling isolation structure, which indicates that the invention has good isolation effect.