阅读说明：本技术 阵列基板及其制备方法 (Array substrate and preparation method thereof ) 是由 梁志伟 曹占锋 王珂 刘英伟 姚舜禹 梁爽 狄沐昕 于 2020-05-27 设计创作，主要内容包括：本公开提供了一种阵列基板及其制备方法,属于显示技术领域。该阵列基板的制备方法包括依次形成层叠的衬底基板、驱动电路层和功能器件层；其中,形成驱动电路层包括：在所述衬底基板的一侧形成导电种子；在所述导电种子层表面形成可移除的图案限定层,所述可移除的图案限定层设置有引线开口,所述引线开口暴露部分所述导电种子层；采用电镀工艺在所述引线开口内形成位于所述导电种子层表面的电镀金属层；移除所述可移除的图案限定层；去除所述导电种子层未被所述电镀金属层覆盖的部分,以形成第一引线层。该制备方法使得电镀工艺适用于任意金属布线层,且提高了第一引线层的形貌。(The disclosure provides an array substrate and a preparation method thereof, and belongs to the technical field of display. The preparation method of the array substrate comprises the steps of sequentially forming a laminated substrate, a driving circuit layer and a functional device layer; wherein forming the driving circuit layer includes: forming a conductive seed on one side of the substrate base plate; forming a removable pattern defining layer on the surface of the conductive seed layer, wherein the removable pattern defining layer is provided with a lead opening which exposes a part of the conductive seed layer; forming an electroplating metal layer positioned on the surface of the conductive seed layer in the lead opening by adopting an electroplating process; removing the removable pattern defining layer; and removing the part of the conductive seed layer which is not covered by the electroplated metal layer to form a first lead layer. The preparation method enables the electroplating process to be suitable for any metal wiring layer, and improves the appearance of the first lead layer.)

1. A preparation method of an array substrate is characterized by comprising the following steps:

providing a substrate base plate;

forming a driving circuit layer on one side of the substrate base plate;

forming a functional device layer on one side of the driving circuit layer, which is far away from the substrate base plate;

wherein forming a driving circuit layer on one side of the substrate base plate includes: forming at least one first lead layer on one side of the substrate base plate; forming any one of the first lead layers includes:

forming a conductive seed layer on one side of the substrate base plate;

forming a removable pattern defining layer on the surface of the conductive seed layer away from the substrate, wherein the removable pattern defining layer is provided with a lead opening which exposes a part of the conductive seed layer;

forming an electroplating metal layer positioned on the surface of the conductive seed layer in the lead opening by adopting an electroplating process;

removing the removable pattern defining layer;

and removing the part of the conductive seed layer which is not covered by the electroplated metal layer.

2. The method for preparing the array substrate according to claim 1, wherein the forming of the removable pattern defining layer on the surface of the conductive seed layer away from the substrate comprises:

forming a removable insulating material layer on the surface of the conductive seed layer away from the substrate base plate;

patterning the removable layer of insulating material to form the removable pattern defining layer.

3. The method for manufacturing the array substrate according to claim 2, wherein the step of forming a removable insulating material layer on the surface of the conductive seed layer away from the substrate comprises:

forming a photoresist material layer on the surface of the conductive seed layer far away from the substrate;

patterning the removable layer of insulating material comprises:

exposing and developing the photoresist material layer to form the removable pattern defining layer.

4. The method for manufacturing the array substrate according to claim 3, wherein the forming a photoresist material layer on the surface of the conductive seed layer away from the substrate comprises:

forming a photoresist material layer on the surface of the conductive seed layer, which is far away from the substrate, by using a degradable photoresist material, wherein the degradable photoresist material can be dissolved in a degradation liquid after being solidified;

removing the removable pattern defining layer comprises:

dissolving the removable pattern defining layer using the degradation liquid.

5. The method for manufacturing the array substrate according to claim 3, wherein the forming a photoresist material layer on the surface of the conductive seed layer away from the substrate comprises:

forming a photoresist material layer on the surface of the conductive seed layer far away from the substrate by using a negative photoresist material;

exposing and developing the photoresist material layer includes:

exposing and developing the photoresist material layer to form a removable pattern defining layer having lead openings such that the lead openings have a greater width at an end proximate to the base substrate than at an end distal from the base substrate.

6. The method for preparing the array substrate according to claim 1, wherein the forming of the removable pattern defining layer on the surface of the conductive seed layer away from the substrate comprises:

forming a removable pattern defining layer on the surface of the conductive seed layer away from the substrate base plate, wherein the minimum value of the width of the lead opening is a first size value;

forming an electroplated metal layer on the surface of the conductive seed layer in the lead opening by adopting an electroplating process comprises:

and forming an electroplating metal layer positioned on the surface of the conductive seed layer in the lead opening by adopting an electroplating process, so that the thickness of the electroplating metal layer is a second size value, and the second size value is not more than 5 times of the first size value.

7. The method for manufacturing an array substrate according to any one of claims 1 to 6, wherein forming at least one first lead layer on one side of the substrate base includes:

forming a first lead layer on one side of the substrate base plate;

forming a first planarization layer on a side of the first lead layer away from the base substrate, the first planarization layer exposing at least a portion of the first lead layer;

forming a first transfer metal layer on one side of the first planarization layer, which is far away from the substrate base plate, wherein the first transfer metal layer is connected with the first lead layer;

forming a second planarization layer on one side of the first transition metal layer, which is far away from the substrate base plate, wherein the second planarization layer is provided with a first connecting through hole; the first connection through hole exposes a part of the first junction metal layer, and an orthographic projection of the first connection through hole on the first lead layer does not overlap with the first lead layer;

and forming another layer of the first lead layer on the surface of the second planarization layer, which is far away from the substrate base plate, wherein the another layer of the first lead layer is connected with the first transfer metal layer through the first connecting through hole.

8. The array substrate is characterized by comprising a substrate, a driving circuit layer and a functional device layer which are sequentially stacked;

the driving circuit layer comprises at least one first lead layer, and any one first lead layer comprises at least one first lead;

any one first lead comprises a seed lead arranged on one side of the substrate base plate and a growth lead arranged on the seed lead far away from the surface of the substrate base plate, and the orthographic projection of the growth lead on the substrate base plate is superposed with the orthographic projection of the seed lead on the substrate base plate.

9. The array substrate of claim 8, wherein the thickness of the first lead is not greater than 5 times the width of the seed lead.

10. The array substrate of claim 8, wherein a width of the first lead away from the substrate base is smaller than a width of the first lead near an end of the substrate base.

11. The array substrate of any one of claims 8 to 10, wherein the driving circuit layer comprises:

the first lead layer is arranged on one side of the substrate base plate;

the first planarization layer is arranged on one side, far away from the substrate, of the first lead layer;

the first transition metal layer is arranged on one side, away from the substrate base plate, of the first planarization layer and is connected with the first lead layer;

the second planarization layer is arranged on one side, away from the substrate base plate, of the first transfer metal layer and is provided with a first connecting through hole; the first connection through hole exposes a part of the first junction metal layer, and an orthographic projection of the first connection through hole on the first lead layer does not overlap with the first lead layer;

the other first lead layer is arranged on the surface, away from the substrate base plate, of the second planarization layer and is connected with the first transfer metal layer through the first connecting through hole.

12. The array substrate of any one of claims 8 to 10, wherein the driving circuit layer comprises:

the driving transistor is arranged on one side of the substrate and comprises a source drain electrode layer consisting of a source electrode and a drain electrode;

the third planarization layer is arranged on one side, away from the substrate base plate, of the driving transistor and is provided with a third connecting through hole exposing at least part of the source drain electrode layer;

the second switching metal layer is arranged on one side, away from the substrate base plate, of the third planarization layer and is connected with the source drain electrode layer through the third connecting through hole;

the fourth planarization layer is arranged on one side, away from the substrate base plate, of the second transfer metal layer and is provided with a fourth connecting through hole; the fourth connecting via hole exposes a part of the second transit metal layer, and the orthographic projection of the fourth connecting via hole on the substrate base plate is not overlapped with the orthographic projection of the third connecting via hole on the substrate base plate;

and the first lead layer is arranged on the surface of the fourth planarization layer, which is far away from the substrate base plate, and is connected with the second transfer metal layer through the fourth connecting through hole.

13. The array substrate of any one of claims 8 to 10, wherein the driving circuit layer comprises:

the driving transistor is arranged on one side of the substrate and comprises a source drain electrode layer consisting of a source electrode and a drain electrode;

the third planarization layer is arranged on one side, away from the substrate base plate, of the source drain electrode layer and is provided with a third connecting through hole exposing at least part of the source drain electrode layer;

the first lead layer is arranged on the surface, far away from the substrate base plate, of the third planarization layer and is connected with the source drain electrode layer through the third connecting through hole.

14. The array substrate of any one of claims 8 to 10, wherein the driving circuit layer comprises a driving transistor, and the driving transistor comprises:

a semiconductor layer provided on one side of the substrate base plate; the semiconductor layer comprises a source contact region and a drain contact region;

the interlayer dielectric layer is arranged on one side of the semiconductor layer, which is far away from the substrate base plate;

the first lead layer is arranged on one side, far away from the substrate, of the interlayer dielectric layer and is provided with a source electrode and a drain electrode; the source electrode is connected with the source electrode contact region, and the drain electrode is connected with the drain electrode contact region.

Technical Field

The disclosure relates to the technical field of display, and in particular relates to an array substrate and a preparation method thereof.

Background

For a medium-and-large-sized self-luminous panel, for example, in a medium-and-large-sized Micro LED display panel, a medium-and-large-sized Mini LED backlight source or a display panel, the metal lead distance is long, which results in a serious voltage drop on the metal lead, and it is difficult to ensure that sufficient driving current is provided for each current-driven light emitting device. In the prior art, a seed lead can be formed on a substrate, and then a copper growth layer is formed on the seed lead by adopting a copper electroplating process, so that a metal lead with a larger thickness is prepared, and the voltage drop on the metal lead is reduced. However, this method is only suitable for directly preparing thick copper metal leads on a substrate, and has a large limitation in applicability, and it is difficult to precisely control the morphology and thickness uniformity of the prepared metal leads, which is not favorable for uniformity of product characteristics.

The above information disclosed in the background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art that is known to a person of ordinary skill in the art.

Disclosure of Invention

The invention aims to provide an array substrate and a preparation method thereof, which can improve the thickness of a part of metal wiring layers of the array substrate.

In order to achieve the purpose, the technical scheme adopted by the disclosure is as follows:

according to a first aspect of the present disclosure, there is provided a method of manufacturing an array substrate, including:

providing a substrate base plate;

forming a driving circuit layer on one side of the substrate base plate;

forming a functional device layer on one side of the driving circuit layer, which is far away from the substrate base plate;

wherein forming a driving circuit layer on one side of the substrate base plate includes: forming at least one first lead layer on one side of the substrate base plate; forming any one of the first lead layers includes:

forming a conductive seed layer on one side of the substrate base plate;

forming a removable pattern defining layer on the surface of the conductive seed layer away from the substrate, wherein the removable pattern defining layer is provided with a lead opening which exposes a part of the conductive seed layer;

forming an electroplating metal layer positioned on the surface of the conductive seed layer in the lead opening by adopting an electroplating process;

removing the removable pattern defining layer;

and removing the part of the conductive seed layer which is not covered by the electroplated metal layer.

In one exemplary embodiment of the present disclosure, forming a removable pattern defining layer on a surface of the conductive seed layer remote from the substrate includes:

forming a removable insulating material layer on the surface of the conductive seed layer away from the substrate base plate;

patterning the removable layer of insulating material to form the removable pattern defining layer.

In an exemplary embodiment of the disclosure, forming a layer of removable insulating material on a surface of the conductive seed layer remote from the substrate includes:

forming a photoresist material layer on the surface of the conductive seed layer far away from the substrate;

patterning the removable layer of insulating material comprises:

exposing and developing the photoresist material layer to form the removable pattern defining layer.

In an exemplary embodiment of the present disclosure, forming a photoresist material layer on a surface of the conductive seed layer away from the substrate includes:

forming a photoresist material layer on the surface of the conductive seed layer, which is far away from the substrate, by using a degradable photoresist material, wherein the degradable photoresist material can be dissolved in a degradation liquid after being solidified;

removing the removable pattern defining layer comprises:

dissolving the removable pattern defining layer using the degradation liquid.

In an exemplary embodiment of the present disclosure, forming a photoresist material layer on a surface of the conductive seed layer away from the substrate includes:

forming a photoresist material layer on the surface of the conductive seed layer far away from the substrate by using a negative photoresist material;

exposing and developing the photoresist material layer includes:

exposing and developing the photoresist material layer to form a removable pattern defining layer having lead openings such that the lead openings have a greater width at an end proximate to the base substrate than at an end distal from the base substrate.

In one exemplary embodiment of the present disclosure, forming a removable pattern defining layer on a surface of the conductive seed layer remote from the substrate includes:

forming a removable pattern defining layer on the surface of the conductive seed layer away from the substrate base plate, wherein the minimum value of the width of the lead opening is a first size value;

forming an electroplated metal layer on the surface of the conductive seed layer in the lead opening by adopting an electroplating process comprises:

and forming an electroplating metal layer positioned on the surface of the conductive seed layer in the lead opening by adopting an electroplating process, so that the thickness of the electroplating metal layer is a second size value, and the second size value is not more than 5 times of the first size value.

In one exemplary embodiment of the present disclosure, forming at least one first lead layer on one side of the substrate base plate includes:

forming a first lead layer on one side of the substrate base plate;

forming a first planarization layer on a side of the first lead layer away from the base substrate, the first planarization layer exposing at least a portion of the first lead layer;

forming a first transfer metal layer on one side of the first planarization layer, which is far away from the substrate base plate, wherein the first transfer metal layer is connected with the first lead layer;

forming a second planarization layer on one side of the first transition metal layer, which is far away from the substrate base plate, wherein the second planarization layer is provided with a first connecting through hole; the first connection through hole exposes a part of the first junction metal layer, and an orthographic projection of the first connection through hole on the first lead layer does not overlap with the first lead layer;

and forming another layer of the first lead layer on the surface of the second planarization layer, which is far away from the substrate base plate, wherein the another layer of the first lead layer is connected with the first transfer metal layer through the first connecting through hole.

According to a second aspect of the present disclosure, an array substrate is provided, which includes a substrate, a driving circuit layer, and a functional device layer, which are sequentially stacked;

the driving circuit layer comprises at least one first lead layer, and any one first lead layer comprises at least one first lead;

any one first lead comprises a seed lead arranged on one side of the substrate base plate and a growth lead arranged on the seed lead far away from the surface of the substrate base plate, and the orthographic projection of the growth lead on the substrate base plate is superposed with the orthographic projection of the seed lead on the substrate base plate.

In an exemplary embodiment of the present disclosure, the thickness of the first lead is not greater than 5 times the width of the seed lead.

In an exemplary embodiment of the present disclosure, a width of an end of the first lead away from the substrate base plate is smaller than a width of an end of the first lead near the substrate base plate.

In an exemplary embodiment of the present disclosure, the driving circuit layer includes:

the first lead layer is arranged on one side of the substrate base plate;

the first planarization layer is arranged on one side, far away from the substrate, of the first lead layer;

the first transition metal layer is arranged on one side, away from the substrate base plate, of the first planarization layer and is connected with the first lead layer;

the second planarization layer is arranged on one side, away from the substrate base plate, of the first transfer metal layer and is provided with a first connecting through hole; the first connection through hole exposes a part of the first junction metal layer, and an orthographic projection of the first connection through hole on the first lead layer does not overlap with the first lead layer;

the other first lead layer is arranged on the surface, away from the substrate base plate, of the second planarization layer and is connected with the first transfer metal layer through the first connecting through hole.

In an exemplary embodiment of the present disclosure, the driving circuit layer includes:

the driving transistor is arranged on one side of the substrate and comprises a source drain metal layer with a source electrode and a drain electrode;

the third planarization layer is arranged on one side, away from the substrate base plate, of the driving transistor and is provided with a third connecting through hole exposing at least part of the source drain metal layer;

the second switching metal layer is arranged on one side, away from the substrate base plate, of the third planarization layer and is connected with the source drain metal layer through the third connecting through hole;

the fourth planarization layer is arranged on one side, away from the substrate base plate, of the second transfer metal layer and is provided with a fourth connecting through hole; the fourth connecting via hole exposes a part of the second transit metal layer, and the orthographic projection of the fourth connecting via hole on the substrate base plate is not overlapped with the orthographic projection of the third connecting via hole on the substrate base plate;

and the first lead layer is arranged on the surface of the fourth planarization layer, which is far away from the substrate base plate, and is connected with the second transfer metal layer through the fourth connecting through hole.

In an exemplary embodiment of the present disclosure, the driving circuit layer includes:

the driving transistor is arranged on one side of the substrate and comprises a source drain metal layer with a source electrode and a drain electrode;

the third planarization layer is arranged on one side, away from the substrate base plate, of the source drain metal layer and is provided with a third connecting through hole exposing at least part of the source drain metal layer; the orthographic projection of the third connecting through hole on the substrate base plate is not overlapped with the orthographic projection of the second connecting through hole on the substrate base plate;

and the first lead layer is arranged on the surface of the third planarization layer, which is far away from the substrate base plate, and is connected with the source drain metal layer through the third connecting through hole.

In one exemplary embodiment of the present disclosure, the driving circuit layer includes a driving transistor including:

a semiconductor layer provided on one side of the substrate base plate; the semiconductor layer comprises a source contact region and a drain contact region;

the interlayer dielectric layer is arranged on one side of the semiconductor, which is far away from the substrate base plate;

the first lead layer is arranged on one side, far away from the substrate, of the interlayer dielectric layer and is provided with a source electrode and a drain electrode; the source electrode is connected with the source electrode contact region, and the drain electrode is connected with the drain electrode contact region.

According to the array substrate and the preparation method thereof provided by the disclosure, the whole conductive seed layer and the removable pattern limiting layer covering the conductive seed layer can be formed firstly, so that the condition that the conductive seed layer is absent in the lead opening is ensured. Then, growing metal in the lead opening by adopting an electroplating process to prepare a precursor growth lead positioned in the lead opening so as to form an electroplated metal layer; the electroplating process of the whole conductive seed layer can be suitable for any metal wiring layer of the array substrate, the thickness of any metal wiring layer of the array substrate can be improved, the thickness uniformity of the formed first lead layer is improved, and the application limitation of the electroplating process in the prior art is overcome. The removable pattern defining layer allows the precursor growth leads to have good side profile during electroplating; the conductive seed layer can provide a complete plating base, resulting in better uniformity of the precursor growth lead surface. The removable pattern defining layer is then removed and the conductive seed layer is patterned by etching to form seed leads that are covered by the precursor growth leads. The precursor growth lead can also be partially etched in the etching process to form a growth lead, and the uniformity of the surface of the growth lead, which is far away from the substrate, can be further improved by utilizing the difference of the etching speeds at different positions in the etching process. Therefore, the first lead layer comprises the first lead, the first lead comprises the seed lead and the growth lead laminated on the surface of the seed lead, the surface uniformity of the first lead is better, and the performance of the array substrate can be improved.

Drawings

The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

Fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

Fig. 3 is a schematic flow chart illustrating the formation of any one of the first lead layers according to an embodiment of the present disclosure.

Fig. 4 is a schematic structural diagram of providing a substrate base plate according to an embodiment of the present disclosure.

Fig. 5 is a schematic structural diagram of forming a conductive seed layer on one side of a substrate according to an embodiment of the disclosure.

Fig. 6 is a schematic structural diagram of forming a removable pattern definition layer on a surface of the conductive seed layer away from the substrate according to an embodiment of the disclosure.

Fig. 7 is a schematic structural diagram of a plated metal layer formed on the surface of the conductive seed layer in the lead opening by using an electroplating process according to an embodiment of the disclosure.

FIG. 8 is a schematic diagram of a removable pattern definition layer removal structure according to an embodiment of the present disclosure.

Fig. 9 is a schematic structural diagram of etching to form a first lead layer according to an embodiment of the disclosure.

Fig. 10 is a schematic structural diagram of forming a passivation layer on a surface of the first lead layer away from the substrate according to an embodiment of the disclosure.

Fig. 11 is a schematic flow chart illustrating formation of a first lead layer group according to an embodiment of the present disclosure.

Fig. 12 is a schematic structural diagram of forming a first planarizing layer on a side of a previous first lead layer away from a substrate according to an embodiment of the disclosure.

Fig. 13 is a schematic structural diagram of forming a first transition metal layer on a side of the first planarization layer away from the substrate base plate according to an embodiment of the disclosure.

Fig. 14 is a schematic structural diagram of forming a second planarization layer on a side of the first transition metal layer away from the substrate according to an embodiment of the disclosure.

Fig. 15 is a schematic structural diagram of a first lead layer after a second planarization layer is formed on a surface of the second planarization layer away from the substrate base according to an embodiment of the disclosure.

Fig. 16 is a schematic structural diagram of forming a pixel defining layer on a side of the driving circuit layer away from the substrate according to an embodiment of the disclosure.

Fig. 17 is a schematic structural diagram of forming a functional device layer on a side of the driving circuit layer away from the substrate according to an embodiment of the present disclosure.

Fig. 18 is a schematic structural view of a driving circuit layer having a plurality of first lead layers sequentially stacked according to an embodiment of the present disclosure.

Fig. 19 is a schematic flow chart illustrating a process of forming a first wiring layer electrically connected to a driving transistor according to an embodiment of the present disclosure.

Fig. 20 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

Fig. 21 is a schematic flow chart illustrating a process of forming a first wiring layer electrically connected to a driving transistor according to an embodiment of the present disclosure.

Fig. 22 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

Fig. 23 is a schematic flow chart illustrating a process of forming a first wiring layer electrically connected to a driving transistor according to an embodiment of the present disclosure.

Fig. 24 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

Fig. 25 is a schematic structural view of an array substrate according to an embodiment of the present disclosure.

Fig. 26 is a schematic top view of an array substrate according to an embodiment of the present disclosure.

Fig. 27 is a schematic top view of an array substrate according to an embodiment of the present disclosure.

The reference numerals of the main elements in the figures are explained as follows:

100. a substrate base plate; 110. aligning the mark layer; 111. aligning the patterns; 120. a buffer layer; 200. a driving circuit layer; 201. a first lead layer; 201a, a previous first lead layer; 201b, a first back lead layer; 2011. a first lead; 202. a second lead layer; 210. a drive transistor; 220. an interlayer dielectric layer; 230. a source drain metal layer; 241. a first planarizing layer; 242. a second planarizing layer; 243. a third planarizing layer; 244. a fourth planarizing layer; 251. a first connecting via; 252. a second connecting via; 253. a third connecting via; 254. a fourth connecting via; 261. a first transition metal layer; 262. a second transfer metal layer; 271. a pixel defining layer; 272. a conductive adhesive; 300. a functional device layer; 310. a functional device; 311. an LED; 410. a conductive seed layer; 411. a seed lead; 420. a removable pattern defining layer; 421. a lead opening; 430. electroplating a metal layer; 431. a precursor growth lead; 432. growing a lead; 440. a passivation layer; 510. scanning the lead; 520. a data lead; 530. a common voltage lead; 540. binding a lead; 610. a backside wiring layer; 620. an insulating layer; 630. bonding a pad layer; 710. a first metal wiring layer; 720. a second metal wiring layer; 711. a first metal lead; 721. and a second metal lead.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure.

In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals denote the same or similar structures in the drawings, and thus detailed descriptions thereof will be omitted.

The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the disclosure can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the primary technical ideas of the disclosure.

When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.

The terms "a," "an," "the," and the like are used to denote the presence of one or more elements/components/parts; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc. The terms "first" and "second", etc. are used merely as labels, and are not limiting on the number of their objects.

In the present disclosure, the width of the lead refers to the dimension of the lead in a plane parallel to the substrate base plate, perpendicular to the extending direction thereof. The thickness of one film layer or lead means the dimension of the film layer or lead in the direction perpendicular to the substrate base plate.

In the related art, a seed lead may be formed on a substrate, and then a copper growth layer may be formed on the seed lead by using a copper electroplating process to form a thick plated metal lead. However, when electroplating copper based on the seed lead, a copper growth layer will grow outward on the surface of the seed lead, and the morphology and width thereof are not easily controlled. In some related arts, it is also possible to provide a bank structure between the seed leads and then perform an electro-coppering process to restrict the width of the copper growth layer. However, due to the alignment error in the preparation of the retaining wall structure, it is difficult to precisely embed the retaining wall between the seed leads, which limits the improvement of the surface uniformity of the copper growth layer.

The present disclosure provides a method for manufacturing an array substrate, as shown in fig. 1 and 2, the array substrate includes a substrate 100, a driving circuit layer 200, and a functional device layer 300, which are sequentially stacked.

The preparation method of the array substrate comprises the following steps:

step S110, as shown in fig. 4, providing a substrate 100;

step S120, forming a driving circuit layer 200 on one side of the base substrate 100;

step S130, forming a functional device layer 300 on the side of the driving circuit layer 200 away from the substrate 100;

wherein, forming the driving circuit layer 200 on one side of the substrate 100 includes: forming at least one first lead layer 201 on one side of the base substrate 100; as shown in fig. 3, forming any one of the first lead layers 201 includes:

step S210, as shown in fig. 5, forming a conductive seed layer 410 on one side of the substrate 100;

step S220, as shown in fig. 6, a removable pattern defining layer 420 is formed on the surface of the conductive seed layer 410 away from the substrate 100, the removable pattern defining layer 420 is provided with a lead opening 421, and the lead opening 421 exposes a portion of the conductive seed layer 410;

step S230, as shown in fig. 7, forming a plated metal layer 430 on the surface of the conductive seed layer 410 in the lead opening 421 by using a plating process;

step S240, as shown in fig. 8, removing the removable pattern defining layer 420;

in step S250, as shown in fig. 9, a portion of the conductive seed layer 410 not covered by the electroplated metal layer 430 is removed to form the first lead layer 201.

According to the preparation method of the array substrate provided by the disclosure, the whole conductive seed layer 410 and the removable pattern limiting layer 420 covering the conductive seed layer 410 can be formed firstly, and the conductive seed layer 410 is not patterned, so that the situation that the conductive seed layer 410 is absent in the lead openings 421 can be ensured, and the problem that the electroplating substrate is likely to be absent in partial areas inside the lead openings 421 is solved. Then, a metal is grown in the lead openings 421 using an electroplating process, and precursor growth leads 431 located in the lead openings 421 are prepared to form an electroplated metal layer 430. During electroplating, the removable pattern-defining layer 420 may define the sides of the precursor growth leads 431 such that the precursor growth leads 431 have good side morphology; the conductive seed layer 410 within the lead openings 421 may provide a complete plating base such that the precursor growth leads 431 have better uniformity away from the surface of the substrate 100. The removable pattern defining layer 420 is then removed and the conductive seed layer 410 is patterned by etching, forming a seed lead 411 covered by a precursor growth lead 431. The precursor growth wire 431 may also be partially etched during the etching process to form the growth wire 432, and the uniformity of the surface of the growth wire 432 away from the substrate base plate 100 may be further improved by using the difference in etching speed at different positions during the etching process. In this way, the first lead layer 201 includes the first lead 2011, the first lead 2011 includes the seed lead 411 and the growth lead 432 stacked on the surface of the seed lead 411, the surface uniformity of the first lead 2011 is better, and the performance of the array substrate can be improved. Moreover, the preparation method of the array substrate provided by the present disclosure overcomes the limitation of the position of the film layer of the plated metal lead in the prior art, and can prepare the first lead layer 201 at a desired position according to the performance requirement of the array substrate, thereby ensuring that the functional device 310 of the functional device layer 300 obtains sufficient driving current.

The steps, principles and effects of the method for manufacturing an array substrate provided by the present disclosure will be further explained and explained with reference to the accompanying drawings.

In step S110, a substrate 100 of an array substrate may be provided. The base substrate 100 may be an inorganic base substrate 100 or an organic base substrate 100. For example, in one embodiment of the present disclosure, the material of the substrate 100 may be a glass material such as soda-lime glass (soda-lime glass), quartz glass, or sapphire glass, or may be a metal material such as stainless steel, aluminum, or nickel. In another embodiment of the present disclosure, the material of the substrate 100 may be Polymethyl methacrylate (PMMA), Polyvinyl alcohol (PVA), Polyvinyl phenol (PVP), Polyether sulfone (PES), polyimide, polyamide, polyacetal, Polycarbonate (PC), Polyethylene terephthalate (PET), Polyethylene naphthalate (PEN), or a combination thereof. In another embodiment of the present disclosure, the substrate 100 may also be a flexible substrate 100, for example, the material of the substrate 100 may be Polyimide (PI). The substrate 100 may also be a composite of multiple layers of materials, for example, in an embodiment of the present disclosure, the substrate 100 may include a Bottom Film layer (Bottom Film), a pressure sensitive adhesive layer, a first polyimide layer, and a second polyimide layer, which are sequentially stacked.

In step S120, a driving circuit layer 200 may be formed on one side of the substrate base plate 100, the driving circuit layer 200 being used to drive each functional device 310 in the functional device layer 300. The driving circuit layer 200 includes a driving circuit composed of at least one metal wiring layer, and any one of the metal wiring layers includes at least one metal lead. Wherein, at least one metal wiring layer is the first lead layer 201 of the present disclosure.

It is understood that, as shown in fig. 1 and fig. 2, all the metal wiring layers in the driving circuit layer 200 may be the first lead layer 201, or may be a part of the first lead layer 201. For example, as shown in fig. 2, in the driving circuit layer 200, a part of the metal wiring layer may be a first lead layer 201, and another part of the metal wiring layer may be a second lead layer 202. The second lead layer 202 may be prepared by forming a metal film layer through a deposition process and performing a patterning operation on the metal film layer; in other words, the second lead layer 202 may not be plated, and each of the second leads included therein may have a lower thickness. In some embodiments, the material of the second lead layer 202 may or may not be the same as the conductive seed layer 410. As an example, one or more of the following metal wiring layers in the driving circuit layer 200 may be the second lead layer 202: a gate lead layer, a source-drain lead layer, a metal transfer layer, a light shielding layer, an electrode layer, a binding layer, or the like; of course, any one of the above films may be prepared as the first lead layer 201 by an electroplating process. When a metal wiring layer in the driving circuit layer 200 is a first lead layer 201, the first lead layer 201 may be prepared according to the preparation method shown in steps S210 to S250, so that any one of the first leads 2011 may include a seed lead 411 and a growth lead 432 laminated on the seed lead 411 away from the surface of the substrate 100.

In some embodiments of the present disclosure, the driving circuit layer 200 may include a passive driving circuit, for example, the driving circuit layer 200 includes a driving circuit composed of at least one metal wiring layer, and any one metal wiring layer includes at least one metal lead.

As an example, the present disclosure provides an array substrate having a passive driving circuit to explain and explain the structure and principle of the array substrate of the present disclosure. Fig. 26 shows only the first metal wiring layer 710, the second metal wiring layer 720 and the functional device layer of the array substrate. In this example, the array substrate includes a substrate 100, a driving circuit layer 200, and a functional device layer 300, which are sequentially stacked. The driving circuit layer 200 includes a first metal wiring layer 710, an insulating layer, and a second metal wiring layer 720 stacked on the substrate 100; the first metal wiring layer 710 includes a plurality of first metal leads 711; the insulating layer is provided with a connecting via hole exposing a part of the first metal lead 711 layer; the second metal lead 721 layer includes a plurality of second metal leads 721, and the second metal leads 721 can be used as an electrode layer of a driving circuit for bonding with the functional device 310. Wherein a portion of the second metal lead 721 is electrically connected to the first metal lead 711 through the connecting via. The functional device layer 300 includes functional devices 310 distributed in an array, and the functional devices 310 may be LEDs 311. One end of the LED 311 is connected to one second metal lead 721 through solder paste, and the other end is connected to the other second metal lead 721 through solder paste.

In this example, the first metal wiring layer 710 may adopt the structure of the first lead layer 201 of the embodiment of the present disclosure to ensure that sufficient current can be transmitted to the second metal wiring layer 720 and to avoid generating a significant voltage drop during driving. The second metal wiring layer 720 may adopt the structure of the first lead layer 201 of the present disclosure, or may adopt the structure of the second lead layer 202 of the present disclosure, which is not limited thereto.

By way of further exemplary introduction, the array substrate may include a plurality of light emitting regions, and four second metal leads 721 adjacent end to end in sequence may be disposed in any one of the light emitting regions, wherein a set of two second metal leads 721 disposed oppositely connects two different first metal leads 711 through connecting vias, respectively, and the other two second metal leads 721 are not electrically connected to the first metal leads 711. An LED 311 is disposed adjacent to the two second metal leads 721, and two ends of the LED 311 are respectively connected to the two second metal leads 721. As such, when the common voltage and the driving voltage are applied to the two first metal wirings 711, respectively, the four LEDs 311 may be driven to emit light.

It is understood that the exemplary array substrate can be used as a backlight source of an LCD display device, and can also be used as a display panel driven passively, which is not limited by the present disclosure. The LED 311 may be an LED lamp bead, or a Micro LED or a Mini LED.

In other embodiments of the present disclosure, the driving circuit layer 200 may include an active driving circuit, and the driving circuit layer 200 of the array substrate may further include electronic components such as a driving transistor, each of the electronic components is electrically connected to the functional device layer 300 through at least one metal wiring layer, and any one of the metal wiring layers includes at least one metal lead. Wherein, at least one metal wiring layer is the first lead layer 201 of the present disclosure. Of course, the driving circuit layer 200 may also be provided with other electronic components, such as a storage capacitor and other transistors besides the driving transistor, according to the requirement of the array substrate.

Alternatively, the transistor may be a Thin Film Transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS). The transistor is a thin film transistor as an example, and in the film structure, the thin film transistor may be a top gate thin film transistor or a bottom gate thin film transistor, which is not limited in this disclosure. On the thin film transistor material, the thin film transistor may be an amorphous silicon thin film transistor, a low temperature polysilicon thin film transistor, or an oxide thin film transistor, which is not limited by the present disclosure. The thin film transistor may be an N-type thin film transistor or a P-type thin film transistor in an on condition of the thin film transistor, which is not limited by the present disclosure. In the driving circuit layer 200, each of the thin film transistors and the storage capacitors may be formed by an active layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, a source/drain metal layer, and the like. The thin film transistor may include a semiconductor layer located in the active layer, a gate insulating layer, a gate located in the gate layer, an interlayer dielectric layer, and a source/drain electrode layer located in the source/drain metal layer, where the source/drain electrode layer is composed of a source and a drain of the thin film transistor. The semiconductor layer includes a channel region, and a source contact region and a drain contact region on both sides of the channel region, the source electrode passing through the interlayer dielectric layer to be connected with the source contact region, the drain electrode passing through the interlayer dielectric layer to be connected with the drain contact region, the gate electrode and the channel region being separated by a gate insulating layer. The position relation of each film layer can be determined according to the film layer structure of the thin film transistor. For example, the driving circuit layer 200 may include an active layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, and a source-drain metal layer, which are sequentially stacked, and the thin film transistor thus formed is a top gate thin film transistor. As another example, the driving circuit layer 200 may include a gate electrode layer, a gate insulating layer, an active layer, an interlayer dielectric layer, and a source/drain metal layer, which are sequentially stacked, and the thin film transistor thus formed is a bottom gate thin film transistor. The driving circuit layer 200 may also employ a double-gate structure, i.e., the gate layers may include a first gate layer and a second gate layer, the gate insulating layer may include a first gate insulating layer for isolating the active layer from the first gate layer, and a second gate insulating layer for isolating the first gate layer from the second gate layer. For example, the driving circuit layer 200 may include an active layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, and a source-drain metal layer, which are sequentially stacked on one side of the substrate 100.

As an example, as shown in fig. 27, the present disclosure provides an array substrate having an active driving circuit to explain and explain the structure and principle of the array substrate of the present disclosure. Fig. 27 shows only the driving transistor of the array substrate, two metal wiring layers, and the LED as a functional device. In this example, the driving circuit is a semi-active driving circuit, which includes a driving transistor 210, a scan line 510, a data line 520, a common voltage line 530 and a bonding line 540, the scan line 510 is used to control the driving transistor 210 to be turned on or off, the data line 520 is connected to the source of the driving transistor 210, the bonding line is connected to the drain of the driving transistor 210, and two ends of an LED as the functional device 310 are respectively connected to the bonding line 540 and the common voltage line 530. When a valid scan signal is applied to scan lead 510 to turn on drive transistor 210, a drive current can flow through the LED via data lead 520, drive transistor 210, the bonding lead, and common voltage lead 530, causing the LED to emit light. In this example, the scan lines 510 may belong to the second lead layer 202, and each scan line 510 need not be prepared using an electroplating process. The data lead 520, the common voltage lead 530 and the bonding lead 540 belong to the same first lead layer 201, and an electroplating process can be adopted to increase the thickness of each lead and reduce the impedance of each lead, so as to reduce the voltage drop of the driving circuit on the data lead 520 and the common voltage lead 530 and ensure the accuracy of the current flowing through the LED.

In the preparation of the driving circuit layer 200, any first lead layer 201 may be prepared according to the preparation method shown in steps S210 to S250.

In step S210, as shown in fig. 5, a metal material may be deposited on one side of the substrate base 100 to form a conductive seed layer 410. For example, a magnetron sputtering method may be used to deposit a metal material on one side of the substrate 100 to prepare the conductive seed layer 410 as an electroplating base.

It will be appreciated that an intermediate substrate may be obtained according to the process steps that have been carried out before the deposition of the metallic material. The intermediate substrate may have a different structure according to the process steps that have been performed, and may be, for example, the base substrate 100 itself, or may include the base substrate 100 and each of the already-formed film layers sequentially stacked on the base substrate 100. In step S210, a metal material may be deposited on a surface of the intermediate substrate on which the conductive seed layer 410 is to be formed. For example, in one embodiment of the present disclosure, if it is desired to form the first lead layer 201 on the surface of the base substrate 100, the base substrate 100 is used as an intermediate substrate in this step, and a metal material is deposited on the surface of the base substrate 100. For another example, in another embodiment of the present disclosure, if there is a film structure between the first lead layer 201 to be formed and the substrate 100, the substrate 100 and the film structure are integrally used as an intermediate substrate in this step when the first lead 2011 is prepared, and the surface of the film structure away from the substrate 100 is the surface on which the conductive seed layer 410 is to be formed.

Optionally, the thickness of the conductive seed layer 410 may not be greater than 1 micron, so as to avoid the excessively thick conductive seed layer 410 from generating an excessive stress on the intermediate substrate, and improve the stability and yield of the array substrate. Preferably, the thickness of the conductive seed layer 410 may be not greater than 0.5 μm, so as to shorten the etching time of the conductive seed layer 410 in step S250 and improve the side profile of the seed lead 411 formed after etching.

The conductive seed layer 410 may be a metal material, an alloy formed by a plurality of metal materials, or a plurality of stacked metal layers, and the disclosure is not limited in particular to meet the requirements of electroplating and the performance requirements of the array substrate.

Alternatively, the conductive seed layer 410 may include a protective metal layer and a target metal layer located on the protective metal layer away from the surface of the substrate 100. The target metal layer may serve as a plating base to form a plated metal layer 430 on its surface remote from the base substrate 100. For example, when the electroplating process is a copper plating process, the material of the target metal layer may be copper.

The protective metal layer serves to protect the target metal layer from corrosion or to protect the intermediate substrate from corrosion by the metal material of the target metal layer. The material of the protective metal layer may be a simple metal or an alloy, and may be, for example, molybdenum, titanium, molybdenum-titanium-nickel alloy, or the like.

In one embodiment of the present disclosure, the conductive seed layer 410 includes a protective metal layer and a target metal layer sequentially stacked on one side of the substrate base 100. Wherein, the material of the protective metal layer can be MTD alloy (molybdenum titanium nickel alloy), and the thickness is 250-350 angstroms; the target metal layer is made of copper and has a thickness of 2500-3500 angstroms.

It is understood that, when different first lead layers 201 are prepared, the kind, thickness, etc. of the metal material deposited in step S210 may be the same or different, so that the structure and material of the seed leads 411 of different first lead layers 201 are the same or different.

In step S220, as shown in fig. 6, a removable pattern defining layer 420 may be formed on a surface of the conductive seed layer 410 away from the substrate 100, the removable pattern defining layer 420 may be provided with a lead opening 421, and the lead opening 421 may include a portion of the conductive seed layer 410. Thus, during the electroplating process, the conductive seed layer 410 exposed by the lead openings 421 can be used as an electroplating base to grow electroplating metal, but the conductive seed layer 410 covered by the removable pattern defining layer 420 cannot grow electroplating metal. Therefore, the orthographic projection of the lead opening 421 on the base substrate 100 can coincide with the orthographic projection of the plated metal layer 430 formed in step S230.

Alternatively, the removable pattern defining layer 420 may be prepared through steps S221 and S222:

step S221, forming a removable insulating material layer on the surface of the conductive seed layer 410 away from the substrate 100;

in step S222, a patterning operation is performed on the removable insulating material layer to form a removable pattern defining layer 420.

Preferably, in step S221, the removable insulating material layer may be a photoresist material layer, that is, a photoresist material layer may be formed on the surface of the conductive seed layer 410 away from the substrate 100. As such, in step S222, patterning of the photoresist material layer may be achieved by exposure and development, forming a removable pattern defining layer 420.

In one embodiment of the present disclosure, in step S221, a layer of photoresist material may be formed on the surface of the conductive seed layer 410 away from the substrate 100 using a degradable photoresist material. The degradable photoresist material is a photoresist material which can be dissolved in a degradation liquid after being solidified.

Alternatively, the degradable photoresist material has a decomposable crosslinking group or forms a decomposable crosslinking group upon curing. After the degradable photoresist material is cured, when the cured degradable photoresist material needs to be removed, the cured degradable photoresist material can be treated by using a degradation solution, and the decomposable cross-linking groups in the cured degradable photoresist material can react with the degradation solution to be broken, so that the cured degradable photoresist material is decomposed into small molecular fragments which can be dissolved in the degradation solution. In this manner, gentle and thorough removal of the cured degradable photoresist material can be achieved.

Preparing a photoresist material layer using a degradable photoresist material in step S221, the material of the removable pattern defining layer 420 prepared in step S222 is a cured degradable photoresist material; in step S240, the removable pattern defining layer 420 may be dissolved using a degradation solution to remove the removable pattern defining layer 420, which both ensures complete removal of the removable pattern defining layer 420 and prevents damage to the plated metal layer 430 when the removable pattern defining layer 420 is removed.

In another embodiment of the present disclosure, in step S221, a negative photoresist material may be used to form a photoresist material layer on the surface of the conductive seed layer 410 away from the substrate 100. As such, in step S222, the photoresist material layer is exposed and developed to form the removable pattern defining layer 420 having the lead openings 421 such that the width of the ends of the lead openings 421 near the base substrate 100 is greater than the width of the ends far from the base substrate 100. In other words, the material properties of the negative photoresist material may be used to reduce the width of the lead openings 421 in a direction away from the substrate base plate 100, which not only facilitates the removal of the removable pattern definition layer 420, but also reduces the width of the growth leads 432 formed by electroplating in a direction away from the substrate base plate 100, thereby improving the strength of the growth leads 432 and reducing the risk of collapse of the growth leads 432. In this manner, in the prepared first lead 2011, the width of the end of the first lead 2011 away from the substrate base plate 100 is smaller than the width of the end of the first lead 2011 close to the substrate base plate 100. In a further embodiment, as shown in fig. 10, a passivation material, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, may be further deposited on the surface of the first lead 2011 away from the substrate 100 and the side of the first lead 2011 to form a passivation layer 440 protecting the first lead 2011. Since the width of the growth wire 432 formed by electroplating is reduced in a direction away from the base substrate 100, the continuity of the passivation layer can be secured.

Of course, in other embodiments of the present disclosure, other removable insulating materials may be used to prepare the removable pattern defining layer 420, and the removable pattern defining layer 420 is removed in step S240 by a corresponding process, for example, the removable pattern defining layer 420 is prepared by silicon oxide and the removable pattern defining layer 420 is removed by an etching process, or the removable pattern defining layer 420 is prepared by photosensitive resin and the removable pattern defining layer 420 is removed by a dry stripping process, which is not further detailed in the present disclosure.

In step S230, as shown in fig. 7, a plating process may be employed to form a plated metal layer 430 on the surface of the conductive seed layer 410 within the lead opening 421. In the electroplating process, an electroplating metal is grown from the surface of the conductive seed layer 410 as an electroplating base, the electroplating metal is grown only within the lead openings 421 under the constraint of the lead openings 421, and finally precursor growth leads 431 located within the lead openings 421 are formed after electroplating, each precursor growth lead 431 forming the electroplating metal layer 430.

Since the conductive seed layer 410 is a full-surface metal, the whole conductive seed layer 410 can be conveniently loaded with the plating current and the conductive seed layer 410 has a small voltage drop, so that the uniformity of the plating rate at the position of each lead opening 421 can be improved, and the uniformity of the surface of the precursor growth lead 431 away from the substrate 100 can be improved. According to the manufacturing method disclosed by the invention, an additional connecting lead is not required to be designed to ensure that power is supplied to the patterned conductive seed layer 410, so that the design process and the manufacturing process of each first lead layer 201 can be simplified, the method for manufacturing the first lead layers 201 disclosed by the invention can be suitable for any film position, and the defect that copper electroplating can be carried out only on the first layer close to the substrate in the prior art is overcome.

In the prior art, the conductive seed layer needs to be patterned and then electroplated, which requires additional conductive leads to electrically connect the seed leads to each other, so as to ensure that current can be applied to the seed leads during electroplating. Since the conductive seed layer is patterned into seed leads, it is difficult to maintain uniformity of the plating current density on the respective seed leads, which is disadvantageous to uniform growth of the plated metal on different seed leads. In addition, the plating metal may grow on the side of the seed lead during the electroplating process, so that the seed lead is completely covered by the plating metal layer, and the pattern definition effect of the seed lead on the plating metal layer is reduced. More importantly, since additional conductive leads need to be designed to connect the various seed leads, the method is only applicable to the metal wiring layer close to the substrate base plate, and cannot be applied to any metal wiring layer.

Alternatively, the thickness of each precursor growth lead 431, i.e., the thickness of the plated metal layer 430, may be controlled by controlling parameters of the plating process, such as plating current, plating time, and the like. Alternatively, in step S230, the thickness of the plated metal layer 430 may be made not more than five times the width of the lead opening 421. In other words, the minimum value of the width of the lead opening 421 is the first size value, that is, the minimum value of the width of the precursor growth lead 431 on the side close to the substrate base plate 100 is the first size value; the thickness of the plated metal layer 430 is a second dimension value, i.e., the thickness of the precursor growth lead 431 is a second dimension value; the second dimension value is no greater than 5 times the first dimension value. Thus, the aspect ratio of the prepared precursor growth lead 431 is not more than 5, which can improve the bonding strength between the precursor growth lead 431 and the conductive seed layer 410, prevent the precursor growth lead 431 from collapsing, and improve the stability of the precursor growth lead 431. As such, in the first lead 2011 formed after step S250, the thickness of the first lead 2011 is not more than 5 times the width of the seed lead 411.

Optionally, the thickness of the plated metal layer 430 is 1.5 to 20 micrometers, for example, it may be 2 micrometers, 5 micrometers, 10 micrometers, 20 micrometers, etc. Preferably, the thickness of the plated metal layer 430 is 5 to 10 μm.

Optionally, the thickness of the plated metal layer 430 is greater than the thickness of the conductive seed layer 410, so as to ensure that the thickness of the first lead 2011 is greater than the thickness of the conductive seed layer 410, thereby achieving the purpose of increasing the thickness of the first lead 2011.

Alternatively, the material of the plated metal layer 430 may be copper through a copper electroplating process. Thus, the resistance of the growth wire 432 can be reduced, and the resistance of the first wire 2011 can be reduced. Further, the conductive seed layer 410 is far away from the surface of the substrate 100 and includes at least one copper metal layer, so as to ensure that the copper electroplating metal layer 430 can be smoothly grown on the surface of the conductive seed layer 410 in the electroplating process.

In step S250, as shown in fig. 9, a portion of the conductive seed layer 410 not covered by the electroplated metal layer 430 may be removed by etching. Alternatively, a suitable etching process may be selected according to the thickness and material of the conductive seed layer 410, including selecting a suitable etching solution, etching time, and the like, so as to etch the exposed portion of the conductive seed layer 410 clean.

When the conductive seed layer 410 is etched, a special protection of the plated metal layer 430 may not be required. In this manner, the surface of each precursor growth lead 431 of the plated metal layer 430 is partially etched in the etching process, and the remaining portion forms a growth lead 432 of the first lead 2011. In some embodiments, the plated metal layer 430 and the conductive seed layer 410 may be etched at a close rate, such that the first lead 2011 is formed to a thickness close to the thickness of the plated metal layer 430. For example, if the thickness of the plated metal layer 430 is 1.5 to 20 micrometers, the thickness of the first lead 2011 is 1.5 to 20 micrometers.

In some embodiments, the surface of the precursor growth lead 431 away from the substrate base plate 100 has a slightly rough surface, the convex portion of which is more easily etched by the etching solution, so that the flatness of the surface of the precursor growth lead 431 away from the substrate base plate 100 is continuously improved during the etching process. Moreover, since the plated metal layer 430 does not need to be protected, in the formed first lead 2011, the orthographic projection of the growth lead 432 on the substrate base plate 100 coincides with the orthographic projection of the seed lead 411 on the substrate base plate 100, so that the flatness of the side surface of the first lead 2011 is ensured, and the problem that the seed lead 411 protrudes out of the growth lead 432 is avoided. Therefore, the first leads 2011 have a higher flatness on the surface and the side surfaces, which can further improve the shape of the first leads 2011 and improve the performance of the array substrate.

Thus, with the array substrate manufacturing method provided by the present disclosure, as shown in fig. 1, fig. 2 and fig. 9, the manufactured array substrate includes a substrate 100, a driving circuit layer 200 and a functional device layer 300, which are sequentially stacked; the driving circuit layer 200 includes at least one first lead layer 201, and any one of the first lead layers 201 includes at least one first lead 2011; any one of the first leads 2011 includes a seed lead 411 disposed on one side of the substrate base 100, and a growth lead 432 disposed on a surface of the seed lead 411 away from the substrate base 100, and an orthographic projection of the growth lead 432 on the substrate base 100 coincides with an orthographic projection of the seed lead 411 on the substrate base 100.

In an embodiment of the present disclosure, as shown in fig. 4, the method for preparing an array substrate provided by the present disclosure may further include: an alignment mark layer 110 is formed on one side of the substrate 100, and the alignment mark layer 110 has an alignment pattern 111 for alignment. Then, a driving circuit layer 200 is formed on the side of the alignment mark layer 110 away from the substrate 100. Thus, the pattern of the first lead layer 201 can be avoided being used as the alignment pattern 111, so as to avoid the problem that the first lead layer 201 is too thick and the edge is not too clear.

Alternatively, the material of the alignment mark layer 110 may be metal, metal oxide, silicon or other materials, for example, the material of the alignment mark layer 110 may be metal such as molybdenum, titanium, copper, aluminum, tungsten, or the like, or may be metal oxide such as ITO (indium zinc oxide), and may also be material such as amorphous silicon, polysilicon, or the like. In one embodiment of the present disclosure, the material of the alignment mark layer 110 is molybdenum.

Optionally, a buffer layer 120 may be further disposed between the alignment mark layer 110 and the driving circuit layer 200, and the buffer layer 120 is made of an insulating material to isolate the alignment mark layer 110 from the driving circuit layer 200.

It is understood that when the structure of other film layers of the array substrate can be used as the alignment pattern, the alignment mark layer 110 may not be required. For example, if the driving circuit layer 200 is prepared to include an active driving circuit, the active layer pattern of the active driving circuit can be used as the alignment pattern 111.

In some embodiments, as shown in fig. 17, in preparing the driving circuit layer 200, a stacked two-layer first lead layer 201 connected by a via metal layer may also be prepared. As shown in fig. 11, forming at least one first lead layer 201 on one side of the base substrate 100 may include:

step S310, as shown in fig. 12, forming a first lead layer 201 on one side of the base substrate 100;

step S320, as shown in fig. 12, forming a first planarizing layer 241 on a side of the first lead layer 201 away from the base substrate 100, the first planarizing layer 241 exposing at least a portion of the first lead layer 201;

step S330, as shown in fig. 13, forming a first transition metal layer 261 on a side of the first planarization layer 241 away from the substrate base plate 100, the first transition metal layer 261 being connected to the first lead layer 201;

step S340, as shown in fig. 14, forming a second planarizing layer 242 on a side of the first transition metal layer 261 away from the substrate base plate 100, the second planarizing layer 242 having the first connection through hole 251; the first connection via 251 exposes a portion of the first transfer metal layer 261, and an orthographic projection of the first connection via 251 on the first lead layer 201 does not overlap with the first lead layer 201;

in step S350, as shown in fig. 15, another first lead layer 201 is formed on the surface of the second planarization layer 242 away from the substrate 100, and the another first lead layer 201 is connected to the first relay metal layer 261 through the first connecting via 251.

Thus, as shown in fig. 17, in the array substrate prepared according to the preparation method, the driving circuit layer 200 may include a first lead layer 201a, a first planarization layer 241, a first relay metal layer 261, a second planarization layer 242, and a second lead layer 201b, which are sequentially stacked, the first lead layer 201a and the second lead layer 201b forming a first lead layer group connected through the first relay metal layer 261. Wherein, the first lead layer 201a is disposed on one side of the substrate 100; the first planarization layer 241 is disposed on a side of the first lead layer 201a away from the substrate 100, and exposes at least a portion of the first lead layer 201 a; the first transition metal layer 261 is disposed on a side of the first planarization layer 241 away from the substrate base plate 100, and is connected to the previous first lead layer 201 a; the second planarization layer 242 is disposed on a side of the first transfer metal layer 261 away from the substrate base plate 100, and is provided with a first connection via hole 251; the first connection via 251 exposes a portion of the first transfer metal layer 261, and an orthographic projection of the first connection via 251 on the previous first lead layer 201a does not overlap with the previous first lead layer 201 a; the last first lead layer 201b is disposed on the surface of the second planarization layer 242 away from the substrate base plate 100, and is connected to the first transition metal layer 261 through the first connection via 251.

In step S310, a previous first lead layer 201a may be formed on one side of the base substrate 100 through steps S210 to S250.

In one embodiment of the present disclosure, before step S320, a first passivation layer may be further formed on the surface of the previous first lead layer 201a away from the substrate base plate 100, where the first passivation layer is used to protect the first lead 2011 from being corroded. Wherein the first passivation layer exposes at least a portion of the previous first lead layer 201a so that the previous first lead layer 201a can be electrically connected to the first transfer metal layer 261.

In step S320, as shown in fig. 12, a first planarization layer 241 may be formed on a side of the previous first lead layer 201a away from the substrate 100, and the first planarization layer 241 may fill up the gap between the respective first leads 2011 to provide a planarized surface for the first transition metal layer 261. The material of the first planarizing layer 241 may be an inorganic material, such as silicon oxide or silicon nitride, or an organic material, such as a resin material, e.g., epoxy resin or polyimide. In one embodiment of the present disclosure, the material of the first planarization layer 241 is a resin material.

In step S330, as shown in fig. 13, a first transition metal layer 261 may be formed on a side of the first planarization layer 241 away from the substrate base plate 100, where the first transition metal layer 261 is used to connect the previous first lead layer 201a and the next first lead layer 201 b.

Alternatively, a transfer metal material layer may be formed by a deposition method such as magnetron sputtering, and then a patterning operation may be performed on the transfer metal material layer to form the first transfer metal. The first transition metal layer may be a layer of conductive material or a stack of layers of conductive material. In one embodiment of the present disclosure, the first transition metal layer 261 may include a first conductive material layer, a second conductive material layer, and a first conductive material layer stacked in sequence, that is, in a sandwich structure. The first conductive material layer may be made of corrosion-resistant metal or alloy, such as molybdenum or titanium; the second conductive material layer may be made of a metal or an alloy having high conductivity, such as copper, aluminum, silver, or the like. For example, the first transition metal layer 261 may include a titanium metal layer, an aluminum metal layer, and a titanium metal layer, which are sequentially stacked, wherein the thickness of the titanium metal layer may be 400 to 600 angstroms, and the thickness of the aluminum metal layer may be 3500 to 5500 angstroms. In another embodiment of the present disclosure, the material of the first junction metal layer 261 may be the same as the material of the conductive seed layer 410. For example, the first transition metal layer 261 includes an MTD alloy layer and a copper layer stacked in sequence, the thickness of the MTD alloy layer is 250 to 350 angstroms, and the thickness of the copper layer is 2500 to 3500 angstroms.

In an embodiment of the present disclosure, if the surface of the first transition metal layer away from the substrate base plate 100 is made of a metal material that is easily corroded, such as copper or aluminum, before step S340, a second passivation layer may be further formed on the surface of the first transition metal layer 261 away from the substrate base plate 100, where the second passivation layer is used to protect the first transition metal layer 261 from corrosion. Wherein the second passivation layer exposes at least a portion of the first transfer metal layer 261 to enable the latter first lead layer 201b to be electrically connected with the first transfer metal layer 261.

In step S340, as shown in fig. 14, a second planarization layer 242 may be formed on a side of the first transition metal layer 261 remote from the substrate base plate 100. Alternatively, the material and the preparation method of the second planarizing layer 242 may be the same as or different from those of the first planarizing layer 241, and the disclosure does not limit this.

Wherein the second planarization layer 242 has a first connection through hole 251; the first connection via 251 exposes a portion of the first junction metal layer 261, and an orthographic projection of the first connection via 251 on the previous first lead layer 201a does not overlap the previous first lead layer 201 a. Thus, the first transition metal layer 261 includes at least a first connection region and a second connection region that do not overlap with each other, wherein the first connection region is electrically connected to the previous first lead layer 201a, and the second connection region is electrically connected to the next first lead layer 201 b. This arrangement can prevent irregularities of the previous first lead layer 201a from being transferred to the next first lead layer 201b, and can enable the next first lead layer 201b to have a good profile without deteriorating the profile under the influence of the previous first lead layer 201 a. In particular, this can avoid forming multiple thick metal layers at the same position, improve the stability of each first lead 2011 in the first lead layer 201, and improve the stress of the array substrate.

In step S350, as shown in fig. 15, a last first lead layer 201b may be formed on one side of the base substrate 100 through steps S210 to S250. In one embodiment of the present disclosure, a third passivation layer may be further formed on a surface of the last first lead layer 201b away from the substrate base plate 100, and the third passivation layer is used to protect the last first lead layer 201b from being corroded. Wherein the third passivation layer exposes at least a portion of the last first lead layer 201b, so that the last first lead layer 201b can be electrically connected with other structures of the array substrate.

It is understood that according to the method for manufacturing the array substrate provided by the present disclosure, in some embodiments, as shown in fig. 18, the array substrate may be formed to have a plurality of first lead layers 201, for example, three, four or five first lead layers 201. A first lead layer group may be formed between two adjacent first lead layers 201, a first lead layer 201 close to the substrate base plate 100 in the first lead layer group may be a previous first lead layer 201a, a first lead layer 201 far from the substrate base plate 100 in the first lead layer group may be a next first lead layer 201b, and the previous first lead layer 201a and the next first lead layer 201b may be electrically connected through a first transition metal layer 261 interposed between the two first lead layers 201. In one embodiment of the present disclosure, when a conductive lead layer is required to have a very thick thickness according to the performance requirements of the array substrate, in order to avoid the problem that the grown lead 432 is easily collapsed due to too thick grown lead 432 formed by one electroplating, each conductive lead layer may be divided into a plurality of first lead layers 201 stacked in sequence, and two adjacent first lead layers 201 are electrically connected through a first transition metal layer 261. Thus, the plurality of first lead layers 201 electrically connected to each other can be effectively equivalent to a required thick conductive lead layer, thereby improving the process feasibility and yield of the array substrate preparation.

In one embodiment of the present disclosure, as shown in fig. 19 and 20, the step S120 may include steps S410 to S450 to form the driving circuit layer 200, and make the driving circuit layer 200 have the driving transistor 210 and the first lead layer 201 connected to the driving transistor 210.

Step S410, a driving transistor 210 is formed on one side of the substrate 100, the driving transistor 210 includes a source-drain electrode layer composed of a source and a drain, and the source-drain electrode layer is located on the source-drain metal layer of the driving circuit layer.

Alternatively, the driving transistor 210 may be formed on one side of the substrate base plate 100 by:

step S411, forming an active layer, a gate insulating layer and a gate electrode layer on one side of the substrate 100 to form a semiconductor layer and a gate electrode of the driving transistor 210, wherein the semiconductor layer of the driving transistor 210 is located on the active layer and includes a channel region and a source contact region and a drain contact region located at both sides of the channel region; the grid electrode of the driving transistor is positioned on the grid electrode layer; the channel region of the semiconductor layer and the gate electrode are isolated by a gate insulating layer.

Step S412, forming an interlayer dielectric layer 220, wherein the active layer, the gate insulating layer and the gate layer are all located between the interlayer dielectric layer 220 and the substrate base plate 100; the interlayer dielectric layer 220 is provided with a second connection via 252, the second connection via 252 exposing the source and drain contact regions.

Step S413, forming a source-drain metal layer 230 on the side of the interlayer dielectric layer 220 away from the substrate base plate 100, where the source-drain metal layer 230 is formed with a source and a drain of the driving transistor, and the source and the drain form the source-drain metal layer of the driving transistor; wherein the source is connected to the source contact region through a second connecting via 252 and the drain is connected to the drain contact region through a second connecting via 252.

Alternatively, the material and thickness of the source-drain metal layer 230 may be the same as or different from those of the first junction metal layer 261.

Optionally, after the source-drain metal layer 230 is formed, a passivation layer may be further formed on the surface of the source-drain metal layer 230 away from the substrate 100. It is understood that the passivation layer exposes at least a portion of the source drain metal layer 230 to enable the source drain metal layer 230 to be electrically connected with other conductive structures of the driving circuit layer 200.

In step S420, a third planarization layer 243 is formed on the side of the driving transistor 210 away from the substrate 100, and the third planarization layer 243 is provided with a third connection via 253 exposing at least a portion of the source-drain electrode layer.

Alternatively, the material of the third planarization layer 243 may be the same as or different from that of the first planarization layer 241.

Optionally, an orthographic projection of the third connecting via 253 on the substrate base plate 100 does not overlap with an orthographic projection of the second connecting via 252 on the substrate base plate 100. In this way, the third connection via 253 may expose a planar surface of the source and drain metal layer 230, which is beneficial to improving the connection strength between the exposed source and drain metal layer 230 and other conductive structures of the driving circuit.

In step S430, a second via metal layer 262 is formed on the third planarization layer 243 at a side away from the substrate base plate 100, and the second via metal layer 262 is connected to the source-drain metal layer 230 through the third connecting via 253.

Alternatively, the material and thickness of the second transition metal layer 262 may be the same as or different from those of the first transition metal layer 261.

Step S440, forming a fourth planarization layer 244 on the second transition metal layer 262 at a side away from the substrate base plate 100, wherein the fourth planarization layer 244 has a fourth connecting via 254; the fourth connection via 254 exposes a portion of the second relay metal layer 262, and an orthographic projection of the fourth connection via 254 on the substrate base 100 does not overlap with an orthographic projection of the third connection via 253 on the substrate base 100.

In this way, the second via metal layer 262 at least includes a third connection region and a fourth connection region that are not overlapped with each other, wherein the third connection region is electrically connected to the source-drain metal layer 230, and the fourth connection region is electrically connected to the first lead layer 201. The arrangement method can prevent the unevenness of the source-drain metal layer 230 from being transmitted to the first lead layer 201, so that the first lead layer 201 can have good appearance without appearance deterioration under the influence of the source-drain metal layer 230.

Alternatively, the material of the fourth planarization layer 244 may be the same as or different from that of the first planarization layer 241.

In step S450, a first lead layer 201 is formed on the surface of the fourth planarization layer 244 away from the substrate base plate 100, and the first lead layer 201 is connected to the second via metal layer 262 through the fourth connecting via 254. The first lead layer 201 may be formed in the method shown in steps S210 to S250.

Thus, according to the method for fabricating an array substrate described in this embodiment, as shown in fig. 20, the fabricated driving circuit layer 200 may include a driving transistor 210, a third planarizing layer 243, a second via metal layer 262, a fourth planarizing layer 244, and a first lead layer 201, which are sequentially stacked.

Wherein the content of the first and second substances,

the driving transistor 210 is disposed on one side of the substrate 100, and the driving transistor 210 includes a source-drain electrode layer composed of a source and a drain; the third planarization layer 243 is disposed on a side of the driving transistor 210 away from the substrate 100, and is provided with a third connection via 253 exposing at least a portion of the source-drain electrode layer; the second transition metal layer 262 is disposed on a side of the third planarization layer 243 away from the substrate base plate 100, and is connected to the source/drain electrode layer through the third connection via 253; the fourth planarization layer 244 is disposed on the second transition metal layer 262 at a side away from the substrate base plate 100 and has a fourth connecting via 254; the fourth connection via 254 exposes a portion of the second relay metal layer 262, and an orthographic projection of the fourth connection via 254 on the substrate base 100 does not overlap with an orthographic projection of the third connection via 253 on the substrate base 100; the first lead layer 201 is disposed on the surface of the fourth planarization layer 244 away from the substrate base plate 100, and is connected to the second via metal layer 262 through the fourth connecting via 254.

In another embodiment of the present disclosure, as shown in fig. 21 and 22, the step S120 may include steps S510 to S530 to form the driving circuit layer 200, and make the driving circuit layer 200 have the driving transistor 210 and the first lead layer 201 connected to the driving transistor 210.

Step S510 is to form a driving transistor 210 on one side of the substrate 100, where the driving transistor 210 includes a source-drain electrode layer composed of a source and a drain, and the source-drain electrode layer is located on a source-drain metal layer of the driving circuit layer.

In step S520, a third planarization layer 243 is formed on the side of the driving transistor 210 away from the substrate 100, and the third planarization layer 243 is provided with a third connection via 253 exposing at least a portion of the source-drain electrode layer.

Optionally, an orthographic projection of the third connecting via 253 on the substrate base plate 100 does not overlap with an orthographic projection of the second connecting via 252 on the substrate base plate 100.

Alternatively, step S510 to step S520 may be implemented with reference to the preparation method shown in step S410 to step S420.

In step S530, a first lead layer 201 is formed on the surface of the third planarization layer 243 away from the substrate base plate 100, and the first lead layer 201 is connected to the source/drain electrode layer through the third connection via 253. The first lead layer 201 may be formed in the method shown in steps S210 to S250.

Thus, according to the method for manufacturing an array substrate described in this embodiment, as shown in fig. 22, the manufactured driving circuit layer 200 may include the driving transistor 210, the third planarizing layer 243, and the first lead layer 201, which are sequentially stacked. Wherein the content of the first and second substances,

the driving transistor 210 is arranged on one side of the substrate, and the driving transistor 210 comprises a source drain electrode layer consisting of a source electrode and a drain electrode; the third planarization layer 243 is disposed on a side of the source/drain electrode layer away from the substrate base plate 100, and is provided with a third connection via 253 exposing at least a portion of the source/drain electrode layer; a first lead layer 201 is disposed on the surface of the third planarization layer 243 away from the substrate 100, and is connected to the source/drain electrode layer through the third via 253.

According to the array substrate prepared by the embodiment, the source drain metal layer 230 can be reused as the second via metal layer 262, so that the second via metal layer 262 and the fourth planarization layer 244 do not need to be prepared, two patterning processes can be reduced in process, related materials can be saved, and two film layers can be reduced in the formed array substrate. Thus, the manufacturing method of the embodiment can reduce the manufacturing cost of the array substrate and improve the manufacturing efficiency, and can make the array substrate have a smaller thickness.

In another embodiment of the present disclosure, as shown in fig. 23 and 24, the step S120 may include steps S610 to S630 to form the driving circuit layer 200, and make the driving circuit layer 200 have the driving transistor 210 and the first lead layer 201 connected to the driving transistor 210.

Step S610, forming an active layer, a gate insulating layer and a gate electrode layer on one side of the substrate 100 to form a semiconductor layer and a gate electrode of the driving transistor 210, wherein the semiconductor layer of the driving transistor 210 is located on the active layer and includes a channel region and a source contact region and a drain contact region located at both sides of the channel region; the gate of the driving transistor 210 is located in the gate layer; the channel region of the semiconductor layer is isolated from the grid electrode through the grid electrode insulating layer;

step S620, forming an interlayer dielectric layer 220, wherein the active layer, the gate insulating layer and the gate layer are all located between the interlayer dielectric layer 220 and the substrate base plate 100; the interlayer dielectric layer 220 is provided with a second connection via 252, the second connection via 252 exposing the source and drain contact regions;

in step S630, a first lead layer 201 is formed on the interlayer dielectric layer 220 at a side away from the substrate 100, the first lead layer 201 has a source and a drain, the source is connected to the source contact region through the second connection via 252, and the drain is connected to the drain contact region through the second connection via 252.

Thus, according to the method of manufacturing an array substrate described in this embodiment, as shown in fig. 24, the manufactured driving circuit layer 200 may include a driving transistor including a semiconductor layer, an interlayer dielectric layer, and a first lead layer; the semiconductor layer is arranged on one side of the substrate base plate; the semiconductor layer comprises a source contact region and a drain contact region; the interlayer dielectric layer is arranged on one side of the semiconductor layer far away from the substrate; the first lead layer is arranged on one side, far away from the substrate, of the interlayer dielectric layer and is provided with a source electrode and a drain electrode; the source electrode is connected with the source electrode contact region, and the drain electrode is connected with the drain electrode contact region.

According to the array substrate prepared by the embodiment, the first lead layer 201 can be reused as the source-drain metal layer 230, so that the patterning process and film layer materials in the preparation process of the array substrate can be further reduced, the preparation cost of the array substrate is reduced, and the thickness of the array substrate is further reduced.

In step S130, a functional device layer 300 may be formed on a side of the driving circuit layer 200 away from the substrate 100. The functional device layer 300 may contain an array of distributed functional devices 310, including, for example, light emitting devices for emitting light, ultrasonic emitting devices for emitting ultrasonic waves, heating devices for generating heat, or other current driven functional devices 310.

Alternatively, the driving circuit layer 200 may include an electrode layer, and the respective functional devices 310 may be electrically connected to the electrode layer. The electrode layer may be the first lead layer 201 or the second lead layer 202, which is not limited in this disclosure. Further, the connection electrode layer may include a first electrode and a second electrode disposed adjacently, a first end of the functional device 310 may be electrically connected to the first electrode, and a second end of the functional device 310 may be electrically connected to the second electrode. In this manner, a driving current may flow through functional device 310 through the first electrode and the second electrode, so that functional device 310 operates.

In some embodiments, as shown in fig. 16 and 17, a pixel defining layer 271 may be formed on a side of the driving circuit layer away from the substrate, and then a conductive adhesive 272 may be coated in an area defined by the pixel defining layer 271, and the functional device 310 may be electrically connected to the electrode layer through the conductive adhesive 272.

Illustratively, the functional device 310 may be an LED, a Mini LED, or a Micro LED, which may be connected to the electrode layer by solder paste.

Optionally, the method for preparing the array substrate of the present disclosure may further include:

preparing fan-out leads on the side surface of the substrate base plate 100, wherein the fan-out leads are electrically connected with the driving circuit layer 200;

a bonding layer is prepared on one side of the substrate 100 away from the driving circuit layer 200, the bonding layer has a plurality of bonding pads, and each bonding pad is electrically connected with the driving circuit layer 200 through a fan-out lead.

Thus, the prepared array substrate may include the substrate 100, the driving circuit layer 200, and the functional device layer 300, which are sequentially stacked, and a bonding layer on a side of the substrate 100 away from the driving circuit layer 200, and fan-out leads on sides of the substrate 100. Therefore, the array substrate can have a smaller edge, a plurality of different array substrates can be conveniently spliced to form a larger substrate, and the larger substrate has a smaller splicing seam.

For example, when the functional device 310 is a Micro LED, a plurality of different small-sized array substrates may be spliced to form a large-sized display screen, and the spliced size of the display screen may be very small, so as to achieve a good display effect. The driving circuits of the array substrates, such as the driving circuit board and the driving chip disposed on the driving circuit board, may be electrically connected through the bonding pads to implement driving of the array substrates.

In one embodiment of the present disclosure, as shown in fig. 25, the bonding layer may include a backside lead layer 610, an insulating layer 620, and a bonding pad layer 630 sequentially stacked on a surface of the substrate 100 away from the driving circuit layer 200, the backside lead layer 610 may be electrically connected to a fan-out lead (not shown in fig. 25), and the insulating layer 620 exposes a portion of the backside lead layer 610, so that the bonding pad layer 630 may be electrically connected to the backside lead layer 610.

Optionally, the backside lead layer 610 may further be provided with a backside alignment pattern, and the material of the backside alignment pattern may be the same as or different from that of the backside lead layer 610. Illustratively, the material of the backside alignment pattern and the bonding pad layer 630 is ITO.

It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc., are all considered part of this disclosure.

The embodiment of the present disclosure also provides an array substrate, as shown in fig. 1 and fig. 2, the array substrate includes a substrate 100, a driving circuit layer 200, and a functional device layer 300, which are sequentially stacked;

the driving circuit layer 200 includes at least one first lead layer 201, and any one of the first lead layers 201 includes at least one first lead 2011; any one of the first leads 2011 includes a seed lead 411 disposed on one side of the substrate base 100, and a growth lead 432 disposed on a surface of the seed lead 411 away from the substrate base 100, and an orthographic projection of the growth lead 432 on the substrate base 100 coincides with an orthographic projection of the seed lead 411 on the substrate base 100.

The array substrate provided by the present disclosure may be prepared by any one of the preparation methods described in the above embodiment of the preparation method of the array substrate, and therefore, the array substrate has the same or similar technical effects, and the details of the present disclosure are not repeated herein.

In one embodiment of the present disclosure, the thickness of the first lead 2011 is not greater than 5 times the width of the seed lead 411.

In one embodiment of the present disclosure, the thickness of the first lead 2011 is 1.5 to 20 micrometers.

In one embodiment of the present disclosure, the width of the end of the first lead 2011 away from the substrate base plate 100 is smaller than the width of the end of the first lead 2011 close to the substrate base plate 100.

In one embodiment of the present disclosure, as shown in fig. 17 and 18, the driving circuit layer 200 includes:

a first lead layer 201a disposed on one side of the substrate 100;

a first planarization layer 241 disposed on a side of the first lead layer 201a away from the base substrate 100 and exposing at least a portion of the first lead layer 201 a;

a first transition metal layer 261 provided on a side of the first planarization layer 241 remote from the substrate base plate 100 and connected to the first lead layer 201 a;

a second planarization layer 242 provided on a side of the first transfer metal layer 261 remote from the substrate base 100 and provided with a first connection via hole 251; the first connection via 251 exposes a portion of the first transfer metal layer 261, and an orthographic projection of the first connection via 251 on the first lead layer 201a does not overlap the first lead layer 201 a;

another first lead layer 201b is disposed on the surface of the second planarization layer 242 away from the substrate base plate 100, and is connected to the first transition metal layer 261 through the first connecting via 251.

In other words, the driving circuit layer 200 includes at least one first lead layer group, and any one of the first lead layer groups includes:

a front first lead layer 201a disposed on one side of the base substrate 100;

a first planarization layer 241, disposed on a side of the first lead layer 201a away from the substrate 100, and exposing at least a portion of the first lead layer 201 a;

a first transition metal layer 261 disposed on a side of the first planarization layer 241 away from the substrate base plate 100 and connected to the previous first lead layer 201 a;

a second planarization layer 242 provided on a side of the first transfer metal layer 261 remote from the substrate base 100 and provided with a first connection via hole 251; the first connection via 251 exposes a portion of the first transfer metal layer 261, and an orthographic projection of the first connection via 251 on the previous first lead layer 201a does not overlap with the previous first lead layer 201 a;

the last first lead layer 201b is disposed on the surface of the second planarization layer 242 away from the substrate 100, and is connected to the first transition metal layer 261 through the first connecting via 251.

In one embodiment of the present disclosure, as shown in fig. 20, the driving circuit layer 200 includes:

a driving transistor 210 disposed at one side of the substrate 100, the driving transistor 210 including a source-drain electrode layer composed of a source and a drain;

a third planarization layer 243, disposed on a side of the source/drain electrode layer away from the substrate 100, and provided with a third connection via 253 exposing at least a portion of the source/drain electrode layer;

the second transition metal layer 262 is arranged on one side of the third planarization layer 243 far away from the substrate base plate 100 and is connected with the source/drain electrode layer through the third connection via 253;

a fourth planarization layer 244 disposed on a side of the second transition metal layer 262 away from the substrate base plate 100 and having a fourth connecting via 254; the fourth connection via 254 exposes a portion of the second relay metal layer 262, and an orthographic projection of the fourth connection via 254 on the substrate base 100 does not overlap with an orthographic projection of the third connection via 253 on the substrate base 100;

a first lead layer 201 disposed on the surface of the fourth planarization layer 244 away from the substrate base plate 100 and connected to the second via metal layer 262 through the fourth connecting via 254.

In one embodiment of the present disclosure, as shown in fig. 22, the driving circuit layer 200 includes:

a driving transistor 210 disposed on one side of the substrate 100, the driving transistor 210 including a source/drain electrode layer including a source and a drain;

a third planarization layer 243, disposed on a side of the source/drain electrode layer away from the substrate 100, and provided with a third connection via 253 exposing at least a portion of the source/drain electrode layer;

a first lead layer 201 disposed on the surface of the third planarization layer 243 away from the substrate 100 and connected to the source/drain electrode layer through the third via 253.

In one embodiment of the present disclosure, as shown in fig. 24, the driving circuit layer 200 includes a driving transistor including:

a semiconductor layer provided on one side of the base substrate 100; the semiconductor layer comprises a source contact region and a drain contact region;

an interlayer dielectric layer 220 provided on a side of the semiconductor layer away from the base substrate 100;

the first lead layer 201 is arranged on one side of the interlayer dielectric layer 220 far away from the substrate and is provided with a source electrode and a drain electrode; the source electrode is connected with the source electrode contact region, and the drain electrode is connected with the drain electrode contact region.

Other details and possible variations of the array substrate provided by the present disclosure are described in detail in the above embodiment of the method for manufacturing the array substrate, and the present disclosure is not repeated herein.

It is to be understood that the disclosure is not limited in its application to the details of construction and the arrangements of the components set forth in the specification. The present disclosure is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications are within the scope of the present disclosure. It should be understood that the disclosure disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present disclosure. The embodiments of this specification illustrate the best mode known for carrying out the disclosure and will enable those skilled in the art to utilize the disclosure.