阅读说明：本技术 显示面板及电子装置 (Display panel and electronic device ) 是由 罗浩俊 康佳昊 袁泽 于 2020-06-15 设计创作，主要内容包括：本发明提供了一种显示面板(10),包括衬底(100)、第一薄膜晶体管(200)、第二薄膜晶体管(300)以及非晶金属层(400),衬底(100)覆盖第一薄膜晶体管区(11)和第二薄膜晶体管区(12)；第一薄膜晶体管(200)位于第一薄膜晶体管区(11),包括第一有源层(210)；第二薄膜晶体管(300)位于第二薄膜晶体管区(12),包括第二有源层(310),第二有源层(310)与第一有源层(210)的材质不同；非晶金属层(400)设置在第一薄膜晶体管区(11)和第二薄膜晶体管区(12)的至少一个中。本发明还提供一种电子装置。本发明提供的显示面板在第一薄膜晶体管区和第二薄膜晶体管区的至少一个中设置具有较高平整度的非晶金属层,以提高显示面板的平整度。(The invention provides a display panel (10), which comprises a substrate (100), a first thin film transistor (200), a second thin film transistor (300) and an amorphous metal layer (400), wherein the substrate (100) covers a first thin film transistor area (11) and a second thin film transistor area (12); the first thin film transistor (200) is positioned in the first thin film transistor area (11) and comprises a first active layer (210); the second thin film transistor (300) is positioned in the second thin film transistor area (12) and comprises a second active layer (310), and the material of the second active layer (310) is different from that of the first active layer (210); an amorphous metal layer (400) is provided in at least one of the first thin film transistor region (11) and the second thin film transistor region (12). The invention also provides an electronic device. According to the display panel provided by the invention, the amorphous metal layer with higher flatness is arranged in at least one of the first thin film transistor area and the second thin film transistor area so as to improve the flatness of the display panel.)

1. A display panel comprising a first thin film transistor region and a second thin film transistor region, the display panel comprising:

the substrate covers the first thin film transistor area and the second thin film transistor area, and the first thin film transistor area and the second thin film transistor area are arranged on the same side of the substrate;

a first thin film transistor, located in the first thin film transistor region, including a first active layer;

the second thin film transistor is positioned in the second thin film transistor area and comprises a second active layer, and the material of the second active layer is different from that of the first active layer;

and the amorphous metal layer is arranged in at least one of the first thin film transistor area and the second thin film transistor area.

2. The display panel according to claim 1, wherein a diameter of the crystal grains in the amorphous metal layer is less than or equal to 20 nm.

3. The display panel according to claim 1, wherein the amorphous metal layer is located in the first thin film transistor region to constitute a first gate electrode of the first thin film transistor; the first active layer is arranged on one side, far away from the substrate, of the first grid electrode.

4. The display panel of claim 3, wherein the display panel further comprises:

the first insulating layer covers the first thin film transistor region and the second thin film transistor region, and is arranged on one side, far away from the substrate, of the first grid electrode in the first thin film transistor region; the first active layer is arranged on one side, far away from the first grid electrode, of the first insulating layer and is positioned in the first thin film transistor area;

and the protective layer covers the first thin film transistor area and the second thin film transistor area, and is arranged on one side, far away from the first insulating layer, of the first active layer in the first thin film transistor area.

5. The display panel of claim 4, wherein the display panel further comprises:

a first buffer layer disposed at one side of the substrate and covering the first thin film transistor region and the second thin film transistor region;

the interlayer dielectric layer covers the first thin film transistor region and the second thin film transistor region, the interlayer dielectric layer is arranged on one side, far away from the substrate, of the first buffer layer in the first thin film transistor region, and the first grid electrode is arranged on one side, far away from the first buffer layer, of the interlayer dielectric layer.

6. The display panel according to claim 4, wherein the first thin film transistor further comprises:

the first source electrode and the first drain electrode are respectively positioned in the two first through holes and connected with the first active layer, and part of the first source electrode and part of the first drain electrode are positioned on the surface of the protective layer far away from the first active layer.

7. The display panel according to claim 1, wherein the amorphous metal layer is located in the first thin film transistor region to constitute a light shielding layer of the first thin film transistor, the amorphous metal layer is disposed on a side of the substrate, the first active layer is disposed on a side of the amorphous metal layer away from the substrate, and the first thin film transistor further includes a first gate electrode disposed on a side of the first active layer away from the amorphous metal layer and located in the first thin film transistor region.

8. The display panel of claim 7, wherein the display panel further comprises:

the second buffer layer at least covers the first thin film transistor area, and is arranged on one side, far away from the substrate, of the amorphous metal layer in the first thin film transistor area; the first active layer is arranged on one side, far away from the amorphous metal layer, of the second buffer layer and is positioned in the first thin film transistor area;

the first insulating layer covers the first thin film transistor region and the second thin film transistor region, the first insulating layer is arranged on one side, far away from the second buffer layer, of the first active layer in the first thin film transistor region, and the first grid electrode is arranged on one side, far away from the first active layer, of the first insulating layer.

9. The display panel of claim 8, wherein the display panel further comprises:

the protective layer is arranged on one side, far away from the first active layer, of the first grid electrode;

the first thin film transistor further includes:

the first thin film transistor comprises a first source electrode and a first drain electrode, wherein in the first thin film transistor region, two second through holes penetrating through two opposite surfaces of the protective layer and the first insulating layer are arranged in the protective layer and the first insulating layer so as to expose part of a first active layer, the second source electrode and the second drain electrode are respectively positioned in the two second through holes and are connected with the first active layer, and part of the second source electrode and part of the second drain electrode are positioned on the surface of the protective layer, which is far away from the first active layer.

10. The display panel according to claim 9, wherein the first thin film transistor further comprises:

and the first connecting piece is arranged in the first thin film transistor area, a third through hole penetrating through two opposite surfaces of the protective layer is formed in the protective layer so as to expose part of the first grid electrode, and the first connecting piece is positioned in the third through hole and is connected with the first grid electrode.

11. The display panel according to claim 3, wherein the amorphous metal layer is located in the first thin film transistor region, and the first thin film transistor is electrically connected to the second thin film transistor through the amorphous metal layer.

12. The display panel according to claim 11, wherein the second active layer is disposed on one side of the substrate and in the second thin film transistor region; the second thin film transistor further comprises a second grid electrode, and the second grid electrode is arranged on one side, far away from the substrate, of the second active layer.

13. The display panel according to claim 12, wherein the display panel further comprises a second insulating layer and an interlayer dielectric layer, and the second thin film transistor further comprises a second source electrode and a second drain electrode;

the second insulating layer is arranged on the surface of the second active layer far away from the substrate;

the second grid electrode is arranged on the surface of the second insulating layer far away from the second active layer;

the interlayer dielectric layer covers the first thin film transistor region and the second thin film transistor region, is positioned on one side of the second active layer far away from the substrate in the second thin film transistor region, and covers the second grid electrode and the second insulating layer;

in the second thin film transistor region, two fourth through holes penetrating through two opposite surfaces of the interlayer dielectric layer are formed in the interlayer dielectric layer to expose a part of the second active layer, the two fourth through holes are respectively located on two sides of the second gate and the second insulating layer, and the second source electrode and the second drain electrode are respectively located in the two fourth through holes;

the amorphous metal layer is connected to one of the second source electrode and the second drain electrode adjacent to the amorphous metal layer.

14. The display panel according to claim 6 or 9, wherein the display panel further comprises:

the flat layer is arranged on one layer of the protective layer far away from the first active layer and covers the first source electrode and the first drain electrode;

a pixel defining layer disposed on a side of the planarization layer away from the protective layer.

15. The display panel according to claim 1, wherein the amorphous metal layer is provided at least in the second thin film transistor region, and the amorphous metal layer is provided on one side of the substrate, the display panel further comprising:

the second buffer layer is arranged on one side, far away from the substrate, of the amorphous metal layer, and the first thin film transistor and the second thin film transistor are arranged on one side, far away from the amorphous metal layer, of the second buffer layer.

16. The display panel according to claim 4, wherein the protective layer includes a first sub-protective layer and a second sub-protective layer, the first sub-protective layer being disposed on a side of the first active layer away from the first insulating layer, the second sub-protective layer being disposed on a side of the first sub-protective layer away from the first active layer in the first thin film transistor region;

the first sub-protection layer is an inorganic protection layer, and the second sub-protection layer is an organic protection layer.

17. The display panel of claim 1, wherein the first active layer is a metal oxide layer and the second active layer is a polysilicon layer.

18. The display panel according to claim 1, wherein the amorphous metal layer includes a first sub amorphous metal layer and a first sub metal layer which are stacked;

or the amorphous metal layer comprises a first sub amorphous metal layer, a first sub metal layer and a second sub amorphous metal layer, and the first sub metal layer is positioned between the first sub amorphous metal layer and the second sub amorphous metal layer;

or the amorphous metal layer comprises a first sub-metal layer, a first sub-amorphous metal layer and a second sub-metal layer, and the first sub-amorphous metal layer is located between the first sub-metal layer and the second sub-metal layer.

19. The display panel according to claim 1, wherein one of the first thin film transistor and the second thin film transistor is a switching transistor, and the other is a driving transistor.

20. The display panel according to claim 1, wherein the display panel further comprises a light emitting element, and one of the first thin film transistor and the second thin film transistor is connected to the light emitting element to drive the light emitting element to emit light.

21. An electronic device, characterized in that the electronic device comprises a display panel according to any one of claims 1-20.

Technical Field

The invention relates to the technical field of display, in particular to a display panel and an electronic device.

Background

The driving circuit in the existing display screen adopts a polysilicon thin film transistor or a piece oxide thin film transistor. The driving circuit composed of the polysilicon thin film transistor has high electron mobility and high driving current ratio, but the polysilicon thin film transistor has high leakage current, while the metal oxide thin film transistor has very low leakage current, but generally the electron mobility is relatively low and the driving current ratio is low. Moreover, most of metal elements related in the current thin film transistor circuit are made of conventional metals, and the surface roughness of the conventional metals is high, so that the surface flatness of the thin film transistor is reduced, and the surface flatness of the display screen is influenced.

Disclosure of Invention

The present disclosure is directed to solving at least one of the problems in the prior art. To this end, in a first aspect of the present application, there is provided a display panel including a first thin film transistor region and a second thin film transistor region, the display panel including:

the substrate covers the first thin film transistor area and the second thin film transistor area, and the first thin film transistor area and the second thin film transistor area are arranged on the same side of the substrate;

a first thin film transistor, located in the first thin film transistor region, including a first active layer;

the second thin film transistor is positioned in the second thin film transistor area and comprises a second active layer, and the material of the second active layer is different from that of the first active layer;

and the amorphous metal layer is arranged in at least one of the first thin film transistor area and the second thin film transistor area.

In a second aspect of the present application, an electronic device is provided, which includes the display panel as described above.

The invention has the beneficial effects that: according to the display panel provided by the invention, the amorphous metal layer with higher flatness is arranged in at least one of the first thin film transistor area and the second thin film transistor area so as to improve the flatness of the display panel.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.

Fig. 1 is a schematic structural diagram of a display panel according to a first embodiment of the present invention.

Fig. 2 is a schematic structural diagram of an amorphous metal layer according to the present invention.

Fig. 3 is a schematic structural diagram of another amorphous metal layer provided by the present invention.

Fig. 4 is a schematic structural diagram of another amorphous metal layer provided in the present invention.

Fig. 5 is a schematic structural diagram of a display panel according to a second embodiment of the present invention.

Fig. 6 is a schematic structural diagram of a display panel according to a third embodiment of the present invention.

Fig. 7 is a schematic structural diagram of a display panel according to a fourth embodiment of the present invention.

Fig. 8 is a schematic structural diagram of a display panel according to a fifth embodiment of the present invention.

Fig. 9 is a schematic structural diagram of an electronic device according to the present invention.

Detailed Description

While the following is a description of the preferred embodiments of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.

The terms "first," "second," and the like in the description and in the claims, and in the drawings, are used for distinguishing between different objects and not necessarily for describing a particular sequential order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

Referring to fig. 1, a display panel 10 according to a first embodiment of the present invention includes a first thin film transistor region 11 and a second thin film transistor region 12, wherein the first thin film transistor region 11 and the second thin film transistor region 12 may be two adjacent regions, or two spaced regions, or two regions stacked up and down, and in this embodiment, the first thin film transistor region 11 and the second thin film transistor region 12 are adjacent. The display panel 10 includes a substrate 100, a first thin film transistor 200, a second thin film transistor 300, and an amorphous metal layer 400, wherein the substrate 100 covers a first thin film transistor region 11 and a second thin film transistor region 12, and the first thin film transistor region 11 and the second thin film transistor region 12 are disposed on the same side of the substrate 100; the first thin film transistor 200 is located in the first thin film transistor region 11, and includes a first active layer 210; the second thin film transistor 300 is located in the second thin film transistor region 12, and includes a second active layer 310, wherein the second active layer 310 is made of a different material than the first active layer 210; the amorphous metal layer 400 is disposed in at least one of the first thin film transistor region 11 and the second thin film transistor region 12.

The amorphous metal layer 400 includes an amorphous metal, which is a metal material with disordered structure on an atomic scale, and is also called as metallic glass or glassy metal. The amorphous metal layer 400 has a higher flatness than a conventional metal layer, and the amorphous metal layer 400 is disposed in at least one of the first thin film transistor region 11 and the second thin film transistor region 12, so that the flatness of the layer where the amorphous metal layer 400 is located can be improved, and the flatness of other film layers formed on the amorphous metal layer 400 can be further improved, thereby improving the flatness of the display panel 10.

In the display panel 10 of the present invention, the amorphous metal layer 400 having a higher flatness is disposed in at least one of the first tft area 11 and the second tft area 12, so as to improve the flatness of the display panel 10.

In a further embodiment, the diameter of the grains in the amorphous metal layer 400 is less than or equal to 20 nm. The conventional metal layer is obtained by cooling and crystallizing liquid metal, and atoms are arranged in a regular form to form crystal grains with larger diameters. In this embodiment, the diameter of the crystal grains in the amorphous metal layer 400 is preferably less than or equal to 20nm, and in the amorphous metal layer 400, the smaller the diameter of the crystal grains is, the more irregular the crystal grains of the amorphous metal layer 400 are, so that the crystal grains close to the surface tend to be flat during the process of forming the amorphous metal layer 400 by cooling the amorphous metal material. In other words, the smaller the grain diameter, the more irregular the grain, and the more easily the molten amorphous metal material forms a highly planar surface upon leveling and cooling.

In a further embodiment, the amorphous metal layer 400 is located in the first tft region 11 to form the first gate 220 of the first tft 200; the first active layer 210 is disposed on a side of the first gate electrode 220 away from the substrate 100. That is, in the present embodiment, the amorphous metal layer 400 is present in the first tft region 11 as the first gate 220, and the amorphous metal layer 400 is used as the first gate 220, which has higher flatness compared to the conventional metal used as the first gate 220, thereby improving the flatness of the first tft 200. Also, in the present embodiment, the first thin film transistor 200 is a bottom gate structure, and the first gate electrode 220 is disposed under the first active layer 210. In other embodiments, the first thin film transistor 200 may also be a top gate structure.

In a further embodiment, the first active layer 210 is a metal oxide layer and the second active layer 310 is a polysilicon layer. Further, the metal oxide layer is a low-temperature semiconductor and includes at least one of indium gallium zinc oxide, zinc tin oxide, zinc oxide, indium gallium zinc tin oxide, indium zinc tin oxide, indium gallium aluminum zinc oxide, and indium gallium zinc zirconium oxide. Wherein the first thin film transistor 200 may be an n-type or p-type transistor, and the second thin film transistor 300 may be an n-type or p-type transistor.

In the present embodiment, the two thin film transistors 200 are combined to make the thin film transistor circuit in the display panel 10 have both a large driving current and a low leakage current, so as to provide the comprehensive electrical performance of the thin film transistor circuit in the display panel 10.

When the second active layer 310 in the second thin film transistor 300 is a polysilicon layer, the first thin film transistor 200 is a top gate structure, that is, the distance between the first active layer 210 and the second active layer 310 is relatively short, and at this time, hydrogen ions in the polysilicon layer in the second active layer 310 will migrate into the first thin film transistor 200 to affect the performance of the metal oxide in the first active layer 210. In the present embodiment, by using the amorphous metal layer 400 as the first gate electrode 220 and setting the first thin film transistor 200 as the bottom gate structure, the amorphous metal layer 400 can effectively prevent hydrogen ions in the polysilicon layer in the second active layer 310 from entering the first active layer 210 in the first thin film transistor 200 and affecting the performance of the metal oxide.

In a further embodiment, one of the first thin film transistor 200 and the second thin film transistor 300 is a switching transistor, and the other is a driving transistor.

In a further embodiment, the display panel 10 further includes a light emitting element (not shown), and one of the first thin film transistor 200 and the second thin film transistor 300 is connected to the light emitting element to drive the light emitting element to emit light.

Here, the first thin film transistor 200 and the second thin film transistor 300 in the present application may be two thin film transistors in a pixel circuit or an address driving circuit.

Referring to fig. 2 to 4, in a further embodiment, the amorphous metal layer 400 includes a first sub-amorphous metal layer 410 and a first sub-metal layer 420 (shown in fig. 2) stacked on each other. Wherein the first sub-amorphous metal layer 410 includes an amorphous metal material, or the first sub-amorphous metal layer 410 is made of an amorphous metal material, and the first sub-metal layer 420 is made of a general metal material.

Alternatively, the amorphous metal layer 400 includes a first sub-amorphous metal layer 410, a first sub-metal layer 420, and a second sub-amorphous metal layer 430, and the first sub-metal layer 420 is located between the first sub-amorphous metal layer 410 and the second sub-amorphous metal layer 430 (as shown in fig. 3). The first sub-amorphous metal layer 410 and the second sub-amorphous metal layer 430 include an amorphous metal material.

Alternatively, the amorphous metal layer 400 includes a first sub-metal layer 420, a first sub-amorphous metal layer 410, and a second sub-metal layer 440, and the first sub-amorphous metal layer 410 is located between the first sub-metal layer 420 and the second sub-metal layer 440 (as shown in fig. 4). The second sub-metal layer 440 is made of a general metal material.

Forming the amorphous metal layer 400 in a combined manner may further improve the surface flatness of the amorphous metal layer 400 or reduce the surface roughness of the amorphous metal layer 400.

Referring to fig. 1 again, in a further embodiment, the display panel 10 further includes a first insulating layer 500 and a protection layer 600, the first insulating layer 500 covers the first thin film transistor region 11 and the second thin film transistor region 12, and in the first thin film transistor region 11, the first insulating layer 500 is disposed on a side of the first gate 220 away from the substrate 100; the first active layer 210 is disposed on a side of the first insulating layer 500 away from the first gate electrode 220 and within the first thin film transistor region 11. The material of the first insulating layer 500 generally includes silicon oxide. The protection layer 600 covers the first thin film transistor region 11 and the second thin film transistor region 12, and in the first thin film transistor region 11, the protection layer 600 is disposed on a side of the first active layer 210 away from the first insulating layer 500. The protection layer 600 may be used to protect the first active layer 210 during a subsequent etching process, so as to reduce the influence of the external environment, gas or water vapor on the surface of the first active layer 210, thereby increasing the stability of the first thin film transistor 200.

In a further embodiment, the first thin film transistor 200 further includes a first source electrode 230 and a first drain electrode 240, two first through holes 610 penetrating through two opposite surfaces of the protection layer 600 are formed in the protection layer 600 in the first thin film transistor region 11 to expose a portion of the first active layer 210, the first source electrode 230 and the first drain electrode 240 are respectively located in the two first through holes 610 and connected to the first active layer 210, and a portion of the first source electrode 230 and a portion of the first drain electrode 240 are located on a surface of the protection layer 600 away from the first active layer 210. In some embodiments, the first through holes 610 may be three, two of which are used for receiving the first source electrode 230 and the first drain electrode 240, and the other one is used for receiving a first connection member for electrically connecting the first gate electrode 220 with an external element. Specifically, the first tft 200 further includes a first connection element 250, in the first tft region 11, a third through hole 640 penetrating through two opposite surfaces of the protection layer 200 is disposed in the protection layer 600 to expose a portion of the first gate 220, and the first connection element 250 is located in the third through hole 640 and connected to the first gate 220.

In a further embodiment, the display panel 10 further includes a planarization layer 700 and a pixel defining layer 800, the planarization layer 700 is disposed on a layer of the protection layer 600 away from the first active layer 210 and covers the first source electrode 230 and the first drain electrode 240; the pixel defining layer 800 is disposed on a side of the planarization layer 700 away from the protective layer 600. The planarization layer 700 is used for planarizing the first thin film transistor region 11 and the second thin film transistor region 12 to further improve the flatness of the surface of the display panel 10, and the pixel definition layer 800 is used for defining the size and the distribution of each pixel in the display panel 10.

In a further embodiment, the protection layer 600 includes a first sub protection layer 620 and a second sub protection layer 630, and in the first thin film transistor region 11, the first sub protection layer 620 is disposed on a side of the first active layer 210 away from the first insulating layer 500, and the second sub protection layer 630 is disposed on a side of the first sub protection layer 620 away from the first active layer 610; the first sub-protective layer 620 is an inorganic protective layer, and the second sub-protective layer 630 is an organic protective layer. In this embodiment, the first sub-protection layer 620 is made of silicon oxide or silicon nitride, and the second sub-protection layer 630 is made of an organic material.

In a further embodiment, the amorphous metal layer 400 is located in the first tft region 11, and the first tft 200 is electrically connected to the second tft 300 through the amorphous metal layer 400. Wherein the amorphous metal layer 400 may be connected to one of a source electrode, a drain electrode, or a gate electrode in the second thin film transistor 300.

In a further embodiment, the second active layer 310 is disposed on one side of the substrate 110 and within the second thin film transistor region 12; the second thin film transistor 300 further includes a second gate electrode 320, and the second gate electrode 320 is disposed on a side of the second active layer 310 away from the substrate 100. That is, in the present embodiment, the second thin film transistor 300 has a bottom gate structure. In some other embodiments, the second thin film transistor 300 may also be a top gate structure.

In a further embodiment, the display panel 10 further includes a second insulating layer 900 and an interlayer dielectric layer 1000, and the second thin film transistor 300 further includes a second source electrode 330 and a second drain electrode 340; the second insulating layer 900 is disposed on a surface of the second active layer 310 away from the substrate 100; the second gate electrode 320 is disposed on a surface of the second insulating layer 900 away from the second active layer 310; the interlayer dielectric layer 1000 covers the first thin film transistor region 11 and the second thin film transistor region 12, and in the second thin film transistor region 12, the interlayer dielectric layer 1000 is located on a side of the second active layer 310 away from the substrate 100 and covers the second gate electrode 320 and the second insulating layer 900.

In this embodiment, the interlayer dielectric layer 1000 is not disposed in the first tft region 11, the interlayer dielectric layer 1000 is generally formed by silicon nitride or silicon oxide, the interlayer dielectric layer 1000 may be one layer or two or more layers, for example, the interlayer dielectric layer 1000 is formed by one layer of silicon nitride or one layer of silicon oxide, or the interlayer dielectric layer 1000 is formed by two layers of silicon oxide and silicon nitride, or the interlayer dielectric layer 1000 is formed by two layers of silicon oxide and one layer of silicon nitride.

The surface flatness of the interlayer dielectric layer 1000 is inferior to that of the amorphous metal layer 400, and if the interlayer dielectric layer 1000 is disposed in the first tft area 11 and then the amorphous metal layer 400 is formed on the interlayer dielectric layer 1000, the surface flatness of the amorphous metal layer 400 is reduced, so in this embodiment, the interlayer dielectric layer 1000 is not disposed in the first tft area 11 to improve the surface flatness of the amorphous metal layer 400.

In the second tft region 12, two fourth through holes 1010 penetrating through two opposite surfaces of the interlayer dielectric layer 1000 are formed in the interlayer dielectric layer 1000 to expose a portion of the second active layer 310, the two fourth through holes 1010 are respectively located at two sides of the second gate 310 and the second insulating layer 900, and the second source 330 and the second drain 340 are respectively located in the two fourth through holes 1010.

The amorphous metal layer 400 is connected to one of the second source electrode 330 and the second drain electrode 340 adjacent to the amorphous metal layer 400. As shown in fig. 1, in the present embodiment, the amorphous metal layer 400 is connected to the second drain electrode 340.

In a further embodiment, the display panel 10 further includes a first buffer layer 1100, the first buffer layer 1100 is disposed on one side of the substrate 100 and covers the first thin film transistor region 11 and the second thin film transistor region 12, and the first thin film transistor 200 and the second thin film transistor 300 are disposed on one side of the first buffer layer 1100 away from the substrate 100. In this embodiment, the amorphous metal layer 400 may be directly disposed on the surface of the first buffer layer 1100 away from the substrate 100, or an insulating layer may be disposed between the amorphous metal layer 400 and the first buffer layer 1100.

In this embodiment, the first thin film transistor 200 and the second thin film transistor 300 are arranged in a horizontal direction. When the first thin film transistor 200 is of a bottom gate structure and the second thin film transistor 300 is of a top gate structure, the first thin film transistor 200 may be disposed above the second thin film transistor 300, and at this time, the first thin film transistor region 11 and the second thin film transistor region 12 are two regions stacked up and down, and by disposing the first thin film transistor 200 on the second thin film transistor 300, the distribution area of the thin film transistors in the display panel 10 may be reduced, thereby increasing the screen occupation ratio of the display panel 10, and a frameless display screen or an irregular screen display screen may be manufactured.

Referring to fig. 5, a display panel 10a according to a second embodiment of the present invention is different from the first embodiment in that an interlayer dielectric layer 1000 covers a first tft region 11 and a second tft region 12. Specifically, the display panel 10a includes a first buffer layer 1100 and an interlayer dielectric layer 1000, the first buffer layer 1100 is disposed on one side of the substrate 100 and covers the first thin film transistor region 11 and the second thin film transistor region 12; the interlayer dielectric layer 1000 covers the first thin film transistor region 11 and the second thin film transistor region 12, in the first thin film transistor region 11, the interlayer dielectric layer 1000 is disposed on a side of the first buffer layer 1100 away from the substrate 100, and the first gate 210 is disposed on a side of the interlayer dielectric layer 1000 away from the first buffer layer. In the present embodiment, the interlayer dielectric layer 1000 covers the first thin film transistor region 11 and the second thin film transistor region 12, and the first gate electrode 210 is disposed on the surface of the interlayer dielectric layer 1000, compared to the first embodiment.

Referring to fig. 6, a third embodiment of the present invention provides a display panel 10b, which is different from the second embodiment in that an amorphous metal layer 400 is used as a light-shielding layer of a first thin film transistor 200, specifically, in the display panel 10b, the amorphous metal layer 400 is located in a first thin film transistor region 11 to form a light-shielding layer 260 of the first thin film transistor 200, the amorphous metal layer 400 is disposed on one side of a substrate 100, a first active layer 210 is disposed on one side of the amorphous metal layer 400 away from the substrate 100, the first thin film transistor 200 further includes a first gate 220, and the first gate 220 is disposed on one side of the first active layer 210 away from the amorphous metal layer 400 and located in the first thin film transistor region 11. In this embodiment, the first thin film transistor 200 has a top gate structure, and in other embodiments, the first thin film transistor 200 may also have a bottom gate structure.

In a further embodiment, the display panel 10b further includes a second buffer layer 1200 and a first insulating layer 500, the second buffer layer 1200 at least covers the first thin film transistor region 11, and the second buffer layer 1200 is disposed on a side of the amorphous metal layer 400 away from the substrate 100 in the first thin film transistor region 11; the first active layer 210 is disposed on a side of the second buffer layer 1200 away from the amorphous metal layer 400, and is located in the first thin film transistor region 11; the first insulating layer 500 covers the first thin film transistor region 11 and the second thin film transistor region 12, and in the first thin film transistor region 11, the first insulating layer 500 is disposed on a side of the first active layer 210 away from the second buffer layer 1200; the first gate electrode 220 is disposed on a side of the first insulating layer 500 away from the first active layer 210.

In a further embodiment, the display panel 10b further includes a protection layer 600, the protection layer 600 is disposed on a side of the first gate electrode 220 away from the first active layer 210, the first thin film transistor 200 further includes a first source electrode 230 and a first drain electrode 240, two second through holes 630 penetrating through opposite surfaces of the protection layer 600 and the first insulating layer 500 are disposed in the protection layer 600 and the first insulating layer 500 in the first thin film transistor region 11 to expose a portion of the first active layer 210, the first source electrode 230 and the first drain electrode 240 are respectively disposed in the two second through holes 630 and connected to the first active layer 210, and a portion of the first source electrode 230 and a portion of the first drain electrode 240 are disposed on a surface of the protection layer 600 away from the first active layer 210.

Referring to fig. 7, a display panel 10c according to a fourth embodiment of the present invention is different from the second embodiment in that the amorphous metal layer 400 is at least disposed in the second tft region 12, the amorphous metal layer 400 is disposed on one side of the substrate 100, the display panel 10c further includes a second buffer layer 1200, the second buffer layer 1200 is disposed on one side of the amorphous metal layer 400 away from the substrate 100, and the first tft 200 and the second tft 300 are disposed on one side of the second buffer layer 1200 away from the amorphous metal layer 400. In this embodiment, the amorphous metal layer 400 is disposed in the second tft region 12, and is used as a light shielding layer of the second tft 300, and can also be used to improve the flatness of the second tft 300.

Referring to fig. 8, a display panel 10d according to a fifth embodiment of the present invention is different from the fourth embodiment in that an amorphous metal layer 400 is disposed in a first tft area 11 and a second tft area 12. As a light shielding layer for the first thin film transistor region 11 and the second thin film transistor 300, the flatness of the first thin film transistor region 11 and the second thin film transistor 300 can be improved.

Referring to fig. 9, the present invention further provides an electronic device 20, wherein the electronic device 20 includes the display panel 10 according to any of the embodiments. The electronic device 20 may be, but not limited to, an electronic book, a smart Phone (e.g., an Android Phone, an iOS Phone, a Windows Phone, etc.), a tablet computer, a flexible palm computer, a flexible notebook computer, a Mobile Internet device (MID, Mobile Internet Devices), or a wearable device.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.