阅读说明：本技术 非易失性存储器及其数据擦除方法 (Nonvolatile memory and data erasing method thereof ) 是由 杨涛 赵冬雪 夏志良 于 2021-09-18 设计创作，主要内容包括：本申请公开了一种非易失性存储器及数据擦除方法。存储器包括多个存储块,存储块包括由下至上堆叠的多个层级,层级包括多个存储单元,相邻的层级之间设置有伪存储单元。方法包括：向多个层级中待进行擦除操作的第一层级施加具有台阶状上升的电压波形的台阶擦除电压；在台阶擦除电压从其中间电平升高至其峰值电平期间,将至少一个预定区域的电压从其起始电平升高至其峰值电平,从而在第一层级中生成栅极感应漏极泄漏电流,其中预定区域邻近第一层级并包括至少一个伪存储单元。通过将预定区域设置在邻近待进行擦除操作的层级处,并对预定区域所包括的伪存储单元施加辅助电压,能够在维持存储器性能的基础上,改善栅极感应漏极泄漏电流。(The application discloses a nonvolatile memory and a data erasing method. The memory comprises a plurality of memory blocks, each memory block comprises a plurality of hierarchies stacked from bottom to top, each hierarchy comprises a plurality of memory units, and dummy memory units are arranged between adjacent hierarchies. The method comprises the following steps: applying a step erase voltage having a step-like rising voltage waveform to a first level to be subjected to an erase operation among the plurality of levels; during the step erase voltage is raised from its intermediate level to its peak level, the voltage of at least one predetermined region is raised from its starting level to its peak level, thereby generating a gate induced drain leakage current in a first level, wherein the predetermined region is adjacent to the first level and comprises at least one dummy memory cell. By disposing the predetermined region at a level adjacent to a level at which an erase operation is to be performed and applying an auxiliary voltage to the dummy memory cells included in the predetermined region, it is possible to improve a gate-induced drain leakage current while maintaining memory performance.)

1. A data erasing method of a nonvolatile memory, wherein the memory comprises a plurality of memory blocks, each memory block comprises a plurality of levels stacked from bottom to top, each level comprises a plurality of memory units, and a dummy memory unit is arranged between adjacent levels, the method comprises the following steps:

applying a step erase voltage to a first level to be subjected to an erase operation among the plurality of levels, the step erase voltage having a voltage waveform stepped up; and

raising a voltage of at least one predetermined region from its initial level to its peak level during the step erase voltage is raised from its intermediate level to its peak level, thereby generating a gate induced drain leakage current in the first level,

wherein the predetermined region is adjacent to the first hierarchy and includes at least one of the dummy memory cells.

2. The method of claim 1, wherein a plurality of the memory cells are connected in series from bottom to top to form a memory cell string, the memory cell string comprises a plurality of sub-memory cell strings belonging to different levels, a bottom select gate transistor and a top select gate transistor, the top select gate transistor belongs to the top select level, the top select level further comprises a top dummy memory cell, the method further comprises:

applying a first voltage to a top selection level corresponding to the first level during performing an erase operation on the first level, the first voltage having a stepped-up voltage waveform; and

raising the voltage of the bottom select-gate transistor from its starting level to its peak level after the step erase voltage reaches its intermediate level,

wherein a peak level of the first voltage is higher than a peak level of the step erase voltage.

3. The method of claim 1, wherein a plurality of the memory cells are connected in series from bottom to top to form a memory cell string, the memory cell string comprises a plurality of sub-memory cell strings belonging to different levels, a bottom select gate transistor and a top select gate transistor, the top select gate transistor belongs to the top select level, the top select level further comprises a top dummy memory cell, the method further comprises:

applying a second voltage to a top selection level corresponding to the first level during performing an erase operation on the first level; and

after the step erase voltage reaches its intermediate level, the top select level is set to a floating state and the voltage of the bottom select gate transistor is raised from its starting level to its peak level.

4. The method according to any one of claims 1 to 3, wherein a plurality of the memory cells are connected in series from bottom to top to form a memory cell string, the memory cell string further comprising a bottom select gate transistor and a top select gate transistor, the plurality of memory cell strings being formed as the memory block, the memory block comprising a bottom level, a top level and a top select level that are vertically stacked,

the predetermined area includes a first predetermined area and a second predetermined area,

wherein the first predetermined region is located between the top level and the top select level and includes at least one of the dummy memory cells, and the second predetermined region is adjacent to the bottom select gate transistor and includes at least one of the dummy memory cells.

5. The method of claim 4, wherein the memory cell string is formed on a well doped region of a substrate and comprises a plurality of memory cells connected in series from bottom to top to a same bit line, and wherein applying a step erase voltage to a first level of the plurality of levels to be erased comprises:

applying the step erase voltages to the bit lines and the well doped regions corresponding to the first level, respectively; and

the memory cells of the other levels except the first level are set to a floating state, and a low level is applied to the memory cells of the first level or grounded.

6. The method according to any one of claims 1 to 3, a plurality of the memory cells being connected in series from bottom to top to form a memory cell string, the memory cell string further comprising a bottom layer select gate transistor and a top layer select gate transistor, the plurality of memory cell strings being formed as the memory block, the memory block comprising a bottom level, a middle level and a top level that are vertically stacked,

the predetermined area includes at least a first predetermined area and a second predetermined area,

wherein, when an erase operation is performed on the bottom level or the middle level,

the first predetermined region is located between the top level and the middle level and includes at least one of the dummy memory cells, and the second predetermined region is adjacent to the bottom select gate transistor and includes at least one of the dummy memory cells.

7. The method according to any one of claims 1 to 3, wherein a plurality of the memory cells are connected in series from bottom to top to form a memory cell string, and a plurality of the memory cell strings are formed as the memory block, the memory block including a bottom level, a middle level, a top level, and a top selection level vertically stacked on the substrate,

the predetermined area includes at least a first predetermined area and a second predetermined area,

wherein, when an erase operation is performed on the top level, the first predetermined region is located between the top level and the top selection level and includes at least one of the dummy memory cells, and the second predetermined region is located between the top level and the middle level and includes at least one of the dummy memory cells.

8. The method of claim 2, a plurality of the memory cell strings on a well doped region of a substrate being formed into the memory block, the memory block comprising a bottom level, a middle level, a top level, and the top select level stacked vertically, wherein applying a first voltage to a top select level corresponding to the first level further comprises:

during performing an erase operation on the bottom level, applying the first voltage to memory cells of the top level, first dummy memory cells between the top selection level and the top level, portions of second dummy memory cells between the top level and the middle level except for the predetermined region, fourth dummy memory cells between the middle level and the bottom level, portions of third dummy memory cells between the bottom selection gate transistor and a well doped region of the substrate except for the predetermined region, respectively, wherein a peak level of the first voltage is higher than a peak level of the step erase voltage; and

the memory cells of the middle level are set to a floating state, and a low level is applied to the memory cells of the bottom level or grounded.

9. The method of claim 3, wherein a plurality of said memory cell strings located on a well doped region of a substrate are formed into said memory block, said memory block comprising a bottom level, a middle level, a top level and said top selection level stacked vertically, wherein applying a second voltage to a top selection level corresponding to said first level and setting said top selection level to a floating state after said step erase voltage reaches an intermediate level thereof further comprises:

applying a second voltage to memory cells of the top level, first dummy memory cells between the top selection level and the top level, portions of second dummy memory cells between the top level and the middle level except the predetermined region, fourth dummy memory cells between the middle level and the bottom level, portions of third dummy memory cells between the bottom selection gate transistor and the well doped region of the substrate except the predetermined region, respectively, during performing an erase operation on the bottom level, after the step erasing voltage reaches the middle level, the parts except the preset area in the storage units of the top level, the first dummy storage units, the second dummy storage units and the fourth dummy storage units and the third dummy storage units are set to be in a floating state; and

the memory cells of the middle level are set to a floating state, and a low level is applied to the memory cells of the bottom level or grounded.

10. The method of claim 2, a plurality of the memory cell strings on a well doped region of a substrate being formed into the memory block, the memory block comprising a bottom level, a middle level, a top level, and the top select level stacked vertically, wherein applying a first voltage to a top select level corresponding to the first level further comprises:

during performing an erase operation on the middle level, applying the first voltage to memory cells of the top level, first dummy memory cells between the top selection level and the top level, portions of second dummy memory cells between the top level and the middle level except the predetermined region, fourth dummy memory cells between the middle level and the bottom level, portions of third dummy memory cells between the bottom selection gate transistor and a well doped region of the substrate except the predetermined region, respectively, wherein a peak level of the first voltage is higher than a peak level of the step erase voltage; and

the memory cells of the bottom level are set to a floating state, and a low level is applied to the memory cells of the middle level or grounded.

11. The method of claim 3, wherein a plurality of said memory cell strings located on a well doped region of a substrate are formed into said memory block, said memory block comprising a bottom level, a middle level, a top level and said top selection level stacked vertically, wherein applying a second voltage to a top selection level corresponding to said first level and setting said top selection level to a floating state after said step erase voltage reaches an intermediate level thereof further comprises:

applying the second voltage to memory cells of the top level, first dummy memory cells between the top selection level and the top level, portions of second dummy memory cells between the top level and the middle level except the predetermined region, fourth dummy memory cells between the middle level and the bottom level, portions of third dummy memory cells between the bottom selection gate transistor and a well doped region of the substrate except the predetermined region, respectively, during performing an erase operation on the middle level, after the step erasing voltage reaches the middle level, the parts except the preset area in the storage units of the top level, the first dummy storage units, the second dummy storage units and the fourth dummy storage units and the third dummy storage units are set to be in a floating state; and

the memory cells of the bottom level are set to a floating state, and a low level is applied to the memory cells of the middle level or grounded.

12. The method of claim 2, a plurality of the memory cell strings being formed into the memory block, the memory block comprising a bottom level, a middle level, a top level, and the top selection level stacked vertically, wherein applying a first voltage to a top selection level corresponding to the first level further comprises:

applying the first voltage to a portion of first dummy memory cells between the top selection level and the top level except the predetermined region, a portion of second dummy memory cells between the top level and the middle level except the predetermined region, memory cells of the middle level, fourth dummy memory cells between the middle level and the bottom level, memory cells of the bottom level, the bottom selection gate transistor, and third dummy memory cells between the bottom selection gate transistor and the well doped region, respectively, during performing an erase operation on the top level, wherein a peak level of the first voltage is higher than a peak level of the step erase voltage; and

a low level is applied to or grounded to the top level of memory cells.

13. The method of claim 3, a plurality of the memory cell strings being formed into the memory block, the memory block including a bottom level, a middle level, a top level, and the top selection level stacked vertically, wherein applying a second voltage to a top selection level corresponding to the first level, and after the step erase voltage reaches an intermediate level thereof, setting the top selection level to a floating state further comprises:

applying the second voltage to a portion of a first dummy memory cell between the top selection level and the top level except the predetermined region, a portion of a second dummy memory cell between the top level and the middle level except the predetermined region, a memory cell of the middle level, a fourth dummy memory cell between the middle level and the bottom level, a memory cell of the bottom level, the bottom selection gate transistor, and a third dummy memory cell between the bottom selection gate transistor and the well doped region, respectively, during performing an erase operation on the top level, and after the step erase voltage reaches an intermediate level thereof, applying the second voltage to a portion of the first dummy memory cell except the predetermined region, a portion of the second dummy memory cell except the predetermined region, and a memory cell of the middle level, The third dummy memory cell, the bottom level memory cell, and the fourth dummy memory cell are set to a floating state; and

a low level is applied to or grounded to the top level of memory cells.

14. A non-volatile memory, wherein the non-volatile memory comprises:

a memory array formed on a well doped region of a substrate and including a plurality of memory cells, wherein memory cell strings in each column are connected to the same bit line to form a memory cell string, a plurality of the memory cell strings are formed as a memory block including a plurality of levels vertically stacked in a direction perpendicular to the substrate, the memory cell string including a plurality of sub memory cell strings belonging to different levels; and

control circuitry coupled with the memory array and configured to control a hierarchy selection of the plurality of levels and the performing of the hierarchy erase operation and the gate induced drain leakage GIDL erase operation of any one of claims 1-13 on the selected level.

15. The non-volatile memory as claimed in claim 14, wherein the memory array is a three-dimensional NAND memory array and the non-volatile memory is a three-dimensional NAND memory.

Technical Field

The present disclosure relates to the field of semiconductor technologies, and more particularly, to a nonvolatile memory and a data erasing method of the nonvolatile memory.

Background

Recently, nonvolatile memories having memory cells stacked "vertically" (i.e., in three dimensions (3D)) are widely used in electronic devices, which typically include multiple levels stacked vertically (e.g., a top level, a middle level, and a bottom level in a nonvolatile memory formed by a multi-stack process), which may be connected from level to level by a middle plug, and further, there may be multiple vertically stacked memory cells in each level. For efficient reading, writing, and erasing in a non-volatile memory having multiple levels, each level may be erased individually.

In addition, as the number of stacked layers of the nonvolatile memory is increased, a level erase mechanism may be used in combination with a Gate Induced Drain Leakage (GIDL) erase mechanism to improve data erase efficiency.

However, in the conventional data erasing method, the erasing carriers of the nonvolatile memory are generally generated between the top plug and the top selection gate transistor of the channel structure, and the middle plug often contains highly doped conductive impurities, so that the erasing carriers are difficult to cross the potential barrier formed by the middle plug and reach the memory cell to be operated, and the effective GIDL erasing is difficult to realize.

Therefore, how to implement an efficient nonvolatile memory level erase operation is a problem to be solved by those skilled in the art.

Disclosure of Invention

In order to solve or partially solve the above problems or other problems in the related art, various embodiments to be further described hereinafter of the present application are proposed.

One aspect of the present application provides a data erasing method for a nonvolatile memory, where the memory includes a plurality of memory blocks, each memory block includes a plurality of levels stacked from bottom to top, each level includes a plurality of memory cells, and a dummy memory cell is disposed between adjacent levels, the method includes: applying a step erase voltage to a first level to be subjected to an erase operation among the plurality of levels, the step erase voltage having a voltage waveform stepped up; raising a voltage of at least one predetermined region from its starting level to its peak level during the step erase voltage is raised from its intermediate level to its peak level, thereby generating a gate induced drain leakage current in the first level, wherein the predetermined region is adjacent to the first level and includes at least one of the dummy memory cells.

According to an embodiment of the present application, a plurality of the memory cells are connected in series from bottom to top to form a memory cell string, the memory cell string includes a plurality of sub memory cell strings belonging to different levels, a bottom select gate transistor and a top select gate transistor, the top select gate transistor belongs to the top select level, the top select level further includes a top dummy memory cell, and the method further includes: applying a first voltage to a top selection level corresponding to the first level during performing an erase operation on the first level, the first voltage having a stepped-up voltage waveform; and after the step erase voltage reaches an intermediate level thereof, raising a voltage of the bottom layer select gate transistor from an initial level thereof to a peak level thereof, wherein the peak level of the first voltage is higher than the peak level of the step erase voltage.

According to an embodiment of the present application, a plurality of the memory cells are connected in series from bottom to top to form a memory cell string, the memory cell string includes a plurality of sub memory cell strings belonging to different levels, a bottom select gate transistor and a top select gate transistor, the top select gate transistor belongs to the top select level, the top select level further includes a top dummy memory cell, and the method further includes: applying a second voltage to a top selection level corresponding to the first level during performing an erase operation on the first level; and after the step erase voltage reaches its intermediate level, setting the top select level to a floating state and raising the voltage of the bottom select gate transistor from its starting level to its peak level.

According to one embodiment of the application, a plurality of the memory cells are connected in series from bottom to top to form a memory cell string, the memory cell string further comprises a bottom layer selection gate transistor and a top layer selection gate transistor, the plurality of memory cell strings are formed into the memory block, the memory block comprises a bottom layer level, a top layer level and a top layer selection level which are vertically stacked, wherein the predetermined region comprises a first predetermined region and a second predetermined region, the first predetermined region is located between the top layer level and the top layer selection level and comprises at least one dummy memory cell, and the second predetermined region is adjacent to the bottom layer selection gate transistor and comprises at least one dummy memory cell.

According to one embodiment of the present application, the memory cell string is formed on a well doped region of a substrate, and includes a plurality of memory cells connected to a same bit line from bottom to top in series, wherein applying a step erase voltage to a first level to be subjected to an erase operation among the plurality of levels includes: applying the step erase voltages to the bit lines and the well doped regions corresponding to the first level, respectively; and setting memory cells of other levels except the first level to a floating state, and applying a low level to the memory cells of the first level or grounding them.

According to one embodiment of the present application, a plurality of the memory cells are connected in series from bottom to top to form a memory cell string, the memory cell string further includes a bottom layer select gate transistor and a top layer select gate transistor, the plurality of memory cell strings are formed as the memory block, the memory block includes a bottom level, a middle level and a top level which are vertically stacked, wherein the predetermined region includes at least a first predetermined region and a second predetermined region, the first predetermined region is located between the top level and the middle level and includes at least one of the dummy memory cells when an erase operation is performed on the bottom level or the middle level, and the second predetermined region is adjacent to the bottom layer select gate transistor and includes at least one of the dummy memory cells.

According to one embodiment of the present application, a plurality of the memory cells are connected in series from bottom to top to form a memory cell string, the plurality of the memory cell strings are formed as the memory block, the memory block includes a bottom level, a middle level, a top level, and a top selection level vertically stacked on the substrate, wherein the predetermined region includes at least a first predetermined region and a second predetermined region, the first predetermined region is located between the top level and the top selection level and includes at least one of the dummy memory cells when an erase operation is performed on the top level, and the second predetermined region is located between the top level and the middle level and includes at least one of the dummy memory cells.

According to an embodiment of the present application, a plurality of the memory cell strings on a well doped region of a substrate are formed into the memory block including a bottom level, a middle level, a top level, and the top selection level which are vertically stacked, wherein applying a first voltage to the top selection level corresponding to the first level further includes: during performing an erase operation on the bottom level, applying the first voltage to memory cells of the top level, first dummy memory cells between the top selection level and the top level, portions of second dummy memory cells between the top level and the middle level except for the predetermined region, fourth dummy memory cells between the middle level and the bottom level, portions of third dummy memory cells between the bottom selection gate transistor and a well doped region of the substrate except for the predetermined region, respectively, wherein a peak level of the first voltage is higher than a peak level of the step erase voltage; and setting the memory cells of the middle level to a floating state and applying a low level to or grounding the memory cells of the bottom level.

According to an embodiment of the present application, the plurality of memory cell strings on a well doped region of a substrate are formed into the memory block including a bottom level, a middle level, a top level, and the top selection level which are vertically stacked, wherein applying a second voltage to the top selection level corresponding to the first level, and setting the top selection level to a floating state after the step erase voltage reaches an intermediate level thereof further includes: applying a second voltage to memory cells of the top level, first dummy memory cells between the top selection level and the top level, portions of second dummy memory cells between the top level and the middle level except the predetermined region, fourth dummy memory cells between the middle level and the bottom level, portions of third dummy memory cells between the bottom selection gate transistor and the well doped region of the substrate except the predetermined region, respectively, during performing an erase operation on the bottom level, after the step erasing voltage reaches the middle level, the parts except the preset area in the storage units of the top level, the first dummy storage units, the second dummy storage units and the fourth dummy storage units and the third dummy storage units are set to be in a floating state; and setting the memory cells of the middle level to a floating state and applying a low level to or grounding the memory cells of the bottom level.

According to an embodiment of the present application, a plurality of the memory cell strings on a well doped region of a substrate are formed into the memory block including a bottom level, a middle level, a top level, and the top selection level which are vertically stacked, wherein applying a first voltage to the top selection level corresponding to the first level further includes: during performing an erase operation on the middle level, applying the first voltage to memory cells of the top level, first dummy memory cells between the top selection level and the top level, portions of second dummy memory cells between the top level and the middle level except the predetermined region, fourth dummy memory cells between the middle level and the bottom level, portions of third dummy memory cells between the bottom selection gate transistor and a well doped region of the substrate except the predetermined region, respectively, wherein a peak level of the first voltage is higher than a peak level of the step erase voltage; and setting the memory cells of the bottom level to a floating state and applying a low level to or grounding the memory cells of the middle level.

According to an embodiment of the present application, the plurality of memory cell strings on a well doped region of a substrate are formed into the memory block including a bottom level, a middle level, a top level, and the top selection level which are vertically stacked, wherein applying a second voltage to the top selection level corresponding to the first level, and setting the top selection level to a floating state after the step erase voltage reaches an intermediate level thereof further includes: applying the second voltage to memory cells of the top level, first dummy memory cells between the top selection level and the top level, portions of second dummy memory cells between the top level and the middle level except the predetermined region, fourth dummy memory cells between the middle level and the bottom level, portions of third dummy memory cells between the bottom selection gate transistor and a well doped region of the substrate except the predetermined region, respectively, during performing an erase operation on the middle level, after the step erasing voltage reaches the middle level, the parts except the preset area in the storage units of the top level, the first dummy storage units, the second dummy storage units and the fourth dummy storage units and the third dummy storage units are set to be in a floating state; and setting the memory cells of the bottom level to a floating state and applying a low level to or grounding the memory cells of the middle level.

According to an embodiment of the present application, a plurality of the memory cell strings are formed as the memory block including a bottom level, a middle level, a top level, and the top selection level which are vertically stacked, wherein applying a first voltage to the top selection level corresponding to the first level further includes: applying the first voltage to a portion of first dummy memory cells between the top selection level and the top level except the predetermined region, a portion of second dummy memory cells between the top level and the middle level except the predetermined region, memory cells of the middle level, fourth dummy memory cells between the middle level and the bottom level, memory cells of the bottom level, the bottom selection gate transistor, and third dummy memory cells between the bottom selection gate transistor and the well doped region, respectively, during performing an erase operation on the top level, wherein a peak level of the first voltage is higher than a peak level of the step erase voltage; and applying a low level to or grounding the memory cells of the top level.

According to an embodiment of the present application, forming a plurality of the memory cell strings into the memory block including a bottom level, a middle level, a top level, and the top selection level that are vertically stacked, wherein applying a second voltage to the top selection level corresponding to the first level, and setting the top selection level to a floating state after the step erase voltage reaches an intermediate level thereof further includes: applying the second voltage to a portion of a first dummy memory cell between the top selection level and the top level except the predetermined region, a portion of a second dummy memory cell between the top level and the middle level except the predetermined region, a memory cell of the middle level, a fourth dummy memory cell between the middle level and the bottom level, a memory cell of the bottom level, the bottom selection gate transistor, and a third dummy memory cell between the bottom selection gate transistor and the well doped region, respectively, during performing an erase operation on the top level, and after the step erase voltage reaches an intermediate level thereof, applying the second voltage to a portion of the first dummy memory cell except the predetermined region, a portion of the second dummy memory cell except the predetermined region, and a memory cell of the middle level, The third dummy memory cell, the bottom level memory cell, and the fourth dummy memory cell are set to a floating state; and applying a low level to or grounding the memory cells of the top level.

Another aspect of the present application provides a nonvolatile memory including: a memory array formed on a well doped region of a substrate and including a plurality of memory cells, wherein memory cell strings in each column are connected to the same bit line to form a memory cell string, a plurality of the memory cell strings are formed as a memory block including a plurality of levels vertically stacked in a direction perpendicular to the substrate, the memory cell string including a plurality of sub memory cell strings belonging to different levels; and a control circuit coupled to the memory array and configured to control a hierarchical selection of the plurality of levels and a gate induced drain leakage GIDL erase operation of any one of the data erase methods of the nonvolatile memory as provided in an aspect of the present application for the selected levels.

According to one embodiment of the present application, the memory array is a three-dimensional NAND memory array and the non-volatile memory is a three-dimensional NAND memory.

According to the nonvolatile memory and the erasing method thereof provided by at least one embodiment of the present application, by providing the predetermined region at a level adjacent to a level to be subjected to an erasing operation and applying the predetermined peak voltage (auxiliary voltage) to the dummy memory cells included in the predetermined region, the gate-induced drain leakage current can be improved while maintaining the overall performance of the nonvolatile memory, and efficient data erasing of the nonvolatile memory can be realized.

Further, in at least one embodiment of the present application, by applying a first voltage having a step-like rising waveform to a top selection level corresponding to a level to be subjected to an erase operation during performing the level erase operation; or by applying the second voltage to the top select level and floating it later in the erase operation (the later floating can make the top select level obtain a predetermined peak voltage through voltage coupling), the data erase efficiency of the non-volatile memory can be improved.

Drawings

Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. Wherein:

FIG. 1 is a block diagram of a non-volatile memory according to one embodiment of the present application;

FIG. 2 is a partial structural cross-sectional view of a non-volatile memory according to one embodiment of the present application;

FIG. 3 is a schematic illustration of a partial equivalent circuit of a memory array according to an embodiment of the present application;

FIG. 4 is a schematic illustration of a partial equivalent circuit of a memory array according to an embodiment of the present application;

FIG. 5 is a flow chart of a method of erasing data from a non-volatile memory according to one embodiment of the present application;

FIG. 6 is a partial circuit block diagram of a non-volatile memory according to one embodiment of the present application;

FIG. 7 is a partial circuit block diagram of a non-volatile memory according to another embodiment of the present application;

FIG. 8 is a timing diagram of voltage waveforms for a non-volatile memory according to one embodiment of the present application;

FIG. 9 is a timing diagram of voltage waveforms for a non-volatile memory according to another embodiment of the present application;

FIG. 10 is a timing diagram of voltage waveforms for a non-volatile memory according to one embodiment of the present application;

FIG. 11 is a timing diagram of voltage waveforms for a non-volatile memory according to another embodiment of the present application;

FIG. 12 is a timing diagram of voltage waveforms for a non-volatile memory according to yet another embodiment of the present application;

FIG. 13 is a graph illustrating a trend of channel potential changes for a three-dimensional memory according to one embodiment of the present application;

FIG. 14 is a timing diagram of voltage waveforms for a non-volatile memory according to one embodiment of the present application; and

FIG. 15 is a timing diagram of voltage waveforms for a non-volatile memory according to another embodiment of the present application.

Detailed Description

Exemplary embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

It will also be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers may be present. When an element or layer is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. To this end, the term "connected" may refer to physical, electrical, and/or fluid connections, with or without intervening elements.

Like reference numerals refer to like elements throughout the specification. In the drawings, the thickness of layers and regions are exaggerated for clarity.

Although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms may be used to distinguish one element from another. Thus, a first level discussed below may be referred to as a second level without departing from the teachings of one or more embodiments. The description of an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first," "second," and the like may also be used herein to distinguish between different classes or groups of elements. For the sake of simplicity, the terms "first", "second", etc. may denote "first class (or first group)", "second class (or second group)", etc. respectively.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, steps, operations, elements, components, and/or groups thereof.

Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. In an exemplary embodiment, when the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can encompass both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, when the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.

FIG. 1 shows a block diagram of a non-volatile memory 100 according to one embodiment of the present application. As shown in FIG. 1, a non-volatile memory 100 includes a memory array 102 and a control circuit 101 coupled together. In some embodiments, the memory array 102 and the control circuit 101 may be disposed on the same chip. In still other embodiments, the memory array 102 may be arranged on an array chip, and the control circuit 101 may be arranged on a different chip (e.g., implemented using Complementary Metal Oxide Semiconductor (CMOS) technology and referred to as a CMOS chip). The array chip and the CMOS chip may be electrically coupled together by a process such as bonding. In some embodiments, non-volatile memory 100 is an Integrated Circuit (IC) package that encapsulates one or more array chips and CMOS chips.

The non-volatile memory 100 may be configured to store data in the memory array 102 and perform operations in response to received Commands (CMDs). In some embodiments, the non-volatile memory 100 may receive write commands, read commands, erase commands, etc., and may perform operations accordingly.

In one embodiment, the non-volatile memory 100 receives an erase command with an address, and the non-volatile memory 100 then resets one or more memory cells at the address to an unprogrammed state (or referred to as an erased state), such as a "1" for a NAND memory cell.

In general, storage array 102 may include one or more storage planes 160, and each of storage planes 160 may include a plurality of storage blocks (e.g., blocks-1 through-N shown in fig. 1). Each memory block may also include multiple levels (e.g., level 1 through level M as shown in fig. 1, which block-1 includes) that are vertically stacked. In some examples, concurrent operations may occur at different storage planes 160. In some embodiments, each of level 1 through level M is the smallest unit to perform an erase operation.

In some embodiments, the storage array 102 is a flash memory array and is implemented using 3d nand flash memory technology. In some embodiments, peripheral circuitry 101 includes row decoder circuitry 110, page buffer circuitry 120, data input/output (I/O) circuitry 130, voltage generator 140, and control circuitry 150 coupled together. The row decoder circuit 110 may receive an address referred to as a row address (R-ADDR), generate a Word Line (WL) signal and a select signal (such as a Top Select Gate (TSG) signal, a Bottom Select Gate (BSG) signal, etc.) based on the row address, and provide the WL signal and the select signal to the memory array 102. Further, the row decoder circuit 110 provided herein may provide the appropriate WL signal and select signal during an erase operation.

The page buffer circuit 120 is coupled to Bit Lines (BL) of the memory array 102 and is configured to buffer data during read and write operations. The data I/O circuit 130 is coupled to the page buffer circuit 120 via data lines DL. In one example (e.g., during a write operation), the data I/O circuitry 130 is configured to receive data from circuitry external to the non-volatile memory 100 and provide the received data to the memory array 102 via the page buffer circuitry 120.

The voltage generator 140 is configured to generate a voltage of an appropriate level for proper operation of the non-volatile memory 100. For example, during a data erase operation, the voltage generator 140 may generate voltages of appropriate levels for a bit line voltage, a well doped region voltage, various word line voltages, a selection voltage, a predetermined region voltage, etc., suitable for the erase operation. For example, during a data erase operation, a step erase voltage is provided to the well doped region of the memory array 102. The first voltage is supplied to the row decoder 110, so the row decoder 110 may output the top select gate signal at an appropriate voltage level during the data erase operation. The peak voltage of the predetermined region is supplied to the row decoder 110, so that the row decoder 110 can output the predetermined region signal at an appropriate voltage level during the data erase operation. The step erase voltage is provided to the page buffer circuit 120 so the page buffer circuit 120 can drive the Bit Line (BL) at an appropriate voltage level during an erase operation. Further, the step erase voltage may also be applied to the bit line without passing through the page buffer circuit 120.

The control circuit 150 is configured to receive a Command (CMD) and an Address (ADDR), and based on the command and the address, supply control signals to circuits such as the row decoder circuit 110, the page buffer circuit 120, the data I/O circuit 130, the voltage generator 140, and the like. For example, control circuitry 150 may generate row addresses R-ADDR and column addresses C-ADDR based on addresses ADDR and provide the row addresses R-ADDR to row decoder 110 and the column addresses to data I/O circuitry 130. In another embodiment, the control circuit 150 may control the voltage generator 140 to generate a voltage of an appropriate level based on the received CMD. The control circuit 150 may coordinate other circuits to provide signals to the memory array 102 at the appropriate time and at the appropriate voltage levels.

The control circuit 150 may include a first portion of control circuitry 155 configured to generate appropriate control signals to control other circuitry to provide appropriate signals to the memory array 102 for an erase operation that uses a hierarchical erase scheme and a GIDL erase scheme, in other words, the first portion of control circuitry 155 is control circuitry for a hybrid erase. Signals with appropriate timing and voltage levels for the memory array 102 can affect the level erase mechanism and the GIDL erase mechanism for data erase operations of the non-volatile memory. The present application will hereinafter describe waveforms of signals in detail with reference to fig. 5 to 15.

Fig. 2 illustrates a cross-sectional view of a partial structure of a non-volatile memory 200 according to an embodiment of the present application. As shown in fig. 2, in one embodiment of the present application, a non-volatile memory 200 may include a three-dimensional memory array chip 202 and a peripheral circuit chip 201 electrically coupled together by a process such as bonding.

In some embodiments, the non-volatile memory 200 may include a plurality of array chips 202 and a peripheral circuit chip 201. The array chip 202 includes a substrate 203 and a stacked structure 290 formed on the substrate 203. The peripheral circuit chip 201 includes a substrate and a peripheral circuit formed on the substrate. For simplicity, the major surface of the substrate 203 is referred to as the X-Y plane, and the direction perpendicular to the major surface is referred to as the Z direction.

The substrate 203 and the substrate of the peripheral circuit chip 201 may be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, and/or a silicon-on-insulator (SOI) substrate, respectively. In other words, the substrate 203 and the substrate of the peripheral circuit chip 201 may include semiconductor materials, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor, respectively. The group IV semiconductor may comprise Si, Ge or SiGe. Alternatively, the substrate 203 and the substrate of the peripheral circuit chip 201 may be a bulk wafer or an epitaxial layer, respectively.

The stacked-layer structure 290 includes gate layers 295 and insulating layers 294 which are alternately stacked. Gate layer 295 is made of a gate stack material such as a high dielectric constant (high-k) gate insulator layer and a Metal Gate (MG) electrode. The insulating layer 294 is made of an insulating material such as silicon nitride, silicon dioxide, or the like. The gate layer 295 and the insulating layer 294 are configured to form a vertically stacked transistor in a Z direction, and the gate layer 295 corresponds to a gate of the transistor.

The nonvolatile memory 200 may include a memory cell array and peripheral circuits (e.g., row decoder circuit 110, page buffer circuit 120, data I/O circuit 130, voltage generator 140, control circuit 150, etc.). The peripheral circuit is formed in the peripheral circuit chip 201, and the memory cell array is formed in the array chip 202. The array chip 202 may include a core region 01 and a step region 02, and the memory cell array is formed in a portion of the stacked structure 290 located in the core region 01 and includes a plurality of vertical memory cell strings 280. The stepped region 02 may facilitate connection, for example, to the gates of memory cells in the memory cell string 280, the gates of select gate transistors, and so forth. The gates of the memory cells in the memory cell string 280 correspond to word lines in the memory architecture.

The memory cell string 280 is formed by a channel structure 281 extending through the stacked structure 200 and vertically (in the Z-direction) into the substrate 203. In other words, the channel structure 281 and the stack structure 290 together form the memory cell string 280.

The channel structure 281 may include a functional layer having a circular shape in an X-Y plane and extending to the substrate 203 in a Z direction and a semiconductor layer, and the functional layer may include a blocking insulating layer (e.g., silicon oxide), a charge storage layer (e.g., silicon nitride), a tunneling insulating layer (e.g., silicon oxide). The semiconductor layer may be made of any suitable semiconductor material, such as polycrystalline or monocrystalline silicon, and the semiconductor material may optionally be undoped, or may also optionally include P-type or N-type dopant impurities. In one embodiment, a blocking insulating layer may be formed on a sidewall of a hole for the channel structure 281 (the hole may penetrate the stack structure 290 and extend into the substrate 203), and then a charge storage layer, a tunneling insulating layer, a semiconductor layer, and an insulating fill layer may be sequentially stacked from the sidewall. The insulating fill layer may be formed of an insulating material such as silicon oxide and/or silicon nitride, and/or may be formed as an air gap.

Substrate 203 may include well doped regions, such as highly doped semiconductor layer 205 (alternatively referred to as well doped regions 205), for making electrical connections to the semiconductor layer in channel structure 281. Alternatively, the semiconductor layer 205 can be electrically connected to the bottom of the semiconductor layer in the channel structure 281, and the semiconductor layer 205 can be electrically connected to the sidewall of the semiconductor layer in the channel structure 281, or can be electrically connected to the bottom and the sidewall of the semiconductor layer in the channel structure 281.

The semiconductor layer 205 may be formed as a source conductive connection of the memory cell string 280. The semiconductor layer 205 may include one or more layers. The semiconductor layer 205 may be made of, for example, a silicon material such as intrinsic polysilicon, doped polysilicon (such as N-type doped silicon or P-type doped silicon, etc.). Alternatively, the semiconductor layer 205 may further include a metal silicide to improve conductivity. The semiconductor layer 205 is similarly conductively connected to the sources of the other memory cell strings 280 and thus forms an Array Common Source (ACS). In some embodiments, when the memory cell string 280 is configured to be erased in a level, the semiconductor layer 205 may extend and cover a core region and a step region of a memory block to which the level belongs.

In some embodiments, the vertically stacked transistors formed by the gate layer 295 and the insulating layer 294 can include memory cells (or can be referred to as memory cell transistors) and select gate transistors (e.g., one or more bottom layer select gate transistors, or one or more top layer select gate transistors, etc.). The semiconductor layer of the above-described channel structure 281 corresponds to a channel portion of a transistor in the memory cell string 280, and the gate layer 295 corresponds to a gate of the transistor in the memory cell string 280.

The memory cells may have different threshold voltages based on carrier trapping in a portion of the charge storage layer of the channel structure 281, which corresponds to the floating gate of the memory cell. For example, when a large number of holes are trapped (stored) in the floating gate of a memory cell transistor whose threshold voltage is below a predefined value, the memory cell transistor is in an unprogrammed state (also referred to as an erased state) corresponding to a logic "1". When holes are drained from the floating gate, the threshold voltage of the memory cell is above a predefined value, and thus the memory cell transistor is in a programmed state corresponding to a logic "0".

A transistor typically includes a gate for controlling the channel and has a drain and a source on each side of the channel. Alternatively, the upper side of the channel of the transistor may be referred to as the drain and the lower side of the channel of the transistor as the source. Alternatively, the drain and source may also be switched under certain drive configurations. In addition, the top selection gate transistor may be connected to a drain above the top selection gate transistor, and the bottom selection gate transistor may be connected to a source below the bottom selection gate transistor.

The one or more top-level select-gate transistors are configured to couple/decouple the memory cells in the memory cell string 280 to bit lines. The one or more underlying select gate transistors are configured to couple/decouple the memory cells in the memory cell string 280 to an ACS (common source line).

The bottom select gate transistor is controlled by the bottom select gate. For example, when the bottom select gate voltage (the voltage applied to the bottom select gate) is greater than the threshold voltage of the bottom select gate transistor, the bottom select gate transistor is turned on and the memory cell is coupled to the ACS. When the bottom select gate voltage is less than the threshold voltage of the bottom select gate transistor, the bottom select gate transistor is turned off and the memory cell is decoupled from the ACS. Similarly, the top select gate transistor is controlled by the top select gate.

In some embodiments, channel structure 281 has a circular shape in the X-Y plane and a cylindrical shape in the X-Z plane and the Y-Z plane. In the X-Y plane, a plurality of channel structures 281 may be disposed separately from each other and form a memory cell array. The array of channel structures 281 may have any suitable array shape, such as a matrix array shape in the X-direction and the Y-direction, a zigzag array shape in the X-or Y-direction, a honeycomb (e.g., hexagonal) array shape, and the like. The memory cell array may be divided into a plurality of memory blocks by the gate line gap structure 270 having a distance from the channel structure 281 in the X direction. Each memory block includes a plurality of levels stacked from bottom to top (Z direction). In other words, the plurality of memory cell strings 280 are formed as a memory block including a plurality of levels stacked vertically in a direction (Z direction) perpendicular to the substrate 203, and thus the memory cell string 280 may include a plurality of sub memory cell strings belonging to different levels.

In some embodiments, a redundancy layer is further disposed between the plurality of levels, the redundancy layer including at least one dummy memory cell. The dummy memory cell and the memory cell are simultaneously prepared and can be used for process and electrical buffering.

FIG. 3 illustrates a partial equivalent circuit schematic of a memory array 300 according to one embodiment of the present application. FIG. 4 illustrates a partial equivalent circuit schematic of a memory array 400 according to one embodiment of the present application.

As shown in fig. 3, by way of example, the three-dimensional memory device 300 may be divided into a plurality of memory blocks, each memory block including two levels, e.g., a top level 452 and a bottom level 450. The three-dimensional memory device 300 may further include a memory string 212 having a plurality of stacked memory cells 340, and the memory cell string 212 may include a plurality of sub-memory cell strings belonging to different levels, wherein the sub-memory cell string formed of the plurality of memory cells 340-1 is in a bottom level 450 and the sub-memory cell string formed of the plurality of memory cells 340-2 is in a top level 452. The three-dimensional memory device 300 also includes a conductive plug 460 between the top level 452 and the bottom level 450. Thus, in a three-dimensional memory device 300 having multiple levels, memory cell 340-2 in the top level 452 can be electrically connected with memory cell 340-1 in the bottom level 450 to form memory string 212. The memory string 212 may also include at least one field effect transistor (e.g., MOSFET) at each end that is controlled by the bottom layer select gates 332 and the top layer select gates 334, respectively. The two corresponding transistors are referred to as a bottom select gate transistor 332-T and a top select gate transistor 334-T. The stacked memory cells 340 may be controlled by control gates 333, the control gates 333 including a control gate 333-1 corresponding to the memory cell 340-1 and a control gate 333-2 corresponding to the memory cell 340-2, wherein the control gate 333 is connected to a word line (not shown) of the three-dimensional memory device 300. The drain terminal of the top select gate transistor 334-T may be connected to the bit line 341 and the source terminal of the bottom select gate transistor 332-T may be connected to a well doped region, from which the ACS464 may be formed and may be shared by the memory strings 212 in the entire memory block.

Further, the present application also provides a three-dimensional memory including memory blocks of a top level, a middle level, and a bottom level.

As shown in fig. 4, the three-dimensional memory device 400 as an example may be divided into a plurality of memory blocks, each memory block including three levels, e.g., a top level 452, a middle level 454, and a bottom level 450. The three-dimensional memory device 500 may further include a memory string 212 having a plurality of stacked memory cells 340, the memory cell string 212 may include a plurality of sub-memory cell strings belonging to different levels, wherein the sub-memory cell string formed of the plurality of memory cells 340-1 is in a bottom level 450, the sub-memory cell string formed of the plurality of memory cells 340-3 is in a middle level 454, and the sub-memory cell string formed of the plurality of memory cells 340-2 is in a top level 452. The three-dimensional memory 500 also includes conductive plugs, such as conductive plug 460 between the top level 452 and the middle level 454. Thus, in a three-dimensional memory device 500 having multiple levels, memory cell 340-2 in the top level 452 can be electrically connected with memory cell 340-3 in the middle level 454, and memory cell 340-1 in the bottom level 450 to form memory string 212. The memory string 212 may also include at least one field effect transistor (e.g., MOSFET) at each end that is controlled by the lower select gate 332 and the top select gate 334, respectively. And the two corresponding transistors are referred to as a lower select gate transistor 332-T and a top select gate transistor 334-T. The stacked memory cells 340 may be controlled by control gates 333, the control gates 333 including a control gate 333-1 corresponding to memory cell 340-1, a control gate 333-3 corresponding to memory cell 340-3, and a gate 333-2 corresponding to memory cell 340-2, wherein the control gate 333 is connected to a word line (not shown) of the three-dimensional memory device 500. The drain terminal of the top select gate transistor 334-T may be connected to a bit line 341 and the source terminal of the lower select gate transistor 332-T may be connected to a doped source line region 344, ACS464 may be formed from the doped source line region 344 (and may be shared by memory strings 212 in the entire memory block).

In a non-volatile memory, the memory cells in each row of each level are connected to the same word line WL, and the memory cell strings in each column are connected to the same bit line BL. Each word line may correspond to a page (page), and a memory block (block) may be composed of a plurality of pages, or a chip (plane) may be composed of a plurality of memory blocks. Further, in a non-volatile memory having multiple levels, each level can be separately processed for efficient reading, writing, and erasing, e.g., each level in a three-dimensional non-volatile memory can perform erase operations independently of other levels. Furthermore, read and write operations may also be performed in a page of memory that includes memory cells that share the same word line.

A three-dimensional non-volatile memory structure comprising two levels or three levels is described above. Hereinafter, a data erasing method for the three-dimensional nonvolatile memory according to the embodiments of the present application will be described in detail with reference to the accompanying drawings.

FIG. 5 is a flow chart of a method 1000 for erasing data from a non-volatile memory according to one embodiment of the present application. As shown in fig. 5, the data erase verification method 1000 of the nonvolatile memory includes:

in step S1, a step erase voltage having a voltage waveform rising stepwise is applied to a first level to be subjected to an erase operation among the plurality of levels.

Step S2, during the step erase voltage is raised from its middle level to its peak level, raising the voltage of at least one predetermined region from its starting level to its predetermined peak level, thereby generating a gate induced drain leakage current in the first level, the predetermined region being adjacent to the first level and including at least one dummy memory cell.

The above steps will be described in detail below so that those skilled in the art can more clearly understand the specific implementation of the method 1000.

Step S1

FIG. 6 is a partial circuit block diagram of a non-volatile memory according to one embodiment of the present application. Fig. 7 is a partial circuit configuration diagram of a nonvolatile memory according to another embodiment of the present application.

In step S1, the non-volatile memory may include a plurality of memory blocks, which may include a memory cell string 212 composed of a top tier 452 and a bottom tier 450, as shown in fig. 6. Alternatively, as shown in FIG. 7, a memory block may also include a memory cell string 212 comprised of memory cells in a top level 452, a middle level 454, and a bottom level 450. Any one of the levels of the memory string 212 at which an erase operation is to be performed may be selected as a first level for a level erase operation. The level erase operation refers to performing an erase operation only on at least one level of the memory block, and not on all memory strings.

In one embodiment of the present application, in conjunction with fig. 6 and 7, the memory cell string 212 includes memory cells, a top select gate transistor 334-T and a bottom select gate transistor 332-T, where TSG represents an electrical signal applied to a top select gate controlling the top select gate transistor 334-T and BSG represents an electrical signal applied to a bottom select gate controlling the bottom select gate transistor 332-T.

Further, a redundancy layer is further provided between the plurality of levels, and the redundancy layer includes at least one dummy memory cell DMY. The dummy memory cell and the memory cell are simultaneously prepared and can be used for process and electrical buffering. For example, in one embodiment of the present application, memory cell string 212 includes three top-level select gate transistors 334-T, which may form a top-level select level. Alternatively, the top select level may include at least one top select gate transistor 334-T, the number of corresponding top select gate transistors 334-T not being limiting in this application. In addition, the top selection level also includes at least one top dummy memory cell 334 ', the top dummy memory cell 334 ' and the top selection gate transistor 334-T being fabricated simultaneously and used for process and electrical buffering, wherein TSG _ DMY represents an electrical signal applied to the gate of the top dummy memory cell 334 '.

In addition, a redundancy layer including at least one first dummy memory cell 452' is further disposed between the top level 452 and the top selection level. The dummy memory cells and the memory cells in the redundancy layer are simultaneously prepared and can be used for process and electrical buffering. GIDL _ T represents an electrical signal applied to a predetermined region of the redundancy layer to which the first dummy memory cell 452' belongs. In other words, when an erase operation is performed on a level adjacent to the predetermined region (e.g., a top level), an electrical signal of GIDL _ T may be applied to the predetermined region in the redundancy layer, and a first voltage or a second voltage (to be described in detail later) may be applied to the first dummy memory cells 452' in the redundancy layer except for the predetermined region.

As shown in fig. 7, a redundancy layer including at least one second dummy memory cell 452 ″ and at least one second dummy memory cell 454' is further disposed between the top and middle levels 452 and 454. The dummy memory cell and the memory cell in the redundancy layer are simultaneously prepared and can be used for process and electrical buffering. GIDL _ M1 represents an electrical signal applied to a predetermined region of the redundancy layer to which the second dummy memory cell 452 ″ belongs. In other words, when an erase operation is performed on a level adjacent to the predetermined region (e.g., a top level), an electrical signal of GIDL _ M1 may be applied to the predetermined region in the redundancy layer, and a first voltage or a second voltage (to be described in detail later) may be applied to the second dummy memory cells 452 ″ of the redundancy layer except for the predetermined region. GIDL _ M0 represents an electrical signal applied to a predetermined region of a redundancy layer to which the second dummy memory cell 454' belongs. In other words, when an erase operation is performed on a level adjacent to the predetermined region (e.g., a bottom level or a middle level), an electrical signal of GIDL _ M0 may be applied to the predetermined region in the redundancy layer, and a first voltage or a second voltage (to be described in detail later) may be applied to the second dummy memory cells 454' in the redundancy layer except for the predetermined region.

A redundancy layer including at least one third dummy memory cell 205' is also disposed between the bottom select gate transistor 332-T and the well doped region 205 of the substrate. The dummy memory cells and the memory cells in the redundancy layer are simultaneously prepared and can be used for process and electrical buffering. GIDL _ B represents an electrical signal applied to a predetermined region of the redundancy layer to which the third dummy memory cell 205' belongs. In other words, when an erase operation is performed on a level adjacent to the predetermined region (e.g., a bottom level or a middle level), the electrical signal of GIDL _ B may be applied to the predetermined region in the redundancy layer, and a first voltage or a second voltage (to be described in detail later) may be applied to the third dummy memory cell 205' in the redundancy layer except for the predetermined region.

In addition, a redundancy layer including at least one fourth dummy memory cell 450' is further disposed between the middle level 454 and the bottom level 450. The dummy memory cells and memory cells in the redundancy layer are fabricated simultaneously and used for process and electrical buffering.

FIG. 8 is a timing diagram of voltage waveforms for a non-volatile memory according to one embodiment of the present application. FIG. 9 is a timing diagram of voltage waveforms for a non-volatile memory according to another embodiment of the present application. FIG. 10 is a timing diagram of voltage waveforms for a non-volatile memory according to one embodiment of the present application. FIG. 11 is a timing diagram of voltage waveforms for a non-volatile memory according to another embodiment of the present application. FIG. 12 is a timing diagram of voltage waveforms for a non-volatile memory according to yet another embodiment of the present application.

According to the erasing method of the nonvolatile memory, the predetermined region is arranged at the position close to the level to be subjected to erasing operation, and the predetermined peak voltage (auxiliary voltage) is applied to the dummy memory cell included in the predetermined region, so that the gate induced drain leakage current can be improved on the basis of maintaining the overall performance of the nonvolatile memory, and efficient data erasing of the nonvolatile memory is realized.

Specifically, as shown in fig. 6 to 12, a step erase voltage having a step-like rising voltage waveform may be first applied to a plurality of first levels to be subjected to an erase operation. For example, the step erase voltage electrical signals may be applied to the bit line 341 and the well doped region 205 corresponding to the first level, respectively.

Taking the example shown in fig. 8, BL represents the electrical signal applied to the bit line 341. HVNW represents the electrical signal applied to well doped region 205. The step erase voltage has a stepped voltage waveform, the first step spanning a period of T0 to T2, the voltage rising from a starting level to an intermediate level Vepre. The second step spans the time period T2 to T3, the voltage rising from the intermediate level Vepre to the peak level Vers. Wherein the value of the intermediate level Vepre may for example be selected between 1 volt and 4 volts. The value of the peak level Vers may, for example, be selected between 16 volts and 22 volts, with the time period T2 to T3 being approximately between 0.4 milliseconds and 0.9 milliseconds.

Further, WLs represents an electric signal applied to the gate of the memory cell included in each level. When performing the data erase operation, the gates of the memory cells included in the first level to be subjected to the erase operation should also be grounded or connected to a low level. Meanwhile, the gates of the memory cells included in the other levels not subjected to the erase operation are set to a floating state. When the other levels not subjected to the erase operation are in a floating state, they do not assume a circuit interconnection function. It will be understood by those skilled in the art that, in the present specification, when an element (or a component, an assembly, a member, etc.) is referred to as being in a floating state, it is intended to explain that the element (or the component, the assembly, the member, etc.) does not form an electrical path with other elements (or the component, the assembly, the member, etc.).

Step S2

In conjunction with fig. 6, 8, and 9, step S2 raises a voltage of at least one predetermined region from its initial level to its peak level during the step erase voltage is raised from its intermediate level to its peak level, thereby generating a gate induced drain leakage current in a first level, the predetermined region being adjacent to the first level and including at least one dummy memory cell, which may include, for example, the following:

in one embodiment of the present application, in conjunction with fig. 6 and 8, a memory block formed of a plurality of memory cell strings 212 includes only a bottom level 450 and a top level 452, and the predetermined region may include a first predetermined region and a second predetermined region when a data erase operation is performed on the bottom level 450. A first predetermined region may be selected in a redundancy layer between a top level 452 and a top level selection level and includes at least one first dummy memory cell 452'; and a second predetermined region is selected in the redundancy layer adjacent to the bottom select-gate transistor 332-T and includes at least one third dummy memory cell 205'.

During the time T2 to T3 when the electrical signals BL and HVNW rise from their intermediate level Vepre to their peak level Vers, the electrical signals GIDL _ T and GIDL _ B may be applied to the above-described first and second predetermined regions, respectively, to rise from the start level to their peak level Vgidl. Alternatively, the starting level of the first and second predetermined regions may be 0 volts, and the peak level Vgidl may be selected, for example, between 8 and 15 volts.

In one embodiment of the present application, in conjunction with fig. 6 and 9, a memory block formed of a plurality of memory cell strings 212 includes only a bottom level 450 and a top level 452, and the predetermined regions may include a first predetermined region and a second predetermined region when a data erase operation is performed on the top level 452. A first predetermined region may be selected in a redundancy layer between a top level 452 and a top level selection level and includes at least one first dummy memory cell 452'; and a second predetermined region is selected in the redundancy layer adjacent to the bottom select-gate transistor 332-T and includes at least one third dummy memory cell 205'.

During the time T2 to T3 when the electrical signals BL and HVNW rise from their intermediate level Vepre to their peak level Vers, the electrical signals GIDL _ T and GIDL _ B may be applied to the above-described first and second predetermined regions, respectively, to rise from the start level to their peak level Vgidl. Alternatively, the starting level of the first and second predetermined regions may be 0 volts, and the peak level Vgidl may be selected, for example, between 8 and 15 volts.

In conjunction with fig. 7, 10, 11 and 12, when a memory block formed of a plurality of memory cell strings 212 includes only a bottom level 450, a middle level 454 and a top level 452, step S2 raises a voltage of at least one predetermined region from its initial level to its peak level during a step erase voltage is raised from its middle level to its peak level, thereby generating a gate-induced drain leakage current in a first level, the predetermined region being adjacent to the first level and including at least one dummy memory cell, which may include, for example, the following:

in an embodiment of the present application, in conjunction with fig. 7 and 10, when the data erasing operation is performed on the lower hierarchy 450, the predetermined regions may include at least a first predetermined region and a second predetermined region. A first predetermined area may be selected between the top level 452 and the middle level 454 and include at least one second dummy memory cell 454'; and a second predetermined region is selected in the redundancy layer adjacent to the bottom select-gate transistor 332-T and includes at least one third dummy memory cell 205'.

During the time T2 to T3 when the electrical signals BL and HVNW rise from their intermediate level Vepre to their peak level Vers, the electrical signals GIDL _ M0 and GIDL _ B may be applied to the first and second predetermined regions, respectively, to rise from the start level to their peak levels Vgidl. Alternatively, the starting level of the first and second predetermined regions may be 0 volts, and the peak level Vgidl may be selected, for example, between 8 and 15 volts.

In an embodiment of the present application, in conjunction with fig. 7 and 11, when performing an operation of erasing data on the middle hierarchy 452, the predetermined regions may include at least a first predetermined region and a second predetermined region. A first predetermined area may be selected between the top level 452 and the middle level 454 and include at least one second dummy memory cell 454'; and a second predetermined region is selected in the redundancy layer adjacent to the bottom select-gate transistor 332-T and includes at least one third dummy memory cell 205'.

During the time T2 to T3 when the electrical signals BL and HVNW rise from their intermediate level Vepre to their peak level Vers, the electrical signals GIDL _ M0 and GIDL _ B may be applied to the first and second predetermined regions, respectively, to rise from the start level to their peak levels Vgidl. Alternatively, the starting level of the first and second predetermined regions may be 0 volts, and the peak level Vgidl may be selected, for example, between 8 and 15 volts.

In one embodiment of the present application, in conjunction with fig. 7 and 12, when performing an operation of erasing data on the top level 452, the predetermined area may include at least a first predetermined area and a second predetermined area. A first predetermined region may be selected in a redundancy layer between a top level 452 and a top level selection level and includes at least one first dummy memory cell 452'; and a second predetermined region is selected between the top level 452 and the middle level 454 and includes at least one second dummy memory cell 452 ".

During the time T2 to T3 when the electrical signals BL and HVNW rise from their intermediate level Vepre to their peak level Vers, the electrical signals GIDL _ T and GIDL _ M1 may be applied to the above-described first and second predetermined regions, respectively, to rise from the start level to their peak levels Vgidl. Alternatively, the starting level of the first and second predetermined regions may be 0 volts, and the peak level Vgidl may be selected, for example, between 8 and 15 volts.

Fig. 13 is a channel potential variation trend diagram of a three-dimensional memory according to an embodiment of the present application. As shown in fig. 13, through the above-described operation, a channel potential as shown in a curve 11 may be formed by applying a step erase voltage as shown in a curve 10 to the bit line and the well doping region, respectively, and applying an auxiliary erase voltage having a peak level Vgidl at least one dummy memory cell of a predetermined region, and holes (n + as shown in fig. 6 and 7) are injected and trapped in (or electrons are extracted from) the charge storage layer of the channel structure. When holes are trapped in the charge storage layer of a memory cell, the threshold voltage of the memory cell is lowered and the memory cell may enter an unprogrammed state (or referred to as an erased state). By selecting the predetermined region near the level where the erase operation is to be performed and applying the auxiliary erase voltage with the peak level of Vgidl at the at least one dummy memory cell in the predetermined region, the generation of erase carriers of the nonvolatile memory between the top plug and the top select gate transistor of the channel structure as in the conventional data erase method can be avoided, and the erase carriers (holes) can avoid the potential barrier formed by the middle plug and reach the memory cell where the operation is to be performed, so that the effective gate-induced drain leakage GIDL erase is realized.

However, in order to further improve the data erase efficiency of the nonvolatile memory, a first voltage having a step-like rising waveform may be applied to a top selection level corresponding to a level to be subjected to an erase operation during performing a level erase operation; or by applying the second voltage to the top select level and floating it later in the erase operation (the later floating can make the top select level obtain a predetermined peak voltage through voltage coupling), the data erase efficiency of the non-volatile memory can be improved.

FIG. 14 is a timing diagram of voltage waveforms for a non-volatile memory according to one embodiment of the present application. FIG. 15 is a timing diagram of voltage waveforms for a non-volatile memory according to another embodiment of the present application.

Specifically, referring to fig. 6 and 14, in one embodiment of the present application, during performing an erase operation of a first level, a first voltage having a step-like rising voltage waveform may be applied to a top selection level (including a top selection gate transistor 334-T and a top dummy memory cell 334') corresponding to the first level. Wherein the first auxiliary step crosses a time period of T0 to T2, the voltage rises from the start level to the intermediate level. The second step spans the time period T2 to T3, with the voltage rising from the intermediate level to the peak level Vtsg. The value of the intermediate level may for example be chosen between 3 volts and 10 volts. The peak level Vtsg may be higher than the peak level Vers of the step erase voltage, and further, the peak level Vtsg may be approximately 5 to 10 volts higher than the peak level Vers.

In addition, after the step erase voltage reaches its intermediate level Vepre, the voltage of the bottom select gate transistor 332-T may be raised from its starting level to its peak level Vbsg to effect conduction of the memory cell string 212.

FIG. 15 is a timing diagram of voltage waveforms for a non-volatile memory according to another embodiment of the present application.

Specifically, referring to fig. 6 and 15, in one embodiment of the present application, during performing an erase operation of a first level, a second voltage may be applied to a top selection level (including top selection gate transistors 334-T and top dummy memory cells 334') corresponding to the first level. In the period of T0 to T2, the voltage rises from the start level to the intermediate level. Alternatively, the value of the intermediate level may be selected, for example, between 3 volts and 10 volts. After the second voltage reaches its intermediate level Vepre (at time T1 shown in fig. 15), the voltage at the top selection level may be set to a floating state while it remains at the intermediate level. The voltage at the top selected level continues to rise due to the coupling of the step erase voltage, resulting in a step-shaped voltage waveform as shown by the dashed line in FIG. 15, and the peak level Vtsg may be approximately equal to 10 volts above the peak level Vers5 volts of the step erase voltage.

In addition, after the step erase voltage reaches its intermediate level Vepre, the voltage of the bottom select gate transistor 332-T may be raised from its starting level to its peak level Vbsg to effect conduction of the memory cell string 212.

As shown in fig. 13, through the above-described operation, the channel potential as shown in the graph 12 can be formed by applying the first voltage having a stepwise rising waveform to the top selection level corresponding to the level to be subjected to the erase operation, or by floating it in the latter stage of the erase operation after applying the second voltage to the above-described top selection level. By increasing the electric field applied across the PN junction, the gate-induced drain leakage (GIDL) current due to band-to-band tunneling can be increased, enabling efficient gate-induced drain leakage GIDL erasure, and thus improving the data erasure efficiency of the non-volatile memory, as compared to the channel potential curve 11 representing the operation not performed.

Since the contents and structures involved in the erasing method of the two hierarchies described above can be fully or partially applied to the nonvolatile memory structure including a plurality of hierarchies described below, the contents related or similar thereto will not be described in detail.

Referring again to fig. 7, 10, 11, and 12, when the memory block formed of the plurality of memory cell strings 212 includes a bottom level 450, a middle level 454, and a top level 452, the above operation of applying the first voltage to the top selection level corresponding to the first level further includes:

in one embodiment of the present application, referring again to fig. 7 and 10, during the erase operation on the bottom level 450, a first voltage (not shown) is applied to the memory cells of the top level 452, the first dummy memory cells 452 ' between the top selection level and the top level 452 ', the portions 452 "and 454 ' of the second dummy memory cells between the top level and the middle level except the first predetermined region, the fourth dummy memory cells 450 ' between the middle level 454 and the bottom level 450, the portions of the third dummy memory cells 205 ' between the bottom selection gate transistors 332-T and the well doped region 205 of the substrate except the second predetermined region, respectively, wherein the peak level of the first voltage may be higher than the peak level Vers of the step erase voltage, and further, the peak level may be approximately 5 to 10 volts higher than the peak level Vers. Further, the operation includes setting the memory cells of the middle tier 454 to a floating state and applying a low level to or grounding the memory cells of the bottom tier 450.

In one embodiment of the present application, referring again to fig. 7 and 11, during the erase operation of middle level 454, a first voltage (not shown) is applied to the memory cells of top level 452, the first dummy memory cells between the top selection level and top level 452, the portions 452 "and 454" of the second dummy memory cells between top level 452 and middle level 454, except for a first predetermined region, the fourth dummy memory cells 450 between middle level 454 and bottom level 450, the third dummy memory cells 205' between bottom selection gate transistors 332-T and well doped region 205 of the substrate, except for a second predetermined region, wherein the peak level of the first voltage may be higher than the peak level Vers of the step erase voltage, and further, the peak level may be approximately 5 to 10 volts higher than the peak level Vers. Further, the operation includes setting the memory cells of the bottom level 450 to a floating state and applying a low level to or grounding the memory cells of the middle level 454.

In one embodiment of the present application, referring again to fig. 7 and 12, during performing an erase operation on top level 452, a first voltage (not shown) may be applied to a portion of first dummy memory cells 452 'between top select level 452 and top level 452, except for a first predetermined region, a portion of second dummy memory cells 454' between top level 452 and middle level 454, except for a second predetermined region, a memory cell of middle level 454, a fourth dummy memory cell 450 'between middle level 454 and bottom level 450, a memory cell of bottom level 450, a bottom select gate transistor 332-T, and a third dummy memory cell 205' between bottom select gate transistor 332-T and well doped region 205, respectively, wherein a peak level of the first voltage may be higher than a peak level Vers of the step erase voltage, further, the peak level is compared to the peak level Vers, which may be approximately 5 to 10 volts higher, the operation further includes applying a low to the memory cells of the top level 452 or grounding them.

Further, as an option, when the memory block formed of the plurality of memory cell strings 212 includes the bottom level 450, the middle level 454, and the top level 452, the above-described operation of applying the second voltage to the top selection level corresponding to the first level and setting the top selection level to the floating state after the step erase voltage reaches the intermediate level thereof further includes:

in one embodiment of the present application, referring again to fig. 7 and 10, during the erase operation on the bottom level 450, a second voltage (solid line portion of the Floating line located at the upper portion in fig. 10) is applied to the memory cells of the top level 452, the first dummy memory cells between the top selection level and the top level 452, the portions 452 "and 454" of the second dummy memory cells between the top level 452 and the middle level 454, the fourth dummy memory cells 450 between the middle level 454 and the bottom level 450, and the portions of the third dummy memory cells 205' between the bottom selection gate transistors 332-T and the well doped region 205 of the substrate, except the second predetermined region, respectively. In a period of T0 to T2, the second voltage is raised from the start level to an intermediate level. Alternatively, the value of the intermediate level may be selected, for example, between 3 volts and 10 volts. After the step erase voltage reaches its intermediate level Vepre (at a time point T2 shown in fig. 14), the memory cells of the top level 452, the first dummy memory cell 452 ', 452 ″ and 454' of the portion of the second dummy memory cell other than the first predetermined region, the fourth dummy memory cell 450 ', and the portion of the third dummy memory cell 205' other than the second predetermined region are set to a floating state. The voltage of the above structure continues to rise by the coupling action of the step erase voltage, forming a step-shaped voltage waveform (Floating line in the upper portion in fig. 10) as shown in fig. 10, and the peak level thereof can also satisfy a peak level Vers5 volts to 10 volts which is substantially higher than the step erase voltage. Further, the operation includes setting the memory cell of the middle level 454 to a Floating state (the Floating line located at the lower portion in fig. 10), and applying a low level to or grounding the memory cell of the bottom level 450.

In one embodiment of the present application, referring again to fig. 7 and 11, during performing an erase operation on the middle level 454, a second voltage (solid line portion of the Floating line located at the upper portion in fig. 11) is applied to the memory cells of the top level 452, the first dummy memory cells between the top selection level and the top level 452, the portions 452 "and 454" of the second dummy memory cells between the top level 452 and the middle level 454, except the first predetermined region, the fourth dummy memory cells 450 between the middle level 454 and the bottom level 450, and the portions of the third dummy memory cells 205' between the bottom selection gate transistors 332-T and the well doped region 205 of the substrate, except the second predetermined region, respectively. In a period of T0 to T2, the second voltage is raised from the start level to an intermediate level. Alternatively, the value of the intermediate level may be selected, for example, between 3 volts and 10 volts. After the step erase voltage reaches its intermediate level Vepre (at a time point T2 shown in fig. 14), the memory cells of the top level 452, the first dummy memory cell 452 ', 452 ″ and 454' of the portion of the second dummy memory cell other than the first predetermined region, the fourth dummy memory cell 450 ', and the portion of the third dummy memory cell 205' other than the second predetermined region are set to a floating state. The voltage of the above structure continues to rise by the coupling action of the step erase voltage, and a step-shaped voltage waveform (Floating line located at the upper portion in fig. 11) is formed as shown in fig. 11, and the peak level thereof can also satisfy a peak level Vers5 v to 10 v which is substantially higher than the step erase voltage. Further, the operation includes setting the memory cell of the bottom level 450 to a Floating state (Floating line in the lower portion of fig. 11), and applying a low level to or grounding the memory cell of the middle level 454.

In one embodiment of the present application, referring again to fig. 7 and 12, during performing an erase operation on the top level 452, a second voltage (solid line portion of Floating line of fig. 12) is applied to a portion of the first dummy memory cells 452 'between the top selection level and the top level 452, a portion 454' of the second dummy memory cells between the top level 452 and the middle level 454, a memory cell of the middle level 454, a fourth dummy memory cell 450 'between the middle level 454 and the bottom level 450, a memory cell of the bottom level 450, the bottom selection gate transistor 332-T, and a third dummy memory cell 205' between the bottom selection gate transistor 332-T and the well doped region 205, respectively. In the period of T0 to T2, the voltage rises from the start level to the intermediate level. Alternatively, the value of the intermediate level may be selected, for example, between 3 volts and 10 volts. After the step erase voltage reaches its middle level Vepre (at a time point T2 shown in fig. 14), a portion of the first dummy memory cell 452 ', excluding the first predetermined region, a portion 454' of the second dummy memory cell, excluding the second predetermined region, a memory cell of the middle level 454, the fourth dummy memory cell 450 ', a memory cell of the bottom level 450, and the third dummy memory cell 205' are set to a floating state. The voltage of the above structure continues to rise by the coupling action of the step erase voltage, and a step-shaped voltage waveform (Floating line of fig. 12) as shown in fig. 12 is formed, and the peak level thereof can also satisfy a peak level Vers5 v to 10 v which is substantially higher than the step erase voltage. Additionally, the operation includes applying a low level to or grounding the memory cells of the top level 452.

By applying a first voltage having a step-like rising waveform to the above-described structure corresponding to the level to be subjected to an erase operation during the execution of the level erase operation, or by applying a second voltage to the above-described top selection level and floating it in the latter stage of the erase operation (the latter floating may cause the top selection level to obtain a predetermined peak voltage by voltage coupling), the electric field applied across the PN junction may be increased, thereby increasing the gate-induced drain leakage (GIDL) current due to band-to-band tunneling, effectively improving the gate-induced drain leakage GIDL erase.

The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by those skilled in the art that the scope of protection covered by this application is not limited to the particular combination of features described above, but also covers other arrangements formed by any combination of features described above or their equivalents without departing from the spirit of the invention. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.