阅读说明：本技术 单层多晶嵌入式非挥发存储单元、存储阵列及其工作方法 (Single-layer polycrystalline embedded non-volatile memory unit, memory array and working method thereof ) 是由 高瑞彬 许军 李�真 于 2021-12-03 设计创作，主要内容包括：本发明提供一种单层多晶嵌入式非挥发存储单元、存储阵列及其工作方法,存储单元包括：第一控制管、第一隧穿管、第一反相器、第二控制管、第二隧穿管、第二反相器、双稳态单元和读出结构,第一反相器包括类型相反的第一子晶体管和第二子晶体管,第二反相器包括类型相反的第三子晶体管和第四子晶体管。所述存储单元的可靠性得到提高。(The invention provides a single-layer polycrystalline embedded non-volatile memory unit, a memory array and a working method thereof, wherein the memory unit comprises: the bistable transistor comprises a first control tube, a first tunneling tube, a first phase inverter, a second control tube, a second tunneling tube, a second phase inverter, a bistable unit and a reading structure, wherein the first phase inverter comprises a first sub transistor and a second sub transistor which are opposite in type, and the second phase inverter comprises a third sub transistor and a fourth sub transistor which are opposite in type. The reliability of the memory cell is improved.)

1. A memory cell, comprising:

the device comprises a control tube, a tunneling tube, a phase inverter and a reading structure, wherein a well region of the control tube is connected with a control end, and a well region of the tunneling tube is connected with a tunneling end;

the phase inverter comprises a first transistor and a second transistor which are opposite in type, a grid electrode of the first transistor, a grid electrode of the second transistor, a grid electrode of the tunneling tube and a grid electrode of the control tube are connected to form a floating grid node, and a drain electrode of the first transistor is connected with a drain electrode of the second transistor and connected with the reading structure.

2. The memory cell of claim 1, wherein the sensing structure comprises a first select transistor and a second select transistor, the first select transistor being of a type opposite to the second select transistor, an input of the first select transistor, an input of the second select transistor, a drain of the first transistor and a drain of the second transistor being connected, an output of the first select transistor and an output of the second select transistor being connected and functioning as an output of the sensing structure, the first select transistor being adapted to be turned on simultaneously with the second select transistor;

or, the readout structure includes a transfer transistor and a selection transistor, the type of the transfer transistor is opposite to the type of the first transistor, the drain of the transfer transistor is connected with the source of the first transistor, and the gate of the transfer transistor is connected with the drain of the first transistor and the drain of the second transistor; the drain electrode of the selection transistor is connected with the source electrode of the transmission transistor, and the source electrode of the selection transistor is used as the output end of the readout structure;

alternatively, the readout structure is a single flip-flop.

3. A memory array comprising a plurality of memory cells according to claim 1 or 2.

4. A method of operating a memory array as claimed in claim 3, comprising:

when the memory cell is selected in a write-in mode, the control terminal is connected with a programming potential, the tunneling terminal is connected with 0V, the source electrode of the first transistor is connected with a power supply potential, the source electrode and the well region of the second transistor are connected with an intermediate potential, the intermediate potential is smaller than the programming potential and larger than 0V, and the floating gate node stores data 1;

when the memory cell is selected in an erasing mode, the tunneling end is connected with an erasing potential, the control end, the source electrode of the second transistor and the well region are connected with 0V, the source electrode of the first transistor is connected with a power supply potential, and the floating gate node stores data 0;

when the storage unit is selected in a reading mode, the control end applies reading voltage, the tunneling end, the source electrode of the second transistor and the well region are connected with 0V, and the source electrode of the first transistor is connected with power supply potential; when reading data '0' stored in the floating gate node, the first transistor is closed, and the second transistor is turned on; when reading the data '1' stored in the floating gate node, the second transistor is closed, and the first transistor is turned on.

5. The method of claim 4, wherein a difference between the gate of the second transistor and the intermediate potential is less than a tunneling voltage of the second transistor when the memory cell is selected in the write mode.

6. A memory cell, comprising:

the first control tube comprises a well region connected with a first control end, the well region of the first tunneling tube is connected with a first tunneling end, the well region of the first tunneling tube is connected with the first tunneling end, the first phase inverter comprises a first sub-transistor and a second sub-transistor which are opposite in type, and a grid electrode of the first sub-transistor, a grid electrode of the second sub-transistor, a grid electrode of the first tunneling tube and a grid electrode of the first control tube are connected to form a first floating gate node;

the well region of the second control tube is connected with a second control end, the well region of the second tunneling tube is connected with a second tunneling end, the second phase inverter comprises a third sub-transistor and a fourth sub-transistor which are opposite in type, and a grid electrode of the third sub-transistor, a grid electrode of the fourth sub-transistor, a grid electrode of the second tunneling tube and a grid electrode of the second control tube are connected to form a second floating gate node;

a bistable cell, the bistable cell comprising: a first additional inverter and a second additional inverter, wherein an output end of the first additional inverter is connected with an input end of the second additional inverter and drains of the third and fourth sub-transistors, and an output end of the second additional inverter is connected with an input end of the first additional inverter and drains of the first and second sub-transistors;

a sense structure connected to an output of the first additional inverter and an output of the second additional inverter.

7. The memory cell according to claim 6, wherein a source of the first sub-transistor is connected to a power supply potential; the voltage difference between the grid electrode and the well region of the second sub-transistor is suitable for being smaller than the tunneling voltage of the second sub-transistor when the first floating grid node writes data '1';

the source electrode of the third sub transistor is connected with a power supply potential; the voltage difference between the grid electrode of the fourth sub-transistor and the well region is suitable for being smaller than the tunneling voltage of the fourth sub-transistor when the second floating grid node writes data '1'.

8. The memory cell of claim 6, wherein the first additional inverter comprises a first additional transistor and a second additional transistor of opposite type, wherein a gate of the first additional transistor and a gate of the second additional transistor are connected as an input of the first additional inverter, and wherein a drain of the first additional transistor and a drain of the second additional transistor are connected as an output of the first additional inverter;

the second additional inverter comprises a third additional transistor and a fourth additional transistor which are opposite in type, the grid electrode of the third additional transistor and the grid electrode of the fourth additional transistor are connected to serve as the input end of the second additional inverter, and the drain electrode of the third additional transistor and the drain electrode of the fourth additional transistor are connected to serve as the output end of the second additional inverter;

the source of the first additional transistor, the source of the third additional transistor, the source of the first sub-transistor and the source of the third sub-transistor are connected and connected to a supply potential; a source of the second additional transistor and a source of the fourth additional transistor are grounded.

9. The memory cell of claim 6, wherein a coupling ratio of a capacitance value of the first control tube to a capacitance value of the first tunneling tube is greater than or equal to 60%; the coupling ratio of the capacitance value of the second control tube to the capacitance value of the second tunneling tube is greater than or equal to 60%.

10. The memory cell of claim 6 or 9, wherein the area of the channel region at the bottom of the gate in the first control tube is 10 times to 30 times that of the channel region at the bottom of the gate in the first tunneling tube; the area of the channel region at the bottom of the grid electrode in the second control tube is 10 times to 30 times that of the channel region at the bottom of the grid electrode in the second tunneling tube.

11. The memory cell of claim 6, wherein the gate dielectric layer of the first tunneling transistor has a thickness of 2nm to 30 nm; the thickness of the gate dielectric layer of the second tunneling tube is 2 nm-30 nm.

12. The memory cell of claim 6, wherein the well region of the first tunneling transistor, the well region of the second tunneling transistor, the well region of the first control transistor, the well region of the second sub-transistor, and the well region of the fourth sub-transistor are separately disposed, and the well region of the first tunneling transistor, the well region of the second tunneling transistor, the well region of the first control transistor, the well region of the second sub-transistor, and the well region of the fourth sub-transistor are separately disposed from the well region of the first sub-transistor, the well region of the third sub-transistor, the well region of the bistable cell, and the well region of the readout structure.

13. The memory cell of claim 6, wherein the sensing structure comprises a first selection transistor and a second selection transistor of the same type, wherein a gate of the first selection transistor is connected to a gate of the second selection transistor, a drain of the first selection transistor is connected to an output of the second additional inverter, a drain of the second selection transistor is connected to an output of the first additional inverter, a source of the first selection transistor serves as a first output, and a source of the second selection transistor serves as a second output;

or, the readout structure comprises a comparator, a first input of the comparator is connected to the output of the second additional inverter, a second input of the comparator is connected to the output of the first additional inverter, and the output of the comparator is used as the output of the readout structure.

14. A memory array comprising a plurality of memory cells as claimed in any one of claims 6 to 13.

15. A method of operating a memory array as claimed in claim 14, comprising:

when writing '1' into a first floating gate node and writing '0' into a second floating gate node of a selected memory cell, the first control end is connected with a programming potential, the second tunneling end is connected with an erasing potential, the second control end, the first tunneling end and the source electrode and well region of the fourth sub-transistor are connected with 0V, the source electrode of the first sub-transistor and the source electrode of the third sub-transistor are connected with a power supply potential, the source electrode and well region of the second sub-transistor are connected with an intermediate potential, and the intermediate potential is smaller than the programming potential and larger than 0V;

when writing '0' into a first floating gate node and writing '1' into a second floating gate node of a selected memory cell, the first tunneling terminal is connected with an erasing potential, the second control terminal is connected with a programming potential, the first control terminal, the second tunneling terminal and the source electrode and well region of the second sub-transistor are connected with 0V, the source electrode of the first sub-transistor and the source electrode of the third sub-transistor are connected with a power supply potential, and the source electrode and well region of the fourth sub-transistor are connected with an intermediate potential;

when the storage unit is selected in a reading mode, the first control end and the second control end apply reading voltage, the first tunneling end, the second tunneling end, the source electrode and the well region of the second sub-transistor and the source electrode and the well region of the fourth sub-transistor are all connected with 0V, and the source electrode of the first sub-transistor and the source electrode of the third sub-transistor are connected with a power supply potential; when reading data '1' stored in the first floating gate node and data '0' stored in the second floating gate node, the second sub-transistor and the third sub-transistor are closed, and the first sub-transistor and the fourth sub-transistor are turned on; when data '0' stored in the first floating gate node and data '1' stored in the second floating gate node are read, the first sub-transistor and the fourth sub-transistor are closed, and the second sub-transistor and the third sub-transistor are turned on.

16. The method of operating a memory array of claim 15, wherein, when writing "1" to the first floating gate node and "0" to the second floating gate node of the selected memory cell, the difference between the gate of the second sub-transistor and the intermediate potential is smaller than the tunneling voltage of the second sub-transistor; when "0" is written to the first floating gate node and "1" is written to the second floating gate node of the selected memory cell, the difference between the gate of the fourth sub-transistor and the intermediate potential is smaller than the tunneling voltage of the fourth sub-transistor.

17. The method of claim 15, wherein when writing a "1" to the first floating gate node and a "0" to the second floating gate node of the selected memory cell, the first control terminal of the non-selected memory cell in the same row as the selected memory cell is programmed to a programming potential, the first control terminal of the non-selected memory cell in a different row from the selected memory cell is programmed to 0 volts, the first tunneling terminal of the non-selected memory cell and the source and well of the second sub-transistor are connected to an intermediate potential, the second tunneling terminal of the non-selected memory cell in the same column as the selected memory cell is programmed to an erase potential, the second tunneling terminal of the non-selected memory cell in a different column from the selected memory cell is connected to 0 volts, and the second control terminal of the non-selected memory cell is connected to the intermediate potential, the source and well regions of the fourth sub-transistor are connected to 0 volt.

18. The method of claim 15, wherein in a write mode, when writing a "0" to the first floating gate node and a "1" to the second floating gate node of the selected memory cell, the second control terminal of the non-selected memory cell in the same row as the selected memory cell is programmed with a potential, the second control terminal of the non-selected memory cell in a different row from the selected memory cell is programmed with a potential of 0V, the potential of the second tunneling terminal of the non-selected memory cell and the source and well junction intermediate potential of the fourth sub-transistor are programmed with a potential, the first tunneling terminal of the non-selected memory cell in the same column as the selected memory cell is erased with a potential, the first tunneling terminal of the non-selected memory cell in a different column from the selected memory cell is programmed with a potential, and the first control terminal of the non-selected memory cell is programmed with an intermediate potential, the source and well regions of the second sub-transistor are connected to 0 volt.

19. The method of claim 15, wherein for the non-selected memory cells in the read mode, the first tunneling terminal, the second tunneling terminal, the source and well region of the second sub-transistor, and the source and well region of the fourth sub-transistor are all connected to 0 volts, the first select transistor and the second select transistor are both turned off, the read voltage is applied to the first control terminal and the second control terminal of the non-selected memory cells in the same row as the selected memory cells, and the potential applied to the first control terminal and the second control terminal of the non-selected memory cells in a different row from the selected memory cells is 0 volts.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a single-layer polycrystalline embedded non-volatile memory unit, a memory array and a working method of the memory array.

Background

In an integrated circuit, a nonvolatile memory (NVM) with a certain size is often used, and the NVM can permanently store recorded data even when the power is off, and is usually used for storing some control programs, instruction codes, or password information.

Several commonly used non-volatile memories include EPROM (erasable programmable read only memory), EEPROM (electrically erasable programmable read only memory), FLASH memory (floating gate FLASH memory), ReRAM (resistive random access memory), FeRAM (ferroelectric memory), and the like. However, these memories are not directly compatible with the existing standard CMOS process and BCD (Bipolar-CMOS-DMOS) process, and additional masks and additional process steps are required in the manufacturing process, so the cost is increased.

With the rapid development of electronic products such as smart phones and computers, some functional module structures also need to introduce a non-volatile memory to store information. For example, power management integrated circuit chip (PMIC) modules are becoming increasingly important to provide stable and efficient power to the overall system, and PMICs also require hundreds or thousands of bits of non-volatile memory to store information. Since the BCD process (Bipolar-CMOS-DMOS) is a process that is compatible with Bipolar, CMOS and DMOS at the same time and can provide transistors that withstand high voltages, the BCD process is generally chosen to fabricate functional block structures such as PMICs. Therefore, how to introduce NVM without adding a reticle in the BCD process is also a focus of attention.

The gate of the Single-layer polysilicon is coupled with the embedded non-volatile memory (Single POLY EEPROM), so that the function of repeated erasing can be realized on the premise of not increasing the layer number of the mask. A circuit diagram of a conventional three-Transistor single-layer polysilicon memory is shown in fig. 1, and mainly includes three parts, namely, a control Transistor (CG), a tunneling Transistor (TG), and a Read Transistor (Read Transistor), where the control Transistor and the tunneling Transistor are usually MOSFET capacitors, and polysilicon gates of the control Transistor, the tunneling Transistor, and the Read Transistor are connected together and coupled to form a Floating Gate (FG) node for storing charges. The charge and discharge of the floating gate node are mainly performed through FN (Fowler-Nordheim) tunneling, electrons can be tunneled from the substrate or the well region to the polysilicon gate through an external bias voltage to be stored, the tunneling current is influenced by the external bias voltage and the thickness of the gate oxide layer, the stored charges influence the switch or current of the sense tube, and therefore "0" or "1" is sensed. However, the loss and variation of the charges stored in the floating gate node of the common structure can cause the voltage fluctuation of the node, affect the current magnitude of the sense tube during the reading process, and possibly cause the reliability of the memory to be reduced.

Disclosure of Invention

Therefore, the technical problem to be solved by the present invention is to overcome the problem of low reliability of the memory in the prior art, so as to provide a single-layer polycrystalline embedded nonvolatile memory cell, a memory array and a working method thereof.

The invention provides a single-layer polycrystal embedded non-volatile memory unit, which comprises: the device comprises a control tube, a tunneling tube, a phase inverter and a reading structure, wherein a well region of the control tube is connected with a control end, and a well region of the tunneling tube is connected with a tunneling end; the phase inverter comprises a first transistor and a second transistor which are opposite in type, a grid electrode of the first transistor, a grid electrode of the second transistor, a grid electrode of the tunneling tube and a grid electrode of the control tube are connected to form a floating grid node, and a drain electrode of the first transistor is connected with a drain electrode of the second transistor and connected with the reading structure.

Optionally, the readout structure includes a first selection transistor and a second selection transistor, the type of the first selection transistor is opposite to that of the second selection transistor, an input terminal of the first selection transistor, an input terminal of the second selection transistor, a drain of the first transistor and a drain of the second transistor are connected, an output terminal of the first selection transistor and an output terminal of the second selection transistor are connected and serve as an output terminal of the readout structure, and the first selection transistor is adapted to be turned on simultaneously with the second selection transistor; or, the readout structure includes a transfer transistor and a selection transistor, the type of the transfer transistor is opposite to the type of the first transistor, the drain of the transfer transistor is connected with the source of the first transistor, and the gate of the transfer transistor is connected with the drain of the first transistor and the drain of the second transistor; the drain electrode of the selection transistor is connected with the source electrode of the transmission transistor, and the source electrode of the selection transistor is used as the output end of the readout structure; alternatively, the readout structure is a single flip-flop.

The invention also provides a memory array comprising the memory cell of the invention.

The invention also provides a working method of the storage array, which comprises the following steps: when the memory cell is selected in a write-in mode, the control terminal is connected with a programming potential, the tunneling terminal is connected with 0V, the source electrode of the first transistor is connected with a power supply potential, the source electrode and the well region of the second transistor are connected with an intermediate potential, the intermediate potential is smaller than the programming potential and larger than 0V, and the floating gate node stores data 1; when the memory cell is selected in an erasing mode, the tunneling end is connected with an erasing potential, the control end, the source electrode of the second transistor and the well region are connected with 0V, the source electrode of the first transistor is connected with a power supply potential, and the floating gate node stores data 0; when the storage unit is selected in a reading mode, the control end applies reading voltage, the tunneling end, the source electrode of the second transistor and the well region are connected with 0V, and the source electrode of the first transistor is connected with power supply potential; when reading data '0' stored in the floating gate node, the first transistor is closed, and the second transistor is turned on; when reading the data '1' stored in the floating gate node, the second transistor is closed, and the first transistor is turned on.

Optionally, when the memory cell is selected in the write mode, a difference between the gate of the second transistor and the intermediate potential is smaller than a tunneling voltage of the second transistor.

The present invention also provides a memory cell comprising: the first control tube comprises a well region connected with a first control end, the well region of the first tunneling tube is connected with a first tunneling end, the well region of the first tunneling tube is connected with the first tunneling end, the first phase inverter comprises a first sub-transistor and a second sub-transistor which are opposite in type, and a grid electrode of the first sub-transistor, a grid electrode of the second sub-transistor, a grid electrode of the first tunneling tube and a grid electrode of the first control tube are connected to form a first floating gate node; the well region of the second control tube is connected with a second control end, the well region of the second tunneling tube is connected with a second tunneling end, the second phase inverter comprises a third sub-transistor and a fourth sub-transistor which are opposite in type, and a grid electrode of the third sub-transistor, a grid electrode of the fourth sub-transistor, a grid electrode of the second tunneling tube and a grid electrode of the second control tube are connected to form a second floating gate node; a bistable cell, the bistable cell comprising: a first additional inverter and a second additional inverter, wherein an output end of the first additional inverter is connected with an input end of the second additional inverter and drains of the third and fourth sub-transistors, and an output end of the second additional inverter is connected with an input end of the first additional inverter and drains of the first and second sub-transistors; a sense structure connected to an output of the first additional inverter and an output of the second additional inverter.

Optionally, the source of the first sub-transistor is connected to a power supply potential; the voltage difference between the grid electrode and the well region of the second sub-transistor is suitable for being smaller than the tunneling voltage of the second sub-transistor when the first floating grid node writes data '1'; the source electrode of the third sub transistor is connected with a power supply potential; the voltage difference between the grid electrode of the fourth sub-transistor and the well region is suitable for being smaller than the tunneling voltage of the fourth sub-transistor when the second floating grid node writes data '1'.

Optionally, the first additional inverter includes a first additional transistor and a second additional transistor of opposite types, a gate of the first additional transistor and a gate of the second additional transistor are connected as an input terminal of the first additional inverter, and a drain of the first additional transistor and a drain of the second additional transistor are connected as an output terminal of the first additional inverter; the second additional inverter comprises a third additional transistor and a fourth additional transistor which are opposite in type, the grid electrode of the third additional transistor and the grid electrode of the fourth additional transistor are connected to serve as the input end of the second additional inverter, and the drain electrode of the third additional transistor and the drain electrode of the fourth additional transistor are connected to serve as the output end of the second additional inverter; the source of the first additional transistor, the source of the third additional transistor, the source of the first sub-transistor and the source of the third sub-transistor are connected and connected to a supply potential; a source of the second additional transistor and a source of the fourth additional transistor are grounded.

Optionally, a coupling ratio of the capacitance value of the first control tube to the capacitance value of the first tunneling tube is greater than or equal to 60%; the coupling ratio of the capacitance value of the second control tube to the capacitance value of the second tunneling tube is greater than or equal to 60%.

Optionally, the area of the channel region at the bottom of the gate in the first control tube is 10 to 30 times that of the channel region at the bottom of the gate in the first tunneling tube; the area of the channel region at the bottom of the grid electrode in the second control tube is 10 times to 30 times that of the channel region at the bottom of the grid electrode in the second tunneling tube.

Optionally, the thickness of the gate dielectric layer of the first tunneling tube is 2 nm-30 nm; the thickness of the gate dielectric layer of the second tunneling tube is 2 nm-30 nm.

Optionally, the well region of the first tunneling tube, the well region of the second tunneling tube, the well region of the first control tube, the well region of the second sub-transistor, and the well region of the fourth sub-transistor are separately disposed, and the well region of the first tunneling tube, the well region of the second tunneling tube, the well region of the first control tube, the well region of the second sub-transistor, and the well region of the fourth sub-transistor are separately disposed with the well region of the first sub-transistor, the well region of the third sub-transistor, the well region of the bistable unit, and the well region of the readout structure.

Optionally, the readout structure includes a first selection transistor and a second selection transistor of the same type, a gate of the first selection transistor is connected to a gate of the second selection transistor, a drain of the first selection transistor is connected to the output terminal of the second additional inverter, a drain of the second selection transistor is connected to the output terminal of the first additional inverter, a source of the first selection transistor serves as the first output terminal, and a source of the second selection transistor serves as the second output terminal; or, the readout structure comprises a comparator, a first input of the comparator is connected to the output of the second additional inverter, a second input of the comparator is connected to the output of the first additional inverter, and the output of the comparator is used as the output of the readout structure.

The invention also provides a memory array comprising a plurality of memory cells of the invention.

The invention also provides a working method of the storage array, which comprises the following steps: when writing '1' into a first floating gate node and writing '0' into a second floating gate node of a selected memory cell, the first control end is connected with a programming potential, the second tunneling end is connected with an erasing potential, the second control end, the first tunneling end and the source electrode and well region of the fourth sub-transistor are connected with 0V, the source electrode of the first sub-transistor and the source electrode of the third sub-transistor are connected with a power supply potential, the source electrode and well region of the second sub-transistor are connected with an intermediate potential, and the intermediate potential is smaller than the programming potential and larger than 0V; when writing '0' into a first floating gate node and writing '1' into a second floating gate node of a selected memory cell, the first tunneling terminal is connected with an erasing potential, the second control terminal is connected with a programming potential, the first control terminal, the second tunneling terminal and the source electrode and well region of the second sub-transistor are connected with 0V, the source electrode of the first sub-transistor and the source electrode of the third sub-transistor are connected with a power supply potential, and the source electrode and well region of the fourth sub-transistor are connected with an intermediate potential; when the storage unit is selected in a reading mode, the first control end and the second control end apply reading voltage, the first tunneling end, the second tunneling end, the source electrode and the well region of the second sub-transistor and the source electrode and the well region of the fourth sub-transistor are all connected with 0V, and the source electrode of the first sub-transistor and the source electrode of the third sub-transistor are connected with a power supply potential; when reading data '1' stored in the first floating gate node and data '0' stored in the second floating gate node, the second sub-transistor and the third sub-transistor are closed, and the first sub-transistor and the fourth sub-transistor are turned on; when data '0' stored in the first floating gate node and data '1' stored in the second floating gate node are read, the first sub-transistor and the fourth sub-transistor are closed, and the second sub-transistor and the third sub-transistor are turned on.

Optionally, when writing "1" to the first floating gate node and "0" to the second floating gate node of the selected memory cell, a difference between the gate of the second sub-transistor and the intermediate potential is smaller than a tunneling voltage of the second sub-transistor; when "0" is written to the first floating gate node and "1" is written to the second floating gate node of the selected memory cell, the difference between the gate of the fourth sub-transistor and the intermediate potential is smaller than the tunneling voltage of the fourth sub-transistor.

Optionally, when writing "1" to the first floating gate node of the selected memory cell and writing "0" to the second floating gate node, the first control terminal of the unselected memory cell located in the same row as the selected memory cell is connected to a programming potential, the first control terminal of the unselected memory cell located in a different row from the selected memory cell is connected to 0v, the first tunneling terminal of the unselected memory cell and the source and well regions of the second sub-transistor are connected to an intermediate potential, the second tunneling terminal of the unselected memory cell located in the same column as the selected memory cell is connected to an erasing potential, the second tunneling terminal of the unselected memory cell located in a different column from the selected memory cell is connected to 0v, the second control terminal of the unselected memory cell is connected to the intermediate potential, and the source and well region of the fourth sub-transistor are connected to 0 v.

Optionally, in the write mode, when writing "0" to the first floating gate node and "1" to the second floating gate node of the selected memory cell, the second control terminal of the non-selected memory cell in the same row as the selected memory cell is connected with the programming potential, the second control terminal of the non-selected memory cell located in a different row from the selected memory cell is connected to 0V, the potential of the second tunneling terminal of the non-selected memory cell and the source and well region of the fourth sub-transistor are connected to the intermediate potential, the first tunneling termination erase potential of the non-selected memory cells in the same column as the selected memory cell, the first tunneling end of the non-selected memory cell located in a different column from the selected memory cell is connected with 0 volt, the first control end of the non-selected memory cell is connected with the middle potential, and the source electrode and the well region of the second sub transistor are connected with 0 volt.

Optionally, for the unselected memory cells in the read mode, the first tunneling terminal, the second tunneling terminal, the source and the well of the second sub-transistor, and the source and the well of the fourth sub-transistor are all connected to 0v, the first selection transistor and the second selection transistor are both turned off, the first control terminal and the second control terminal of the unselected memory cell located in the same row as the selected memory cell are applied with a read voltage, and the first control terminal and the second control terminal of the unselected memory cell located in different rows from the selected memory cell are applied with a potential of 0 v.

The technical scheme of the invention has the following beneficial effects:

according to the storage unit provided by the technical scheme of the invention, the inverter is added behind the floating gate node, so that the reliability of data storage and the accuracy of an output result of the storage unit are improved, and a relatively simple operation method is provided for realizing a storage function.

According to the storage unit provided by the technical scheme of the invention, the first inverter is added behind the first floating gate node, and the second inverter is added behind the second floating gate node, so that the reliability of data storage and the accuracy of an output result of the storage unit are improved, and a relatively simple operation method is provided for realizing a storage function. The bistable unit has two stable working points and one metastable working point, and the structure can ensure that the output voltage automatically recovers to a high level when the input low voltage is subjected to the excursion caused by the external influences of noise or charge loss of a first floating gate node and a second floating gate node and the like; similarly, when the input high voltage is shifted, the output voltage can be restored to a low level. The bistable unit introduced into the storage unit improves the reliability and the retention characteristic of the storage unit, so that the anti-noise and anti-interference capability of the storage unit is enhanced; and because the types of the data stored on the first floating gate node and the second floating gate node are opposite, two output currents with larger difference can be read, the data reading speed is improved, a certain self-detection function can be provided for the circuit, and when one side stores data and is lost, the data can be found in time.

The storage unit provided by the technical scheme of the invention is directly compatible with the prior art, can be used in a BCD (binary-coded decimal) process, a standard CMOS (complementary metal oxide semiconductor) process and an SOI (silicon on insulator) process under the condition of not increasing masks, has strong universality and reduces the development cost; and because the BCD process is high-voltage resistant, the BCD process has the characteristics of various high-voltage devices and electrostatic discharge (ESD) protection. The implementation of the present application on BCD process would have greater advantages.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a circuit diagram of a prior art three-transistor single-layer polysilicon memory;

FIG. 2 is a circuit diagram of a memory cell according to an embodiment of the present invention;

FIG. 3 is a circuit diagram of a memory cell according to another embodiment of the present invention;

FIG. 4 is a circuit diagram of a memory cell according to another embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a memory cell according to another embodiment of the present invention;

FIG. 6 is a voltage transfer characteristic curve of an inverter in a memory cell showing an input-output voltage relationship according to another embodiment of the present invention;

FIG. 7 is a circuit diagram of a memory cell according to another embodiment of the present invention;

FIG. 8 is a circuit diagram of a memory cell according to another embodiment of the present invention;

FIG. 9 is a schematic structural diagram of a memory cell according to another embodiment of the present invention;

FIG. 10 is a voltage transfer characteristic curve representing an input-output voltage relationship for a bistable cell in a memory cell according to another embodiment of the present invention;

FIG. 11 is a circuit diagram of a memory array according to another embodiment of the present invention;

FIG. 12 is a circuit diagram of a memory array according to another embodiment of the present invention;

FIG. 13 is a circuit diagram of a memory array according to another embodiment of the present invention.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

An embodiment of the present invention provides a memory cell, please refer to fig. 2, which includes:

the device comprises a control tube M1, a tunneling tube M2, an inverter and a reading structure, wherein a well region of the control tube M1 is connected with a control end CG, and a well region of the tunneling tube M2 is connected with a tunneling end TG;

the inverter comprises a first transistor M3 and a second transistor M4 which are opposite in type, wherein the grid electrode of the first transistor M3, the grid electrode of the second transistor M4, the grid electrode of the tunneling transistor M2 and the grid electrode of the control transistor M1 are connected to form a floating grid node FG, and the drain electrode of the first transistor M3 and the drain electrode of the second transistor M4 are connected and connected with the reading structure.

In this embodiment, the memory cell is a single-layer poly-embedded non-volatile memory cell.

The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor. The source of the first transistor M3 is connected to the supply potential VDD. The voltage difference between the gate and the well of the second transistor M4 is suitable for being less than the tunneling voltage of the second transistor M4 when the memory cell is selected in the write mode.

In this embodiment, the control transistor M1 is a MOS transistor, such as an NMOS transistor or a PMOS transistor, in which the source, the drain, and the well are connected together, and the source, the drain, and the well of the control transistor M1 are connected together to lead out the control terminal CG. In other embodiments, the control transistor is a MOS capacitor, and the well region of the control transistor M1 leads out the control terminal. In other embodiments, the control tube may also be a MIM capacitor or a MOM capacitor.

In this embodiment, the tunneling tube M2 is a MOS transistor, such as an NMOS transistor or a PMOS transistor, in which a source, a drain, and a well region are connected together, and a tunneling terminal TG is led out by connecting the source, the drain, and the well region of the tunneling tube M2 together. In other embodiments, the tunneling tube is a MOS capacitor, and the well region of the tunneling tube leads out a tunneling end. The tunneling tube conducts or erases charges through FN (Fowler-Nordheim) tunneling of a grid dielectric layer.

In this embodiment, in fig. 2, the control transistor M1 and the tunneling transistor M2 are both PMOS transistors as an example.

In one embodiment, the capacitance C1 of the control transistor M1 is much larger than the capacitance C2 of the tunneling transistor M2, so that the high voltage applied to the control terminal CG or the tunneling terminal TG can be fully coupled to the floating gate node FG. In a specific embodiment, the coupling ratio η between the capacitance value C1 of the control tube M1 and the capacitance value C2 of the tunneling tube M2 is close to 1, for example, greater than or equal to 0.98 and less than 1, η = n. In another embodiment, the coupling ratio η between the capacitance C1 of the control transistor M1 and the capacitance C2 of the tunneling transistor M2 is greater than or equal to 60%, so that the high voltage applied to the control terminal CG or the tunneling terminal TG needs to be large enough to ensure tunneling in the tunneling transistor M2.

In this embodiment, the capacitance C1 of the control tube M1 is much larger than the capacitance C2 of the tunneling tube M2, and accordingly, the area of the channel region at the bottom of the gate in the control tube M1 is much larger than the area of the channel region at the bottom of the gate in the tunneling tube M2, and in a specific embodiment, the area of the channel region at the bottom of the gate in the control tube M1 is 10 times to 30 times the area of the channel region at the bottom of the gate in the tunneling tube M2. In other embodiments, the ratio of the area of the channel region at the bottom of the gate in the control tube M1 to the area of the channel region at the bottom of the gate in the tunneling tube M2 may also be greater than 30 times.

In one embodiment, the gate dielectric layer of the tunneling tube M2 has a thickness of 2nm to 30 nm. According to an FN (Fowler-Nordheim) tunneling current model, the thicker the gate dielectric layer of the tunneling transistor M2 is, the smaller the electric field intensity of the gate dielectric layer is under the same applied voltage, and the smaller the tunneling current is, the longer the required erasing time is; however, if the gate dielectric layer of the tunnel transistor M2 is too thin, direct tunneling or trap-assisted tunneling may occur, which may result in fast charge loss of the floating gate node FG, and thus the retention characteristics of the memory cell may be degraded. Therefore, the thickness of the gate dielectric layer of the tunneling tube M2 is 2 nm-30 nm, and the performance of the storage unit is optimized. The thickness of the corresponding gate dielectric layer can be selected within the range of 2 nm-30 nm according to specific use requirements.

In this embodiment, in order to simplify the manufacturing process and achieve better matching between different structures, the gate dielectric layers of the transistors in the control transistor M1, the first transistor M3, the second transistor M4, and the readout structure are all the same as the gate dielectric layer of the tunneling transistor M2.

In other embodiments, the thicknesses of the gate dielectric layer of the control transistor M1, the first transistor M3, the second transistor M4, the transistors in the readout structure, and at least a portion of the tunneling transistor M2 are different.

In this embodiment, the gate dielectric layer is a gate oxide layer. In other embodiments, the material of the gate dielectric layer may be other high K (dielectric constant) materials, where K is greater than or equal to 3.9). The material of the gate comprises polysilicon.

In this embodiment, the readout structure includes a first selection transistor M6 and a second selection transistor M5, the type of the first selection transistor M6 is opposite to the type of the second selection transistor M5, an input terminal of the first selection transistor M6, an input terminal of the second selection transistor M5, a drain of the first transistor M3 and a drain of the second transistor M4 are connected, an output terminal of the first selection transistor M6 and an output terminal of the second selection transistor M5 are connected and serve as an output terminal OUT of the readout structure, and the first selection transistor M6 is adapted to be turned on simultaneously with the second selection transistor M5.

One of the input terminal and the output terminal of the first selection transistor M6 is the source of the first selection transistor M6, and the other is the drain of the first selection transistor M6. One of the input terminal and the output terminal of the second selection transistor M5 is the source of the second selection transistor M5, and the other is the drain of the second selection transistor M5.

A gate of the first selection transistor M6 as a first selection terminal Select, and a gate of the second selection transistor M5 as a second selection terminal。

In this embodiment, referring to fig. 2, the first selection transistor M6 is an NMOS transistor, and the second selection transistor M5 is a PMOS transistor. In other embodiments, the first selection transistor is a PMOS transistor, and the second selection transistor M5 is an NMOS transistor.

In another embodiment, referring to fig. 3, the readout structure includes a pass transistor M7 and a select transistor M8, the type of the pass transistor M7 is opposite to the type of the first transistor M3, the drain of the pass transistor M7 is connected to the source of the first transistor M3, and the gate of the pass transistor M7 is connected to the drain of the first transistor M3 and the drain of the second transistor M4; the drain of the selection transistor M8 is connected to the source of the pass transistor M7, and the source of the selection transistor M8 serves as the output OUT of the readout structure.

In another embodiment, referring to fig. 4, the sensing structure is a single flip-flop 10, and the flip-flop 10 is a D flip-flop. In other embodiments, the flip-flop may also be an RS flip-flop.

Referring to fig. 5, fig. 5 is a structural diagram corresponding to the memory cell in fig. 2 to 3, in fig. 5, only the control transistor M1, the tunneling transistor M2, the first transistor M3 and the second transistor M4 are shown, and the readout structure is not shown.

Referring to fig. 5, for convenience of description, the well region of the tunneling transistor M2 is referred to as a first well region 201, the well region of the control transistor M1 is referred to as a second well region 202, the well region of the first transistor M3 is referred to as a third well region 203, the well region of the second transistor M4 is referred to as a fourth well region 204, and the first well region 201, the second well region 202, the third well region 203, and the fourth well region 204 are located in the substrate 200. The gate structure of the tunneling transistor M2 includes a gate dielectric layer 100 and a gate 101 on the gate dielectric layer 100. The gate structure of the control transistor M1 includes a gate dielectric layer 102 and a gate 103 on the gate dielectric layer 102. The gate structure of the first transistor M3 includes a gate dielectric layer 104 and a gate electrode 105 on the gate dielectric layer 104. The gate structure of the second transistor M4 includes a gate dielectric layer 106 and a gate electrode 107 on the gate dielectric layer 104.

It should be noted that, in this embodiment, at least the well region of the tunneling transistor M2, the well region of the control transistor M1, and the well region of the second transistor need to be separately disposed, that is, the well region of the tunneling transistor M2 and the other well regions are separately disposed, the well region of the control transistor M1 and the other well regions are separately disposed, and the well region of the second transistor and the other well regions are separately disposed. The tunneling tube M2, the control tube M1 and the second transistor which need to bear high voltage are all arranged in a single well region, so that the interference of the high voltage borne by the substrate to other devices is reduced.

The storage unit in the embodiment is directly compatible with the existing process, can be used in a BCD (binary-coded decimal) process, a standard CMOS (complementary metal oxide semiconductor) process and an SOI (silicon on insulator) process under the condition of not increasing masks, has strong universality and reduces development cost; and because the BCD process is high-voltage resistant, the BCD process has the characteristics of various high-voltage devices and electrostatic discharge (ESD) protection. The implementation of the present application on BCD process would have greater advantages.

In the memory cell in the embodiment, the inverter is added behind the floating gate node, so that the reliability of data storage and the accuracy of an output result of the memory cell are improved, and a relatively simple operation method is provided to realize a storage function.

Accordingly, the present invention also provides a memory array, referring to fig. 11 and 12, including a plurality of memory cells (refer to fig. 2 to 5) as described above. The plurality of memory cells are arranged in an array.

For the memory cell of the current output type (refer to fig. 3), a current serial output array as shown in fig. 11 is employed, and for the memory cell of the voltage output type (refer to fig. 2), a voltage parallel output array as shown in fig. 12 is employed. The current output type only needs one sensitive amplifier to sample and amplify signals in the same column, and the voltage output type needs more multiplexers to select output end units, so that the area needed by the voltage type is larger.

Correspondingly, the present invention further provides a working method of a memory array, referring to the content of table 1, where table 1 shows the potentials of each port of the memory array during the write, erase, and read operations, including:

when the memory cell is selected in the write mode, the control terminal CG is connected to a programming potential VPP, the tunneling terminal TG is connected to 0v, the source of the first transistor M3 is connected to a power supply potential VDD, the source Vs and the well region of the second transistor M4 are connected to an intermediate potential VMID, the intermediate potential VMID is smaller than the programming potential and greater than 0v, and the floating gate node stores data "1";

when the memory cell is selected in an erasing mode, the tunneling terminal TG is connected with an erasing potential VE, the control terminal CG and the source and well region of the second transistor M4 are connected with 0v, the source of the first transistor M3 is connected with a power supply potential VDD, and the floating gate node stores data "0";

when the memory cell is selected in a reading mode, the control terminal CG applies a reading voltage Vr, the tunneling terminal TG, the second transistor M4 and the source of the well region are connected with 0V, and the source of the first transistor M3 is connected with a power supply potential VDD; when reading a data "0" stored by the floating gate node, the first transistor M3 is turned off and the second transistor M4 is turned on; when reading data "1" stored by the floating gate node FG, the second transistor M4 is turned off and the first transistor M3 is turned on.

When the memory cell is selected in the write mode, the difference between the gate of the second transistor M4 and the intermediate potential VMID is smaller than the tunneling voltage of the second transistor M4.

In one specific embodiment, VDD is 5 volts, VPP is 18.5 volts, VE is 18.5 volts, VMID is 10V, and Vr is 5 volts. It should be noted that in other embodiments, reasonable data may also be set as needed, which is not limited.

In this embodiment, data writing and erasing are performed through the tunneling transistor M2, so that repeated erasing and writing can be prevented from affecting the performance of the first transistor M3 and the second transistor M4, and readout errors can be avoided.

When the memory cell is selected in the write mode, the first selection transistor M6 is turned off by the potential of the first selection terminal, and the second selection transistor M5 is turned off by the potential of the second selection terminal. Specifically, when the first selection transistor M6 is an NMOS transistor and the second selection transistor M5 is a PMOS transistor, the first selection terminal is connected to 0v, and the second selection terminal is connected to a high potential, so that the second selection transistor M5 is turned off.

TABLE 1

When the memory cell is selected in the write mode, a large forward voltage drop occurs on the tunneling transistor M2, electrons tunnel from the channel below the gate dielectric layer of the tunneling transistor M2 through the gate dielectric layer and are stored in the gate of the tunneling transistor M2, the data stored in the floating gate node FG is "1", and in this process, the potential on the floating gate node FG continuously drops, so that the forward voltage on the tunneling transistor M2 continuously drops, the threshold voltage of the first transistor M3 decreases, the threshold voltage of the second transistor M4 increases, and the tunneling transistor M2 is tunneled until the threshold voltage is insufficient.

For the unselected memory cells in the write mode, the control terminals CG of the unselected memory cells in the same row as the selected memory cell are connected to the programming potential VPP, the control terminals CG of the unselected memory cells in a different row as the selected memory cell are connected to 0v, the potential of the tunneling terminal TG is the intermediate potential VMID to ensure that the voltage drop across the tunneling transistor M2 cannot reach the tunneling voltage of the tunneling transistor M2, and the source Vs of the second transistor M4 and the well region are connected to the intermediate potential VMID to ensure that the voltage drop across the second transistor M4 cannot reach the tunneling voltage of the second transistor M4. For the memory cells that are not selected in the write mode, the potential of the first selection terminal causes the first selection transistor M6 to turn off, and the potential of the second selection terminal causes the second selection transistor M5 to turn off.

When the memory cell is selected in the erase mode, the first selection transistor M6 is turned off by the potential of the first selection terminal, and the second selection transistor M5 is turned off by the potential of the second selection terminal. Specifically, when the first selection transistor M6 is an NMOS transistor and the second selection transistor M5 is a PMOS transistor, the first selection terminal is connected to 0v, and the second selection terminal is connected to a high potential, so that the second selection transistor M5 is turned off.

For the memory cell selected in the erase mode, a large reverse voltage drop occurs in the tunneling transistor M2, electrons will tunnel from the gate of the tunneling transistor M2 through the gate dielectric layer of the tunneling transistor M2 and be extracted into the well region of the tunneling transistor M2, the data stored in the floating gate node FG is "0", and in the process, the potential on the floating gate node FG will continuously increase, so the reverse voltage on the tunneling transistor M2 will continuously decrease, the threshold voltage of the first transistor M3 increases, and the threshold voltage of the second transistor M4 decreases until eventually the tunneling transistor M2 is not enough.

For the unselected memory cells in the erase mode, the potential of the tunneling terminal TG of the unselected memory cells in the same column as the selected memory cell is the erase potential VE, the potential of the tunneling terminal TG of the unselected memory cells in the different column from the selected memory cell is 0v, the potential of the control terminal CG is the intermediate potential VMID to ensure that the voltage drop across the tunneling transistor cannot reach the tunneling voltage, and the potentials of the source Vs of the second transistor and the well region are 0 v.

When the memory cell is not selected in the erase mode, the first selection terminal is at a potential that turns off the first selection transistor M6, and the second selection terminal is at a potential that turns off the second selection transistor M5. Specifically, when the first selection transistor M6 is an NMOS transistor and the second selection transistor M5 is a PMOS transistor, the first selection terminal is connected to 0v, and the second selection terminal is connected to a high potential, so that the second selection transistor M5 is turned off.

When the memory cell is selected in the read mode, the first and second selection transistors M6 and M5 are both turned on.

For the unselected memory cells in the read mode, the tunneling terminal TG and the source of the second transistor M4 are both connected to 0v, the first selection transistor M6 and the second selection transistor M5 are both turned off, the read voltage Vr is applied to the control terminal CG of the unselected memory cells in the same row as the selected memory cell, and the potential applied to the control terminal CG of the unselected memory cells in different rows from the selected memory cell is 0 v.

In the present application, an inverter is used to amplify a voltage signal generated by charges stored in a floating gate node FG, a voltage transfer characteristic curve (VTC) of the inverter, which represents an input-output voltage relationship, is shown in fig. 6, a horizontal axis in fig. 6 represents an input voltage of the inverter, a vertical axis in fig. 6 represents an output voltage of the inverter, the inverter has a high noise margin, and when the input voltage is less than VIL, the output of the inverter is all logic "1", and when the input voltage is greater than VIH, the output of the inverter is all logic "0". Even if the electrons stored in the floating gate node FG change to a certain extent, the voltage output from the memory cell can be kept at a constant high level or low level, and the output result hardly changes. Therefore, the reliability of reading the storage data of the floating gate node FG is obviously improved.

Another embodiment of the present invention further provides a memory cell, referring to fig. 7, including:

the first control tube M11, the first tunneling tube M21 and the first inverter, the well region of the first control tube M11 is connected with the first control end CG11, the well region of the first tunneling tube M21 is connected with the first tunneling end TG11, the first inverter comprises a first sub-transistor M31 and a second sub-transistor M41 which are opposite in type, and the gate of the first sub-transistor M31, the gate of the second sub-transistor M41, the gate of the first tunneling tube M21 and the gate of the first control tube M11 are connected to form a first floating gate node FG 11;

the second control tube M12, the second tunneling tube M22 and the second inverter, the well region of the second control tube M12 is connected to the second control end CG12, the well region of the second tunneling tube M22 is connected to the second tunneling end TG12, the second inverter includes a third sub-transistor M32 and a fourth sub-transistor M42, which are opposite in type, and the gate of the third sub-transistor M32, the gate of the fourth sub-transistor M42, the gate of the second tunneling tube M22 and the gate of the second control tube M12 are connected to form a second floating gate node FG 10;

a bistable cell, the bistable cell comprising: a first additional inverter and a second additional inverter, an output terminal of the first additional inverter being connected to an input terminal of the second additional inverter and to the drains of the third and fourth sub-transistors M32 and M42, an output terminal of the second additional inverter being connected to an input terminal of the first additional inverter and to the drains of the first and second sub-transistors M31 and M41;

a sense structure connected to an output of the first additional inverter and an output of the second additional inverter.

In this embodiment, the memory cell is a single-layer poly-embedded non-volatile memory cell.

In this embodiment, the first control transistor M11 is a MOS transistor, such as an NMOS transistor or a PMOS transistor, in which the source, the drain, and the well are connected together, and the source, the drain, and the well of the first control transistor M11 are connected together to lead out the first control terminal CG 11. In other embodiments, the first control tube is a MOS capacitor, and the well region of the first control tube leads out the first control end. In other embodiments, the first control tube may also be a MIM capacitor or a MOM capacitor.

In this embodiment, the second control transistor M12 is a MOS transistor, such as an NMOS transistor or a PMOS transistor, in which the source, the drain, and the well are connected together, and the source, the drain, and the well of the second control transistor M12 are connected together to lead out the second control terminal CG 12. In other embodiments, the second control tube is a MOS capacitor, and the well region of the second control tube leads out the second control end. In other embodiments, the second control tube may also be a MIM capacitor or a MOM capacitor.

In this embodiment, the first tunneling transistor M21 is a MOS transistor, such as an NMOS transistor or a PMOS transistor, in which a source, a drain, and a well region are connected together, and the source, the drain, and the well region of the first tunneling transistor M21 are connected together to lead out the first tunneling terminal TG 11. In other embodiments, the first tunneling transistor is a MOS capacitor, and the well region of the first tunneling transistor leads out a tunneling end. The first tunneling tube conducts or erases charges through FN (Fowler-Nordheim) tunneling of a grid dielectric layer.

In this embodiment, the second tunneling transistor M22 is a MOS transistor, such as an NMOS transistor or a PMOS transistor, in which the source, the drain, and the well region are connected together, and the source, the drain, and the well region of the second tunneling transistor M22 are connected together to lead out the second tunneling terminal TG 12. In other embodiments, the second tunneling transistor is a MOS capacitor, and the well region of the second tunneling transistor leads out a tunneling end. The second tunneling tube conducts or erases charges through FN (Fowler-Nordheim) tunneling of the grid dielectric layer.

In this embodiment, in fig. 7, the first control tube M11, the second control tube M12, the first tunneling tube M21, and the second tunneling tube M22 are all PMOS transistors as an example.

In one embodiment, the capacitance of the first control transistor M11 is much larger than that of the first tunneling transistor M21, so that the high voltage applied to the first control terminal CG11 or the first tunneling terminal TG11 can be fully coupled to the first floating gate node FG 11. In a specific embodiment, the coupling ratio of the capacitance value of the first control tube M11 to the capacitance value of the first tunneling tube M21 is close to 1, for example, greater than or equal to 0.98 and less than 1. In another embodiment, the coupling ratio of the capacitance of the first control transistor M11 to the capacitance of the first tunneling transistor M21 is greater than or equal to 60%, so that the high voltage applied to the first control terminal CG11 or the first tunneling terminal TG11 needs to be large enough to ensure tunneling of the first tunneling transistor M21.

In this embodiment, the capacitance of the first control tube M11 is much larger than that of the first tunneling tube M21, and accordingly, the area of the gate of the first control tube M11 is much larger than that of the gate of the first tunneling tube M21, and in a specific embodiment, the area of the channel region at the bottom of the gate of the first control tube M11 is 10 to 30 times larger than that of the channel region at the bottom of the gate of the first tunneling tube M21. In other embodiments, the ratio of the area of the channel region at the bottom of the gate in the first control tube M11 to the area of the channel region at the bottom of the gate in the first tunneling tube M21 may also be greater than 30 times.

In one embodiment, the capacitance of the second control transistor M12 is much larger than that of the second tunneling transistor M22, so that the high voltage applied to the second control terminal CG12 or the second tunneling terminal TG12 can be fully coupled to the second floating gate node FG 10. In a specific embodiment, the coupling ratio of the capacitance value of the second control tube M12 to the capacitance value of the second tunneling tube M22 is close to 1, for example, greater than or equal to 0.98 and less than 1. In another embodiment, the coupling ratio of the capacitance of the second control transistor M12 to the capacitance of the second tunneling transistor M22 is greater than or equal to 60%, so that the high voltage applied to the second control terminal CG12 or the second tunneling terminal TG12 needs to be large enough to ensure tunneling at the first tunneling terminal TG 11.

In this embodiment, the capacitance of the second control tube M12 is much larger than that of the second tunneling tube M22, and accordingly, the area of the gate of the second control tube M12 is much larger than that of the gate of the second tunneling tube M22, and in a specific embodiment, the area of the channel region at the bottom of the gate of the second control tube M12 is 10 to 30 times larger than that of the channel region at the bottom of the gate of the second tunneling tube M22. In other embodiments, the ratio of the area of the channel region at the bottom of the gate in the second control tube M12 to the area of the channel region at the bottom of the gate in the second tunneling tube M22 may also be greater than 30 times.

In one embodiment, the thickness of the gate dielectric layer of the first tunneling tube M21 is 2nm to 30nm, and the thickness of the gate dielectric layer of the second tunneling tube M22 is 2nm to 30 nm.

In this embodiment, in order to simplify the manufacturing process in terms of process and achieve better matching between different structures, the first control tube M11, the first tunneling tube M21, the first sub transistor M31, the second sub transistor M41, the second control tube M12, the second tunneling tube M22, the third sub transistor M32, the fourth sub transistor M42, the first additional inverter, the second additional inverter, the readout structure, and the gate dielectric layers of the middle and upper transistors are arranged to have the same thickness. In other embodiments, the thicknesses of the gate dielectric layers of at least some of the first control transistor M11, the first tunneling transistor M21, the first sub transistor M31, the second sub transistor M41, the second control transistor M12, the second tunneling transistor M22, the third sub transistor M32, the fourth sub transistor M42, the first additional inverter, the second additional inverter, and the readout structure and the transistors in the middle are different.

In this embodiment, the gate dielectric layer is a gate oxide layer. In other embodiments, the material of the gate dielectric layer may be other high K (dielectric constant) materials, where K is greater than or equal to 3.9). The material of the gate comprises polysilicon.

In this embodiment, the first sub-transistor M31 and the third sub-transistor M32 are PMOS transistors, and the second sub-transistor M41 and the fourth sub-transistor M42 are NMOS transistors. The source electrode of the first sub transistor M31 is connected with a power supply potential VDD; the voltage difference between the gate and well regions of the second sub-transistor M41 is suitable for being less than the tunneling voltage of the second sub-transistor M41 when the first floating gate node FG11 writes data "1"; the source of the third sub-transistor M32 is connected to a power supply potential; the voltage difference between the gate and well regions of the fourth sub-transistor M42 is suitable for being less than the tunneling voltage of the fourth sub-transistor M42 when the second floating gate node FG10 writes data "1".

The first additional inverter comprises a first additional transistor M51 and a second additional transistor M61 of opposite types, the gate of the first additional transistor M51 and the gate of the second additional transistor M61 are connected as input terminals of the first additional inverter, and the drain of the first additional transistor M51 and the drain of the second additional transistor M61 are connected as output terminals of the first additional inverter.

The second additional inverter comprises a third additional transistor M71 and a fourth additional transistor M81 of opposite types, the gate of the third additional transistor M71 and the gate of the fourth additional transistor M81 are connected as the input of the second additional inverter, and the drain of the third additional transistor M71 and the drain of the fourth additional transistor M81 are connected as the output of the second additional inverter. The source of the first additional transistor M51, the source of the third additional transistor M71, the source of the first sub-transistor M31 and the source of the third sub-transistor M32 are connected and connected to a supply potential VDD; the source of the second additional transistor M61 and the source of the fourth additional transistor M81 are grounded.

The first additional transistor M51 and the third additional transistor M71 are PMOS transistors, and the second additional transistor M61 and the fourth additional transistor M81 are NMOS transistors.

The information stored by the first floating gate node FG11 and the second floating gate node FG10 are reversed, with the second floating gate node FG10 storing data "1" when the first floating gate node FG11 stores data "0" and the second floating gate node FG10 storing data "0" when the first floating gate node FG11 stores data "1".

In this embodiment, the readout structure includes a first selection transistor M9 and a second selection transistor M10 of the same type, the gate of the first selection transistor M9 is connected to the gate of the second selection transistor M10, the drain of the first selection transistor M9 is connected to the output of the second additional inverter, the drain of the second selection transistor M10 is connected to the output of the first additional inverter, the source of the first selection transistor M9 is used as the first output terminal OUT1, and the source of the second selection transistor M10 is used as the second output terminal OUT 2.

The first selection transistor M9 and the second selection transistor M10 are both NMOS transistors.

The gate of the first Select transistor M9 and the gate of the second Select transistor M10 are connected to a Select terminal Select'.

In another embodiment the sensing structure is a comparator Q, a first input of said comparator Q being connected to an output of said second additional inverter, a second input of said comparator Q being connected to an output of said first additional inverter, an output of said comparator Q being an output of said sensing structure.

Referring to fig. 9, fig. 9 is a structural view corresponding to the memory cell in fig. 7.

Referring to fig. 9, for convenience of explanation, the well region of the first tunneling transistor M21, the well region of the second tunneling transistor M22, the well region of the first control transistor M11, the well region of the second control transistor M12, the well regions of the second sub-transistor M41 and the fourth sub-transistor M42, the well region of the first sub-transistor M31, the well region of the third sub-transistor M32, the well region of the first additional transistor M51 and the well region of the second additional transistor M61, the well region of the third additional transistor M71 and the well region of the fourth additional transistor M81, and the well region of the first selection transistor M9 and the well region of the second selection transistor M10 are located in the substrate 200. In this embodiment, the well region of the first tunneling transistor M21, the well region of the second tunneling transistor M22, the well region of the first control transistor M11, the well region of the second control transistor M12, the well region of the second sub transistor M41, and the well region of the fourth sub transistor M42 are separately disposed, and the well region of the first tunneling transistor M21, the well region of the second tunneling transistor M22, the well region of the first control transistor M11, the well region of the second control transistor M12, the well region of the second sub transistor M41, and the well region of the fourth sub transistor M42, the well region of the first sub transistor, the well region of the third sub transistor, the well region of the bistable unit, and the well region of the readout structure are separately disposed. The first tunneling tube M21, the second tunneling tube M22, the first control tube M11, the second control tube M12, the second sub transistor M41 and the fourth sub transistor M42 which need to bear high voltage are all made in separate well regions, so that the interference of the high voltage borne by the substrate on other devices is reduced.

The storage unit in the embodiment is directly compatible with the existing process, can be used in a BCD (binary-coded decimal) process, a standard CMOS (complementary metal oxide semiconductor) process and an SOI (silicon on insulator) process under the condition of not increasing masks, has strong universality and reduces development cost; and because the BCD process is high-voltage resistant, the BCD process has the characteristics of various high-voltage devices and electrostatic discharge (ESD) protection. The implementation of the present application on BCD process would have greater advantages.

In the memory cell in the embodiment, the first inverter is added behind the first floating gate node, and the second inverter is added behind the second floating gate node, so that the reliability of data storage and the accuracy of an output result of the memory cell are improved, and a relatively simple operation method is provided to realize a storage function.

The input-output Voltage Transformation Curve (VTC) of the bistable cell is shown in fig. 10, the bistable cell has A, B two stable operating points and a metastable operating point C, such a structure can make the output voltage automatically recover to high level when the input low voltage is deviated by external influences such as noise or charge loss of the first floating gate node and the second floating gate node, and the recovery process is shown as the voltage variation process of V0 → V1 → V2 → V3 in fig. 10; similarly, when the input high voltage is shifted, the output voltage can be restored to a low level.

In the embodiment, the bistable unit is introduced into the storage unit, so that the reliability and the retention characteristic of the storage unit are improved, and the anti-noise and anti-interference capability of the storage unit is enhanced; and because the types of the data stored on the first floating gate node and the second floating gate node are opposite, two output currents with larger difference can be read, the data reading speed is improved, a certain self-detection function can be provided for the circuit, and when one side stores data and is lost, the data can be found in time.

Accordingly, the present invention also provides a memory array, referring to fig. 13, including a plurality of memory cells (refer to fig. 7 to 8) as described above. The plurality of memory cells are arranged in an array.

In fig. 13, TG includes TG11 and TG12, CG includes CG11 and CG12, and Vs includes Vs1 and Vs 2.

Correspondingly, the present invention further provides a method for operating a memory array, which, with reference to the contents in table 2, includes:

when writing "1" into the first floating gate node FG11 and "0" into the second floating gate node FG10 of the selected memory cell in the write mode, the first control terminal CG11 is connected to the programming potential VPP, the second tunnel is connected to the erasing potential VE, the sources and well regions of the second control terminal CG12, the first tunnel terminal TG11 and the fourth sub-transistor M42 are connected to 0 volt, the source of the first sub-transistor M31 and the source of the third sub-transistor M32 are connected to the power supply potential VDD, the source Vs1 and the well region of the second sub-transistor M41 are connected to the intermediate potential VMID, the intermediate potential VMID is smaller than the programming potential and larger than 0 volt, the first floating gate node FG11 stores data "1", and the second floating gate node FG10 stores data "0";

when writing "0" into the first floating gate node FG11 and "1" into the second floating gate node FG10 of the selected memory cell in the write mode, the first tunneling terminal TG11 is connected to the erase potential VE, the second control terminal CG12 is connected to the program potential VPP, the first control terminal CG11, the second tunneling terminal TG12 and the source and well region of the second sub-transistor M41 are connected to 0v, the source of the first sub-transistor M31 and the source of the third sub-transistor M32 are connected to the power supply potential VDD, the source Vs1 and well region of the fourth sub-transistor M42 are connected to the intermediate potential VMID, the first floating gate node FG11 stores data "0", and the second floating gate node FG10 stores data "1";

when the memory cell is selected in the read mode, the first control terminal CG11 and the second control terminal CG12 apply a read voltage Vr, the first tunneling terminal TG11, the second tunneling terminal TG12, the source Vs1 and the well region of the second sub-transistor M41, and the source Vs2 and the well region of the fourth sub-transistor M42 are all connected to 0 volt, and the source of the first sub-transistor M31 and the source of the third sub-transistor M32 are connected to a power supply potential VDD; when reading data "1" stored by the first floating gate node FG11 and data "0" stored by the second floating gate node FG10, the second sub-transistor M41 and the third sub-transistor M32 are turned off, and the first sub-transistor M31 and the fourth sub-transistor M42 are turned on; when reading data "0" stored by the first floating gate node FG11 and data "1" stored by the second floating gate node FG10, the first sub-transistor M31 and the fourth sub-transistor M42 are turned off, and the second sub-transistor M41 and the third sub-transistor M32 are turned on.

When "1" is written to the first floating gate node FG11 and "0" is written to the second floating gate node FG10 of the selected memory cell in the write mode, the difference between the gate of the second sub-transistor M41 and the intermediate potential VMID is smaller than the tunneling voltage of the second sub-transistor M41.

When "0" is written to the first floating gate node FG11 and "1" is written to the second floating gate node FG10 of the selected memory cell in the write mode, the difference between the gate of the fourth sub-transistor M42 and the intermediate potential VMID is smaller than the tunneling voltage of the fourth sub-transistor M42.

In one specific embodiment, VDD is 5 volts, VPP is 18.5 volts, VE is 18.5 volts, VMID is 10V, and Vr is 5 volts. It should be noted that in other embodiments, reasonable data may also be set as needed, which is not limited.

In this embodiment, the writing of "0" and "1" into the first floating gate node FG11 is performed through the first tunneling transistor M21, so that the repeated writing of "0" and "1" into the first floating gate node FG11 can be prevented from affecting the performance of the first sub-transistor M31 and the third sub-transistor M32, and the readout error can be avoided. The writing of "0" and "1" into the second floating gate node FG10 is performed through the second tunneling transistor M22, which prevents the repeated writing of "0" and "1" into the second floating gate node FG10 from affecting the performance of the second sub-transistor M41 and the fourth sub-transistor M42, and thus avoids the occurrence of a read error.

In the write mode, the potential of the selection terminal Select' turns off the first selection transistor M9 and the second selection transistor M10. Specifically, when the first and second selection transistors M9 and M10 are NMOS transistors, the selection terminal Select' is connected to 0v, so that the first and second selection transistors M9 and M10 are turned off.

When "1" is written into the first floating gate node FG11 and "0" is written into the second floating gate node FG10 of the selected memory cell in the write mode, a large forward voltage drop occurs in the first tunneling transistor M21, electrons will tunnel from the channel under the gate dielectric layer of the first tunneling transistor M21 through the gate dielectric layer and are stored into the gate of the first tunneling transistor M21, the data stored in the first floating gate node FG11 is "1", and in this process, the potential on the first floating gate node FG11 will continuously drop, so the forward voltage on the first tunneling transistor M21 will continuously drop, the threshold voltage of the first sub-transistor M31 decreases, the threshold voltage of the second sub-transistor M41 increases, and the tunneling of the first tunneling transistor M21 will occur until the threshold voltage is not sufficient.

When "0" is written into the first floating gate node FG11 and "1" is written into the second floating gate node FG10 of the selected memory cell in the write mode, a large forward voltage drop occurs on the second tunneling transistor M22, electrons will tunnel through the gate dielectric layer from the channel under the gate dielectric layer of the second tunneling transistor M22 and are stored into the gate of the second tunneling transistor M22, the data stored in the second floating gate node FG10 is "1", in this process, the potential on the second floating gate node FG10 will continuously drop, so the forward voltage on the second tunneling transistor M22 will continuously drop, the threshold voltage of the third sub-transistor M32 decreases, the threshold voltage of the fourth sub-transistor M42 increases, and the tunneling of the second tunneling transistor M22 will occur until the threshold voltage is not sufficient.

When writing '1' into the first floating gate node FG11 of the selected memory cell and writing '0' into the second floating gate node FG10 in the write mode, the first control terminal CG11 of the unselected memory cell in the same row with the selected memory cell is connected to the programming potential VPP, the first control terminal CG11 of the unselected memory cell in the different row with the selected memory cell is connected to 0V, the potential of the first tunneling terminal TG11 of the unselected memory cell is the intermediate potential VMID to ensure that the voltage drop on the first tunneling transistor can not reach the tunneling voltage of the first tunneling transistor, the source and well region of the second sub-transistor are connected to the intermediate potential VMID to ensure that the voltage drop on the second sub-transistor can not reach the tunneling voltage of the second sub-transistor, the second tunneling terminal TG12 of the unselected memory cell in the same column with the selected memory cell is connected to the erasing potential VE, and the second tunneling terminal 12 of the unselected memory cell in the different column with the selected memory cell is connected to TG 0V, the second control terminal CG12 of the unselected memory cell is connected to the intermediate potential VMID to ensure that the voltage drop across the second tunneling transistor cannot reach the tunneling voltage, and the source and well of the fourth sub-transistor are connected to 0 v.

When writing '0' into the first floating gate node FG11 of the selected memory cell and writing '1' into the second floating gate node FG10 in the write mode, the second control terminal CG12 of the unselected memory cell in the same row with the selected memory cell is connected to the programming potential VPP, the second control terminal CG12 of the unselected memory cell in the different row with the selected memory cell is connected to 0V, the potential of the second tunneling terminal TG12 of the unselected memory cell is the intermediate potential VMID to ensure that the voltage drop of the second tunneling transistor can not reach the tunneling voltage of the second tunneling transistor, the source and the well of the fourth sub-transistor are connected to the intermediate potential VMID to ensure that the voltage drop of the fourth sub-transistor can not reach the tunneling voltage of the fourth sub-transistor, the first tunneling terminal TG11 of the unselected memory cell in the same column with the selected memory cell is connected to the erasing potential VE, and the first tunneling terminal 11 of the unselected memory cell in the different column with the selected memory cell is connected to TG 0V, the unselected first control terminal CG11 is connected to the intermediate potential VMID to ensure that the voltage drop across the first tunneling transistor cannot reach the tunneling voltage, and the source and well regions of the second sub-transistor are connected to 0 v.

When the memory cell is selected in the read mode, the potential of the selection terminal Select' makes both the first selection transistor M9 and the second selection transistor M10 conductive. When the first selection transistor M9 and the second selection transistor M10 are NMOS transistors, VDD is applied to the gates of the first selection transistor M9 and the second selection transistor M10, so that both the first selection transistor M9 and the second selection transistor M10 are turned on.

For the unselected memory cells in the read mode, the first tunneling terminal TG11, the second tunneling terminal TG12, the source and well region of the second sub-transistor, and the source and well region of the fourth sub-transistor are all connected to 0v, the first selection transistor M9 and the second selection transistor M10 are all turned off, the read voltage Vr is applied to the first control terminal CG11 and the second control terminal CG12 of the unselected memory cells in the same row as the selected memory cell, and the potential applied to the first control terminal CG11 and the second control terminal CG12 of the unselected memory cells in a different row from the selected memory cell is 0 v.

TABLE 2

Finally, the first floating gate node FG11 and the second floating gate node FG10 store two opposite data, thereby realizing differential output.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.