阅读说明：本技术 显示面板及显示屏 (Display panel and display screen ) 是由 金玉 李磊 王恩来 陆蕴雷 张鹏辉 马明冬 黄佳兵 胡月敏 于 2021-01-27 设计创作，主要内容包括：本申请实施例提供的显示面板及显示屏,涉及显示技术领域。源极层远离有效显示区的一端相对于平坦化层伸出,在刻蚀该源极层上的阳极膜层时,源极层可以作为正极,阳极膜层可以作为负极进行刻蚀,如此可以加速位于源极层上阳极膜层的刻蚀速度,避免在源极层远离有效显示区的一端残留阳极膜层,从而可以在源极层远离有效显示区的一侧有效的隔断残留阳极膜层,避免残留阳极膜层形成连续的导电走线。此外,在覆晶薄膜的金手指与显示面板的邦定焊盘邦定的过程中,可以避免金手指上的导电金球与连续导电走线接触而导致相邻源极层短路引起的显示暗线问题,提升显示面板的显示效果及市场竞争力。(The embodiment of the application provides a display panel and a display screen, and relates to the technical field of display. The one end that effective display area was kept away from to the source electrode layer stretches out for the planarization layer, when the positive pole rete on this source electrode layer of sculpture, the source electrode layer can regard as anodal, the positive pole rete can be as the negative pole and carry out the sculpture, so can be with higher speed lie in the etching speed of positive pole rete on the source electrode layer, avoid keeping away from the one end in effective display area at the source electrode layer and remain the positive pole rete, thereby can keep away from the effectual wall in one side in effective display area at the source electrode layer and remain the positive pole rete, avoid remaining the continuous electrically. In addition, in the process of bonding the golden finger of the chip on film and the bonding pad of the display panel, the problem of display dark lines caused by short circuit of an adjacent source layer due to the fact that the conductive golden ball on the golden finger is in contact with the continuous conductive routing can be avoided, and the display effect and the market competitiveness of the display panel are improved.)

1. The display panel, wherein the display panel comprises an active display area and a bonding area far away from one side of the active display area, the display panel further comprises:

an array substrate;

the planarization layer is positioned on the array substrate, a plurality of planarization layer openings are formed in the bonding area corresponding to the array substrate by the planarization layer, each planarization layer opening is positioned on a different source electrode layer of the array substrate, and a source electrode layer exposed at the planarization layer openings forms a bonding pad bonded with a golden finger of a chip on film;

the end of the source layer far away from the effective display area is positioned outside the orthographic projection of the planarization layer.

2. The display panel of claim 1, wherein the planarization layer openings include a first planarization layer opening on a side near the active display area and a second planarization layer opening on a side away from the active display area;

the first planarization layer opening comprises a first opening edge, a second opening edge and a third opening edge, wherein the first opening edge and the second opening edge extend in the direction far away from the effective display area, and the third opening edge is connected with one end, close to the effective display area, of the first opening edge and the second opening edge;

the second planarization layer opening comprises a fourth opening edge, a fifth opening edge, a sixth opening edge and a seventh opening edge, wherein the sixth opening edge and the seventh opening edge extend along the direction far away from the effective display area, the fourth opening edge is connected between one end, far away from the effective display area, of the first opening edge and one end, close to the effective display area, of the sixth opening edge, and the fifth opening edge is connected between one end, far away from the effective display area, of the second opening edge and one end, close to the effective display area, of the seventh opening edge.

3. The display panel of claim 2, wherein a distance between the first opening edge and the second opening edge is less than a distance between the sixth opening edge and a seventh opening edge.

4. The display panel of claim 3, wherein orthographic projections of the first opening edge, the second opening edge and the third opening edge are located in the corresponding source layers, and orthographic projections of the sixth opening edge and the seventh opening edge are located on two sides of the corresponding source layers, respectively.

5. The display panel of claim 4, wherein a distance between the sixth opening edge and the seventh opening edge is greater than a sum of a width of the gold finger and a diameter of two conductive gold balls.

6. The display panel of claim 5, wherein a distance between an edge of the sixth opening and an edge of a source layer adjacent to the edge of the sixth opening is greater than 1 um; the distance between the edge of the seventh opening and the edge of the source layer close to the edge of the seventh opening is larger than 1 um.

7. The display panel of claim 1, wherein the planarization layer opening includes an eighth opening edge, a ninth opening edge, and a tenth opening edge connecting the eighth opening edge and the ninth opening edge near an end of the effective display area, extending in a direction away from the effective display area;

orthographic projections of the eighth opening edge, the ninth opening edge and the tenth opening edge are positioned in the corresponding source electrode layers.

8. The display panel according to any one of claims 1 to 7,

the different source electrode layers are mutually isolated, and a plurality of bonding pads are mutually parallel;

preferably, the width of the source layer is 17um to 19um, the spacing distance between adjacent source layers is 6um to 7um, the spacing distance between adjacent bonding pads is 10um to 11um, and the width of the bonding pads is 13.5um to 14.5 um;

preferably, the width of the source layer is 18um, the spacing distance between adjacent source layers is 6.7um, the spacing distance between adjacent bonding pads is 10.7um, and the width of the bonding pads is 14 um.

9. The display panel according to any one of claims 1 to 7, further comprising a demultiplexing circuit and a test circuit;

the demultiplexing circuit is positioned on one side of the bonding pad close to the effective display area and connected with one end of the bonding pad close to the effective display area, and the demultiplexing circuit is used for decomposing one path of signal into multiple paths of signals of layers;

the testing circuit is located the bonding pad is kept away from one side of effective display area, and with the bonding pad is kept away from the one end of effective display area is connected, the testing circuit is used for testing whether there is the short circuit between the adjacent electrically conductive pad.

10. A display screen, wherein the display screen comprises a chip on film, a gold finger located on the chip on film, and the display panel of any one of claims 1 to 9;

the chip on film is bonded with the bonding pad on the display panel through the golden finger.

Technical Field

The application relates to the technical field of display, in particular to a display panel and a display screen.

Background

The display effect of the display panel is a key index for measuring the quality of the display screen, however, when the display effect of the display panel is detected, the problem that the picture displayed by the display panel has a display dark line is found, the dark line can influence the watching experience of a user, and the market competitiveness of the product is reduced. How to remove the dark lines existing in the display panel when displaying the picture is a technical problem that needs to be solved urgently by the technical personnel in the field.

Disclosure of Invention

In order to overcome the technical problem of displaying dark lines mentioned in the above technical background, embodiments of the present application provide a display panel and a display screen.

In a first aspect of the present application, a display panel is provided, where the display panel includes an effective display area and a bonding area away from one side of the effective display area, and the display panel further includes:

an array substrate;

the planarization layer is positioned on the array substrate, a plurality of planarization layer openings are formed in the bonding area corresponding to the array substrate by the planarization layer, each planarization layer opening is positioned on a different source electrode layer of the array substrate, and a source electrode layer exposed at the planarization layer openings forms a bonding pad bonded with a golden finger of a chip on film;

the end of the source layer far away from the effective display area is positioned outside the orthographic projection of the planarization layer.

In the structure, one end of the source electrode layer, which is far away from the effective display area, extends out relative to the planarization layer, in the process of subsequently manufacturing the anode film layer, the anode film layer can cover the source electrode layer, when the anode film layer on the source electrode layer is etched, the source electrode layer can be used as an anode, the anode film layer can be used as a cathode for etching, the etching speed of the anode film layer on the source electrode layer can be accelerated, the anode film layer is prevented from being remained at one end of the source electrode layer, which is far away from the effective display area, and therefore continuous conductive wiring can be formed by effectively blocking the remained anode film layer on one side of the source electrode layer, which. In the process of bonding the golden finger of the chip on film and the bonding pad of the display panel, the problem of display dark lines caused by short circuit of an adjacent source electrode layer due to the contact of the conductive golden ball on the golden finger and the continuous conductive routing can be avoided.

In one possible embodiment of the present application, the planarization layer openings include a first planarization layer opening on a side close to the effective display area and a second planarization layer opening on a side far from the effective display area;

the first planarization layer opening comprises a first opening edge, a second opening edge and a third opening edge, wherein the first opening edge and the second opening edge extend in the direction far away from the effective display area, and the third opening edge is connected with one end, close to the effective display area, of the first opening edge and the second opening edge;

the second planarization layer opening comprises a fourth opening edge, a fifth opening edge, a sixth opening edge and a seventh opening edge, wherein the sixth opening edge and the seventh opening edge extend along the direction far away from the effective display area, the fourth opening edge is connected between one end, far away from the effective display area, of the first opening edge and one end, close to the effective display area, of the sixth opening edge, and the fifth opening edge is connected between one end, far away from the effective display area, of the second opening edge and one end, close to the effective display area, of the seventh opening edge.

In one possible embodiment of the application, the distance between the first opening edge and the second opening edge is smaller than the distance between the sixth opening edge and the seventh opening edge.

In one possible embodiment of the present disclosure, orthographic projections of the first opening edge, the second opening edge and the third opening edge are located in the corresponding source layers, and orthographic projections of the sixth opening edge and the seventh opening edge are located on two sides of the corresponding source layers, respectively.

In one possible embodiment of the present application, the distance between the sixth opening edge and the seventh opening edge is greater than the sum of the width of the gold finger and the diameter of the two conductive gold balls.

In one possible embodiment of the present application, a distance between an edge of the sixth opening and an edge of the source layer near the edge of the sixth opening is greater than 1 um; the distance between the edge of the seventh opening and the edge of the source layer close to the edge of the seventh opening is larger than 1 um.

In one possible embodiment of the present application, the planarization layer opening includes an eighth opening edge, a ninth opening edge, and a tenth opening edge, wherein the eighth opening edge and the ninth opening edge extend in a direction away from the active display area, and the tenth opening edge connects one end of the eighth opening edge and one end of the ninth opening edge close to the active display area;

orthographic projections of the eighth opening edge, the ninth opening edge and the tenth opening edge are positioned in the corresponding source electrode layers.

In one possible embodiment of the present application, the different source layers are isolated from each other, and the bonding pads are also parallel to each other;

the width of source layer is 17um ~ 19um, and the spacing distance between the adjacent source layer is 6um ~ 7um, and the spacing distance between the adjacent bonding pad is 10um ~ 11um, the width 13.5um ~ 14.5um of bonding pad.

Preferably, the width of the source layer is 18um, the spacing distance between adjacent source layers is 6.7um, the spacing distance between adjacent bonding pads is 10.7um, and the width of the bonding pad is 14 um.

In one possible embodiment of the present application, the display panel further includes a demultiplexing circuit and a test circuit;

the demultiplexing circuit is positioned on one side of the bonding pad close to the effective display area and connected with one end of the bonding pad close to the effective display area, and the demultiplexing circuit is used for decomposing one path of signal into multiple paths of signals of layers;

the testing circuit is located one side that the effective display area was kept away from to the bonding pad, and with the bonding pad is kept away from the one end of effective display area and is connected, the testing circuit is used for testing whether there is the short circuit between the adjacent electrically conductive pad.

In a second aspect of the present application, a display screen is further provided, where the display screen includes a chip on film, a gold finger located on the chip on film, and the display panel of the first aspect;

the chip on film is bonded with the bonding pad on the display panel through the golden finger so as to drive the display panel to display through the display driving chip.

Compared with the prior art, the display panel and the display screen that this application embodiment provided, the one end that makes the source electrode layer keep away from effective display area stretches out for the planarization layer, when the positive pole rete on this source electrode layer of sculpture, the source electrode layer can regard as anodal, the positive pole rete can regard as the negative pole to carry out the sculpture, so can be with higher speed the etching speed that is located the positive pole rete on the source electrode layer, avoid keeping away from the one end in effective display area at the source electrode layer and remain the positive pole rete, thereby can keep away from the effectual wall of one side in effective display area at the source electrode layer and remain the continuous line of. In addition, in the process of bonding the golden finger of the chip on film and the bonding pad of the display panel, the problem of display dark lines caused by short circuit of an adjacent source layer due to the fact that the conductive golden ball on the golden finger is in contact with the continuous conductive routing can be avoided, and the display effect and the market competitiveness of the display panel are improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.

FIG. 1 is a schematic diagram of the distribution of Data lines in a V-Style pixel arrangement;

FIG. 2 is a diagram illustrating a film structure of a display panel according to the prior art;

FIG. 3 is a schematic diagram illustrating etching of the anode film layer on the planarization layer in FIG. 2;

FIG. 4 is another schematic diagram illustrating etching of the anode film layer on the planarization layer in FIG. 2;

FIG. 5 is a schematic diagram of adjacent bond pad shorts;

fig. 6 is a schematic diagram of a film structure of a display panel according to an embodiment of the present disclosure;

FIG. 7 is a diagram illustrating the relationship between the planarization layer and the source layer according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of electrochemical etching for etching an anode layer on a planarization layer;

FIG. 9 is a schematic diagram of electrochemical etching for etching an anode layer over a source layer;

FIG. 10 is a diagram illustrating the dimension relationship between a source layer and a bond pad according to an embodiment of the present invention;

FIG. 11 is a schematic view illustrating a position relationship between a planarization layer opening and a source layer according to one possible implementation of the present disclosure;

FIG. 12 is a schematic view of a position relationship between a planarization layer opening and a source layer according to another possible implementation of the present disclosure;

FIG. 13 is a schematic diagram of a possible circuit for connection to a bond pad according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that, in case of conflict, different features in the embodiments of the present application may be combined with each other.

The inventors have found, by analyzing the cause of the occurrence of the display dark line, that one of the causes of the occurrence of the display dark line is as follows.

For the sake of example, referring to fig. 1, in the V-Style pixel arrangement, G pixel units only use one Data line, and R pixel units and B pixel units share the Data line and are alternately arranged. In a pixel driving circuit of a G pixel unit, when a scanning signal line is turned on, a Data line for all G pixel units provides a low potential signal and writes the low potential signal into a lower plate of a storage capacitor, the lower plate of the storage capacitor is connected to a gate of a driving transistor, the driving transistor is turned on, a power supply potential can act on an anode of a light emitting device (e.g., an OLED) through the driving transistor, the light emitting device controls a light emitting material to emit light according to a potential difference between the anode and a cathode, and the G pixel unit is turned on. At this time, all the R pixel units and the B pixel units are required to be in an off state, in the pixel driving circuits of the R pixel units and the B pixel units, a Data line shared by the R pixel units and the B pixel units supplies a high potential, and the high potential is correspondingly written into the lower electrode plate of the corresponding storage capacitor, so that the driving transistor is in a high-resistance state, and a power supply potential cannot be written into the anodes of the light emitting devices corresponding to the R pixel units and the B pixel units, so that a potential difference between the anodes and the cathodes of the light emitting devices is small, and the R pixel units and the B pixel units emit light poorly. If the adjacent bonding pad is short-circuited (namely, the Data line of the G pixel unit is short-circuited with the Data lines of the R pixel unit and the B pixel unit), when a green picture is displayed, the electric potential provided by the Data lines of the R pixel unit and the B pixel unit can be pulled high by the electric potential provided by the Data lines of the adjacent G pixel unit, so that the adjacent G pixel unit does not emit light, and a dark line appears. Similarly, when displaying a red image and a blue image, the adjacent bonding pads are short-circuited, so that the R pixel unit does not emit light or the B pixel unit does not emit light, thereby forming a dark line.

Referring to fig. 2, the inventor further analyzes the reason for the short circuit between adjacent bonding pads, and finds that, in the manufacturing process of the display panel 1 ', a planarization layer opening 210' is formed On the bonding Area 40 'On the side of the Active Area (AA) away from the display panel 1', and a bonding pad 1101 'for bonding with a gold finger 30' of a Chip On Flex (COP) is formed On the bonding Area 40 ', wherein the bonding pad 1101' is formed by the source layer 110 'exposed at the position corresponding to the planarization layer opening 210'. The planarization layer 20 ' protrudes with respect to the source layer 110 ' on the side of the effective display area away from the display panel 1 '.

The following describes the etching process of the anode film layer 16 'at the end of the bonding pad 1101' away from the active display area with reference to the drawings.

Firstly, coating photoresist on an anode film layer 16 'on the whole array substrate 10'; then, removing the photoresist at the position of the anode film layer 16' to be etched; finally, the etching solution is used to remove the anode film layer 16' at the position to be etched. Referring to fig. 3 and 4, since the side surface of the planarization layer at the end of the bonding pad 1101 'away from the effective display area has a certain inclination angle, when the photoresist is coated, the photoresist is easy to accumulate in the area (the tape area, the area shown by the dashed line frame in the figure) adjacent to the bottom surface when the photoresist flows to the area, which results in a thicker photoresist layer in the area, and further, when the photoresist is exposed by developing, the photoresist is easy to remain in the tape area, which affects the etching of the subsequent anode film layer 16'. In addition, when carrying out the sculpture, can know according to bernoulli's principle among the hydrodynamics, when the sculpture liquid medicine upwards flows along the side, the kinetic energy of sculpture liquid medicine can partially convert gravitational potential energy into for the velocity of flow of sculpture liquid medicine in the Taper district is a little bigger than the velocity of flow on inclined plane, and the vortex is formed easily in the Taper district, and it is big to lead to the sculpture liquid medicine to climb the degree of difficulty in the Taper district, and the sculpture liquid medicine replacement is slower, makes the sculpture speed slower. When the etching liquid medicine flows downwards along the side surface, the gravitational potential energy of the etching liquid medicine can be partially converted into kinetic energy, so that the flow velocity of the etching liquid medicine in the Taper area is larger than that of the inclined surface, a vortex is easily formed in the Taper area, the acting force of the etching liquid medicine in the Taper area is smaller, the etching effect of the etching liquid medicine is poor, and the etching speed is slower. Referring to fig. 5, the anode film 16 ' in the Taper region is difficult to remove during etching due to the above two reasons, and a continuous conductive line formed by the remaining anode film 16 ' is formed on the side of the planarization layer 20 ' at the end of the bonding pad away from the active display region.

Referring to fig. 2 again, when the bond pad 1101 ' of the display panel 1 is bonded to the gold finger 30 ' of the chip on film, the conductive gold ball (Au ball)31 ' on the gold finger 30 ' is electrically connected to the residual anode film layer 16 '. Referring to fig. 5 again, if the remaining anode film layer 16 ' on the side of the adjacent bonding pad 1101 ' away from the effective display area of the display panel 1 ' is conducted with the conductive gold ball 31 ' on the corresponding gold finger 30 ', the adjacent bonding pad 1101 ' and the corresponding adjacent gold finger 30 ' are shorted by the remaining anode film layer 16 ', so that a dark line is formed when the display panel 1 ' displays.

In order to solve the above technical problems, the inventor has innovatively designed the following technical scheme that the end of the source electrode layer far away from the effective display area extends out relative to the planarization layer, so that the etching speed of the anode film layer on the source electrode layer can be accelerated, the anode film layer is prevented from remaining at the end of the source electrode layer far away from the effective display area, and the remaining anode film layer can be effectively blocked at the side of the source electrode layer far away from the effective display area. Specific implementations of the present application will be described in detail below with reference to the accompanying drawings.

Referring to fig. 6, fig. 6 is a schematic diagram illustrating a film structure of a display panel according to an embodiment of the present disclosure, in which a display panel 1 may include an array substrate 10 and a planarization layer 20 on the array substrate 10. The planarization layer 20 forms a plurality of planarization layer openings 210 in the corresponding bonding region 40 of the array substrate 10. Referring to fig. 7, different planarization layer openings 210 are formed on different source layers 110 of the array substrate 10, and the source layer exposed at the planarization layer openings 210 forms bonding pads 1101 for bonding with the gold fingers 30 of the chip on film.

In the embodiment, the end of the source layer 110 away from the effective display area is outside the front projection of the planarization layer 20.

Taking the material of the anode film 16 as ITO/Ag/ITO and the material of the source layer 110 as Ti/Al/Ti as an example, the following description is made with reference to fig. 8 and 9, where fig. 8 shows a schematic diagram of etching when the anode film 16 is on the planarization layer 20, and fig. 9 shows a schematic diagram of etching when the anode film 16 is on the source layer 110. As can be seen from fig. 8, when the anode film layer 16 is etched, the Ag in the anode film layer 16 is used as a negative electrode, the ITO is used as a positive electrode, and electrochemical etching is performed, and the ITO layer and the Ag layer in the anode film layer 16 are etched one by one; in a reverse view of fig. 9, when the anode film layer 16 is etched, the whole anode film layer 16 is used as a negative electrode, Ti is used as a positive electrode for electrochemical corrosion, and the ITO layer and the Ag layer in the anode film layer 16 are simultaneously etched away. From the above comparison, the anode film layer 16 on the source layer 110 is etched faster and easier. In addition, the source layer 110 has a better light reflection performance, and the light dose when the photoresist layer is removed can be increased through the reflected light, so that the photoresist layer is not easy to remain, and the anode film layer 16 on the source layer 110 can be further ensured to be etched and removed.

It can be seen that, in the above structure, the end of the source layer 110 away from the effective display area of the display panel 1 protrudes relative to the planarization layer 20, in the subsequent process of fabricating the anode layer 16, the anode layer 16 covers the source layer 110, when the anode layer on the source layer 110 is etched, the source layer 110 can be used as an anode, and the anode layer 16 can be used as a cathode for etching, so as to accelerate the etching speed of the anode layer 16 on the source layer 110. Meanwhile, the light reflection of the source layer 110 can increase the light dose to ensure that the etching of the anode film 16 is not affected due to the existence of the photoresist layer residue, and the anode film line is prevented from being remained at the end of the source layer 110 far away from the effective display area of the display panel 1, so that the conductive line formed by the remained anode film 16 can be effectively cut off at the side of the source layer 110 far away from the effective display area of the display panel 1. Therefore, in the process of bonding the gold finger 30 of the chip on film to the bonding pad 1101 of the display panel 1, the problem of display dark lines caused by short circuit of the adjacent source layer 110 due to the contact of the conductive gold ball on the gold finger 30 and the residual anode film layer 16 is solved, and the display effect and the market competitiveness of the display panel 1 are improved.

Referring to fig. 6 again, the array substrate 10 may include a substrate 11, a buffer layer 12 and a driving layer 13.

The substrate 11 may be a glass substrate, the buffer layer 12 is located on one side of the substrate 11, and the driving layer 13 is located on one side of the buffer layer 12 away from the substrate 11. In the present embodiment, the buffer layer 12 may be made of an inorganic material, such as silicon oxide, silicon nitride, silicon oxynitride, etc. In the present embodiment, the buffer layer 12 may have a double-layer structure of a silicon nitride (SiNx) layer and a silicon oxide (SiOx) layer sequentially formed on the substrate 11.

The driving layer 13 may include an active layer 131, a gate insulating layer 132, a gate electrode 133, a source electrode 134, a drain electrode 135, a first insulating layer 136, a second insulating layer 137, and a first electrode 138 and a second electrode 139 for forming a capacitor.

The active layer 131 is formed on the buffer layer 12 and partially covers the buffer layer 12, the active layer 131 may be formed of an inorganic semiconductor (e.g., amorphous silicon or polycrystalline silicon), an organic semiconductor, or an oxide semiconductor, and the active layer 131 may include a source region (S), a drain region (D), and a channel region (ACT) in an effective display region, and a channel layer (P-Si) in a non-display region.

A gate insulating layer 132 is formed on the active layer 131 and the buffer layer 12 not covered by the active layer 131 to insulate the active layer 131 from the gate electrode 133. The gate insulating layer 132 may be made of, but not limited to, silicon oxide or silicon nitride.

The gate electrode 133 is formed on one side of the gate insulating layer 132 at a corresponding position of the active layer 131, and the gate electrode 133 may be formed using one or more of metal Al, Mo, Cu, Ti, or other low resistivity metal material. Meanwhile, a first electrode 138 of a capacitor is also formed on the gate insulating layer 132. The first electrode 138 is formed on the gate insulating layer 132 and partially covers the gate insulating layer 132, the materials of the first electrode 138 and the gate electrode 133 may be the same, and a first metal layer M1 may be formed on the gate insulating layer 132 to form the gate electrode 133 and the first electrode 138 at the same time.

The first insulating layer 136 is formed on the gate insulating layer 132 and covers the gate 133 and the first electrode 138, and the second electrode 139 is located on a side of the first insulating layer 136 corresponding to the first electrode 138. The first insulating layer 136 serves to insulate and isolate the gate electrode 133 from the source and drain electrodes 134 and 135, and the first electrode 138 from the second electrode 139. The first insulating layer 136 electrically insulates the gate electrode 133 from the source and drain electrodes 134 and 135, respectively, and forms a capacitance between the first electrode 138 and the second electrode 139. The first insulating layer 136 may also be made of inorganic materials, such as: silicon nitride and silicon oxide. The second electrode 138 is located in the second metal layer M2 formed over the first insulating layer 136.

The second insulating layer 137 is formed on the first insulating layer 136 and covers the second electrode 139, and is used for isolating the source 134, the drain 135 and the second electrode 139, so that the source 134, the drain 135 and the second electrode 139 are insulated from each other. The second insulating layer 137 may also be formed of an inorganic material such as silicon nitride and silicon oxide. The second insulating layer 137 may have a double-layer structure or a triple-layer structure of silicon nitride and silicon oxide.

A source electrode 134 and a drain electrode 135 are formed on the second insulating layer 137, the source electrode 134 is electrically connected to a source region (S) in the active layer 131 through a via hole, and the drain electrode 135 is electrically connected to a drain region (D) in the active layer 131 through a via hole. The electrode material of the gate electrode 133, the source electrode 134, the drain electrode 135, the first electrode 138, and the second electrode 139 may be one or more of Al, Mo, Cu, Ti, or other low resistivity metal material. The source 134 and the drain 135 are located on the second insulating layer 137 in the third metal layer M3. In the present embodiment, the third metal layer M3 further includes a source signal receiving layer 111 for receiving a power signal (ELVDD signal) and electrically connected to the second electrode 139 through a via hole formed in the second insulating layer 137, and a source layer 110 for receiving a data signal (Vdata signal).

A planarization layer 20, an anode film layer 16, a pixel defining layer 17, a pixel layer 18, and a cathode film layer 19 are formed in this order on the side of the driving layer 13 remote from the substrate 11. The driving layer 13 includes a TFT (Thin Film Transistor) structure formed of a gate electrode 133, a source electrode 134, a drain electrode 135, an active layer 131, and the like. The anode film layer 16 is electrically connected to the drain electrode 135 of the TFT through the planarization layer via. A pixel layer 18 is located in the pixel opening defined by the pixel defining layer 17, and a cathode film layer 19 is located on a side of the pixel layer 18 remote from the substrate 11.

In the present embodiment, the different source layers 110 are isolated from each other, and the bonding pads 1101 defined by the planarization layer openings 210 of the different source layers 110 may be parallel to each other. Referring to fig. 10, the width La of the source layer 110 may range from 17um to 19um, the spacing distance Lb between adjacent source layers may range from 6um to 7um, the spacing distance Lc between adjacent bonding pads 1101 may range from 10um to 11um, and the width Ld of the bonding pads 1101 may range from 13.5um to 14.5 um.

In the embodiment, the width La of the source layer 110 may be 17um, 17.2um, 17.6um, 18um, 18.5um, 19um, etc., and preferably, the width La of the source layer 110 is 18 um. The distance Lb between adjacent source layers 110 may be 6um, 6.3um, 6.5um, 6.7um, 6.9um, 7um, etc., and preferably the distance Lb between adjacent source layers 110 is 6.7 um. The spacing distance Lc between adjacent bonding pads 1101 may be 10um, 10.3um, 10.4um, 10.7um, 10.9um, 11um, etc., and preferably, the spacing distance Lc between adjacent bonding pads 1101 is 10.7 um. The width of bond pad 1101 may range from 13.5um, 13.8um, 14um, 14.2um, 14.3um, 14.5um, etc., with the width of bond pad 1101 preferably being 14 um. When the source layer 110 and the bonding pad 1101 are fabricated with the above dimensions, the width of the gold finger may preferably be 12 um.

In one possible implementation manner of the embodiment of the present application, referring to fig. 11, the planarization layer opening 210 may include a first planarization layer opening 211 at a side far from the effective display area of the display panel 1 and a second planarization layer opening 212 at a side close to the effective display area of the display panel 1. Wherein the width of the first planarizing layer opening 211 is greater than the width of the second planarizing layer opening 212.

The first planarization layer opening 211 may include a first opening edge 211a, a second opening edge 211b extending in a direction away from the effective display area of the display panel 1, and a third opening edge 211c connecting the first opening edge 211a and the second opening edge 211b and being close to one end of the effective display area of the display panel 1.

The second planarizing layer opening 212 may include a fourth opening edge 212a, a fifth opening edge 212b, and a sixth opening edge 212c and a seventh opening edge 212d extending in a direction away from the effective display area of the display panel 1, wherein the fourth opening edge 212a is connected between an end of the first opening edge 211a away from the effective display area of the display panel 1 and an end of the sixth opening edge 212c close to the effective display area of the display panel 1, and the fifth opening edge 212b is connected between an end of the second opening edge 211b away from the effective display area of the display panel 1 and an end of the seventh opening edge 212d close to the effective display area of the display panel 1.

In the present embodiment, the distance between the first opening edge 211a and the second opening edge 211b is smaller than the distance between the sixth opening edge 212c and the seventh opening edge 212d, that is, the width of the opening of the first planarizing layer 211 is smaller than the width of the opening of the second planarizing layer 212.

In this embodiment, orthographic projections of the first opening edge 211a, the second opening edge 211b and the third opening edge 211c are located in the corresponding source layer 110, and orthographic projections of the sixth opening edge 212c and the seventh opening edge 212d are located on two sides of the corresponding source layer 110, respectively. In this embodiment, the shape of the planarization layer opening 210 may be a raised letter.

Further, in the present embodiment, the distance between the sixth opening edge 212c and the seventh opening edge 212d is greater than the sum of the width of the gold finger and the diameter of the two conductive gold balls. This arrangement ensures that the conductive gold balls do not contact the remaining anode film layer 16 when the bond pad 1101 of the display panel 1 is bonded by the gold finger 30 of the chip on film, thereby further ensuring that the problem of dark line display caused by short circuit in the adjacent source layer 110 is avoided.

In a preferred embodiment of the above embodiment, the distance between the edge of the opening of the second planarization layer opening 212 extending in the direction away from the effective display area of the display panel 1 and the edge of the source layer close to the opening edge is greater than 1um for the given dimensions of the source layer 110 and the bonding pad 1101. That is, as shown in fig. 11, the distance d2 between the sixth opening edge 212c and the source layer edge near the sixth opening edge 212c is greater than 1 um; the distance d1 between the seventh opening edge 212d and the source layer edge near the seventh opening edge 212d is greater than 1 um.

Further, in the present embodiment, the length of the second planarizing layer opening 212 in the direction away from the effective display area of the display panel 1 may be greater than 15 um. By the arrangement, complex migration in the etching liquid medicine can be avoided in the process of etching the anode film layer 16, and the etching effect of the anode film layer 16 is ensured.

Referring to fig. 12, in another possible implementation manner of the embodiment of the present application, the planarization layer opening 210 may include an eighth opening edge 210a, a ninth opening edge 210b extending in a direction away from the effective display area of the display panel 1, and a tenth opening edge 210c connecting the eighth opening edge 210a and the ninth opening edge 210b to one end of the effective display area of the display panel 1. The orthographic projections of the eighth opening edge 210a, the ninth opening edge 210b and the tenth opening edge 210c are located in the corresponding source layers 110.

The planarization layer opening 210 of the two embodiments provided above can make one end of the source layer 110 away from the effective display area of the display panel 1 extend out relative to the planarization layer 210, when etching the anode layer 16 on the source layer 110, the source layer 110 can be used as an anode, and the anode layer 16 can be used as a cathode for etching, so as to accelerate the etching speed of the anode layer 16 on the source layer 110, and avoid the anode layer 16 remaining at one end of the source layer 110 away from the effective display area of the display panel 1, thereby effectively blocking the remaining anode layer 16 at one side of the source layer 110 away from the effective display area of the display panel 1, and avoiding the remaining anode layer 16 forming a continuous conductive trace. Therefore, in the process of bonding the gold finger 30 of the chip on film to the bonding pad 1101 of the display panel 1, the problem of display dark lines caused by short circuits of the adjacent source layer 110 due to the contact of the conductive gold ball on the gold finger 30 and the conductive trace is solved, and the display effect and the market competitiveness of the display panel 1 are improved.

In the embodiment of the present application, referring to fig. 13, the display panel 1 may further include a multiplexing circuit (Demux circuit) and a testing circuit (CT circuit); the demultiplexing circuit is located on one side of the bonding pad 1101 close to the effective display area of the display panel 1, and is connected to one end of the bonding pad 1101 close to the effective display area of the display panel 1, and the demultiplexing circuit is used for decomposing one path of signal into multiple paths of signals of layers.

The testing circuit is located on one side of the bonding pad 1101 far away from the effective display area of the display panel 1, and is connected to one end of the bonding pad 1101 far away from the effective display area of the display panel 1, and the testing circuit is used for testing whether a short circuit exists between adjacent bonding pads 1101, specifically, because the end of the source layer 110 far away from the effective display area of the display panel 1 protrudes relative to the planarization layer, it can be detected through the CT circuit whether the adjacent bonding pad 1101 is short-circuited due to the fact that the end of the source layer 110 far away from the effective display area of the display panel 1 is communicated with the residual anode film layer 16. Can detect above-mentioned harmfulness after display panel 1 preparation is accomplished, in time screen out bad display panel 1, avoid will having the display panel 1 that adjacent bonding pad 1101 short circuit to flow into subsequent display screen equipment link, lead to the bad technical problem of display screen after the equipment. Therefore, after the display panel 1 is manufactured, the CT circuit can detect the display defect caused by the short circuit between the adjacent source layers 110 due to the communication between the residual anode film layer 16 and the source layers 110 at the end far from the effective display area of the display panel 1.

The embodiment of the present application further provides a display screen, where the display screen includes a chip on film, a gold finger located on the chip on film, and the display panel described above. The chip on film is bonded with the bonding pad on the display panel through the golden finger. The display screen adopting the display panel can effectively avoid bad display dark lines, and the display effect and the market competitiveness of the display screen are improved.

The display panel and display screen that this application embodiment provided, the one end that effective display area was kept away from to the source electrode layer stretches out for the planarization layer, when the positive pole rete on this source electrode layer of sculpture, the source electrode layer can be as anodal, the positive pole rete can regard as the negative pole to carry out the sculpture, so can be with higher speed the etching speed that lies in the positive pole rete on the source electrode layer, avoid keeping away from the one end in effective display area at the source electrode layer and remain the positive pole rete, thereby can keep away from the effectual wall in one side in effective display area at the source electrode layer and remain the positive pole rete, avoid remaining the continuous. In addition, in the process of bonding the golden finger of the chip on film and the bonding pad of the display panel, the problem of display dark lines caused by short circuit of an adjacent source layer due to the fact that the conductive golden ball on the golden finger is in contact with the continuous conductive routing can be avoided, and the display effect and the market competitiveness of the display panel are improved.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.