Discrete metal-insulator-metal (MIM) energy storage components and methods of manufacture

文档序号：573182 发布日期：2021-05-18 浏览：41次中文

阅读说明：本技术 分立金属-绝缘体-金属(mim)能量存储部件和制造方法 (Discrete metal-insulator-metal (MIM) energy storage components and methods of manufacture ) 是由文森特·德马里斯里卡德·安德森穆罕默德·阿明·萨利姆玛丽亚·比隆德安德斯·约翰逊于 2019-10-07 设计创作，主要内容包括：一种分立金属-绝缘体-金属(MIM)能量存储部件,该能量存储部件包括：MIM布置；用于电容器部件的外部电连接的第一连接结构；用于电容器部件的外部电连接的第二连接结构；以及至少部分地嵌入MIM布置的电绝缘封装材料。该MIM布置包括：第一电极层；从第一电极层生长的多个传导纳米结构；传导控制材料,其覆盖多个传导纳米结构中的每个纳米结构以及未被传导纳米结构覆盖的第一电极层；以及覆盖传导控制材料的第二电极层。(A discrete metal-insulator-metal (MIM) energy storage component, the energy storage component comprising: MIM arrangement; a first connection structure for external electrical connection of the capacitor component; a second connection structure for external electrical connection of the capacitor component; and an electrically insulating encapsulation material at least partially embedded in the MIM arrangement. The MIM arrangement comprises: a first electrode layer; a plurality of conductive nanostructures grown from a first electrode layer; a conductive control material covering each of the plurality of conductive nanostructures and the first electrode layer not covered by the conductive nanostructures; and a second electrode layer overlying the conduction control material.)

1. A discrete metal-insulator-metal (MIM) energy storage component, the energy storage component comprising:

a MIM arrangement, comprising:

a first electrode layer;

a plurality of conductive nanostructures grown from the first electrode layer;

a conductive control material covering each of the plurality of conductive nanostructures and the first electrode layer not covered by the conductive nanostructures; and

a second electrode layer overlying the conduction control material;

a first connection structure for external electrical connection of the energy storage component;

a second connection structure for external electrical connection of the energy storage component; and

an electrically insulating encapsulation material at least partially embedded in the MIM arrangement.

2. The MIM energy storage component of claim 1, wherein the conduction control material conformally coats each of the plurality of conductive nanostructures and the first electrode layer not covered by the conductive nanostructures.

3. The MIM energy storage component of claim 1 or 2, wherein the electrically insulating encapsulation material leaves the first connection structure and the second connection structure uncovered by encapsulation material.

4. The MIM energy storage component of any preceding claim, wherein the electrically insulating encapsulation material at least partially forms an outer boundary surface of the energy storage component.

5. The MIM energy storage component of any preceding claim, wherein each of the first connection structure and the second connection structure at least partially forms an outer boundary surface of the energy storage component.

6. The MIM energy storage component of any preceding claim, wherein the second electrode layer completely fills the spaces between adjacent nanostructures of the plurality of conductive nanostructures by at least half of the distance between the base and the top of the nanostructures.

7. The MIM energy storage component of claim 6, wherein the second electrode layer completely fills spaces between adjacent nanostructures of the plurality of conductive nanostructures, from the base to the top of the nanostructures.

8. The MIM energy storage component of any preceding claim, wherein the second electrode layer comprises:

conformally coating a first sub-layer of the conduction control material; and

a second sublayer formed on the first sublayer.

9. The MIM energy storage component of claim 8, wherein the second electrode layer comprises a third sub-layer between the first and second sub-layers, the third sub-layer conformally coating the first sub-layer.

10. The MIM energy storage component according to any preceding claim, wherein the conductive nanostructures are Carbon Nanofibers (CNF).

11. The MIM energy storage component of claim 10, wherein the carbon nanofibers are formed at least in part from amorphous carbon.

12. The MIM energy storage component according to claim 10 or 11, wherein the carbon nanofibers have a corrugated surface structure and/or are branched nanofibers.

13. The MIM energy storage component of any preceding claim, wherein the MIM arrangement further comprises a catalyst layer between the first electrode layer and a nanostructure of the plurality of nanostructures.

14. The MIM energy storage component of claim 13, wherein the catalyst layer is a pre-patterned catalyst layer.

15. The MIM energy storage component of claim 14, wherein the catalyst layer is pre-patterned in a periodic configuration.

16. The MIM energy storage component of any of claims 13-15, wherein each nanostructure of the plurality of nanostructures included in the MIM arrangement comprises a catalyst material at a tip of the nanostructure.

17. The MIM energy storage component of any preceding claim, wherein the surface density of nanostructures of the plurality of nanostructures included in the MIM arrangement is at least 1000/mm²。

18. The MIM energy storage component of any preceding claim, further comprising a substrate directly supporting the first electrode layer.

19. The MIM energy storage component of claim 18, wherein the substrate is electrically non-conductive.

20. The MIM energy storage component of any preceding claim, wherein:

the MIM energy storage component having a top surface, a bottom surface, and a side surface connecting the top surface and the bottom surface;

the first connecting structure constitutes a first portion of the top surface; and is

The second connection structure constitutes a second portion of the top surface.

21. The MIM energy storage component of any one of claims 1-19, wherein:

the MIM energy storage component having a top surface, a bottom surface, and a side surface connecting the top surface and the bottom surface;

the first connecting structure constitutes a portion of the top surface; and is

The second connection structure forms a portion of the bottom surface.

22. The MIM energy storage component of any one of claims 1-19, wherein:

the MIM energy storage component having a top surface, a bottom surface, and a side surface connecting the top surface and the bottom surface;

the first connecting structure constitutes a part of the side surface; and is

The second connecting structure constitutes a part of the side surface.

23. The MIM energy storage component of any one of claims 20-22, further comprising at least one via extending from the bottom surface to the top surface.

24. The MIM energy storage component of any preceding claim, wherein:

the first connection structure is conductively connected to a first electrode layer of the MIM arrangement; and is

The second connection structure is conductively connected to a second electrode layer of the MIM arrangement.

25. The MIM energy storage component of any of the preceding claims, comprising at least a first MIM arrangement and a second MIM arrangement, each of the at least first MIM arrangement and second MIM arrangement comprising:

a first electrode layer;

a plurality of conductive nanostructures grown vertically from a first electrode layer;

a conductive control material covering each of the plurality of conductive nanostructures and the first electrode layer not covered by the conductive nanostructures; and

a second electrode layer overlying the conduction control material.

26. The MIM energy storage component of claim 25, wherein:

the first connection structure is connected to one of a first electrode layer and a second electrode layer of the first MIM arrangement;

the other of the first and second electrode layers of the first MIM arrangement is connected to one of the first and second electrode layers of the second MIM arrangement; and is

The second connection structure is connected to the other of the first electrode layer and the second electrode layer of the second MIM arrangement.

27. The MIM energy storage component of claim 25, wherein:

the first connection structure is connected to the first electrode layer of the first MIM arrangement and one of the first and second electrode layers of the second MIM arrangement; and is

The second connection structure is connected to the second electrode layer of the first MIM arrangement and to the other of the first and second electrode layers of the second MIM arrangement.

28. The MIM energy storage component of claim 26 or 27, wherein the first MIM arrangement and the second MIM arrangement are arranged in a layered configuration.

29. The MIM energy storage component of any of the preceding claims, wherein the conduction control material is a solid dielectric and the MIM energy storage component is a nanostructured capacitor component.

30. The MIM energy storage component of any one of claims 1-28, wherein the conduction control material is an electrolyte and the MIM energy storage component is a nanostructured cell component.

31. The MIM energy storage component of any one of claims 1-28, wherein the conduction control material comprises an electrolyte and a solid dielectric in a layered configuration.

32. An electronic device, comprising:

a Printed Circuit Board (PCB);

an Integrated Circuit (IC) on the PCB; and

the discrete MIM energy storage component of any of the preceding claims connected to the IC.

33. A discrete metal-insulator-metal (MIM) energy storage component, comprising:

at least a first MIM arrangement and a second MIM arrangement, each MIM arrangement comprising:

a first electrode layer;

a plurality of conductive nanostructures grown vertically from a first electrode layer;

a conductive control material covering each of the plurality of conductive nanostructures and the first electrode layer not covered by the conductive nanostructures; and

a second electrode layer overlying the conduction control material;

a first connection structure for external electrical connection of the capacitor component, the first connection structure being conductively connected to a first electrode layer of the first MIM arrangement;

a second connection structure for external electrical connection of the capacitor component, the second connection structure being conductively connected to a second electrode layer of the first MIM arrangement;

a third connection structure for external electrical connection of the capacitor component, the third connection structure being conductively connected to the first electrode layer of the second MIM arrangement;

a fourth connection structure for external electrical connection of the capacitor component, the fourth connection structure being conductively connected to the second electrode layer of the second MIM arrangement; and

an electrically insulating encapsulation material at least partially embedded in the at least first and second MIM arrangements.

34. An electronic device, comprising:

a Printed Circuit Board (PCB);

an Integrated Circuit (IC) on the PCB; and

the discrete MIM energy storage component of claim 33 connected to the IC.

35. A method of fabricating a discrete metal-insulator-metal (MIM) energy storage component, comprising the steps of:

providing a substrate;

forming a MIM arrangement on the substrate;

forming a first connection structure for external electrical connection of the energy storage component;

forming a second connection structure for external electrical connection of the energy storage component; and

at least partially embedding the MIM arrangement in an electrically insulating encapsulation material.

36. The method of claim 35, wherein the step of forming the MIM arrangement comprises the steps of:

providing a substrate;

forming a first electrode layer on the substrate;

growing a plurality of conductive nanostructures from the first electrode layer;

covering each of the plurality of conductive nanostructures and the first electrode layer not covered by the conductive nanostructures with a conductive control material; and

a second electrode layer is formed to cover the conduction control material.

37. The method of claim 36, wherein the step of forming the second electrode layer comprises the steps of:

conformally coating the conduction control material with a first metal sublayer; and

a second metal sub-layer is provided on the first metal sub-layer.

38. The method of claim 37, wherein the first metallic sub-layer is deposited directly on the conduction control material using atomic layer deposition.

39. A method according to any one of claims 36 to 38, wherein electroplating is used to provide the second metallic sub-layer.

40. A method according to any one of claims 36 to 39, wherein the nanostructures are grown using material and process settings such that Carbon Nanofibers (CNF) are formed.

41. The method of any one of claims 35 to 40, further comprising the step of:

the substrate is removed after the step of forming the MIM arrangement.

42. The method of any one of claims 35 to 41, wherein the substrate is provided in the form of a wafer.

43. A method according to any one of claims 35 to 41, wherein the substrate is provided in the form of a panel.

44. A method according to any one of claims 35 to 41, wherein the substrate is provided in the form of a film on a roll.

Technical Field

The present invention relates to discrete metal-insulator-metal (MIM) electrostatic and/or electrochemical energy storage components, including capacitors and batteries, and to methods of manufacturing such discrete metal-insulator-metal (MIM) energy storage components.

Background

The miniaturization of electronic devices has been a trend for decades, which has enabled us to see different kinds of gadgets with many functions. To a large extent, this development has been achieved by miniaturizing and integrating transistors, resistors and capacitors onto silicon for logic applications. By comparison, passive components at the circuit board level (resistors, capacitors and inductors) have only made incremental progress in size and density. Passive components therefore occupy an ever increasing area and mass fraction in electronic systems, and are a major obstacle to further miniaturization of many electronic systems at lower system costs. Current smart phones typically use more than 1000 discrete capacitor components. The circuit board of an electric automobile uses about 10000 of such discrete capacitor parts, and the trend is rising. The need for such a large number of capacitors is mainly due to the need to solve the following problems: the power management system drives power from the energy source (battery/mains) through the packaging scheme (PCB/SLP/SoC/SiP) to the functional silicon chip/die and to the on-chip integrated circuit. Different power management issues are addressed at different stages of integration of such gadgets.

The miniaturization of silicon circuits enables us to achieve more functions per unit area. These efforts are costly and have forced the power management system of the die to the utmost. Today's silicon chips suffer from severe effects of power noise caused by leakage currents from transistors, high frequency reflections in the interconnect grid, parasitic switching noise along the power grid, etc. Such power noise may cause voltage fluctuations and impedance mismatches of the circuit, and may produce gate delays and logic errors, jitter, etc., and may be catastrophic. There is a wide area of research on how to address such on-chip power management solutions. One approach to solving such problems is to use Metal Insulator Metal (MIM) decoupling capacitors integrated with the circuit. However, such integration schemes to solve the in-die problem are limited by the white space (expensive real estate space available on the die) in which the decoupling capacitors are integrated on the die surface. It is reported that the white space is reduced and only about 10% is allocated for on-chip decoupling capacitors in each die of today's generation.

Therefore, it is necessary to increase the capacitance density of such decoupling capacitors in a prescribed 2D region. Some solutions are proposed and proven in the Solid State Electronics of Saleem et al, "Integrated on-chip specific anode based on vertical aligned carbon nanotubes, growth using a CMOS temperature compatible process" and EP2074641, volume 139, page 75 (1.2018). The prior art has shown an improvement in capacitance values over conventional MIM capacitors. However, the device shown is susceptible to parasitic capacitance from field oxide present on the contact, or from randomly grown nanostructures outside the device area, resulting in unintentional and uncontrolled parasitic effects (capacitive/resistive/inductive) in the device, which would adversely affect circuit implementation. It is expected that many design and process modification steps (e.g., CMP planarization process, field oxide removal, etc.) are required to make such devices parasiticless, which essentially reduces the benefits of such technical concepts of practical implementations.

From another perspective, PCB/SLP board level, it is seen that the power supply rails (e.g., ± 2.5V, ± 12V or 3.3V, etc.) that provide power in most cases are generated by linear power supply or switch mode power supply technology. Although the electric power has a rectifying and filtering or conditioning stage before being fed to the grid of the electronic circuit, they may still have ripple noise. Therefore, many capacitors are typically found on the board, and as the switching frequency of the IC increases, the number and value of the capacitors becomes higher. Furthermore, as the power requirements of ICs evolve toward lower operating voltages, the power requirements and noise margins become increasingly stringent. In addition, power management is becoming a major issue with advances in system-level packaging (e.g., different IC/heterogeneous integrated SoC/SiP, FOWLP/FIWLP/chip wafer-level packaging). Noise may occur in the voltage levels due to poor power regulation, length/shape of PCB power interconnects, wire parasitics, switching frequency and EMI effects of the IC, etc. For such complex integrated packages, capacitors closer to different ICs are required for better performance.

The challenge facing today's industry standard MLCC/TSC/LICC capacitor technology for manufacturing such discrete components is to comply with the ever increasing demand for lower heights (Z-heights) that are less than 100 μm and preferably less than 20 μm. This need is due to the fact that: due to the reduction in bump interconnect height and pitch/spacing, ICs integrated in packaged SoC/SiP packages require capacitors with a height of less than 70 μm to be accommodated between SoC/SiP packaging solutions.

To avoid this problem, US20170012029 illustrates an embodiment where a MIM capacitor configuration is accommodated at the die backside. However, this solution needs to be CMOS compatible and must be done on every die to be assembled. This may lead to limitations of such technical concepts due to the adaptation complexity of such MIM structures in different technical nodes and the costs associated with such implementations. This may substantially increase the substantial cost per die and may sacrifice the cost advantage per function required at the packaging level.

MLCCs are the most prominent type of discrete capacitor components used in the world. In any given system/gadget, tens of trillions of such discrete components are used each year. There have been some advances in the miniaturization of these components, and solar power induction (Taiyo Yuden) claims to be the thinnest 110 μm that can be found in the market. The electromechanical system of Samsung has introduced the concept of LICC to reduce thickness even further and to achieve a lower ESL (effective series inductance). Ipdia (now part of Murata) has introduced TSC discrete capacitor components as thin as 80 μm with a surprising capacitance value in excess of 900nF/mm 2. However, MLCCs, LICCs, and TSCs tend to fall further in the Z dimension (height) due to the materials involved (raw metal/dielectric particles, processing schemes (sintering/silicon etching), and the cost of raw materials and processing the MLCC process requires a thorough understanding of the limitations of the raw materials used in capacitor fabrication (including copper, nickel, silver, gold, tantalum, barium titanate, alumina, etc.).

Therefore, further miniaturization of these components based on these established technologies may not be as cost competitive as before. It is particularly challenging to match the need for being small enough in 2D and 3D space so that discrete capacitor components can be assembled between flip-chip bump interconnects without reducing cost.

There is a need to produce tens of trillions of discrete capacitor components to meet industry demands, and CMOS compatible technologies are too costly to develop for producing discrete components for MLCCs or LICCs or TSCs.

Disclosure of Invention

It is therefore evident that there is a major divergence between integrated capacitor component and discrete capacitor component products that requires innovative solutions. The same applies to other types of energy storage components.

According to a first aspect of the present invention, there is therefore provided a discrete metal-insulator-metal (MIM) energy storage component, comprising: MIM arrangement; a first connection structure for external electrical connection of the energy storage component; a second connection structure for external electrical connection of the energy storage component; and an electrically insulating encapsulation material at least partially embedded in the MIM arrangement, the MIM arrangement comprising: a first electrode layer; a plurality of conductive nanostructures grown from the first electrode layer; a conductive control material covering each of the plurality of conductive nanostructures and the first electrode layer not covered by the conductive nanostructures; and a second electrode layer covering the conduction control material.

According to embodiments, the energy storage component may facilitate storage of electrostatic or electrochemical energy, or a combination thereof.

According to an embodiment, the conduction control material may be a solid dielectric and the MIM energy storage component may be a nanostructured capacitor component.

According to other embodiments, the conduction control material may be an electrolyte and the MIM energy storage component may be a nanostructured battery component.

Advantageously, the nanostructures may be "non-horizontally" grown, e.g., generally vertically grown. The nanostructures may be generally straight, helical, branched, wavy, or slanted.

In the context of the present application, the term "conformally coated" is understood to mean that a layer of material is deposited on a surface in such a way that the thickness of the layer of material becomes the same regardless of the orientation of the surface. Various deposition methods for achieving such so-called conformal layers or films are known to those skilled in the art. Notable examples of deposition processes that may be suitable are various vapor deposition processes, such as CVD, ALD, and PVD.

By "solid dielectric material" is understood a dielectric material that is in a solid state at room temperature. Thus, the term does not include any material that is liquid at room temperature.

By "solid electrolyte material" is understood an electrolyte material that is in a solid state or sol-gel state at room temperature.

The solid dielectric material may advantageously be a so-called high-k dielectric. Examples of high-k dielectric materials include, for example, HfOx, TiOx, TaOx, and other well-known high-k dielectrics. Alternatively, the dielectric may be polymer based (e.g., polypropylene, polystyrene, poly (p-xylylene), parylene, etc.). Other known dielectric materials, such as Al, may also be used₂O_xSiOx, SiNx, or the like. The present invention contemplates the use of at least one layer of dielectric material, if desired. More than one dielectric material or multiple different dielectric layers are also contemplated to control the effective dielectric or electric field properties.

In nanostructured electrochemical storage devices or batteries, the conduction control material is primarily concerned with ions as part of the energy storage mechanism present in the conduction control material, for example to provide energy storage by allowing the transport of ions through the conduction control material. Suitable electrolytes may be solid or semi-solid electrolytes, and may be selected in the form of solid crystals, ceramics, garnets or polymers or gels, such as strontium titanate, yttria-stabilized zirconia, PMMA, KOH, lithium phosphorus oxynitride, lithium-based composites, and the like. The electrolyte layer may include a polymer electrolyte. The polymer electrolyte may include a polymer matrix, an additive, and a salt.

The conductivity controlling electrolyte material may be deposited by CVD, thermal treatment or spin or spray coating or any other suitable method used in the industry.

According to embodiments of the present invention, the conduction control material may include an electrolyte and a solid dielectric in a layered configuration. In such embodiments, the MIM energy storage component may be considered as a hybrid between a capacitor-type (electrostatic) energy storage device and a battery-type (electrochemical) energy storage device. This configuration may provide higher energy and power densities than purely capacitor components, and faster charging than purely battery components.

The present invention contemplates the use of any substrate, such as Si, glass, SiC, stainless steel, metal foil (e.g., Al/Cu/Ag, etc.) or any other suitable substrate used in the industry. The substrate may present a substantially planar surface or may be non-planar.

One or both of the first and second electrode layers may advantageously be a uniform and uninterrupted layer, substantially free of internal patterns or holes or the like. In another aspect, one or both of the electrodes may be patterned to accommodate any particular desired design of capacitor electrodes, such as in a circular pattern or where a capacitor is to be fabricated around a via.

The present invention contemplates the use of any metal or metal alloy or doped silicon or metal oxide, such as LiCoO2 or the like, as required by the design and performance of the energy storage component. For example, the metal layer may include a transition metal oxide, a composite oxide of lithium and a transition metal, or a mixture thereof. The transition metal oxide may include lithium cobalt oxide, lithium manganese oxide, or vanadium oxide. The metal contact layer may include one selected from the group consisting of Li, silicon tin oxynitride, Cu, and combinations thereof.

The invention also contemplates using the substrate as or in the first electrode layer. The invention is based on the following recognition: a metal-insulator-metal (MIM) arrangement, particularly a thin MIM energy storage component, comprising a plurality of vertically grown conductive nanostructures can be used to achieve cost-effective and extremely compact. By means of embodiments of the present invention, passive energy storage components with a profile height below 100 μm may be achieved and may be a competitive alternative to currently existing MLCC/TSC components. The reduced component height may allow for more efficient use of the available space on the circuit board. For example, very thin discrete MIM capacitors or battery components according to embodiments of the present invention may be arranged on the bottom side of an Integrated Circuit (IC) package, which provides a more compact circuit layout and shorter conductor distances between the IC and the capacitor. The shorter conductor distance between the IC and the capacitor provides at least reduced parasitic capacitance and inductance, which in turn provides improved performance of the IC.

However, the invention does not exclude the possibility of producing profile heights with a thickness of more than 100 μm, which may be suitable for use in other industrial applications where the profile height is not limited.

Embodiments of the present invention may meet the following requirements: (a) very high electrostatic or electrochemical capacitance values per unit area/volume, (b) low profile in the 2D and Z directions, (c) surface mounting compatible and suitable for 2D, 2.5D and 3D packaging/assembly/embedding technologies, (D) easy design form factor, (e) stable and robust performance at temperature and applied voltage, (f) low equivalent series inductance per square (ESL), (g) long lifetime or enhanced lifetime without capacitance degradation, and (h) cost effective.

According to various embodiments of the present invention, the second electrode layer may completely fill a space from the substrate toward the tip between adjacent nanostructures of the plurality of conductive nanostructures at least halfway between the substrate and the tip of the nanostructures. This configuration increases the robustness and reliability of the MIM arrangement included in the energy storage component, which in turn provides a more robust and reliable energy storage component. In particular, the mechanical stability of the nanostructures in the MIM arrangement may be increased. Furthermore, voids that may occur between nanostructures may be reduced, which may be beneficial for the reliability of the energy storage component, particularly in terms of temperature cycling, etc.

In an embodiment, the second electrode layer may completely fill the space between adjacent nanostructures of the plurality of conductive nanostructures, from the substrate of the nanostructures all the way to between the tips, which may even further improve the robustness and reliability of the energy storage component.

According to various embodiments, the second electrode layer may advantageously comprise: conformally coating a first sub-layer of a layer of solid dielectric material; and a second sublayer formed on the first sublayer.

In these embodiments, different deposition techniques may be used to form the second electrode layer. The first sub-layer may be deposited using a deposition technique suitable for conformal coatings, such as Atomic Layer Deposition (ALD), and the second sub-layer may be deposited using a relatively inexpensive and fast deposition technique that ensures bottom-to-top deposition, such as electroplating or electroless plating. Thus, this configuration may provide an advantageous trade-off between performance and cost.

Advantageously, the second electrode layer may additionally comprise a third sub-layer between the first and second sub-layers, the third sub-layer conformally coating the first sub-layer. In such a configuration, the first sub-layer may be a so-called adhesion layer, the third sub-layer may be a seed layer for electroplating, and the second sub-layer may be an electroplated layer. Furthermore, additional sub-layers, for example, as metal diffusion barriers, may be conveniently deposited in accordance with the present disclosure. The present invention also contemplates the use of a first sublayer that can serve as both a metal diffusion barrier and an adhesion layer.

The present invention also contemplates the use of different materials or material compositions in the first electrode layer and the second electrode layer.

The use of grown nanostructures allows for a wide range of tailoring of the properties of the nanostructures. For example, the growth conditions may be selected to achieve a morphology that gives a large surface area per nanostructure, increasing the charge carrying capacity of the nanostructure, which in turn provides increased capacitance for capacitor component embodiments and increased energy density for battery component embodiments.

The conductive nanostructures may advantageously be Carbon Nanofibers (CNF). Alternatively, the conductive nanostructures may be Carbon Nanotubes (CNTs) or carbide-derived carbon nanostructures or graphene walls. Furthermore, in embodiments, the nanostructures may be nanowires, such as copper, aluminum, silver, silicide, or other types of nanowires having conductive properties.

However, the use of CNFs may be particularly advantageous for discrete energy storage components according to embodiments of the present invention. CNTs are known to provide higher conductivity than CNFs. However, the process of forming conductive CNTs also tends to result in the formation of a proportion of semiconducting CNTs, and this proportion may not be known or precisely controllable. On the other hand, CNF is metallic, which provides improved reproducibility. Furthermore, the surface area of the CNF can be made much larger than that of CNTs with the same overall size (diameter and height), which provides more charge accumulation sites and thus higher charge carrying capacity, resulting in higher capacitance for the same number and overall size of nanostructures in the MIM arrangement.

In an embodiment, the carbon nanofibers may be formed at least in part from amorphous carbon. This results in a higher number of carbon atoms per surface area, resulting in more charge accumulation sites, which in turn results in higher capacitance for the same number and overall size of nanostructures in a MIM arrangement.

In an embodiment, the carbon nanofibers may be branched carbon nanofibers. This may allow for a further increase in accessible surface area, resulting in more charge accumulation sites, which in turn results in higher capacitance for the same number and overall size of nanostructures in a MIM arrangement.

Further, according to an embodiment, each CNF of the plurality of CNFs may have a corrugated surface structure, which also increases the number of charge accumulation sites (of each CNF).

To fully benefit from the use of CNFs having a corrugated surface structure or branched nanofiber structure, it may be particularly advantageous to deposit the solid dielectric material as a very thin conformal film capable of reproducing the very fine corrugated or branched nanostructures of CNFs.

Furthermore, the discrete MIM energy storage component according to an embodiment of the first aspect of the present invention may advantageously be comprised in an electronic device, the electronic device further comprising: a Printed Circuit Board (PCB); and an Integrated Circuit (IC) on the PCB. The discrete MIM energy storage components may be connected to the IC via a conductor pattern on the PCB. Alternatively, the discrete MIM energy storage component may be connected to the IC package. The circuit board does not have to be a conventional PCB but may be a Flexible Printed Circuit (FPC) or an SLP (substrate-like PCB).

Such CNF MIM energy storage based components may be conveniently referred to as CNF-MIM energy storage components.

According to a second aspect of the invention, there is provided a discrete metal-insulator-metal (MIM) energy storage component, comprising: at least a first MIM arrangement and a second MIM arrangement; a first connection structure for external electrical connection of an energy storage component, the first connection structure being conductively connected to the first electrode layer of the first MIM arrangement; a second connection structure for external electrical connection of the energy storage component, the second connection structure being conductively connected to the second electrode layer of the first MIM arrangement; a third connection structure for external electrical connection of the energy storage component, the third connection structure being conductively connected to the first electrode layer of the second MIM arrangement; a fourth connection structure for external electrical connection of the energy storage component, the fourth connection structure being conductively connected to the second electrode layer of the second MIM arrangement; and an electrically insulating encapsulation material at least partially embedded in at least the first and second MIM arrangements, each MIM arrangement comprising: a first electrode layer; a plurality of conductive nanostructures grown from a first electrode layer; a conductive control material covering each of the plurality of conductive nanostructures and the first electrode layer not covered by the conductive nanostructures; and a second electrode layer overlying the conduction control material.

Other embodiments of this second aspect of the invention and the effects obtained by this second aspect of the invention are largely similar to those described above for the first aspect of the invention.

According to a third aspect of the invention, there is provided a method of manufacturing a discrete metal-insulator-metal (MIM) energy storage component, comprising the steps of: providing a substrate; forming a MIM arrangement on a substrate; forming a first connection structure for external electrical connection of the energy storage component; forming a second connection structure for external electrical connection of the energy storage component; and at least partially embedding the MIM arrangement in a dielectric encapsulation material.

In an embodiment, the method may further comprise the step of removing the substrate after the step of forming the MIM arrangement.

In an embodiment, the substrate may constitute or be included in the first electrode layer. In such embodiments, the substrate will not be removed after the MIM arrangement is formed.

Further embodiments of, and effects obtained by, this third aspect of the invention are largely analogous to the embodiments and effects described above for the first and second aspects of the invention.

Drawings

These and other aspects of the present invention will now be described in more detail, with reference to the appended drawings showing exemplary embodiments of the invention, wherein:

figure 1 schematically illustrates the use of discrete MIM energy storage components according to an embodiment of the present invention in the form of a schematic mobile phone;

fig. 2 schematically shows an example of a circuit board according to the prior art, which may represent a typical circuit board in current electronic devices;

FIG. 3 schematically illustrates a possible meaning of replacing a conventional energy storage component on the circuit board in FIG. 2 with an energy storage component according to an example embodiment of the invention;

fig. 4 is a schematic illustration of a MIM energy storage component according to a first example embodiment of the invention;

fig. 5A is an enlarged illustration of a first example MIM arrangement of MIM capacitor components;

fig. 5B is an enlarged illustration of a second example MIM arrangement of MIM cell components;

fig. 6 is a flow chart illustrating an exemplary embodiment of a manufacturing method according to the present invention.

Fig. 7 is a schematic illustration of a MIM energy storage component according to a second example embodiment of the invention;

fig. 8 is a schematic illustration of a MIM energy storage component according to a third example embodiment of the invention;

fig. 9 is a schematic illustration of a MIM energy storage component according to a fourth example embodiment of the invention;

fig. 10 is a schematic illustration of a MIM energy storage component according to a fifth example embodiment of the invention;

fig. 11 is a schematic illustration of a MIM energy storage component according to a sixth example embodiment of the invention; and

fig. 12 is a schematic illustration of a MIM energy storage component according to a seventh example embodiment of the invention.

Detailed Description

Fig. 1 schematically shows an electronic device according to an embodiment of the invention, here in the form of a mobile phone 1. In the simplified and schematic illustration of fig. 1, the mobile phone is indicated to comprise like most electronic devices a circuit board 3, the circuit board 3 being provided with a packaged integrated circuit 5 and passive components, the passive components comprising energy storage components, here in the form of capacitors 7.

In fig. 2, fig. 2 is an exemplary illustration of a circuit board 3 using techniques currently available for reasonable and cost-effective mass production, there being a large number of capacitors 7 mounted on a Printed Circuit Board (PCB) 9. The capacitors 7 used today are usually so-called multilayer ceramic capacitors (MLCC) with a minimum package height of about 0.4 mm.

In order to provide even more compact electronic devices at even higher processing speeds, it is desirable to reduce the space occupied by the capacitor 7 required for decoupling and temporary energy storage, and to reduce the distance between the IC 5 and the capacitor 7 serving that IC 5.

The above described electronics can be implemented using discrete MIM energy storage components according to embodiments of the present invention, in this case MIM capacitor components, because the packing height of such MIM capacitor components is significantly smaller compared to conventional MLCCs having the same capacitance and footprint.

Fig. 3 is a schematic illustration of the possible implications of replacing a conventional capacitor component on the circuit board in fig. 2 with a MIM capacitor component according to an exemplary embodiment of the present invention. As is apparent from fig. 3, the reduced package height of the MIM capacitor component 11 according to an embodiment of the present invention allows to place the capacitor 11 under the IC package 5 between the connection balls 13 of the IC package 5. Obviously, this arrangement of the capacitor 11 enables a smaller PCB 9 and thus a more compact electronic device 1. A shorter distance between the active circuitry in IC 5 and capacitor 11 is also explicitly provided.

Fig. 4 is a schematic illustration of a MIM energy storage component 11 according to a first example embodiment of the invention. The MIM energy storage component is a discrete MIM energy storage component comprising a MIM arrangement 13, a first connection structure, here in the form of a first bump 15, a second connection structure, here in the form of a second bump 17, and a dielectric encapsulation material 19 at least partially embedded in the MIM arrangement 13. As shown in fig. 4, the electrically insulating encapsulating material 19 at least partially forms the outer boundary surface of the energy storage component. The first connection structure 15 and the second connection structure 17 also at least partially form an outer boundary surface of the energy storage component.

A first example configuration of the MIM arrangement 13 will now be described with reference to fig. 5A. The MIM energy storage components comprising the MIM arrangement 13 in fig. 5A are MIM capacitor components. As schematically shown in fig. 5A, the MIM arrangement 13 comprises: a first electrode layer 21; a plurality of conductive nanostructures 23 grown vertically from the first electrode layer 21; a solid dielectric material layer 25 conformally coating each nanostructure 23 of the plurality of conductive nanostructures and the first electrode layer 21 not covered by the conductive nanostructure 23; and a second electrode layer 27 covering the solid dielectric material layer 25. As shown in fig. 5A, the second electrode layer 27 completely fills more than half of the space between adjacent ones of the nanostructures 23 between the substrate 29 and the top 31. In the exemplary MIM arrangement 13 in fig. 5A, the second electrode layer 27 completely fills the space between adjacent nanostructures 23, from the substrate 29 all the way to the top 31 and higher.

As shown in the enlarged view of the boundary between the nanostructure 23 and the second electrode layer 27 in fig. 5A, the second electrode layer 27 includes a first sublayer 33 conformally coating the solid dielectric material layer 25, a second sublayer 35, and a third sublayer 37 between the first sublayer 33 and the second sublayer 35.

Furthermore, additional sub-layers, not shown in the figures, for example as metal diffusion barriers, may be conveniently present according to the present disclosure.

The dielectric material layer 25 may be a multilayer structure, which may include sublayers of different material compositions.

A second example configuration of the MIM arrangement 13 will now be described with reference to fig. 5B. The MIM energy storage component comprising the MIM arrangement 13 in fig. 5B is a MIM electrochemical energy storage/cell component. As schematically shown in fig. 5B, the MIM arrangement 13 comprises: a first electrode layer 21; a plurality of conductive nanostructures 23 grown vertically from the first electrode layer 21; an optional anode/cathode material layer 34 coating each nanostructure 23 of the plurality of conductive nanostructures and the first electrode layer 21 not covered by the conductive nanostructures 23; an electrolyte 36 covering the nanostructures 23; and a second electrode layer 27 covering the electrolyte 36. In the example embodiment of fig. 5B, the electrolyte 36 completely fills more than half of the space between adjacent ones of the nanostructures 23 between the base 29 and the top 31. In the exemplary MIM arrangement 13 in fig. 5B, the electrolyte 36 completely fills the space between adjacent nanostructures 23, from the base 29 all the way to the top 31 and higher. However, in embodiments, it may be beneficial to provide the electrolyte 36 as a conformal coating on the nanostructures 23.

Furthermore, additional sub-layers, not shown in the figures, for example as metal diffusion barriers, may be conveniently present according to the present disclosure.

The hybrid component may comprise a MIM arrangement 13 which is a combination of the MIM arrangements in fig. 5A and 5B. For example, the dielectric layer 25 in fig. 5A may be disposed between the nanostructures 23 and the electrolyte 36 in fig. 5B. Such a hybrid component may also include an additional dielectric layer between electrolyte 36 and top electrode 27 in fig. 5B.

An example method of fabricating a discrete MIM capacitor component comprising the example MIM arrangement 13 of figure 5A according to an embodiment of the invention will now be described with reference to the flow chart of figure 6. It should be understood that similar steps may be used to form the MIM arrangement 13 in fig. 5B.

In a first step 601, a substrate 39 is provided (see fig. 5A). Various substrates may be used, such as silicon, glass, stainless steel, ceramic, SiC, or any other suitable substrate material found in the industry. However, the substrate may be a high temperature polymer such as polyamide. The primary function of the substrate is to facilitate the fabrication of MIM capacitors according to the present disclosure.

In a subsequent step 602, a first electrode layer 21 is formed on the substrate 39. The first electrode layer 21 may be formed via Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or any other method used in the industry. In some implementations, the first electrode layer 21 can include one or more metals selected from the group consisting of: cu, Ti, W, Mo, Co, Pt, Al, Au, Pd, Ni, Fe and silicide. In some implementations, the first electrode layer 21 can include one or more conductive alloys selected from the group consisting of: TiC, TiN, WN, and AIN. In some implementations, the first metal layer 21 can include one or more conductive polymers. In some implementations, the first electrode layer 21 can be a metal oxide, such as LiCoO2, doped silicon. In some implementations, the first metal layer 21 may be the substrate itself, such as an Al/Cu/Ag foil or the like.

In a next step 603, a catalyst layer is provided on the first electrode layer 21. The catalyst may be, for example, nickel, iron, platinum, palladium, nickel silicide, cobalt, molybdenum, Au, or alloys thereof, or may be combined with other materials (e.g., silicon). The catalyst may be optional, as the techniques described herein may also be applied in a catalyst-free growth process for nanostructures. The catalyst may also be deposited by spin coating the catalyst particles.

In some embodiments, the catalyst layer is used to grow nanostructures and is used as a connecting electrode. In such implementations, the catalyst may be the following thick layers: nickel, iron, platinum, palladium, nickel silicide, cobalt, molybdenum, Au or alloys thereof, or may be combined with other materials from the periodic table. The catalyst layer (not shown in fig. 5A) may be provided as a uniform layer or a patterned layer. The formation of a patterned layer of course requires more processing than an unpatterned layer, but may provide higher or lower and more regular density of nanostructures 23, which in turn may provide higher capacitance for the completed MIM capacitor component or more control over the absolute capacitance value of each capacitor device in the case of more than one capacitor embedded in the capacitor component 11.

In step 604, nanostructures 23 are grown from the catalyst layer. As explained in the summary section above, the inventors found that vertically grown Carbon Nanofibers (CNF) may be particularly suitable for MIM capacitor components 11. The use of vertically grown nanostructures allows for a wide range of tailoring of the properties of the nanostructures. For example, growth conditions may be selected to achieve a morphology that gives a large surface area per nanostructure, which in turn may increase the charge storage capacitance or capacitance per 2D occupied space. As an alternative to CNF, the nanostructures may be metallic carbon nanotubes or carbide-derived carbon nanostructures, nanowires (such as copper, aluminum, silver, silicides or other types of nanowires with conductive properties). Advantageously, the catalyst material and the growth gas or the like may be selected in a manner known per se to achieve so-called tip growth of the nanostructures 23, which may form the catalyst layer material at the tips 31 of the nanostructures 23. After growth of the vertically aligned conductive nanostructures 23, the nanostructures 23 and the first electrode layer 21 may optionally be conformally coated with a metal layer, primarily to improve adhesion between the nanostructures 23 and the conduction control material.

After growth of the vertically aligned conductive nanostructures 23, in step 605, the solid dielectric material layer 25 conformally coats the nanostructures 23 and the portions of the first electrode layer 21 not covered by the nanostructures 23. The solid dielectric material layer 25 may advantageously be made of a so-called high-k dielectric. The high-k dielectric material may be, for example, HfOx, TiOx, TaOx or other well-known high-k dielectrics. Alternatively, the dielectric may be polymer-based, such as polypropylene, polystyrene, poly (p-xylene), parylene, and the like. Other known dielectric materials (e.g., SiOx, SiNx, etc.) may be used as the dielectric layer. Any other suitable conductivity control material may be suitably used. The dielectric material may be deposited via CVD, thermal treatment, Atomic Layer Deposition (ALD), or spin or spray coating or any other suitable method used in the industry. In various embodiments, it may be advantageous to use more than one dielectric layer or different dielectric materials with different dielectric constants or different thicknesses of dielectric material to control the effective dielectric constant or to influence the breakdown voltage or a combination thereof to control the dielectric film properties. Advantageously, the layer 25 of solid dielectric material with atomic uniformity is uniformly coated on the nanostructures 23, so that the dielectric layer covers the entire nanostructures 23, thereby minimizing the leakage current of the capacitor device. Another advantage of providing a solid dielectric layer 25 with atomic uniformity is that the solid dielectric layer 25 may conform to the very small surface irregularities of the conductive nanostructures 23, which may be introduced during growth of the nanostructures. This provides an increased total electrode surface area of the MIM arrangement 13, which in turn provides a higher capacitance for a given component size. The step of conformally coating a metal layer on the nanostructures may optionally be introduced between step 604 and step 605, for example to facilitate adhesion of the dielectric layer 25 or electrolyte layer (if applicable) to the nanostructures 23.

In a next step 606, an adhesion metal layer, i.e. the above mentioned first sub-layer 33 of the second electrode layer 27, is conformally coated on the solid dielectric material layer 25. Adhesion metal layer 33 may be advantageously formed using ALD, and an example of a suitable material for adhesion metal layer 33 may be Ti or TiN.

In step 607, a so-called seed metal layer 37, i.e. the above-mentioned third sub-layer 37 of the second electrode layer 27, may optionally be formed on top of the adhesion metal layer 33. Seed metal layer 37 may be conformally coated on adhesion metal layer 33. The seed metal layer 37 may be made of, for example, Al, Cu, or any other suitable seed metal material.

After the formation of the seed metal layer 37, the above-mentioned second sub-layer 35 is provided in step 608. The second sub-layer 35 of the second electrode layer 21 may be formed, for example, by chemical means, such as electroplating, electroless plating or any other method known in the art. As schematically indicated in fig. 5, the second sub-layer 35 may advantageously fill the spaces between the nanostructures 23 to provide improved structural robustness, etc.

In step 609, first and second connection structures 15, 17, such as bumps, balls or pillars, are formed using techniques known per se.

In a subsequent step 610, an insulating encapsulation material 19 is provided to at least partially embed the MIM arrangement 13. Any known suitable encapsulant material may be used for the encapsulant layer, for example, silicone, epoxy, polyimide, BCB, resin, silicone, epoxy underfill, and the like. In some aspects, a silicone material may be advantageous if it is suitable for some other IC packaging scheme. The encapsulant may be cured to form an encapsulation layer. In some aspects of the invention, the encapsulant layer may be a curable material such that passive components may be attached by a curing process. In some aspects, the dielectric constant of the encapsulant is different than the dielectric constant of the dielectric material used in the MIM construction. In some aspects, encapsulant materials having lower dielectric constants are preferred compared to the dielectric materials used in fabricating MIM capacitors. In some aspects, SiN, SiO, or spin-on glass may also be used as the encapsulant material. The encapsulant layer may be spin-coated and dried, deposited by CVD or by any other method known in the art.

Following this step, in optional step 611, the substrate 39 may optionally be thinned or completely removed, depending on the desired configuration of the completed MIM capacitor component.

For the case where the substrate is the first electrode, this step is optional unless further thinning of the substrate is required.

In the following step 612, the panel or wafer is singulated using known techniques to provide discrete MIM capacitor components 11.

Any of the foregoing embodiments are suitable for fabrication in wafer-level processes and panel-level processes used in the industry. They may conveniently be referred to as wafer level processing and panel level processing, respectively. In wafer-level processing, circular substrates ranging in size from 2-inch to 12-inch wafers are typically used. In panel-level machining, the dimensions are defined by the machine capacity and may be a large range of dimensions, circular or rectangular or square, typically but not limited to 12 inches to 100 inches. Panel level processing is commonly used to produce smart tvs. Thus, the size may be that of a television or larger. In aspects of wafer level processing, at least one of the above embodiments is processed at the wafer level in a semiconductor processing factory. In another aspect, at least one of the above embodiments is treated with panel level processing for a panel level process. After processing, the wafer or panel is cut into smaller pieces using standard dicing, plasma dicing, or laser dicing, depending on design requirements. Such singulation processing steps may be configured by cutting or plasma cutting or laser cutting to customize the shape and size of the discrete components formed as desired.

The present invention also contemplates compatibility with use in roll-to-roll manufacturing techniques. Roll-to-roll processing is a method of producing flexible and large area electronic devices on rolls of plastic or metal foil. The method is also described as a printing method. The substrate material used in roll-to-roll printing is typically paper, plastic film or metal foil or stainless steel. The roll-to-roll approach enables much higher throughput, with a much smaller carbon footprint and with less energy usage than other approaches (e.g., wafer-level or panel-level). Roll-to-roll processing finds application in many manufacturing areas, such as flexible and large area electronics, flexible solar panels, printed/flexible thin film batteries, fibers and textiles, metal foil and sheet manufacturing, medical products, energy products in construction, films and nanotechnology.

Fig. 7 is a schematic illustration of a MIM energy storage component 11 according to a second example embodiment of the invention. The MIM energy storage component 11 of figure 7 differs from the MIM energy storage component described above with reference to figure 4 in that conductive vias 41 are provided to facilitate component stacking.

Fig. 8 is a schematic illustration of a MIM energy storage component 11 according to a third example embodiment of the invention. The MIM energy storage component 11 in fig. 8 differs from the MIM energy storage component described above with reference to fig. 4 in that the first connection structure 15 and the second connection structure 17 are provided as terminal contacts on opposite side surfaces of the MIM energy storage component 11. In fig. 8, the first connection structure 15 and the second connection structure 17 are shown as being arranged on the short sides of the rectangular part 11. In an embodiment, the first and second connection structures 15, 17 may alternatively be arranged on the long sides of the component. Such a configuration may provide reduced series inductance of the components.

Fig. 9 is a schematic illustration of a MIM energy storage component 11 according to a fourth example embodiment of the invention. The MIM energy storage component 11 in fig. 9 differs from the MIM energy storage component described above with reference to fig. 4 in that the first connection structure 15 and the second connection structure 17 are provided as top and bottom surfaces of the MIM energy storage component 11. In this exemplary embodiment, the substrate used in the manufacture of the MIM arrangement 13 described above has been completely or partially removed after the formation of the first connection structure 15 and the second connection structure 17.

Fig. 10 is a schematic illustration of a MIM energy storage component 11 according to a fifth example embodiment of the invention. The MIM energy storage component 11 in fig. 10 comprises a first MIM arrangement 13a and a second MIM arrangement 13 b. As indicated in fig. 10, the second electrode 27a of the first MIM arrangement 13a is connected to the first connection structure 15 and the second electrode 27b of the second MIM arrangement 13b is connected to the second connection structure 17. The first electrode 21 is common to the first MIM arrangement 13a and the second MIM arrangement 13 b. The resulting MIM energy storage component 11 thus comprises two energy storage devices connected in series. This means that the total voltage across the MIM energy storage components 11 between the first connection structure 15 and the second connection structure 17 is distributed between the first energy storage (first MIM arrangement 13a) and the second energy storage (second MIM arrangement 13 b). Thereby, a higher operating voltage of the component may be provided and the breakdown voltage may be increased.

Fig. 11 is a schematic illustration of a MIM energy storage component in the form of a multilayer MIM energy storage component 11 according to a sixth example embodiment of the invention. The energy storage component 11 in fig. 11 is conceptually similar to an MLCC component, but instead of a layer of dielectric material, an MIM arrangement similar to the MIM energy storage component described above in connection with fig. 9 is provided between the electrodes respectively connected to the first connection structure 15 and the second connection structure 17. The MIM energy storage component 11 in fig. 11 may exhibit a package height similar to conventional MLCC components, but with a much higher capacitance.

Fig. 12 is a schematic illustration of a MIM energy storage component according to a seventh example embodiment of the invention. The MIM energy storage component 11 includes a plurality of MIM energy storage devices and vias 41. Different MIM energy storage devices can be tuned to different energy storage capacity values, if desired. In some applications, the MIM energy storage component 11 in fig. 12 may be a beneficial alternative to a large number of discrete energy storage components.

The person skilled in the art realizes that the present invention by no means is limited to the preferred embodiments described above. On the contrary, many modifications and variations are possible within the scope of the appended claims.

In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims shall not be construed as limiting the scope.

The claims (modification according to treaty clause 19)