阅读说明：本技术 半导体器件 (Semiconductor device with a plurality of transistors ) 是由 李性柱 金柱赫 于 2020-04-09 设计创作，主要内容包括：一种半导体器件包括内部时钟生成电路,其被配置成在第一模式和第二模式中从第一和第三分频时钟以及地电压生成第一至第四内部时钟。该半导体器件还包括数据处理电路,其被配置成根据第一至第四输入控制信号锁存第一至第四内部数据。该数据处理电路还被配置成通过根据第一至第四内部时钟、第一至第四上升输出控制信号以及第一至第四下降输出控制信号确定锁存的第一和第三内部数据和锁存的第二和第四内部数据的输出优先级来生成第一至第四输出数据。(A semiconductor device includes an internal clock generation circuit configured to generate first to fourth internal clocks from first and third divided clocks and a ground voltage in a first mode and a second mode. The semiconductor device further includes a data processing circuit configured to latch the first to fourth internal data according to the first to fourth input control signals. The data processing circuit is further configured to generate first to fourth output data by determining output priorities of the latched first and third internal data and the latched second and fourth internal data according to the first to fourth internal clocks, the first to fourth rising output control signals, and the first to fourth falling output control signals.)

1. A semiconductor device, comprising:

an internal clock generation circuit configured to generate a first internal clock, a second internal clock, a third internal clock, and a fourth internal clock from the first divided clock, the second divided clock, the third divided clock, the fourth divided clock, and a ground voltage in the first mode and the second mode; and

a data processing circuit configured to:

latching first internal data, second internal data, third internal data and fourth internal data according to a first input control signal, a second input control signal, a third input control signal and a fourth input control signal; and

generating first, second, third, and fourth output data by determining output priorities of the latched first and third internal data and the latched second and fourth internal data according to the first, second, third, fourth, and fourth internal clocks, a first rising output control signal, a second rising output control signal, a third rising output control signal, a first falling output control signal, a second falling output control signal, a third falling output control signal, and a fourth falling output control signal.

2. The semiconductor device according to claim 1, wherein the internal clock generation circuit is configured to generate the first internal clock and the third internal clock from the ground voltage in the second mode, and is configured to generate the second internal clock and the fourth internal clock from the ground voltage in the first mode.

3. The semiconductor device according to claim 1, wherein the internal clock generation circuit is configured to generate the first internal clock and the third internal clock from the first divided clock, the third divided clock, and the ground voltage, and subsequently generate the second internal clock and the fourth internal clock in the first mode,

wherein the internal clock generation circuit is configured to generate the second internal clock and the fourth internal clock from the second divided clock, the fourth divided clock, and the ground voltage in the second mode, and then generate the first internal clock and the third internal clock.

4. The semiconductor device according to claim 1, wherein the data processing circuit is configured to generate the first output data and the second output data from the first internal data and the third internal data and subsequently generate the third output data and the fourth output data from the second internal data and the fourth internal data in the first mode,

wherein the data processing circuit is configured to generate the first output data and the second output data from the second internal data and the fourth internal data and subsequently generate the third output data and the fourth output data from the first internal data and the third internal data in the second mode.

5. The semiconductor device according to claim 1, wherein the internal clock generation circuit comprises:

a first transmission circuit configured to generate the first internal clock from the first divided clock in the first mode and generate the first internal clock from the ground voltage in the second mode;

a second transmission circuit configured to generate the second internal clock from the ground voltage in the first mode and generate the second internal clock from the first divided clock in the second mode;

a third transmission circuit configured to generate the third internal clock from the third divided clock in the first mode and generate the third internal clock from the ground voltage in the second mode; and

a fourth transmission circuit configured to generate the fourth internal clock from the ground voltage in the first mode and generate the fourth internal clock from the third divided clock in the second mode.

6. The semiconductor device according to claim 5, wherein the first transfer circuit comprises:

a first internal transmission circuit configured to invert and buffer the first divided clock and output the inverted and buffered signal to a first node in the first mode;

a second internal transmission circuit configured to invert and buffer the ground voltage and output the inverted and buffered signal to the first node in the second mode; and

a first internal clock output circuit configured to invert and buffer a signal of the first node and output the inverted and buffered signal as the first internal clock.

7. The semiconductor device according to claim 5, wherein the second transmission circuit comprises:

a third internal transmission circuit configured to invert and buffer the ground voltage and output the inverted and buffered signal to a second node in the first mode;

a fourth internal transmission circuit configured to invert and buffer the first divided clock and output the inverted and buffered signal to the second node in the second mode; and

a second internal clock output circuit configured to invert and buffer a signal of the second node and output the inverted and buffered signal as the second internal clock.

8. The semiconductor device according to claim 5, wherein the third transmission circuit comprises:

a fifth internal transmission circuit configured to invert and buffer the third divided clock and output the inverted and buffered signal to a third node in the first mode;

a sixth internal transmission circuit configured to invert and buffer the ground voltage and output the inverted and buffered signal to the third node in the second mode; and

a third internal clock output circuit configured to invert and buffer a signal of the third node and output the inverted and buffered signal as the third internal clock.

9. The semiconductor device according to claim 5, wherein the fourth transmission circuit comprises:

a seventh internal transmission circuit configured to invert and buffer the ground voltage and output the inverted and buffered signal to a fourth node in the first mode;

an eighth internal transmission circuit configured to invert and buffer the third divided clock and output the inverted and buffered signal to the fourth node in the second mode; and

a fourth internal clock output circuit configured to invert and buffer a signal of the fourth node and output the inverted and buffered signal as the fourth internal clock.

10. The semiconductor device of claim 1, wherein the data processing circuit comprises:

a pipe circuit configured to latch the first internal data, the second internal data, the third internal data, and the fourth internal data according to the first input control signal, the second input control signal, the third input control signal, and the fourth input control signal, and outputting the latched first internal data, second internal data, third internal data, and fourth internal data as first latch data, second latch data, third latch data, and fourth latch data according to the first rising output control signal, the second rising output control signal, the third rising output control signal, the fourth rising output control signal, the first falling output control signal, the second falling output control signal, the third falling output control signal, and the fourth falling output control signal; and

a data sorting circuit configured to generate the first, second, third, and fourth output data from the first, second, third, and fourth latch data in synchronization with the first, second, third, and fourth internal clocks.

11. The semiconductor device of claim 10, wherein the pipeline circuit comprises:

a first pipe latch configured to: latching the first internal data according to the first input control signal, and generating the first latch data from the latched first internal data according to one of the first rising output control signal and the first falling output control signal;

a second pipe latch configured to: latching the second internal data according to the second input control signal, and generating the second latched data from the latched second internal data according to one of the second rising output control signal and the second falling output control signal;

a third pipe latch configured to: latching the third internal data according to the third input control signal, and generating the third latched data from the latched third internal data according to one of the third rising output control signal and the third falling output control signal; and

a fourth pipe latch configured to: latching the fourth internal data according to the fourth input control signal, and generating the fourth latched data from the latched fourth internal data according to one of the fourth rising output control signal and the fourth falling output control signal.

12. The semiconductor device of claim 10, wherein the data sorting circuit comprises:

a first driver configured to drive a fifth node according to a logic level of the first latch data in synchronization with the first internal clock;

a second driver configured to drive the fifth node according to a logic level of the second latched data in synchronization with the second internal clock;

a third driver configured to drive the fifth node according to a logic level of the third latched data in synchronization with the third internal clock;

a fourth driver configured to drive the fifth node according to a logic level of the fourth latch data in synchronization with the fourth internal clock; and

a transmitter configured to drive the first, second, third, and fourth output data according to a logic level of the fifth node and output the first, second, third, and fourth output data to the outside.

13. A semiconductor device, comprising:

a mode setting circuit configured to generate a first mode setting signal, a second mode setting signal, and a third mode setting signal according to a combination of the first mode signal and the second mode signal;

an internal clock generation circuit configured to generate a first internal clock, a second internal clock, a third internal clock, and a fourth internal clock from a first divided clock, a second divided clock, a third divided clock, a fourth divided clock, and a ground voltage according to the first mode setting signal, the second mode setting signal, and the third mode setting signal; and

a data processing circuit configured to:

latching first internal data, second internal data, third internal data and fourth internal data according to a first input control signal, a second input control signal, a third input control signal and a fourth input control signal; and

generating first, second, third, and fourth output data by determining output priorities of the latched first and third internal data and the latched second and fourth internal data according to the first, second, third, fourth, and fourth internal clocks, a first rising output control signal, a second rising output control signal, a third rising output control signal, a first falling output control signal, a second falling output control signal, a third falling output control signal, and a fourth falling output control signal.

14. The semiconductor device according to claim 13, wherein each of the first divided clock, the second divided clock, the third divided clock, and the fourth divided clock includes at least one pulse, and the first divided clock, the second divided clock, the third divided clock, and the fourth divided clock have different phases.

15. The semiconductor device of claim 13, wherein the internal clock generation circuit is configured to:

entering a first mode according to the first mode setting signal, generating the first internal clock and the third internal clock from the first divided clock, the third divided clock, and the ground voltage, and then generating the second internal clock and the fourth internal clock;

entering a second mode according to the second mode setting signal, generating the second internal clock and the fourth internal clock from the second divided clock, the fourth divided clock, and the ground voltage, and then generating the first internal clock and the third internal clock; and

entering a third mode according to the third mode setting signal and generating the first internal clock, the second internal clock, the third internal clock, and the fourth internal clock from the first divided clock, the second divided clock, the third divided clock, and the fourth divided clock.

16. The semiconductor device according to claim 13, wherein the internal clock generation circuit comprises:

a first transmission circuit configured to generate the first internal clock from one among the first frequency-divided clock and the ground voltage according to the first mode setting signal, the second mode setting signal, and the third mode setting signal;

a second transmission circuit configured to generate the second internal clock from one among the first frequency-divided clock, the second frequency-divided clock, and the ground voltage according to the first mode setting signal, the second mode setting signal, and the third mode setting signal;

a third transmission circuit configured to generate the third internal clock from one among the third divided clock and the ground voltage according to the first mode setting signal, the second mode setting signal, and the third mode setting signal; and

a fourth transmission circuit configured to generate the fourth internal clock from one of the third divided clock, the fourth divided clock, and the ground voltage according to the first mode setting signal, the second mode setting signal, and the third mode setting signal.

17. The semiconductor device according to claim 16, wherein the first transfer circuit comprises:

a first internal transmission circuit configured to: inverting and buffering the first frequency-divided clock and outputting the resulting inverted and buffered first frequency-divided clock signal to a first node when the first mode setting signal is enabled;

a second internal transmission circuit configured to: inverting and buffering the ground voltage and outputting the resultant inverted and buffered ground voltage signal to the first node when the second mode setting signal is enabled;

a third internal transmission circuit configured to: inverting and buffering the first frequency-divided clock and outputting the resulting inverted and buffered first frequency-divided clock signal to the first node when the third mode setting signal is enabled; and

a first internal clock output circuit configured to invert and buffer a signal of the first node and output the inverted and buffered signal as the first internal clock.

18. The semiconductor device according to claim 16, wherein the second transmission circuit comprises:

a fourth internal transmission circuit configured to: inverting and buffering the ground voltage and outputting the resultant inverted and buffered ground voltage signal to a second node when the first mode setting signal is enabled;

a fifth internal transmission circuit configured to: inverting and buffering the first frequency-divided clock and outputting the resulting inverted and buffered first frequency-divided clock signal to the second node when the second mode setting signal is enabled;

a sixth internal transmission circuit configured to: inverting and buffering the second frequency-divided clock and outputting the resulting inverted and buffered second frequency-divided clock signal to the second node when the third mode setting signal is enabled; and

a second internal clock output circuit configured to invert and buffer a signal of the second node and output the inverted and buffered signal as the second internal clock.

19. The semiconductor device according to claim 16, wherein the third transmission circuit comprises:

a seventh internal transmission circuit configured to: inverting and buffering the third divided clock and outputting the resulting inverted and buffered third divided clock signal to a third node when the first mode setting signal is enabled;

an eighth internal transmission circuit configured to: inverting and buffering the ground voltage and outputting the resultant inverted and buffered ground voltage signal to the third node when the second mode setting signal is enabled;

a ninth internal transmission circuit configured to: inverting and buffering the third divided-frequency clock and outputting the resulting inverted and buffered third divided-frequency clock signal to the third node when the third mode setting signal is enabled; and

a third internal clock output circuit configured to invert and buffer a signal of the third node and output the inverted and buffered signal as the third internal clock.

20. The semiconductor device according to claim 16, wherein the fourth transmission circuit comprises:

a tenth internal transmission circuit configured to: inverting and buffering the ground voltage and outputting the resultant inverted and buffered ground voltage signal to a fourth node when the first mode setting signal is enabled;

an eleventh internal transmission circuit configured to: inverting and buffering the third divided clock and outputting the resulting inverted and buffered third divided clock signal to the fourth node when the second mode setting signal is enabled;

a twelfth internal transmission circuit configured to: inverting and buffering the fourth divided clock and outputting the resulting inverted and buffered fourth divided clock signal to the fourth node when the third mode setting signal is enabled; and

a fourth internal clock output circuit configured to invert and buffer a signal of the fourth node and output the inverted and buffered signal as the fourth internal clock.

21. The semiconductor device of claim 13, wherein the data processing circuit comprises:

a pipe circuit configured to: latching the first internal data, the second internal data, the third internal data, and the fourth internal data according to the first input control signal, the second input control signal, the third input control signal, and the fourth input control signal, and outputting the latched first internal data, second internal data, third internal data, and fourth internal data as first latch data, second latch data, third latch data, and fourth latch data according to the first rising output control signal, the second rising output control signal, the third rising output control signal, the fourth rising output control signal, the first falling output control signal, the second falling output control signal, the third falling output control signal, and the fourth falling output control signal; and

a data sorting circuit configured to generate the first, second, third, and fourth output data from the first, second, third, and fourth latch data in synchronization with the first, second, third, and fourth internal clocks.

22. The semiconductor device of claim 21, wherein the pipeline circuit comprises:

a first pipe latch configured to: latching the first internal data according to the first input control signal, and generating the first latch data from the latched first internal data according to one of the first rising output control signal and the first falling output control signal;

a second pipe latch configured to: latching the second internal data according to the second input control signal, and generating the second latched data from the latched second internal data according to one of the second rising output control signal and the second falling output control signal;

a third pipe latch configured to: latching the third internal data according to the third input control signal, and generating the third latched data from the latched third internal data according to one of the third rising output control signal and the third falling output control signal; and

a fourth pipe latch configured to: latching the fourth internal data according to the fourth input control signal, and generating the fourth latched data from the latched fourth internal data according to one of the fourth rising output control signal and the fourth falling output control signal.

23. The semiconductor device of claim 21, wherein the data sorting circuit comprises:

a first driver configured to drive a fifth node according to a logic level of the first latch data in synchronization with the first internal clock;

a second driver configured to drive the fifth node according to a logic level of the second latched data in synchronization with the second internal clock;

a third driver configured to drive the fifth node according to a logic level of the third latched data in synchronization with the third internal clock;

a fourth driver configured to drive the fifth node according to a logic level of the fourth latch data in synchronization with the fourth internal clock; and

a transmitter configured to drive the first, second, third, and fourth output data according to a logic level of the fifth node and output the first, second, third, and fourth output data to the outside.

24. The semiconductor device of claim 13, further comprising a pipeline control circuit configured to: the first, second, third, and fourth input control signals are generated from a rising clock and a falling clock according to the first, second, and third mode setting signals, and the first, second, third, and fourth rising output control signals are generated from the rising clock, the falling clock, and the ground voltage according to the first, second, and third mode setting signals.

25. The semiconductor device of claim 24, wherein the pipe control circuit comprises:

an input control signal generation circuit configured to: generating the first input control signal, the second input control signal, the third input control signal, and the fourth input control signal that are simultaneously enabled by the rising clock and the falling clock when one of the first mode setting signal, the second mode setting signal, and the third mode setting signal is enabled; and

an output control signal generation circuit configured to: generating the first rising output control signal, the second rising output control signal, the third rising output control signal, the fourth rising output control signal, the first falling output control signal, the second falling output control signal, the third falling output control signal, and the fourth falling output control signal from the rising clock, the falling clock, and the ground voltage according to the first mode setting signal, the second mode setting signal, and the third mode setting signal.

26. The semiconductor device according to claim 25, wherein the output control signal generation circuit comprises:

a first transmission clock generation circuit configured to generate a first transmission clock from the rising clock and the ground voltage according to the first mode setting signal, the second mode setting signal, and the third mode setting signal;

a second transmission clock generation circuit configured to generate a second transmission clock from the rising clock, the falling clock, and the ground voltage according to the first mode setting signal, the second mode setting signal, and the third mode setting signal;

a rising output control signal generation circuit configured to generate the first rising output control signal, the second rising output control signal, the third rising output control signal, and the fourth rising output control signal in synchronization with the first transmission clock in accordance with the first mode setting signal, the second mode setting signal, and the third mode setting signal; and

a falling output control signal generation circuit configured to generate the first, second, third, and fourth falling output control signals in synchronization with the second transmission clock according to the first, second, and third mode setting signals.

27. The semiconductor device according to claim 26, wherein the first transmission clock generation circuit comprises:

a first clock transmission circuit configured to: inverting and buffering the rising clock and outputting the resulting inverted and buffered rising clock signal to a sixth node when the first mode setting signal is enabled;

a second clock transmission circuit configured to: inverting and buffering the ground voltage and outputting the resultant inverted and buffered ground voltage signal to the sixth node when the second mode setting signal is enabled;

a third clock transmission circuit configured to: inverting and buffering the rising clock and outputting the resulting inverted and buffered rising clock signal to the sixth node when the third mode setting signal is enabled; and

a first transmission clock output circuit configured to invert and buffer a signal of the sixth node and output the inverted and buffered signal as the first transmission clock.

28. The semiconductor device according to claim 26, wherein the second transmission clock generating circuit comprises:

a fourth clock transmission circuit configured to: inverting and buffering the ground voltage and outputting the resultant inverted and buffered ground voltage signal to a seventh node when the first mode setting signal is enabled;

a fifth clock transmission circuit configured to: inverting and buffering the rising clock and outputting the resulting inverted and buffered rising clock signal to the seventh node when the second mode setting signal is enabled;

a sixth clock transmission circuit configured to: inverting and buffering the falling clock and outputting the resulting inverted and buffered falling clock signal to the seventh node when the third mode setting signal is enabled; and

a second transmission clock output circuit configured to invert and buffer a signal of the seventh node and output the inverted and buffered signal as the second transmission clock.

29. The semiconductor device of claim 26, wherein the rising output control signal generation circuit is configured to:

generating the first rising output control signal and the third rising output control signal that are enabled in synchronization with the first transmission clock when the first mode setting signal is enabled;

generating the second rising output control signal and the fourth rising output control signal that are enabled in synchronization with the first transmission clock when the second mode setting signal is enabled; and

the first rising output control signal, the second rising output control signal, the third rising output control signal, and the fourth rising output control signal that are enabled are generated in synchronization with the first transmission clock when the third mode setting signal is enabled.

30. The semiconductor device of claim 26, wherein the falling output control signal generation circuit is configured to:

generating the second falling output control signal and the fourth falling output control signal that are enabled in synchronization with the second transmission clock when the first mode setting signal is enabled;

generating the first falling output control signal and the third falling output control signal that are enabled in synchronization with the second transmission clock when the second mode setting signal is enabled; and

generating the first, second, third, and fourth falling output control signals that are disabled when the third mode setting signal is enabled.

Technical Field

Embodiments of the present disclosure relate to a semiconductor device that outputs data in synchronization with a divided internal clock.

Background

In general, a semiconductor device including a DDR SDRAM (double data rate synchronous DRAM) performs a data read/write operation according to a command input from an external chipset. The semiconductor device needs to include various circuits therein in order to perform such read/write operations, and the various circuits include a pipe latch circuit (pipe latch circuit) for efficiently controlling more data. In general, pipe latch circuits configured to store a plurality of input signals at desired timings, respectively, and output a plurality of input signals at desired timings, respectively, may be included in a semiconductor device, and signal transmission/reception capability between internal circuits or between an external device of the semiconductor device and the internal circuits of the semiconductor device is increased.

Semiconductor devices including DDR SDRAM use various methods to increase operating speed. As a representative example, the semiconductor device may generate a plurality of divided clocks by dividing a clock input from the outside, and control the pipe latch circuit to operate in synchronization with the plurality of divided clocks in order to improve an operation speed.

The semiconductor device supports an operation for determining a data input/output order and an operation for changing an output order of odd data and even data.

Disclosure of Invention

A semiconductor device according to an embodiment of the present disclosure includes an internal clock generation circuit configured to generate a first internal clock, a second internal clock, a third internal clock, and a fourth internal clock from a first divided clock, a second divided clock, a third divided clock, a fourth divided clock, and a ground voltage in a first mode and a second mode. The semiconductor device further includes a data processing circuit configured to latch the first internal data, the second internal data, the third internal data, and the fourth internal data according to the first input control signal, the second input control signal, the third input control signal, and the fourth input control signal. The data processing circuit is further configured to generate first output data, second output data, third output data, and fourth output data by determining output priorities of the latched first and third internal data and the latched second and fourth internal data according to the first to fourth internal clocks, the first rising output control signal, the second rising output control signal, the third rising output control signal, the fourth rising output control signal, the first falling output control signal, the second falling output control signal, the third falling output control signal, and the fourth falling output control signal.

Another semiconductor device according to an embodiment of the present disclosure includes a mode setting circuit configured to generate a first mode setting signal, a second mode setting signal, and a third mode setting signal according to a combination of a first mode signal and a second mode signal. The semiconductor device further includes an internal clock generation circuit configured to generate a first internal clock, a second internal clock, a third internal clock, and a fourth internal clock from the first divided clock, the second divided clock, the third divided clock, the fourth divided clock, and the ground voltage according to the first to third mode setting signals. The semiconductor device further includes a data processing circuit configured to latch the first internal data, the second internal data, the third internal data, and the fourth internal data according to the first input control signal, the second input control signal, the third input control signal, and the fourth input control signal. The data processing circuit is further configured to generate first output data, second output data, third output data, and fourth output data by determining output priorities of the latched first and third internal data and the latched second and fourth internal data according to the first to fourth internal clocks, the first rising output control signal, the second rising output control signal, the third rising output control signal, the fourth rising output control signal, the first falling output control signal, the second falling output control signal, the third falling output control signal, and the fourth falling output control signal.

According to an embodiment, a semiconductor device is configured to selectively generate a plurality of internal clocks for determining an input/output order of data from a plurality of divided clocks and a ground voltage according to an operation mode, and determine an input/output order of data synchronized with the selectively generated internal clocks, thereby outputting data at high speed.

Further, the semiconductor device according to the embodiment determines the input/output order of data synchronized with the plurality of internal clocks selectively generated according to the operation mode, and a separate circuit for changing the input/output order of data is not required, which makes it possible to reduce the area.

Further, the semiconductor device according to the embodiment determines the input/output order of data synchronized with the plurality of internal clocks selectively generated according to the operation mode, and a separate circuit for changing the input/output order of data is not required, which makes it possible to reduce current consumption.

Drawings

Fig. 1 is a block diagram showing a configuration of a semiconductor device according to an embodiment.

Fig. 2 is a circuit diagram showing a configuration of a mode setting circuit included in the semiconductor device shown in fig. 1.

Fig. 3 is a block diagram showing a configuration of a pipe control circuit included in the semiconductor device shown in fig. 1.

Fig. 4 is a circuit diagram showing a configuration of a first transmission clock generation circuit included in the pipe control circuit shown in fig. 3.

Fig. 5 is a circuit diagram showing a configuration of a second transmission clock generation circuit included in the pipe control circuit shown in fig. 3.

Fig. 6 is a block diagram showing a configuration of an internal clock generation circuit included in the semiconductor device shown in fig. 1.

Fig. 7 is a circuit diagram showing a configuration of a first transmission circuit included in the internal clock generation circuit shown in fig. 6.

Fig. 8 is a circuit diagram showing a configuration of a second transmission circuit included in the internal clock generation circuit shown in fig. 6.

Fig. 9 is a circuit diagram showing a configuration of a third transmission circuit included in the internal clock generation circuit shown in fig. 6.

Fig. 10 is a circuit diagram showing a configuration of a fourth transmission circuit included in the internal clock generation circuit shown in fig. 6.

Fig. 11 is a block diagram showing a configuration of a pipe circuit included in the semiconductor device shown in fig. 1.

Fig. 12 is a block diagram showing a configuration of a data sorting circuit included in the semiconductor device shown in fig. 1.

Fig. 13 to 16 are timing charts for describing the operation of the semiconductor device according to the embodiment.

Fig. 17 is a diagram illustrating a configuration of an electronic system according to an embodiment to which the semiconductor device illustrated in fig. 1 to 16 is applied.

Detailed Description

Hereinafter, a semiconductor device is described by various embodiments with reference to the accompanying drawings. It should be noted that the embodiments are merely examples for describing the present disclosure, and the scope of the present disclosure is not limited thereto.

Various embodiments relate to a semiconductor device capable of selectively generating a plurality of internal clocks for determining an input/output order of data from a plurality of divided clocks and a ground voltage according to an operation mode and determining the input/output order of data in synchronization with the plurality of internal clocks that are selectively generated.

As shown in fig. 1, a semiconductor device 1 according to an embodiment may include a mode setting circuit 10, a pipe control circuit 20, an internal clock generation circuit 30, a memory area 40, and a data processing circuit 50.

The MODE setting circuit 10 may generate the first MODE setting signal EV, the second MODE setting signal OD, and the third MODE setting signal NOR that are selectively enabled according to a combination of logic levels of the first and second MODE signals MODE <1:2 >. The MODE setting circuit 10 may generate the first MODE setting signal EV enabled in the first MODE according to a combination of logic levels of the first and second MODE signals MODE <1:2 >. The MODE setting circuit 10 may generate the second MODE setting signal OD enabled in the second MODE according to a combination of logic levels of the first and second MODE signals MODE <1:2 >. The MODE setting circuit 10 may generate the third MODE setting signal NOR enabled in the third MODE according to a combination of logic levels of the first and second MODE signals MODE <1:2 >. The first mode may be set to a mode for outputting the second bit ID <2>, the fourth bit ID <4>, the sixth bit ID <6> and the eighth bit ID <8> of the internal data after outputting the first bit ID <1>, the third bit ID <3>, the fifth bit ID <5> and the seventh bit ID <7> of the internal data. The second mode may be set to a mode for outputting the first bit ID <1>, the third bit ID <3>, the fifth bit ID <5> and the seventh bit ID <7> of the internal data after outputting the second bit ID <2>, the fourth bit ID <4>, the sixth bit ID <6> and the eighth bit ID <8> of the internal data. The third mode may be set to a mode of outputting the first to eighth bits ID <1:8> of the internal data without changing the order of the first to eighth bits ID <1:8> of the internal data. As used herein, first through nth refer to first, second, third, … nth, where N is a count. For example, "the first to eighth bits" include a first bit, a second bit, a third bit, a fourth bit, a fifth bit, a sixth bit, a seventh bit, and an eighth bit.

The pipe control circuit 20 may enter the first to third modes to generate the first to fourth input control signals PIN <1:4> from the rising clock RCLK and the falling clock FCLK. When any one of the first to third mode setting signals EV, OD and NOR is enabled, the pipe control circuit 20 may generate the first to fourth input control signals PIN <1:4> from the rising clock RCLK and the falling clock FCLK.

When entering the first mode, the pipe control circuit 20 may generate first and third rising output control signals ROUT <1,3> from the rising clock RCLK, the falling clock FCLK, and the ground voltage VSS, and then generate second and fourth falling output control signals FOUT <2,4 >. When the first mode setting signal EV is enabled, the pipe control circuit 20 may generate first and third rising output control signals ROUT <1,3> from the rising clock RCLK, the falling clock FCLK, and the ground voltage VSS, and then generate second and fourth falling output control signals FOUT <2,4 >.

When entering the second mode, the pipe control circuit 20 may generate the second and fourth rising output control signals ROUT <2,4> from the rising clock RCLK, the falling clock FCLK, and the ground voltage VSS, and then generate the first and third falling output control signals FOUT <1,3 >. When the second mode setting signal OD is enabled, the pipe control circuit 20 may generate the second and fourth rising output control signals ROUT <2,4> from the rising clock RCLK, the falling clock FCLK, and the ground voltage VSS, and then generate the first and third falling output control signals FOUT <1,3 >.

When entering the third mode, the pipe control circuit 20 may generate the first to fourth rising output control signals ROUT <1:4> from the rising clock RCLK and the falling clock FCLK. When the third mode setting signal NOR is enabled, the pipe control circuit 20 may generate the first to fourth rising output control signals ROUT <1:4> from the rising clock RCLK and the falling clock FCLK. Although the pipe control circuit 20 is configured to generate the first to fourth rising output control signals ROUT <1:4> when the third mode setting signal NOR is enabled, the pipe control circuit 20 may be configured to generate the first to fourth falling output control signals FOUT <1:4> in another embodiment. The rising clock RCLK may be set to a signal that transitions in synchronization with a rising edge of a clock input from the outside. The falling clock FCLK may be set to a signal that transitions in synchronization with a falling edge of a clock input from the outside. The ground voltage VSS may be set to a general ground voltage used in the semiconductor device 1.

When entering the first mode, the internal clock generation circuit 30 may generate the first and third internal clocks ICLK and IBCLK from the first and third divided clocks ICLK _ PRE and IBCLK _ PRE and the ground voltage VSS, and then generate the second and fourth internal clocks QCLK and QBCLK. When the first mode setting signal EV is enabled, the internal clock generation circuit 30 may generate the first and third internal clocks ICLK and IBCLK from the first and third divided clocks ICLK _ PRE and IBCLK _ PRE and the ground voltage VSS, and then generate the second and fourth internal clocks QCLK and QBCLK.

When entering the second mode, the internal clock generation circuit 30 may generate the second and fourth internal clocks QCLK and QBCLK from the second and fourth frequency-divided clocks QCLK _ PRE and QBCLK _ PRE and the ground voltage VSS, and then generate the first and third internal clocks ICLK and IBCLK. When the second mode setting signal OD is enabled, the internal clock generation circuit 30 may generate the second and fourth internal clocks QCLK and QBCLK from the second and fourth frequency-divided clocks QCLK _ PRE and QBCLK _ PRE and the ground voltage VSS, and then generate the first and third internal clocks ICLK and IBCLK.

When entering the third mode, the internal clock generation circuit 30 may generate the first, second, third, and fourth internal clocks ICLK, QCLK, IBCLK, and QBCLK from the first, second, third, and fourth divided clocks ICLK _ PRE, QCLK _ PRE, IBCLK _ PRE, and QBCLK _ PRE. When the third mode setting signal NOR is enabled, the internal clock generation circuit 30 may generate the first, second, third, and fourth internal clocks ICLK, QCLK, IBCLK, and QBCLK from the first, second, third, and QBCLK _ PRE. The first, second, third, and fourth frequency-divided clocks ICLK _ PRE, QCLK _ PRE, IBCLK _ PRE, and QBCLK _ PRE may be set as signals generated by dividing a clock input from the outside. The first, second, third, and fourth divided clocks ICLK _ PRE, QCLK _ PRE, IBCLK _ PRE, and QBCLK _ PRE may be set to signals including one or more pulses. The first, second, third, and fourth divided clocks ICLK _ PRE, QCLK _ PRE, IBCLK _ PRE, and QBCLK _ PRE may be set to signals having different phases.

The memory area 40 may output first to eighth bits ID <1:8> of internal data stored therein in first to third modes. The first bit ID <1> and the fifth bit ID <5> of the internal data may be successively output through the same input/output line. The second bit ID <2> and the sixth bit ID <6> of the internal data may be successively output through the same input/output line. The third bit ID <3> and the seventh bit ID <7> of the internal data may be successively output through the same input/output line. The fourth bit ID <4> and the eighth bit ID <8> of the internal data may be successively output through the same input/output line.

The data processing circuit 50 may include a pipeline circuit 51 and a data sorting circuit (data sorting circuit) 52.

The pipe circuit 51 may latch first to eighth bits ID <1:8> of the internal data according to the first to fourth input control signals PIN <1:4 >. The pipe circuit 51 may output the first to eighth bits ID <1:8> of the latched internal data as the first latch data LD1<1:2>, the second latch data LD2<1:2>, the third latch data LD3<1:2> and the fourth latch data LD4<1:2> according to the first to fourth rising output control signals ROUT <1:4> and the first to fourth falling output control signals FOUT <1:4 >.

The data sorting circuit 52 may generate the first to eighth output data DOUT <1:8> from the first latch data LD1<1:2>, the second latch data LD2<1:2>, the third latch data LD3<1:2> and the fourth latch data LD4<1:2> in synchronization with the first internal clock ICLK, the second internal clock QCLK, the third internal clock IBCLK and the fourth internal clock QBCLK.

The data processing circuit 50 may latch the first to eighth bits ID <1:8> of the internal data according to the first to fourth input control signals PIN <1:4 >. The data processing circuit 50 may generate the first to eighth output data DOUT <1:8> by determining output priorities of the first to eighth bits ID <1:8> of the latched internal data according to the first to fourth internal clocks ICLK, QCLK, IBCLK, and QBCLK, and the first to fourth rising output control signals ROUT <1:4> and FOUT <1:4 >.

Referring to fig. 2, the mode setting circuit 10 may include a first logic circuit 11, a second logic circuit 12, and a third logic circuit 13.

The first logic circuit 11 may include inverters IV11 and IV 12. The first logic circuit 11 may generate the first MODE setting signal EV by buffering the first MODE signal MODE <1 >. The first mode setting signal EV may be set to a signal that is enabled to a logic high level to enter the first mode.

The second logic circuit 12 may include inverters IV13 and IV 14. The second logic circuit 12 may generate the second MODE setting signal OD by buffering the second MODE signal MODE <2 >. The second mode setting signal OD may be set to a signal that is enabled to a logic high level to enter the second mode.

The third logic circuit 13 may include inverters IV15, IV16, IV17, and IV18, and a NAND gate NAND 11. The third logic circuit 13 may generate the third MODE setting signal NOR according to the logic levels of the first MODE signal MODE <1> and the second MODE signal MODE <2 >. The third mode setting signal NOR may be set to a signal that is enabled to a logic high level to enter the third mode.

The MODE setting circuit 10 may generate the first MODE setting signal EV enabled to a logic high level when the first MODE signal MODE <1> is at a logic high level and the second MODE signal MODE <2> is at a logic low level in order to enter the first MODE. The MODE setting circuit 10 may generate the second MODE setting signal OD enabled to a logic high level when the first MODE signal MODE <1> is at a logic low level and the second MODE signal MODE <2> is at a logic high level in order to enter the second MODE. The MODE setting circuit 10 may generate the third MODE setting signal NOR enabled to a logic high level when the first MODE signal MODE <1> is at a logic low level and the second MODE signal MODE <2> is at a logic low level in order to enter the third MODE.

Referring to fig. 3, the pipe control circuit 20 may include an input control signal generation circuit 21 and an output control signal generation circuit 22.

The input control signal generation circuit 21 may generate the first to fourth input control signals PIN <1:4> that are simultaneously enabled to a logic high level by the rising clock RCLK and the falling clock FCLK when any one of the first to third mode setting signals EV, OD and NOR is enabled to a logic high level. The first to fourth input control signals PIN <1:4> may be generated as signals including high-level first and second pulses.

The output control signal generation circuit 22 may include a first transmission clock generation circuit 210, a second transmission clock generation circuit 220, a rising output control signal generation circuit 230, and a falling output control signal generation circuit 240.

The first transmission clock generation circuit 210 may generate a first transmission clock TCLK <1> from a rising clock RCLK and a ground voltage VSS according to a first mode setting signal EV, a second mode setting signal OD, and a third mode setting signal NOR. When the first mode setting signal EV is enabled to a logic high level, the first transmission clock generation circuit 210 may generate the first transmission clock TCLK <1> from the rising clock RCLK. When the second mode setting signal OD is enabled to a logic high level, the first transmission clock generation circuit 210 may generate the first transmission clock TCLK <1> from the ground voltage VSS. When the third mode setting signal NOR is enabled to a logic high level, the first transfer clock generation circuit 210 may generate the first transfer clock TCLK <1> from the rising clock RCLK.

The second transfer clock generation circuit 220 may generate a second transfer clock TCLK <2> from the rising clock RCLK, the falling clock FCLK, and the ground voltage VSS according to the first mode setting signal EV, the second mode setting signal OD, and the third mode setting signal NOR. When the first mode setting signal EV is enabled to a logic high level, the second transfer clock generation circuit 220 may generate the second transfer clock TCLK <2> from the ground voltage. When the second mode setting signal OD is enabled to a logic high level, the second transmission clock generation circuit 220 may generate the second transmission clock TCLK <2> from the rising clock RCLK. When the third mode setting signal NOR is enabled to a logic high level, the second transfer clock generation circuit 220 may generate the second transfer clock TCLK <2> from the falling clock FCLK.

The rising output control signal generating circuit 230 may generate the first to fourth rising output control signals ROUT <1:4> in synchronization with the first transmission clock TCLK <1> according to the first mode setting signal EV, the second mode setting signal OD, and the third mode setting signal NOR. When the first mode setting signal EV is enabled to a logic high level, the rising output control signal generating circuit 230 may generate the first and third rising output control signals ROUT <1,3> in synchronization with the first transmission clock TCLK <1 >. When the second mode setting signal OD is enabled to a logic high level, the rising output control signal generating circuit 230 may generate the second and fourth rising output control signals ROUT <2,4> in synchronization with the first transmission clock TCLK <1 >. When the third mode setting signal NOR is enabled to a logic high level, the rising output control signal generating circuit 230 may generate the first to fourth rising output control signals ROUT <1:4> in synchronization with the first transmission clock TCLK <1 >.

The falling output control signal generating circuit 240 may generate the first to fourth falling output control signals FOUT <1:4> in synchronization with the second transfer clock TCLK <2> according to the first mode setting signal EV, the second mode setting signal OD, and the third mode setting signal NOR. When the first mode setting signal EV is enabled to the logic high level, the falling output control signal generation circuit 240 may generate the second and fourth falling output control signals FOUT <2,4> in synchronization with the second transfer clock TCLK <2 >. When the second mode setting signal OD is enabled to a logic high level, the falling output control signal generating circuit 240 may generate the first and third falling output control signals FOUT <1,3> in synchronization with the second transmission clock TCLK <2 >. When the third mode setting signal NOR is enabled to a logic high level, the falling output control signal generation circuit 240 may generate the first to fourth falling output control signals FOUT <1:4> that are enabled to a logic low level.

The output control signal generation circuit 22 may generate first to fourth rising output control signals ROUT <1:4> from a rising clock RCLK and a ground voltage VSS according to a first mode setting signal EV, a second mode setting signal OD, and a third mode setting signal NOR. The output control signal generation circuit 22 may generate first to fourth falling output control signals FOUT <1:4> from the rising clock RCLK, the falling clock FCLK, and the ground voltage VSS according to the first mode setting signal EV, the second mode setting signal OD, and the third mode setting signal NOR.

Referring to fig. 4, the first transmission clock generation circuit 210 may include a first clock transmission circuit 211, a second clock transmission circuit 212, a third clock transmission circuit 213, and a first transmission clock output circuit 214.

The first clock transmission circuit 211 may include inverters IV21 and IV 22. When the first mode setting signal EV is enabled to a logic high level, the first clock transfer circuit 211 may invert and buffer the rising clock RCLK, and output the inverted and buffered signal to the node nd 21.

The second clock transmission circuit 212 may include inverters IV23 and IV 24. When the second mode setting signal OD is enabled to a logic high level, the second clock transfer circuit 212 may invert and buffer the ground voltage VSS and output the inverted and buffered signal to the node nd 21.

The third clock transmission circuit 213 may include inverters IV25 and IV 26. When the third mode setting signal NOR is enabled to a logic high level, the third clock transfer circuit 213 may invert and buffer the rising clock RCLK, and output the inverted and buffered signal to the node nd 21.

The first transmission clock output circuit 214 may include an inverter IV 27. The first transmission clock output circuit 214 may invert and buffer the signal of the node nd21 and output the inverted and buffered signal as the first transmission clock TCLK <1 >.

Referring to fig. 5, the second transmission clock generation circuit 220 may include a fourth clock transmission circuit 221, a fifth clock transmission circuit 222, a sixth clock transmission circuit 223, and a second transmission clock output circuit 224.

The fourth clock transmission circuit 221 may include inverters IV31 and IV 32. When the first mode setting signal EV is enabled to a logic high level, the fourth clock transfer circuit 221 may invert and buffer the ground voltage VSS and output the inverted and buffered signal to the node nd 31.

The fifth clock transmission circuit 222 may include inverters IV33 and IV 34. When the second mode setting signal OD is enabled to a logic high level, the fifth clock transmission circuit 222 may invert and buffer the rising clock RCLK, and output the inverted and buffered signal to the node nd 31.

The sixth clock transmission circuit 223 may include inverters IV35 and IV 36. When the third mode setting signal NOR is enabled to a logic high level, the sixth clock transfer circuit 223 may invert and buffer the falling clock FCLK and output the inverted and buffered signal to the node nd 31.

The second transmission clock output circuit 224 may include an inverter IV 37. The second transmission clock output circuit 224 may invert and buffer the signal of the node nd31 and output the inverted and buffered signal as the second transmission clock TCLK <2 >.

Referring to fig. 6, the internal clock generation circuit 30 may include a first transmission circuit 31, a second transmission circuit 32, a third transmission circuit 33, and a fourth transmission circuit 34.

The first transfer circuit 31 may generate the first internal clock ICLK from the first frequency division clock ICLK _ PRE or the ground voltage VSS according to the first mode setting signal EV, the second mode setting signal OD, and the third mode setting signal NOR. When the first mode setting signal EV is enabled to the logic high level, the first transfer circuit 31 may generate the first internal clock ICLK from the first frequency division clock ICLK _ PRE. When the second mode setting signal OD is enabled to a logic high level, the first transfer circuit 31 may generate the first internal clock ICLK from the ground voltage VSS. When the third mode setting signal NOR is enabled to a logic high level, the first transfer circuit 31 may generate the first internal clock ICLK from the first frequency division clock ICLK _ PRE.

The second transfer circuit 32 may generate the second internal clock QCLK from the first frequency-divided clock ICLK _ PRE, the second frequency-divided clock QCLK _ PRE, or the ground voltage VSS according to the first mode setting signal EV, the second mode setting signal OD, and the third mode setting signal NOR. When the first mode setting signal EV is enabled to a logic high level, the second transfer circuit 32 may generate the second internal clock QCLK from the ground voltage VSS. When the second mode setting signal OD is enabled to a logic high level, the second transmission circuit 32 may generate the second internal clock QCLK from the first frequency division clock ICLK _ PRE. When the third mode setting signal NOR is enabled to a logic high level, the second transfer circuit 32 may generate the second internal clock QCLK from the second frequency-divided clock QCLK _ PRE.

The third transfer circuit 33 may generate the third internal clock IBCLK from the third divided clock IBCLK _ PRE or the ground voltage VSS according to the first mode setting signal EV, the second mode setting signal OD, and the third mode setting signal NOR. When the first mode setting signal EV is enabled to a logic high level, the third transmission circuit 33 may generate the third internal clock IBCLK from the third divided clock IBCLK _ PRE. When the second mode setting signal OD is enabled to a logic high level, the third transmission circuit 33 may generate the third internal clock IBCLK from the ground voltage VSS. When the third mode setting signal NOR is enabled to a logic high level, the third transfer circuit 33 may generate the third internal clock IBCLK from the third divided clock IBCLK _ PRE.

The fourth transmission circuit 34 may generate the fourth internal clock QBCLK from the third divided clock IBCLK _ PRE, the fourth divided clock QBCLK _ PRE or the ground voltage VSS according to the first mode setting signal EV, the second mode setting signal OD and the third mode setting signal NOR. When the first mode setting signal EV is enabled to a logic high level, the fourth transfer circuit 34 may generate the fourth internal clock QBCLK from the ground voltage VSS. When the second mode setting signal OD is enabled to a logic high level, the fourth transmission circuit 34 may generate the fourth internal clock QBCLK from the third divided clock IBCLK _ PRE. When the third mode setting signal NOR is enabled to a logic high level, the fourth transmission circuit 34 may generate the fourth internal clock QBCLK from the fourth frequency division clock QBCLK _ PRE.

Referring to fig. 7, the first transmission circuit 31 may include a first internal transmission circuit 311, a second internal transmission circuit 312, a third internal transmission circuit 313, and a first internal clock output circuit 314.

The first internal transmission circuit 311 may include inverters IV41 and IV 42. When the first mode setting signal EV is enabled to a logic high level, the first internal transmission circuit 311 may invert and buffer the first frequency division clock ICLK _ PRE and output the inverted and buffered signal to the node nd 41.

The second internal transmission circuit 312 may include inverters IV43 and IV 44. When the second mode setting signal OD is enabled to a logic high level, the second internal transmission circuit 312 may invert and buffer the ground voltage VSS and output the inverted and buffered signal to the node nd 41.

The third internal transmission circuit 313 may include inverters IV45 and IV 46. When the third mode setting signal NOR is enabled to a logic high level, the third internal transmission circuit 313 may invert and buffer the first frequency division clock ICLK _ PRE and output the inverted and buffered signal to the node nd 41.

The first internal clock output circuit 314 may include an inverter IV 47. The first internal clock output circuit 314 may invert and buffer the signal of the node nd41 and output the inverted and buffered signal as the first internal clock ICLK.

Referring to fig. 8, the second transmission circuit 32 may include a fourth internal transmission circuit 321, a fifth internal transmission circuit 322, a sixth internal transmission circuit 323, and a second internal clock output circuit 324.

The fourth internal transmission circuit 321 may include inverters IV51 and IV 52. When the first mode setting signal EV is enabled to a logic high level, the fourth internal transfer circuit 321 may invert and buffer the ground voltage VSS and output the inverted and buffered signal to the node nd 51.

The fifth internal transmission circuit 322 may include inverters IV53 and IV 54. When the second mode setting signal OD is enabled to a logic high level, the fifth internal transmission circuit 322 may invert and buffer the first frequency division clock ICLK _ PRE and output the inverted and buffered signal to the node nd 51.

The sixth internal transmission circuit 323 may include inverters IV55 and IV 56. When the third mode setting signal NOR is enabled to a logic high level, the sixth internal transmission circuit 323 may invert and buffer the second frequency division clock QCLK _ PRE and output the inverted and buffered signal to the node nd 51.

The second internal clock output circuit 324 may include an inverter IV 57. The second internal clock output circuit 324 may invert and buffer the signal of the node nd51 and output the inverted and buffered signal as the second internal clock QCLK.

Referring to fig. 9, the third transmission circuit 33 may include a seventh internal transmission circuit 331, an eighth internal transmission circuit 332, a ninth internal transmission circuit 333, and a third internal clock output circuit 334.

The seventh internal transmission circuit 331 may include inverters IV61 and IV 62. When the first mode setting signal EV is enabled to a logic high level, the seventh internal transmission circuit 331 may invert and buffer the third divided clock IBCLK _ PRE and output the inverted and buffered signal to the node nd 61.

The eighth internal transmission circuit 332 may include inverters IV63 and IV 64. When the second mode setting signal OD is enabled to a logic high level, the eighth internal transmission circuit 332 may invert and buffer the ground voltage VSS and output the inverted and buffered signal to the node nd 61.

The ninth internal transmission circuit 333 may include inverters IV65 and IV 66. When the third mode setting signal NOR is enabled to a logic high level, the ninth internal transmission circuit 333 may invert and buffer the third divided clock IBCLK _ PRE and output the inverted and buffered signal to the node nd 61.

The third internal clock output circuit 334 may include an inverter IV 67. The third internal clock output circuit 334 may invert and buffer the signal of the node nd61 and output the inverted and buffered signal as the third internal clock IBCLK.

Referring to fig. 10, the fourth transmission circuit 34 may include a tenth internal transmission circuit 341, an eleventh internal transmission circuit 342, a twelfth internal transmission circuit 343, and a fourth internal clock output circuit 344.

The tenth internal transmission circuit 341 may include inverters IV71 and IV 72. When the first mode setting signal EV is enabled to a logic high level, the tenth internal transfer circuit 341 may invert and buffer the ground voltage VSS and output the inverted and buffered signal to the node nd 71.

The eleventh internal transmission circuit 342 may include inverters IV73 and IV 74. When the second mode setting signal OD is enabled to a logic high level, the eleventh internal transmission circuit 342 may invert and buffer the third divided clock IBCLK _ PRE and output the inverted and buffered signal to the node nd 71.

The twelfth internal transmission circuit 343 may include inverters IV75 and IV 76. When the third mode setting signal NOR is enabled to a logic high level, the twelfth internal transmission circuit 343 may invert and buffer the fourth frequency division clock QBCLK _ PRE and output the inverted and buffered signal to the node nd 71.

The fourth internal clock output circuit 344 may include an inverter IV 77. The fourth internal clock output circuit 344 may invert and buffer the signal of the node nd71 and output the inverted and buffered signal as the fourth internal clock QBCLK.

Referring to fig. 11, the pipe circuit 51 may include a first pipe latch 511, a second pipe latch 512, a third pipe latch 513, and a fourth pipe latch 514.

The first pipe latch 511 may latch the first bit ID <1> and the fifth bit ID <5> of the internal data according to the first input control signal PIN <1 >. The first pipe latch 511 may generate first latch data LD1<1:2> from first and fifth bits ID <1,5> of the latched internal data according to the first rising output control signal ROUT <1 >. The first pipe latch 511 may generate the first latch data LD1<1:2> from the first and fifth bits ID <1,5> of the latched internal data according to the first falling output control signal FOUT <1 >.

The second pipe latch 512 may latch the second bit ID <2> and the sixth bit ID <6> of the internal data according to the second input control signal PIN <2 >. The second pipe latch 512 may generate second latch data LD2<1:2> from the second and sixth bits ID <2,6> of the latched internal data according to the second rising output control signal ROUT <2 >. The second pipe latch 512 may generate second latch data LD2<1:2> from the second and sixth bits ID <2,6> of the latched internal data according to the second falling output control signal FOUT <2 >.

The third pipe latch 513 may latch the third bit ID <3> and the seventh bit ID <7> of the internal data according to the third input control signal PIN <3 >. The third pipe latch 513 may generate third latch data LD3<1:2> from third and seventh bits ID <3,7> of the latched internal data according to a third rising output control signal ROUT <3 >. The third pipe latch 513 may generate third latch data LD3<1:2> from the third and seventh bits ID <3,7> of the latched internal data according to the third falling output control signal FOUT <3 >.

The fourth pipe latch 514 may latch the fourth bit ID <4> and the eighth bit ID <8> of the internal data according to the fourth input control signal PIN <4 >. The fourth pipe latch 514 may generate fourth latch data LD4<1:2> from fourth and eighth bits ID <4,8> of the latched internal data according to a fourth rising output control signal ROUT <4 >. The fourth pipe latch 514 may generate fourth latch data LD4<1:2> from fourth and eighth bits ID <4,8> of the latched internal data according to a fourth falling output control signal FOUT <4 >.

According to fig. 12, the data sorting circuit 52 may include a first driver 521, a second driver 522, a third driver 523, a fourth driver 524, and a transmitter 525.

The first driver 521 may drive the node nd81 in synchronization with the first internal clock ICLK according to the logic level of the first latch data LD1<1:2 >. The first driver 521 may drive the node nd81 according to the logic level of the first latch data LD1<1:2> during an interval in which the first internal clock ICLK is input at a logic high level.

The second driver 522 may drive the node nd81 in synchronization with the second internal clock QCLK according to the logic level of the second latch data LD2<1:2 >. The second driver 522 may drive the node nd81 according to the logic level of the second latch data LD2<1:2> during an interval in which the second internal clock QCLK is input at a logic high level.

The third driver 523 may drive the node nd81 in synchronization with the third internal clock IBCLK according to the logic level of the third latch data LD3<1:2 >. The third driver 523 may drive the node nd81 according to the logic level of the third latch data LD3<1:2> during an interval in which the third internal clock IBCLK is input at a logic high level.

The fourth driver 524 may drive the node nd81 in synchronization with the fourth internal clock QBCLK according to the logic level of the fourth latch data LD4<1:2 >. The fourth driver 524 may drive the node nd81 according to the logic level of the fourth latch data LD4<1:2> during an interval in which the fourth internal clock QBCLK is input at the logic high level.

The transmitter 525 may drive the first to eighth output data DOUT <1:8> according to the logic level of the node nd 81. The transmitter 525 may output the first to eighth output data DOUT <1:8> driven according to the logic level of the node nd81 to the outside.

Referring to fig. 13 and 14, the operation of the semiconductor device 1 according to the present embodiment will be described. During this operation, the second mode is continuously executed after the first mode.

Before describing the operation, the MODE setting circuit 10 generates the first MODE setting signal EV enabled to a logic high level in order to enter the first MODE, based on the first MODE signal MODE <1> of a high level and the second MODE signal MODE <2> of a low level.

The memory area 40 outputs first to eighth bits ID <1:8> of internal data stored therein.

Referring to fig. 13, the input control signal generation circuit 21 of the pipeline control circuit 20 generates the first pulses of the first to fourth input control signals PIN <1:4> that are simultaneously enabled to a logic high level through the high-level first mode setting signal EV from time T1 to time T2 in synchronization with the rising clock RCLK and the falling clock FCLK.

The pipeline circuit 51 of the data processing circuit 50 latches the first to eighth bits ID <1:8> of the internal data according to the first to fourth input control signals PIN <1:4 >.

At this time, the pipe circuit 51 of the data processing circuit 50 stores the first bit ID <1>, the second bit ID <2>, the third bit ID <3>, and the fourth bit ID <4> of the internal data.

The input control signal generation circuit 21 of the pipe circuit 20 generates the second pulses of the first to fourth input control signals PIN <1:4> that are simultaneously enabled to a logic high level by the first mode setting signal EV of a high level from time T3 to time T4 in synchronization with the rising clock RCLK and the falling clock FCLK.

The pipeline circuit 51 of the data processing circuit 50 latches the first to eighth bits ID <1:8> of the internal data according to the first to fourth input control signals PIN <1:4 >.

At this time, the pipe circuit 51 of the data processing circuit 50 stores the fifth bit ID <5>, the sixth bit ID <6>, the seventh bit ID <7> and the eighth bit ID <8> of the internal data.

The time T11 in fig. 14 is set to the same time as the time T1 in fig. 13, and the time T12 in fig. 14 is set to the same time as the time T4 in fig. 13.

Referring to fig. 14, the output control signal generation circuit 22 generates the first and third rising output control signals ROUT <1,3> of a high level from the rising clock RCLK according to the first mode setting signal EV of a high level at time T13. At this time, the output control signal generation circuit 22 generates the second and fourth rising output control signals ROUT <2,4> of a low level from the ground voltage VSS according to the first mode setting signal EV of a high level.

The pipe circuit 51 outputs the first and third bits ID <1,3> of the latched internal data as the first bit LD1<1> of the first latch data and the first bit LD3<1> of the third latch data according to the first and third rising output control signals ROUT <1,3> of high level.

The internal clock generation circuit 30 generates a first pulse of the first internal clock ICLK from the first divided clock ICLK _ PRE according to the first mode setting signal EV of the high level.

The data sorting circuit 52 generates the first output data DOUT <1> from the first bit LD1<1> of the first latch data in synchronization with the first internal clock ICLK. The first output data DOUT <1> is generated from the first bit ID <1> of the internal data.

At time T14, the internal clock generation circuit 30 generates the first pulse of the third internal clock IBCLK from the third divided clock IBCLK _ PRE according to the first mode setting signal EV of the high level.

The data sorting circuit 52 generates the second output data DOUT <2> from the first bit LD3<1> of the third latch data in synchronization with the third internal clock IBCLK. Second output data DOUT <2> is generated from a third bit ID <3> of the internal data.

At time T15, the pipe circuit 51 outputs the fifth and seventh bits ID <5,7> of the latched internal data as the second bit LD1<2> of the first latch data and the second bit LD3<2> of the third latch data according to the first and third rising output control signals ROUT <1,3> of high level.

The internal clock generation circuit 30 generates the second pulse of the first internal clock ICLK from the first divided clock ICLK _ PRE according to the first mode setting signal EV of the high level.

The data sorting circuit 52 generates the third output data DOUT <3> from the second bit LD1<2> of the first latch data in synchronization with the first internal clock ICLK. Third output data DOUT <3> is generated from a fifth bit ID <5> of the internal data.

At time T16, the internal clock generation circuit 30 generates a second pulse of the third internal clock IBCLK from the third divided clock IBCLK _ PRE according to the first mode setting signal EV of the high level.

The data sorting circuit 52 generates the fourth output data DOUT <4> from the second bit LD3<2> of the third latched data in synchronization with the third internal clock IBCLK. The fourth output data DOUT <4> is generated from the seventh bit ID <7> of the internal data.

At time T17, MODE setting circuit 10 generates second MODE setting signal OD enabled to a logic high level in order to enter the second MODE, based on first MODE signal MODE <1> at a low level and second MODE signal MODE <2> at a high level.

The output control signal generation circuit 22 generates the second and fourth falling output control signals FOUT <2,4> of high level from the falling clock FCLK according to the second mode setting signal OD of high level. At this time, the output control signal generating circuit 22 generates the first and third falling output control signals FOUT <1,3> of a low level from the ground voltage VSS according to the second mode setting signal OD of a high level.

The pipe circuit 51 outputs the second and fourth bits ID <2,4> of the latched internal data as the first bit LD2<1> of the second latched data and the first bit LD4<1> of the fourth latched data according to the second and fourth falling output control signals FOUT <2,4> of high level.

The internal clock generation circuit 30 generates a first pulse of the second internal clock QCLK from the first frequency-divided clock ICLK _ PRE according to the second mode setting signal OD of the high level.

The data sorting circuit 52 generates the fifth output data DOUT <5> from the first bit LD2<1> of the second latch data in synchronization with the second internal clock QCLK. The fifth output data DOUT <5> is generated from the second bit ID <2> of the internal data.

At time T18, the internal clock generation circuit 30 generates the first pulse of the fourth internal clock QBCLK from the third divided clock IBCLK _ PRE according to the second mode setting signal OD of the high level.

The data sorting circuit 52 generates sixth output data DOUT <6> from the first bit LD4<1> of the fourth latch data in synchronization with the fourth internal clock QBCLK. The sixth output data DOUT <6> is generated from the fourth bit ID <4> of the internal data.

At time T19, the pipe circuit 51 outputs the sixth and eighth bits ID <6,8> of the latched internal data as the second bit LD2<2> of the second latched data and the second bit LD4<2> of the fourth latched data according to the second and fourth falling output control signals FOUT <2,4> of the high level.

The internal clock generation circuit 30 generates a second pulse of the second internal clock QCLK from the first frequency-divided clock ICLK _ PRE according to the second mode setting signal OD of the high level.

The data sorting circuit 52 generates the seventh output data DOUT <7> from the second bit LD2<2> of the second latch data in synchronization with the second internal clock QCLK. The seventh output data DOUT <7> is generated from the sixth bit ID <6> of the internal data.

At time T20, the internal clock generation circuit 30 generates a second pulse of the fourth internal clock QBCLK from the third divided clock IBCLK _ PRE in accordance with the second mode setting signal OD of the high level.

The data sorting circuit 52 generates eighth output data DOUT <8> from the second bit LD4<2> of the fourth latch data in synchronization with the fourth internal clock QBCLK. The eighth output data DOUT <8> is generated from the eighth bit ID <8> of the internal data.

Referring to fig. 13 and 15, the operation of the semiconductor device 1 according to the present embodiment will be described. During this operation, the first mode is continuously executed after the second mode.

Before describing the operation, the MODE setting circuit 10 generates the second MODE setting signal OD enabled to a logic high level in order to enter the second MODE, based on the first MODE signal MODE <1> of a low level and the second MODE signal MODE <2> of a high level.

The memory area 40 outputs first to eighth bits ID <1:8> of internal data stored therein.

Referring to fig. 13, the input control signal generation circuit 21 of the pipeline control circuit 20 generates the first pulses of the first to fourth input control signals PIN <1:4> that are simultaneously enabled to a logic high level through the second mode setting signal OD of a high level from time T1 to time T2 in synchronization with the rising clock RCLK and the falling clock FCLK.

The pipeline circuit 51 of the data processing circuit 50 latches the first to eighth bits ID <1:8> of the internal data according to the first to fourth input control signals PIN <1:4 >.

At this time, the pipe circuit 51 of the data processing circuit 50 stores the first bit ID <1>, the second bit ID <2>, the third bit ID <3>, and the fourth bit ID <4> of the internal data.

The input control signal generation circuit 21 of the pipe circuit 20 generates the second pulses of the first to fourth input control signals PIN <1:4> that are simultaneously enabled to a logic high level by the second mode setting signal OD of a high level from time T3 to time T4 in synchronization with the rising clock RCLK and the falling clock FCLK.

The pipeline circuit 51 of the data processing circuit 50 latches the first to eighth bits ID <1:8> of the internal data according to the first to fourth input control signals PIN <1:4 >.

At this time, the pipe circuit 51 of the data processing circuit 50 stores the fifth bit ID <5>, the sixth bit ID <6>, the seventh bit ID <7> and the eighth bit ID <8> of the internal data.

Time T21 in fig. 15 is set to the same time as time T1 in fig. 13, and time T22 in fig. 15 is set to the same time as time T4 in fig. 13.

Referring to fig. 15, the output control signal generation circuit 22 generates the second and fourth rising output control signals ROUT <2,4> of a high level from the rising clock RCLK according to the second mode setting signal OD of a high level at time T23. At this time, the output control signal generation circuit 22 generates the first and third rising output control signals ROUT <1,3> of a low level from the ground voltage VSS according to the second mode setting signal OD of a high level.

The pipe circuit 51 outputs the second and fourth bits ID <2,4> of the latched internal data as the first bit LD2<1> of the second latched data and the first bit LD4<1> of the fourth latched data according to the second and fourth rising output control signals ROUT <2,4> of high level.

The internal clock generation circuit 30 generates a first pulse of the second internal clock QCLK from the first frequency-divided clock ICLK _ PRE according to the second mode setting signal OD of the high level.

The data sorting circuit 52 generates the first output data DOUT <1> from the first bit LD2<1> of the second latch data in synchronization with the second internal clock QCLK. The first output data DOUT <1> is generated from the second bit ID <2> of the internal data.

At time T24, the internal clock generation circuit 30 generates the first pulse of the fourth internal clock QBCLK from the third divided clock IBCLK _ PRE according to the second mode setting signal OD of the high level.

The data sorting circuit 52 generates the second output data DOUT <2> from the first bit LD4<1> of the fourth latch data in synchronization with the fourth internal clock QBCLK. The second output data DOUT <2> is generated from the fourth bit ID <4> of the internal data.

At time T25, the pipe circuit 51 outputs the sixth and eighth bits ID <6,8> of the latched internal data as the second bit LD2<2> of the second latched data and the second bit LD4<2> of the fourth latched data according to the second and fourth rising output control signals ROUT <2,4> of the high level.

The internal clock generation circuit 30 generates a second pulse of the second internal clock QCLK from the first frequency-divided clock ICLK _ PRE according to the second mode setting signal OD of the high level.

The data sorting circuit 52 generates the third output data DOUT <3> from the second bit LD2<2> of the second latch data in synchronization with the second internal clock QCLK. Third output data DOUT <3> is generated from a sixth bit ID <6> of the internal data.

At time T26, the internal clock generation circuit 30 generates a second pulse of the fourth internal clock QBCLK from the third divided clock IBCLK _ PRE in accordance with the second mode setting signal OD of the high level.

The data sorting circuit 52 generates the fourth output data DOUT <4> from the second bit LD4<2> of the fourth latch data in synchronization with the fourth internal clock QBCLK. Fourth output data DOUT <4> is generated from the eighth bit ID <8> of the internal data.

At time T27, MODE setting circuit 10 generates first MODE setting signal EV enabled to a logic high level in order to enter the first MODE, based on first MODE signal MODE <1> at a high level and second MODE signal MODE <2> at a low level.

The output control signal generation circuit 22 generates the first and third falling output control signals FOUT <1,3> of high level from the falling clock FCLK according to the first mode setting signal EV of high level. At this time, the output control signal generation circuit 22 generates the second and fourth falling output control signals FOUT <2,4> of a low level from the ground voltage VSS according to the first mode setting signal EV of a high level.

The pipe circuit 51 outputs the first and third bits ID <1,3> of the latched internal data as the first bit LD1<1> of the first latch data and the first bit LD3<1> of the third latch data according to the first and third falling output control signals FOUT <1,3> of high level.

The internal clock generation circuit 30 generates a first pulse of the first internal clock ICLK from the first divided clock ICLK _ PRE according to the first mode setting signal EV of the high level.

The data sorting circuit 52 generates the fifth output data DOUT <5> from the first bit LD1<1> of the first latch data in synchronization with the first internal clock ICLK. The fifth output data DOUT <5> is generated from the first bit ID <1> of the internal data.

At time T28, the internal clock generation circuit 30 generates the first pulse of the third internal clock IBCLK from the third divided clock IBCLK _ PRE according to the first mode setting signal EV of the high level.

The data sorting circuit 52 generates sixth output data DOUT <6> from the first bit LD3<1> of the third latch data in synchronization with the third internal clock IBCLK. Sixth output data DOUT <6> is generated from third bit ID <3> of the internal data.

At time T29, the pipe circuit 51 outputs the fifth and seventh bits ID <5,7> of the latched internal data as the second bit LD1<2> of the first latch data and the second bit LD3<2> of the third latch data according to the first and third falling output control signals FOUT <1,3> of the high level.

The internal clock generation circuit 30 generates the second pulse of the first internal clock ICLK from the first divided clock ICLK _ PRE according to the first mode setting signal EV of the high level.

The data sorting circuit 52 generates the seventh output data DOUT <7> from the second bit LD1<2> of the first latch data in synchronization with the first internal clock ICLK. The seventh output data DOUT <7> is generated from the fifth bit ID <5> of the internal data.

At time T30, the internal clock generation circuit 30 generates a second pulse of the third internal clock IBCLK from the third divided clock IBCLK _ PRE according to the first mode setting signal EV of the high level.

The data sorting circuit 52 generates eighth output data DOUT <8> from the second bit LD3<2> of the third latch data in synchronization with the third internal clock IBCLK. The eighth output data DOUT <8> is generated from the seventh bit ID <7> of the internal data.

Referring to fig. 13 and 16, the operation of the semiconductor device 1 according to the present embodiment will be described. During this operation, the third mode is executed.

Before describing the operation, the MODE setting circuit 10 generates the third MODE setting signal NOR enabled to a logic high level according to the first MODE signal MODE <1> of a low level and the second MODE signal MODE <2> of a low level in order to enter the third MODE.

The memory area 40 may output first to eighth bits ID <1:8> of internal data stored therein.

Referring to fig. 13, the input control signal generation circuit 21 of the pipeline control circuit 20 generates the first pulses of the first to fourth input control signals PIN <1:4> that are simultaneously enabled to a logic high level through the third mode setting signal NOR of a high level from time T1 to time T2 in synchronization with the rising clock RCLK and the falling clock FCLK.

The pipeline circuit 51 of the data processing circuit 50 latches the first to eighth bits ID <1:8> of the internal data according to the first to fourth input control signals PIN <1:4 >.

At this time, the pipe circuit 51 of the data processing circuit 50 stores the first bit ID <1>, the second bit ID <2>, the third bit ID <3>, and the fourth bit ID <4> of the internal data.

The input control signal generation circuit 21 of the pipeline circuit 20 generates the second pulses of the first to fourth input control signals PIN <1:4> that are simultaneously enabled to the logic high level by the third mode setting signal NOR of the high level in synchronization with the rising clock RCLK and the falling clock FCLK from time T3 to time T4.

The pipeline circuit 51 of the data processing circuit 50 latches the first to eighth bits ID <1:8> of the internal data according to the first to fourth input control signals PIN <1:4 >.

At this time, the pipe circuit 51 of the data processing circuit 50 stores the fifth bit ID <5>, the sixth bit ID <6>, the seventh bit ID <7> and the eighth bit ID <8> of the internal data.

Time T31 in fig. 16 is set to the same time as time T1 in fig. 13, and time T32 in fig. 16 is set to the same time as time T4 in fig. 13.

Referring to fig. 16, the output control signal generation circuit 22 generates the first to fourth rising output control signals ROUT <1:4> of high level from the rising clock RCLK according to the third mode setting signal NOR of high level at time T33.

The pipe circuit 51 outputs the first to fourth bits ID <1:4> of the latched internal data as the first bit LD1<1> of the first latch data, the first bit LD2<1> of the second latch data, the first bit LD3<1> of the third latch data, and the first bit LD4<1> of the fourth latch data according to the first to fourth rising output control signals ROUT <1:4> of a high level.

The internal clock generation circuit 30 generates a first pulse of the first internal clock ICLK from the first divided clock ICLK _ PRE according to the third mode setting signal NOR of the high level.

The data sorting circuit 52 generates the first output data DOUT <1> from the first bit LD1<1> of the first latch data in synchronization with the first internal clock ICLK. The first output data DOUT <1> is generated from the first bit ID <1> of the internal data.

At time T34, the internal clock generation circuit 30 generates the first pulse of the second internal clock QCLK from the second frequency-divided clock QCLK _ PRE according to the third mode setting signal NOR of the high level.

The data sorting circuit 52 generates the second output data DOUT <2> from the first bit LD2<1> of the second latch data in synchronization with the second internal clock QCLK. Second output data DOUT <2> is generated from a second bit ID <2> of the internal data.

At time T35, the internal clock generation circuit 30 generates the first pulse of the third internal clock IBCLK from the third divided clock IBCLK _ PRE according to the third mode setting signal NOR of the high level.

The data sorting circuit 52 generates third output data DOUT <3> from the first bit LD3<1> of the third latch data in synchronization with the third internal clock IBCLK. Third output data DOUT <3> is generated from a third bit ID <3> of the internal data.

At time T36, the internal clock generation circuit 30 generates the first pulse of the fourth internal clock QBCLK from the fourth frequency division clock QBCLK _ PRE in accordance with the third mode setting signal NOR of the high level.

The data sorting circuit 52 generates the fourth output data DOUT <4> from the first bit LD4<1> of the fourth latch data in synchronization with the fourth internal clock QBCLK. The fourth output data DOUT <4> is generated from the fourth bit ID <4> of the internal data.

At time T37, the mode setting circuit 10 generates the first to fourth rising output control signals ROUT <1:4> of high level from the rising clock RCLK according to the third mode setting signal NOR of high level.

The pipe circuit 51 outputs fifth to eighth bits ID <5:8> of the latched internal data as a second bit LD1<2> of the first latch data, a second bit LD2<2> of the second latch data, a second bit LD3<2> of the third latch data, and a second bit LD4<2> of the fourth latch data according to the first to fourth rising output control signals ROUT <1:4> of a high level.

The internal clock generation circuit 30 generates the second pulse of the first internal clock ICLK from the first divided clock ICLK _ PRE according to the third mode setting signal NOR of the high level.

The data sorting circuit 52 generates the fifth output data DOUT <5> from the second bit LD1<2> of the first latch data in synchronization with the first internal clock ICLK. Fifth output data DOUT <5> is generated from a fifth bit ID <5> of the internal data.

At time T38, the internal clock generation circuit 30 generates the second pulse of the second internal clock QCLK from the second frequency-divided clock QCLK _ PRE according to the third mode setting signal NOR of the high level.

The data sorting circuit 52 generates the sixth output data DOUT <6> from the second bit LD2<2> of the second latch data in synchronization with the second internal clock QCLK. Sixth output data DOUT <6> is generated from sixth bit ID <6> of the internal data.

At time T39, the internal clock generation circuit 30 generates a second pulse of the third internal clock IBCLK from the third divided clock IBCLK _ PRE according to the third mode setting signal NOR of the high level.

The data sorting circuit 52 generates the seventh output data DOUT <7> from the second bit LD3<2> of the third latched data in synchronization with the third internal clock IBCLK. The seventh output data DOUT <7> is generated from the seventh bit ID <7> of the internal data.

At time T40, the internal clock generation circuit 30 generates the second pulse of the fourth internal clock QBCLK from the fourth frequency division clock QBCLK _ PRE in accordance with the third mode setting signal NOR of the high level.

The data sorting circuit 52 generates eighth output data DOUT <8> from the second bit LD4<2> of the fourth latch data in synchronization with the fourth internal clock QBCLK. The eighth output data DOUT <8> is generated from the eighth bit ID <8> of the internal data.

The semiconductor device according to this embodiment can selectively generate a plurality of internal clocks for determining an input/output order of data from a plurality of divided clocks and a ground voltage according to an operation mode and determine an input/output order of data synchronized with the selectively generated internal clocks, thereby outputting data at high speed. Further, the semiconductor device according to the embodiment can determine the input/output order of data synchronized with the plurality of internal clocks selectively generated according to the operation mode, and does not require a separate circuit for changing the input/output order of data, which makes it possible to reduce the area.

The semiconductor devices described with reference to fig. 1 to 16 can be applied to electronic systems including a memory system, a graphic system, a computing system, a mobile system, and the like. For example, referring to fig. 17, an electronic system 1000 according to an embodiment may include a data storage unit 1001, a memory controller 1002, a buffer memory 1003, and an input/output interface 1004.

In accordance with a control signal from the memory controller 1002, the data storage unit 1001 stores data applied from the memory controller 1002, reads the stored data, and outputs the read data to the memory controller 1002. The data storage unit 1001 may include the semiconductor device 1 shown in fig. 1. The data storage unit 1001 may include a nonvolatile memory capable of continuously maintaining data stored therein even when power is removed. The nonvolatile memory may be implemented as a flash memory (NOR flash memory or NAND flash memory), a PRAM (phase change random access memory), a RRAM (resistive random access memory), an STTRAM (spin transfer torque random access memory), or an MRAM (magnetic random access memory).

The memory controller 1002 decodes a command applied from an external device (host device) through the input/output interface 1004, and recognizes input/output of data of the data storage unit 1001 from the decoding result. Fig. 17 shows the memory controller 1002 as one module. However, the memory controller 1002 may include a controller for controlling the nonvolatile memory and a controller for controlling the volatile memory serving as the buffer memory 1003, which are independently constructed.

The buffer memory 1003 may temporarily store data to be processed by the memory controller 1002, i.e., data input/output to/from the data storage unit 1001. The buffer memory 1003 may store data applied from the memory controller 1002 according to a control signal. The buffer memory 1003 reads data stored therein and outputs the read data to the memory controller 1002. The buffer memory 1003 may include volatile memories such as a DRAM (dynamic random access memory), a mobile DRAM, and an SRAM (static random access memory).

The input/output interface 1004 may provide a physical connection between the memory controller 1002 and an external device (host device) so that the memory controller 1002 can receive a control signal for data input/output from the external device and exchange data with the external device. The input/output interface 1004 may include one of various interface protocols such as USB, MMC, PCI-E, SAS, SATA, PATA, SCSI, ESDI, and IDE.

Electronic system 1000 may function as a secondary memory device or an external storage device for a host device. The electronic system 1000 may include SSD (solid state disk), USB (universal serial bus) memory, SD (secure digital) card, mSD (small secure digital) card, micro SD card, SDHC (secure digital high capacity) card, memory stick card, SM (smart media) card, MMC (multimedia card), eMMC (embedded MMC), CF (compact flash) card, and the like.

Although the preferred embodiments of the present disclosure have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and/or substitutions are possible, without departing from the scope and spirit of the disclosure as disclosed in the accompanying claims. Therefore, the true technical scope of the present disclosure should be defined by the appended claims.