阅读说明：本技术 一种三维存储器件及其制造方法 (Three-dimensional memory device and manufacturing method thereof ) 是由 张坤 吴林春 于 2021-01-14 设计创作，主要内容包括：本公开提供一种三维存储器件及其制造方法,其中,所述三维存储器件包括：衬底；多个支撑结构,所述支撑结构贯穿部分所述衬底并沿横向方向延伸；堆叠体,设于所述衬底和所述多个支撑结构上,且包括层叠交替的导电层和电介质层；多个第一沟道结构,所述第一沟道结构垂直贯穿所述堆叠体和所述支撑结构并延伸至所述衬底内；多个栅极线狭缝,垂直贯穿所述堆叠体至所述衬底以将所述堆叠体沿纵向方向划分为多个区块；其中,所述支撑结构与所述堆叠体中的顶部选择栅切槽结构位置对应。本方案通过在沟道结构下方增加支撑结构,使得在芯片支撑过程中,支撑结构能够协助衬底对存储阵列起到良好的支撑,从而避免薄膜结构对晶圆过渡压迫,导致晶圆发生变形。(The present disclosure provides a three-dimensional memory device and a method of manufacturing the same, wherein the three-dimensional memory device includes: a substrate; a plurality of support structures extending through a portion of the substrate and in a lateral direction; a stack disposed on the substrate and the plurality of support structures and comprising a stack of alternating conductive and dielectric layers; a plurality of first channel structures extending vertically through the stack and the support structures and into the substrate; a plurality of gate line slits vertically penetrating the stacked body to the substrate to divide the stacked body into a plurality of blocks in a longitudinal direction; wherein the support structure corresponds in position to a top select gate kerf structure in the stack. According to the scheme, the supporting structure is additionally arranged below the channel structure, so that in the chip supporting process, the supporting structure can assist the substrate to well support the storage array, and the thin film structure is prevented from transitively pressing the wafer to cause the wafer to deform.)

1. A three-dimensional memory device, comprising:

a substrate;

a plurality of support structures extending through a portion of the substrate and in a lateral direction;

a stack disposed on the substrate and the plurality of support structures and comprising a stack of alternating conductive and dielectric layers;

a plurality of first channel structures extending vertically through the stack and the support structures and into the substrate;

a plurality of gate line slits vertically penetrating the stacked body to the substrate to divide the stacked body into a plurality of blocks in a longitudinal direction;

wherein the support structure corresponds in position to a top select gate kerf structure in the stack.

2. The three-dimensional memory device of claim 1, wherein the plurality of channel structures between two adjacent gate line slits are arranged in an array.

3. The three-dimensional memory device of claim 1 or 2, wherein the top select gate trench structure is located within the stack above the first channel structure and extends along a vertical direction and the lateral direction.

4. The three-dimensional memory device of claim 1, wherein the support structure is a continuous structure or comprises a plurality of discontinuous structural segments.

5. The three-dimensional memory device of claim 1, wherein the support structures are filled with an oxide material.

6. The three-dimensional memory device of claim 1, wherein the substrate comprises: a first semiconductor layer and a second semiconductor layer;

the support structure penetrates through the second semiconductor layer.

7. The three-dimensional memory device of claim 1 or 6, comprising a plurality of second channel structures; the plurality of second channel structures vertically extend through the stack and into the substrate.

8. The three-dimensional memory device of claim 1, further comprising: a driving circuit on the substrate on a side opposite to a memory array in the three-dimensional memory device; alternatively, the first and second electrodes may be,

and the driving circuit is positioned at the same side of the storage array in the three-dimensional storage device.

9. The three-dimensional memory device of claim 8, wherein the three-dimensional memory device is structured to: the driving circuit is positioned below the storage array;

the three-dimensional memory device further includes: a pick-up region of the three-dimensional memory device and a memory array output pad;

the storage array output pad and the pick-up area of the three-dimensional storage device are positioned on one side of a storage array in the three-dimensional storage device; or the like, or, alternatively,

the storage array output pad is positioned on one side of a storage array in the three-dimensional storage device, and the pick-up area of the three-dimensional storage device is positioned on one side of a driving circuit in the three-dimensional storage device.

10. The three-dimensional memory device of claim 8, wherein the three-dimensional memory device is structured to: the driving circuit is positioned above the storage array;

the three-dimensional memory device further includes: a pick-up region of the three-dimensional memory device and a drive circuit output pad;

the drive circuit output pad and the pick-up area of the three-dimensional storage device are both positioned on one side of the drive circuit in the three-dimensional storage device; or the like, or, alternatively,

the driving circuit output pad is positioned on one side of the driving circuit in the three-dimensional storage device, and the pickup area of the three-dimensional storage device is positioned in the substrate on one side of the storage array in the three-dimensional storage device.

11. A method of fabricating a three-dimensional memory device, the method comprising the steps of:

providing a substrate;

forming a plurality of support structures in a substrate, the support structures extending through a portion of the substrate and extending in a lateral direction;

forming a stack comprising stacked alternating conductive and dielectric layers on the substrate and support structure;

a plurality of first channel structures extending vertically through the stack and the support structure and into the substrate;

vertically penetrating the stacked body to the substrate to form a plurality of gate line slits dividing the stacked body into a plurality of blocks along a longitudinal direction;

wherein the support structure corresponds in position to a top select gate kerf structure in the stack.

12. The manufacturing method according to claim 11, wherein the forming of the substrate comprises:

providing a substrate;

forming a first semiconductor layer on the substrate;

a second semiconductor layer is formed on the first semiconductor layer.

13. The method of manufacturing of claim 12, wherein the plurality of trenches for forming support structures are formed in a second semiconductor layer of the substrate.

14. The method of manufacturing of claim 13, wherein filling the trench with a dielectric layer material forms a support structure.

Technical Field

The present invention relates to the field of semiconductor technology, and more particularly, to a three-dimensional (3D) memory device and a method of manufacturing the same.

Background

With the development of memory technology, the volume of a memory device is gradually reduced, the data processing amount is increased, and the planar memory technology is difficult to meet the performance requirement of the memory device, so that the three-dimensional memory technology is gradually concerned by people, the three-dimensional memory technology can break through the limitation of the planar memory technology, more memory cells can be integrated in the vertical direction under the condition of the same area, and the performance of the memory device is greatly improved.

Currently, in a conventional three-dimensional memory device manufacturing process, a silicon substrate is used as a carrier for manufacturing a three-dimensional memory device. As the number of stacked layers increases, more dielectric films (e.g., TEOS, SIN, POLY) are needed. For example, the step Area (SS Area), the Channel Hole (CH), and the gate Area (GL Area) in the 3D NAND need to be filled with more media, so that the film structure becomes more complicated, and after the heat treatment in the process, the film is deformed, and the silicon substrate is difficult to support the pressure generated by the film, resulting in the deformation of the wafer. Each machine has a limit to the bending of the wafer, and the wafer is deformed too much, which eventually causes the problem that the wafer is subjected to arc discharge or the process cannot be performed in the machine.

Disclosure of Invention

The present scheme is intended to provide a three-dimensional (3D) memory device and a method of fabricating the same.

In order to achieve the purpose, the technical scheme is as follows:

in a first aspect, the present scheme provides a three-dimensional memory device comprising,

a substrate;

a plurality of support structures extending through a portion of the substrate and in a lateral direction;

a stack disposed on the substrate and the plurality of support structures and comprising a stack of alternating conductive and dielectric layers;

a plurality of channel structures extending vertically through the stack and the support structures and into the substrate;

a plurality of gate line slits vertically penetrating the stacked body to the substrate to divide the stacked body into a plurality of blocks in a longitudinal direction;

wherein the support structure corresponds in position to a top select gate kerf structure in the stack.

In a second aspect, the present disclosure provides a method for manufacturing a three-dimensional memory device, including:

providing a substrate;

forming a plurality of support structures in a substrate, the support structures extending through a portion of the substrate and extending in a lateral direction;

forming a stack comprising stacked alternating conductive and dielectric layers on the substrate and support structure;

a plurality of first channel structures extending vertically through the stack and the support structure and into the substrate;

vertically penetrating the stacked body to the substrate to form a plurality of gate line slits dividing the stacked body into a plurality of blocks along a longitudinal direction;

wherein the support structure corresponds in position to a top select gate kerf structure in the stack.

Advantageous effects

According to the scheme, the supporting structure is additionally arranged on the lower side of the channel structure positioned in the middle between the slits of the adjacent gate lines, so that the supporting structure can assist the substrate to well support the storage array of the three-dimensional storage device in the chip supporting process, and the problem that the wafer is deformed due to transition compression of the thin film structure on the wafer is avoided;

according to the scheme, a complex process is not required to be additionally added, only the zero layer alignment mark etching (zero etch) is required, and a continuous or discontinuous supporting structure is formed on the polycrystalline silicon layer of the substrate at the same time, so that the process is simple in step, easy to implement and free of extra cost increase.

Drawings

FIG. 1 is a schematic diagram illustrating a wafer deformation state during a manufacturing process of a three-dimensional memory device in the prior art;

FIG. 2 illustrates a schematic diagram of stack and channel structure deformation during fabrication of a three-dimensional memory device in the prior art;

FIG. 3 illustrates a cross-sectional view of a three-dimensional memory device structure in the prior art;

fig. 4 shows a cross-sectional view of a three-dimensional memory device formed based on the present scheme;

fig. 5 shows a schematic view of an example of a support structure according to the present solution;

fig. 6 shows a schematic view of another example of a support structure according to the present solution;

fig. 7 shows a flow chart of a method of manufacturing a three-dimensional memory device according to the present scheme;

FIG. 8 is a schematic diagram showing a substrate and support structure formation process in the fabrication process of the three-dimensional memory device according to the present embodiment;

fig. 9 is a schematic view showing a stack forming process in the manufacturing process of the three-dimensional memory device according to the present embodiment;

FIG. 10 is a schematic diagram showing a channel structure formation process in the fabrication process of the three-dimensional memory device according to the present embodiment;

FIG. 11 is a schematic diagram showing a gate line slit forming process in the manufacturing process of the three-dimensional memory device according to the present embodiment;

FIG. 12 is a schematic diagram showing an example of a channel structure forming process in the manufacturing process of the three-dimensional memory device according to the present embodiment;

FIG. 13 is a schematic diagram showing a gate line slit filling process in the manufacturing process of the three-dimensional memory device according to the present embodiment;

fig. 14 is a schematic diagram showing the formation of a driving circuit in the manufacturing process of the three-dimensional memory device according to the present embodiment;

FIG. 15 is a schematic diagram showing the locations of the output pads of the memory array in the three-dimensional memory device according to the present embodiment;

FIG. 16 is a schematic diagram showing another memory array output pad location in the three-dimensional memory device according to the present embodiment;

FIG. 17 is a schematic diagram showing another memory array output pad location in the three-dimensional memory device according to the present embodiment;

fig. 18 is a schematic diagram showing the location of an output pad of still another memory array in the three-dimensional memory device according to the present embodiment.

Description of the reference symbols

1. A substrate; 101. a substrate layer; 102. a well layer; 103. a polysilicon layer; 104. a support structure;

2. a stack; 201. a conductive layer; 202. a dielectric layer;

3. a channel structure; 301. a storage layer; 302. a semiconductor channel layer; 303. a cover layer; 304. a channel structure;

4. a gate line slit;

5. a pickup area;

6. a storage array output pad;

7. the driving circuit outputs the pad.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity, position relationship and proportion of the components in actual implementation can be changed freely on the premise of implementing the technical solution of the present invention, and the layout form of the components may be more complicated. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments should not be construed as limited to the particular shapes of regions illustrated in the drawings, but may also include deviations in shapes that result, for example, from manufacturing processes. In the drawings, the length and size of some layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like parts. It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present.

Through research and analysis, as shown in fig. 1, in general, a silicon substrate is used as a carrier for fabricating a three-dimensional memory device during the fabrication process of the three-dimensional memory device. As the number of stacked layers increases, more dielectric films (e.g., TEOS, SIN, POLY) are needed. For example, the step Area (SS Area), the Channel Hole (CH), and the gate Area (GL Area) in the 3D NAND need to be filled with more media, so that the film structure becomes more complicated, and after the heat treatment in the process, the film is deformed, and the silicon substrate layer hardly supports the pressure generated by the film, so that the wafer is deformed. Each machine has a limit to the bending of the wafer, and the wafer is deformed too much, which eventually causes the problem that the wafer is subjected to arc discharge or the process cannot be performed in the machine.

As shown in fig. 2, since the gate line cuts the entire memory array region and the step region into a plurality of small structures, the structure becomes more and more unstable as the number of layers of the dielectric thin film increases, and meanwhile, due to process limitations, the polysilicon at the bottom of the trench hole needs to be removed, and after the polysilicon is removed at the bottom of the trench hole by means of aligned etching, the instability of the structure is aggravated.

Based on the above problems, the prior art generally adopts a process of adjusting the pressure of the film or depositing the film on the back surface to solve the pressing of the wafer, but these methods have poor effects, and the problem of excessive bending of the wafer still occurs. In addition, some prior arts adopt a method of increasing storage capacity per unit area, such as increasing storage capacity of each storage unit, increasing the number of layers, or making the storage unit smaller, but as long as the number of films on the wafer is increased, the wafer still suffers from unstable structure and excessive stress, which causes excessive bending.

Therefore, the scheme aims to provide the three-dimensional memory device and the manufacturing method thereof, and the supporting structure is added on the lower side of the first channel structure positioned in the middle between the slits 4 of the adjacent gate lines, so that in the chip supporting process, the supporting structure can assist the substrate to well support the memory array of the three-dimensional memory device, and the problem that the wafer is deformed due to the excessive compression of the thin film structure on the wafer is avoided; meanwhile, the storage performance of the device is not affected, and even the number of layers of the film can be increased on the basis of the process of the scheme, so that the storage performance is further improved.

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail with reference to fig. 3 to 18.

The three-dimensional memory device of the present scheme may include a memory region and a gate line slit. The storage area is divided into a plurality of blocks by the gate line slits and is positioned on the wafer. Fig. 4 is a schematic diagram of an exemplary three-dimensional memory device according to the present invention. The three-dimensional memory device may include: a substrate 1; forming a support structure 104 within the substrate 1; a stacked body 2 composed of conductive layers 201 and dielectric layers 202 arranged alternately is formed on a substrate 1; a plurality of channel structures 3 pass through the stack 2 and extend into the substrate 1, the support structure 104 corresponding to the position of the top select gate kerf structure in the stack. The three-dimensional memory device comprises a plurality of channel structures 3, wherein a first channel structure in the plurality of channel structures 3 simultaneously penetrates through a stacked body 2 and a support structure 104 and extends into a substrate 1; a second channel structure of the plurality of channel structures 3 extends only through the stack 2 into the substrate 1. A plurality of gate line slits 4 vertically penetrate the stack 2 and are connected to the front surface of the substrate 1.

For a clearer comparison, the difference between the present solution and the prior art is further illustrated in fig. 3, which is a schematic diagram of a three-dimensional memory device without adding a support structure. The structural and technological differences between fig. 3 and fig. 4 can be clearly seen by comparison.

In this embodiment, the plurality of gate line slits 4 are arranged in parallel and divide the plurality of channel structures 3 into different storage regions. The plurality of channel structures 3 between two adjacent gate line slits 4 are arranged in an array. The top select gate trench structure is located within the stack above the first channel structure and extends in a vertical direction and the lateral direction.

In one embodiment, as shown in fig. 4, a storage Area (chip Area) and a step Area (SS Area) are divided between two adjacent gate line slits 4. In the storage region, nine rows of channel structures 3 are arranged in parallel in the Y direction, and a plurality of channel structures 3 are arranged at equal intervals in each row. The direction perpendicular to the gate line slit 4 is the X direction, and the direction parallel to the gate line slit 4 is the Y direction.

The above is merely an example, the number and the manner of the channel structures 3 disposed between the gate line slits 4 may be adjusted appropriately according to the structural change of the storage region, and those skilled in the art may implement the arrangement of other numbers of channel structures 3 according to the above example.

The substrate 1 in the three-dimensional memory device may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. The substrate 1 may be a semiconductor layer thinned by grinding, etching, Chemical Mechanical Polishing (CMP), or any combination thereof. In this aspect, the substrate may include: a first semiconductor layer and a second semiconductor layer. In one embodiment, as shown in fig. 8, the substrate 1 comprises, in order from bottom to top: a substrate layer 101, a well layer 102 (first semiconductor layer), and a polysilicon layer 103 (second semiconductor layer). It is noted here that after the fabrication of the three-dimensional memory device is completed, the substrate layer 101 may be removed from the formed three-dimensional memory device.

In this embodiment, the support structure 104 penetrates the polysilicon layer 103 in the substrate 1, and the support structure 104 is formed by filling an oxide material therein, so as to assist the substrate 1 in supporting the storage region. The oxide material may include, but is not limited to, silicon oxide, etc., and in addition, the oxide material may be replaced by silicon nitride, silicon oxynitride, or other materials of the same nature. The support structure 104 is disposed in the polysilicon layer 103 under the first trench structure, so that the support structure 104 can support the storage region above the support structure after being filled again. As shown in fig. 5, the support structure 104 may be a continuous structure. As shown in fig. 6, the support structure 104 may also include a plurality of discontinuous structural segments; the intermittent second channels 104 are spaced apart by a distance D₁Dn may be the same or may have any value.

In one embodiment, the support structure 104 may be disposed in the substrate 1 under the first channel structure arranged in the Y direction at an intermediate position between two adjacent gate line slits 4. The middle position is the position of the symmetry axis of the two adjacent gate line slits 4. As shown in fig. 4, the support structure 104 is disposed in the substrate 1 under the first channel structure of the middle row between two adjacent gate line slits 4. Furthermore, if the number of rows of channel structures 3 between the gate line slits 4 is even, the area at the middle position may be expanded to a width between the central axes of the nearest two rows of channel structures 3 on both sides of the symmetry axis of the two adjacent gate line slits 4.

In one embodiment, as shown in fig. 6, it is necessary to ensure for the width C of the support structure (the distance in the X direction is the width): (SAC POLY OX Loss +20nm) < C < A-B; wherein SAC POLY OX Loss is the thickness of the polysilicon oxide layer removed in the self-aligned contact process, i.e. the thickness of the polysilicon layer 103; a is the distance between the centers of the channel holes which are symmetrically arranged at the two sides of the middle position and are used for forming the channel structure 3; b is a diameter of a channel hole for forming a channel structure.

The stack 2 in the three-dimensional memory device is located on the front side of a substrate 1, which comprises alternating electrically conductive layers 201 and dielectric layers 202 (i.e. pairs of conductor/dielectric layers 202). As shown in fig. 9, the number of conductor/dielectric layers (e.g., 32, 64, 96, or 128) in the stack 2 determines the number of memory cells of the three-dimensional memory device. The stack 2 may comprise a stepped structure (not shown in the figures) at least on one side in the lateral direction. The conductive layers 201 and the dielectric layers 202 in the stack 2 may alternate in the vertical direction. The conductive layer 201 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. The dielectric layer 202 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the conductive layer 201 in stack 2 may serve as a gate electrode/gate conductor/gate line for a memory cell in a memory string in a three-dimensional memory. The conductive layer 201 may comprise a plurality of control gates for a plurality of memory cells and may extend laterally as a word line ending at an edge of the stack 2.

As shown in fig. 10, the channel structure 3 may be formed in a cylindrical channel hole vertically passing through the stack 2, the channel hole being filled with a semiconductor material and a dielectric material, thereby forming a memory string; wherein the semiconductor material may serve as the semiconductor channel layer 302 and the dielectric material may serve as the storage layer 301.

In this scheme, channel structure 3 includes: a first channel structure and a second channel structure. Wherein the first channel structure includes: a channel hole penetrating the stack 2 and the support structure 104 and extending into the substrate 1, and a memory layer 301 and a semiconductor channel layer 302 filling in the channel hole. The portion of the first channel structure corresponding to the polysilicon layer 103 in the substrate 1 is directly contacted with the support structure 104, so as to form a dummy channel structure, which is mainly matched with the support structure 104 to assist the substrate in supporting the memory array of the three-dimensional memory device. The second channel structure includes: a channel hole penetrating the stack 2 and the support structure 104 and extending into the substrate 1, and a memory layer 301 and a semiconductor channel layer 302 filling in the channel hole. The second channel structure is located in a portion of the substrate 1 corresponding to the polysilicon layer 103 and is in direct contact with the polysilicon in the polysilicon layer 103, thereby forming an electrically operative channel structure that can be used as a memory.

In one embodiment, the semiconductor channel layer 302 includes silicon, such as amorphous, polycrystalline, or monocrystalline silicon. In one embodiment, the storage layer 301 may be a composite layer comprising: a tunneling layer, a storage layer (also referred to as a "charge trapping layer"), and a blocking layer. The remaining space of the channel hole of the channel structure 3 may be partially or completely filled with a capping layer 303, the capping layer 303 comprising a dielectric material such as silicon oxide. In one embodiment, the capping layer 303, the semiconductor channel layer 302, the tunneling layer, the storage layer, and the blocking layer are radially disposed in this order from the center of the trench hole toward the outer surface thereof. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In another example, the memory layer 301 may further include a composite layer of silicon oxide/silicon oxynitride (or silicon nitride)/silicon oxide (ONO).

As shown in fig. 11 and 12, a channel structure 304 is formed in a direction perpendicular to the second channel structure on a portion of the memory layer 301 in the channel structure 3 where the second channel structure extends into the substrate 1. In one embodiment, the three-dimensional memory device may employ a P-Well (P-Well) erase architecture, wherein a voltage is applied to polysilicon on the substrate 1, and electrons on the polysilicon flow through the channel structure 304 to the memory layer 301 in the channel structure to perform a read operation. A voltage is applied to the P-well of the substrate 1, and an erasing operation is performed on the memory layer 301 with the channel structure 304 as a channel for performing erasing.

As shown in fig. 13, on the side walls of the gate line slits 4, a uniform concavo-convex structure is formed by an etching process, i.e., the edge of each conductive layer 201 in the stacked body 2 is slightly shorter laterally than the edge of the dielectric layer 202 at the edges of the gate line slits 4. The deposition of tungsten material on the relief structure is continued and the gate line slit 4 is filled with a conductive first oxide material.

As shown in fig. 14, in this embodiment, after the above-described process is completed, a driving circuit may be formed on the other side of the substrate 1. In one embodiment, the driving circuit may be a complementary metal oxide semiconductor CMOS.

In this aspect, the three-dimensional memory device may further include: a memory array output pad 6 and a pick up region 5(pick up region) of the three dimensional memory device. The memory array output pad 6 may also be located on the side of the memory array in the three-dimensional memory device, and the pickup area 5 of the three-dimensional memory device is located on the side of the driving circuit in the three-dimensional memory device. In one embodiment, as shown in fig. 15, the memory array output pads 6 may be led out from the step area; and the pickup region 5 of the three-dimensional memory device may be formed on the rear surface of the substrate 1 before the driving circuit is formed. Further, the memory array output pad 6 and the pickup area 5 of the three-dimensional memory device are located on the memory array side in the three-dimensional memory device. In one embodiment, as shown in FIG. 16, the three-dimensional memory device has the structure: the storage area is on the top, and the drive circuit is on the bottom; the storage array output pad 6 can be led out from the step area through the packaging layer; the pickup area 5 of the three-dimensional memory device may be disposed above the memory array (not shown in the drawings), and it should be noted that, as in fig. 16, the "above of the memory array" refers to the top of the memory array on the side of the driving circuit.

In this aspect, the three-dimensional memory device may further include: a drive circuit output pad 7 and a pick-up region 5 of the three-dimensional memory device. Wherein the driving circuit output pad 7 is located at a side of the driving circuit in the three-dimensional memory device, and the pickup region 5 of the three-dimensional memory device is located in the substrate 1 at a side of the three-dimensional memory device opposite to the memory array. In one embodiment, as shown in FIG. 15, the three-dimensional memory device has the structure: the drive circuit is on top and the memory array is on the bottom. The drive circuit output pads 7 may be led out from one side of the drive circuit, the pick-up region 5 of the three-dimensional memory device being located in the substrate 1 on the opposite side of the three-dimensional memory device to the memory array. Further, the driving circuit output pad 7 and the pickup region 5 of the three-dimensional memory device may be both located on the driving circuit side in the three-dimensional memory device. As shown in fig. 18, in one embodiment, the drive circuit output pad 7 is led out from one side of the drive circuit; the pickup area 5 of the three-dimensional memory device is located above the memory array, and it should be noted that, as shown in fig. 18, the "above the memory array" refers to the top of the memory array located on the side of the driving circuit.

In this scheme, the pickup region 5 of the three-dimensional memory device can be transferred to the back surface of the substrate 1, so that the storage area of the three-dimensional memory device is not occupied. Specifically, a contact hole is formed in the back surface of the substrate 1, a layer of second oxide material is deposited in the contact hole, the second oxide material at the bottom of the contact hole is removed, a notch is etched, a conductive material is inserted into the notch, and the bottom of the conductive material is in contact with the silicon well layer 102 of the substrate 1, thereby completing the manufacture of the pickup region 5. In one embodiment, the contact hole may correspond to a location of the three-dimensional memory device. In another embodiment, the contact holes may correspond to regions where the plurality of channel structures 3 are located. The pickup region 5 is filled with a conductive material, the periphery of which is filled with an oxide material. In one embodiment, the conductive material is tungsten (W), which corresponds to the material of the gate structure 501 in the three-dimensional memory device 5. In this aspect, the second oxide material may be an insulating material. Preferably, the second oxide material is selected from silicon dioxide.

The three-dimensional memory device may be designed as part of a monolithic three-dimensional memory device. By "monolithic" it is meant that the components of the three-dimensional memory device (e.g., peripheral devices and memory array devices) are formed on a single substrate 1. For monolithic three-dimensional memory devices, additional limitations are encountered in fabrication due to the convolution of peripheral device processing and memory array device processing. For example, the fabrication of a memory array device (e.g., a NAND memory string) is constrained by the thermal budget associated with peripheral devices that have been or will be formed on the same substrate 1. Thus, the three-dimensional memory device may be designed as part of a non-monolithic three-dimensional memory device, wherein components (e.g., peripheral devices and memory array devices) may be separately formed on different substrates 1 and then bonded, e.g., in a face-to-face manner. In some embodiments, the memory array device substrate 1 remains the substrate 1 of a bonded non-monolithic three-dimensional memory device, and peripheral devices (e.g., any suitable digital, analog, and/or mixed signal peripheral circuitry, such as page buffers, decoders, and latches, not shown, that may be used to facilitate operation of the three-dimensional memory device) are flipped and face down toward the memory array device (e.g., NAND memory string) for hybrid bonding. It should be understood that in some embodiments, the memory array device substrate 1 is flipped and faced down towards the peripheral devices for hybrid bonding such that in a bonded non-monolithic three-dimensional memory device, the memory array device is above the peripheral devices. The memory array device substrate 1 may be a thinned substrate 1 (which is not a substrate for a bonded non-monolithic three-dimensional memory device), and back-end-of-line (BEOL) interconnects for the non-monolithic three-dimensional memory device may be formed on a backside of the thinned memory array device substrate 1.

Accordingly, the present solution also provides an exemplary fabrication process for fabricating a three-dimensional memory device of some embodiments. It should be understood that the operations described below are not exhaustive and that other operations can be performed before, after, or between any of the illustrated operations. Further, some operations may be performed concurrently, or in a different order.

As shown in fig. 7, the manufacturing method includes:

s1, providing a substrate;

s2, forming a plurality of support structures penetrating through the substrate and extending along the transverse direction in the substrate;

s3, forming a stacked body comprising stacked alternating conductive layers and dielectric layers on the substrate and the supporting structure;

s4, a plurality of first channel structures extending vertically through the stack and the support structure and into the substrate;

s5, vertically penetrating the stacked body to the substrate to form a plurality of gate line slits dividing the stacked body into a plurality of blocks along the longitudinal direction;

wherein the support structure corresponds in position to a top select gate kerf structure in the stack.

As shown in fig. 8, in step S1, the wafer is processed by grinding, etching, Chemical Mechanical Polishing (CMP), and the like to form a semiconductor layer. The semiconductor layer is used as a substrate 1 of a three-dimensional memory device. In one embodiment, the first layer of the substrate 1 is P-doped with a silicon substrate layer 101 to form a P-type silicon substrate layer 101. Further, epitaxial growth is performed on the P-type silicon substrate layer 101, and the grown well layer 102 is N-doped by means of ion implantation, thereby forming an N-type silicon well layer 102. A polysilicon layer 103 is deposited on the N-type silicon well layer 102.

As shown in fig. 8, in step S2, a plurality of trenches for the support structures 104 are formed at a time at a predetermined interval within the polysilicon layer 103 of the substrate 1 based on the zero-layer alignment mark etching process, and then the support structures 104 are formed by filling an oxide material within the trenches. In an embodiment, the support structure 104 may also be filled during the deposition of the dielectric layer 202 in the stack 2.

As shown in fig. 9, in step S3, a stacked body 2 composed of conductive layers 201 and dielectric layers 202 stacked and staggered may be formed on a substrate 1, that is, one conductive layer 201 and one dielectric layer 202 constitute one pair of conductor/dielectric layers, and a plurality of pairs of conductor/dielectric layers 202 are formed on the substrate 1. In some embodiments, each dielectric layer 202 comprises a silicon oxide layer and each conductive layer 201 comprises a silicon nitride layer. Stack 2 may be formed by one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof.

As shown in fig. 10, in step S4, a plurality of channel structures 3 are formed through the stacked body 2 and extending into the substrate 1. In one embodiment, an etch mask may be patterned on the stack 2 by photolithography, development, and etching processes. The etch mask may be a photoresist mask or a hard mask patterned based on a photolithographic mask. The lithography mask and/or the etch mask has a pattern of channel holes thereon. The etch mask includes an array of openings for forming the channel holes. The patterned etch mask may be used to etch through the stack 2 along the array of openings by one or more wet and/or dry etch processes, such as DRIE, forming channel holes in a pattern defined by the lithographic mask and/or the etch mask.

In some embodiments, the etching process through the stack 2 may not stop at the surface of the substrate 1 and may continue to etch into the silicon well layer 102 in the substrate 1, thereby extending the channel hole vertically into the silicon well layer 102 in the substrate 1.

Further, a row of channel holes located at the right middle position between the two gate line slits 4, while passing through the stack 2 and the support structure 104, extends into the silicon well layer 102 in the substrate 1, according to the pre-designed position. The channel holes in the other rows extend directly into the silicon well layer 102 in the substrate 1 only after passing through the stack 2.

As shown in fig. 10, a memory layer 301, a semiconductor channel layer 302, and a cap layer 303 are sequentially formed in the channel hole, and a channel structure 3 is formed. In this scheme, channel structure 3 includes: a first channel structure and a second channel structure. Wherein the first channel structure includes: a channel hole penetrating the stack 2 and the support structure 104 and extending into the substrate 1, and a memory layer 301 and a semiconductor channel layer 302 filling in the channel hole. The portion of the first channel structure corresponding to the polysilicon layer 103 within the substrate 1 is in direct contact with the support structure 104, thereby forming a dummy channel structure. The second channel structure includes: a channel hole penetrating the stack 2 and the support structure 104 and extending into the substrate 1, and a memory layer 301 and a semiconductor channel layer 302 filling in the channel hole. The second channel structure is located in the substrate 1 corresponding to the polysilicon layer 103 and directly contacts the polysilicon in the polysilicon layer 103, so as to form an electrically functioning channel structure for storage.

In one embodiment, the memory layer 301 is first deposited along the sidewalls and bottom surface of the channel hole, then the semiconductor channel layer 302 is deposited on the memory thin layer, and then the capping layer 303 is deposited on the semiconductor channel layer 302. Subsequently, the semiconductor channel layer 302 is deposited on the inner side of the memory layer 301 to fill the space above the cap layer 303, and finally, a channel plug is formed on the semiconductor channel layer 302 and the memory layer 301 to block the channel hole. Among them, the barrier layer, the storage layer, and the tunneling layer in the storage layer 301 may be sequentially deposited in this order using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. The semiconductor channel layer 302 may be deposited on the storage layer 301 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. Capping layer 303 may be deposited on semiconductor channel layer 302 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

As shown in fig. 11, in step S5, a plurality of gate line slits 4 are formed vertically through the stacked body 2, connected to the front surface of the substrate 1. In one embodiment, an etch mask may be patterned on the stack 2 by photolithography, development, and etching processes. The gate line slits 4 in the pattern defined by the photolithographic mask and/or the etch mask may be formed by etching through the stack 2 using a patterned etch mask by one or more wet etch and/or dry etch processes, such as DRIE. Further, a dielectric material layer is deposited on the side and bottom surfaces of the gate line strap 4 by using a self-aligned contact process and a Spacer process, thereby reducing a channel effect formed by lateral diffusion. Subsequently, the dielectric material layer at the bottom of the gate line slit 4 is removed by an etching process. In one embodiment, the dielectric material is silicon oxide.

The channel structure 304 is formed on the second one of the channel structures 3 at the portion located in the substrate 1. In an embodiment, as shown in fig. 12, firstly, the polysilicon in the polysilicon layer 103 in the substrate 1 is removed by using a self-aligned contact process, and since the support structure 104 is provided in advance, the substrate 1 can be assisted to support the memory array above the support structure 104, thereby preventing the problem of overvoltage deformation to the wafer. Then, the dielectric material in the gate line slit 4 is removed; finally, the memory layer 301 in the channel structure 3, which is located in the polysilicon layer 103 in the substrate 1, is removed by an etching process, so that a channel structure 304 is formed on the channel structure. It should be noted here that: since the channel structure 3 with the support structure 104 underneath serves as an auxiliary support, the support structure is not subjected to an etching process, while the memory layer 301 of the channel structure 3 within the support structure 104 remains. The removal of the memory layer 301 is performed only for the channel structure 3 without the support structure 104 underneath, so that the channel structure 304 is formed on the channel structure.

In the scheme, through the channel structure 304, when a voltage is applied to polysilicon on the substrate 1 under the condition that a P-Well (P-Well) erasing architecture is adopted in the three-dimensional memory device, electrons on the polysilicon flow to the memory layer 301 in the channel structure through the channel structure 304 to perform reading operation; when a voltage is applied to the P-well of the substrate 1, the channel structure 304 serves as a channel for performing erasing, and an erasing operation is performed on the memory layer 301. In addition, in order to ensure the flatness of the contact surface between the polysilicon layer 103 and another layer, after the step of removing the polysilicon layer 103 on the substrate 1, the interface adjacent to the polysilicon layer 103 needs to be planarized.

After the step of forming the channel structure 304 on the channel structure 3 in the portion of the substrate 1, a filling operation is also required on the substrate 1 in the empty position. In one embodiment, first, polysilicon is deposited on the inner wall of the gate line slit 4 and in the polysilicon layer 103; then, the polysilicon on the inner wall and bottom of the gate line slit 4 is removed.

As shown in fig. 13, the gate line slit 4 is filled. First, oxide (silicon oxide) on the inner wall of the gate line slit 4 is removed; then, processing the edge of each conductive layer 201 in the stacked body 2 at the edge of the gate line slit 4 by using an etching process, so that the edges of the conductive layers 201 are slightly shorter than the edges of the dielectric layers 202 in the transverse direction, and forming a concave-convex structure; subsequently, the gate line slit 4 is filled with a conductive first oxide material as a pickup region. The first oxide material is an oxide of a metal such as tungsten (W), cobalt (Co), copper (Cu), or aluminum (Al).

This scheme, as shown in fig. 14, can further form a driving circuit above or below the three-dimensional memory device. In an embodiment, the driving circuit is a CMOS, which is a manufacturing process of a CMOS driving circuit in a conventional three-dimensional memory device and is not described herein again.

In this aspect, the three-dimensional memory device may further include: a memory array output pad 6 and a pick up region 5(pick up region) of the three dimensional memory device. The memory array output pad 6 may also be located on the side of the memory array in the three-dimensional memory device, and the pickup area 5 of the three-dimensional memory device is located on the side of the driving circuit in the three-dimensional memory device. In one embodiment, as shown in fig. 15, the memory array output pads 6 may be led out from the step area; and the pickup region 5 of the three-dimensional memory device may be formed on the rear surface of the substrate 1 before the driving circuit is formed. Further, the memory array output pad 6 and the pickup area 5 of the three-dimensional memory device are located on the memory array side in the three-dimensional memory device. In one embodiment, as shown in FIG. 16, the three-dimensional memory device has the structure: the storage area is on the top, and the drive circuit is on the bottom; the storage array output pad 6 can be led out from the step area through the packaging layer; the pickup area 5 of the three-dimensional memory device may be disposed above the memory array (not shown in the drawings), and it should be noted that, as in fig. 16, the "above of the memory array" refers to the top of the memory array on the side of the driving circuit.

In this aspect, the three-dimensional memory device may further include: a drive circuit output pad 7 and a pick-up region 5 of the three-dimensional memory device. Wherein the driving circuit output pad 7 is located at a side of the driving circuit in the three-dimensional memory device, and the pickup region 5 of the three-dimensional memory device is located in the substrate 1 at a side of the three-dimensional memory device opposite to the memory array. In one embodiment, as shown in FIG. 17, the three-dimensional memory device has the structure: the drive circuit is on top and the memory array is on the bottom. The drive circuit output pads 7 may be led out from one side of the drive circuit, the pick-up region 5 of the three-dimensional memory device being located in the substrate 1 on the opposite side of the three-dimensional memory device to the memory array. Further, the driving circuit output pad 7 and the pickup region 5 of the three-dimensional memory device may be both located on the driving circuit side in the three-dimensional memory device. As shown in fig. 18, in one embodiment, the drive circuit output pad 7 is led out from one side of the drive circuit; the pickup area 5 of the three-dimensional memory device is located above the memory array, and it should be noted that, as shown in fig. 18, the "above the memory array" refers to the top of the memory array located on the side of the driving circuit.

In this embodiment, a pickup region 5 may be formed on the back surface of the substrate 1. The pickup region 5 may be on the back side of the substrate 1 at a position corresponding to the three-dimensional memory device, or may be on the back side of the substrate 1 at a position corresponding to the channel structure 3. Specifically, an etching mask may be patterned on the back surface of the substrate 1 by photolithography, development, etching, and the like. Forming a contact hole having a width smaller than that of the gate line slit 4 at a position corresponding to the three-dimensional memory device on the rear surface of the substrate 1 by one or more wet etching and/or dry etching processes (such as DRIE) using the patterned etch mask; depositing an oxide material on the memory layer 301 of the contact hole by using a deposition process, and reserving an insertion hole for inserting a conductive material; removing the second oxide material at the bottom of the contact hole by using an etching process, and forming a notch in the silicon well layer 102; and depositing metal tungsten on the gaps along the jack, so that the metal tungsten is formed in the pickup region 5 and is in contact with the N-type silicon well layer 102 of the substrate 1. Wherein the second oxide material is silicon oxide, and the silicon oxide isolates the Si and tungsten material on the sidewall of the pickup region 5. Further, according to the above method, the pickup region 5 may be formed on the back surface of the substrate 1 corresponding to the region where the plurality of channel structures are located.

In this embodiment, when the pickup area 5 is disposed on the storage array side of the three-dimensional storage device, the pickup area 5 may be disposed in the gate line slit 4 or above the storage array. The manufacturing process of the pickup region 5 on one side of the memory array is a manufacturing process of forming the pickup region 5 of the three-dimensional memory device on the front surface in the conventional three-dimensional memory device, and is not described herein again.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.