阅读说明：本技术 具有假晶高电子迁移率晶体管的单晶集成电路元件 (Single crystal integrated circuit device with pseudomorphic high electron mobility transistors ) 是由 钟荣涛 张家铭 曾隆镒 林彦丞 于 2020-10-23 设计创作，主要内容包括：一种具有假晶高电子迁移率晶体管的单晶集成电路元件,其包括一低夹止电压pHEMT和一高夹止电压pHEMT。在多层结构中的一萧基层包含至少三个半导体材料的层叠区域,其中两个相邻的层叠区域的每一者与另一者的材料不同且两者之间设有一层叠区域接面。pHEMT的每一者包括一栅极接触、一第一栅极金属层、一栅极沉降区域和一栅极沉降底边界。第一栅极金属层与萧基层的最上层层叠区域接触。栅极沉降区域位于第一栅极金属层下方。高夹止电压pHEMT的栅极沉降底边界位于萧基层的层叠区域接面的一者的上或下之内且比低夹止电压pHEMT的栅极沉降底边界更接近半导体基板。(A single crystal integrated circuit device having pseudomorphic HEMTs includes a low pinch-off voltage pHEMT and a high pinch-off voltage pHEMT. A Schottky layer in the multilayer structure comprises at least three laminated regions of semiconductor material, wherein each of two adjacent laminated regions is different from the other laminated region in material and a laminated region junction is arranged between the two laminated regions. Each of the phemts includes a gate contact, a first gate metal layer, a gate sinker region, and a gate sinker bottom boundary. The first gate metal layer and the uppermost layer of the Schottky layerAnd (4) contacting. The gate sinker region is located below the first gate metal layer. The gate landing bottom boundary of the high pinch-off voltage pHEMT is located above one of the junction of the stack regions of the Schottky layer Or below And closer to the semiconductor substrate than the gate-sinker bottom boundary of the low pinch-off voltage pHEMT.)

1. A single crystal integrated circuit device having a gate sinker pseudomorphic high electron mobility transistor, comprising:

a first pseudomorphic HEMT and a second pseudomorphic HEMT in a multilayer structure;

the multilayer structure comprises a semiconductor substrate, wherein a multilayer epitaxial semiconductor layer shared by the first pseudomorphic high-electron-mobility transistor and the second pseudomorphic high-electron-mobility transistor is superposed on the semiconductor substrate, the multilayer epitaxial semiconductor layer comprises a buffer layer, a channel layer is superposed on the buffer layer, a schottky layer is superposed on the channel layer, and a first covering layer is superposed on the schottky layer;

wherein the schottky layer comprises at least three laminated regions of semiconductor materials from bottom to top, wherein each of two adjacent laminated regions is made of a different material from the other laminated region, and a laminated region junction is arranged between the two laminated regions, wherein the distances from any two of the laminated region junctions to the semiconductor substrate are different;

wherein the source and drain contacts of the first and second pseudomorphic high electron mobility transistors are coupled to the first cap layer;

wherein each of the first pseudomorphic HEMT and the second pseudomorphic HEMT comprises a gate contact, a first gate metal layer, a gate sinker region, and a gate sinker bottom boundary;

wherein the respective gate contacts of the first and second pseudomorphic HEMTs are coupled to the Schottky layer, wherein the respective first gate metal layers of the first and second pseudomorphic HEMTs are in contact with the uppermost tier region of the Schottky layer;

wherein the gate sinker region of the first pseudomorphic high electron mobility transistor and the gate sinker region of the second pseudomorphic high electron mobility transistor are located below the first gate metal layers of the first pseudomorphic high electron mobility transistor and the second pseudomorphic high electron mobility transistor, respectively;

wherein the respective gate landing bottom boundaries of the first and second pseudomorphic HEMTs are located within the Schottky layer, wherein the gate landing bottom boundary of the second pseudomorphic HEMT is closer to the semiconductor substrate than the gate landing bottom boundary of the first pseudomorphic HEMT, and the gate landing bottom boundary of the second pseudomorphic HEMT is located above one of the stack region junctions of the Schottky layerOr belowWithin.

2. The high voltage with gate sinker pseudomorphic of claim 1A single crystal integrated circuit device of a mobility transistor, wherein the gate sinker bottom boundary of the first pseudomorphic HEMT is located above one of the junction of the Schottky layerOr belowWithin.

3. A single crystal integrated circuit device according to claim 1 having a gate sinker pseudomorphic hemt, wherein the gate sinker bottom boundary of the second pseudomorphic hemt is at one of the junction of the stacked regions of the schottky layer.

4. A single crystal integrated circuit device according to claim 1 having a gate sinker pseudomorphic hemt, wherein the gate sinker bottom boundary of the first pseudomorphic hemt is at one of the junction of the stacked regions of the schottky layer.

5. The device of claim 1, wherein in any two adjacent stacking regions of said schottky layer, a stacking region of AlGaAs-based semiconductor material comprising at least one of AlGaAs, AlGaAsP and inalgas and another stacking region of InGaP-based semiconductor material comprising at least one of InGaP, InGaPAs and AlInGaP are stacked alternately.

6. The single crystal integrated circuit device of claim 1 wherein said multilayer epitaxial semiconductor layer further comprises a first contact layer in contact with an upper surface of said uppermost stacked region of said schottky layer and said first cap layer is formed on said first contact layer, said first contact layer comprising at least one of GaAs, AlGaAs, AlGaAsP, inalgas, InGaP, InGaAsP and InAlGaP, and said first contact layer being of a different material than said uppermost stacked region of said schottky layer.

7. A single crystal integrated circuit device having gate sinker pseudomorphic HEMTs as recited in claim 6 wherein the respective first gate metal layers of the first and second pseudomorphic HEMTs are in contact with the first contact layer.

8. A single crystal integrated circuit device having gate sinker pseudomorphic hemts according to claim 1, wherein said first gate metal layer of each of said first and second pseudomorphic hemts comprises at least one of molybdenum, tungsten silicide, titanium, iridium, palladium, platinum, nickel, cobalt, chromium, ruthenium, osmium, rhodium, tantalum nitride, aluminum and rhenium.

9. A single crystal integrated circuit device having gate sinker pseudomorphic hemts according to claim 8 wherein said first gate metal layers of said first and second pseudomorphic hemts are made of different materials.

10. A single crystal integrated circuit device having gate sinker pseudomorphic hemts according to claim 8 wherein said first gate metal layer of each of said first and second pseudomorphic hemts is made of the same material.

11. A single crystal integrated circuit device having gate sinker pseudomorphic hemts according to claim 10 wherein said first gate metal layer of said second pseudomorphic hemt has a thickness greater than that of said first gate metal layer of said first pseudomorphic hemt.

12. A single crystal integrated circuit device of claim 1, wherein said multilayer epitaxial semiconductor layer further comprises an etch stop layer formed on said first cap layer and a second cap layer formed on said etch stop layer, and respective source and drain contacts of said first and second pseudomorphic hemts are formed on said second cap layer.

13. A single crystal integrated circuit element having a gate sinker pseudomorphic hemt according to claim 12 wherein said etch stop layer comprises at least one of InGaP, InGaAsP, InAlGaP and AlAs and said second cap layer comprises GaAs.

14. A single crystal integrated circuit element having a gate sinker pseudomorphic high electron mobility transistor according to claim 1, wherein the first cap layer comprises GaAs, the channel layer comprises at least one of GaAs and InGaAs, the buffer layer comprises at least one of GaAs and AlGaAs, and the compound semiconductor substrate comprises GaAs.

15. The device of claim 1, wherein the plurality of epitaxial semiconductor layers further comprises a carrier supply layer formed on the channel layer and the schottky layer formed on the carrier supply layer, the carrier supply layer comprising at least one of AlGaAs, AlGaAsP, and inalgas.

16. A single crystal integrated circuit device having a gate sinker pseudomorphic high electron mobility transistor, comprising:

a first pseudomorphic HEMT and a second pseudomorphic HEMT in a multilayer structure;

the multilayer structure comprises a semiconductor substrate, wherein a multilayer epitaxial semiconductor layer shared by the first pseudomorphic high-electron-mobility transistor and the second pseudomorphic high-electron-mobility transistor is superposed on the semiconductor substrate, the multilayer epitaxial semiconductor layer comprises a buffer layer, a channel layer is superposed on the buffer layer, a schottky layer is superposed on the channel layer, a first contact layer is superposed on the schottky layer, and a first covering layer is superposed on the first contact layer;

wherein the schottky layer comprises at least three laminated regions of semiconductor materials from bottom to top, wherein each of two adjacent laminated regions is made of a different material from the other laminated region, and a laminated region junction is arranged between the two laminated regions, wherein the distances from any two of the laminated region junctions to the semiconductor substrate are different;

wherein the first contact layer is in contact with an upper surface of the uppermost laminated region of the schottky layer, and an uppermost contact junction surface is arranged between the first contact layer and the uppermost laminated region of the schottky layer;

wherein the source and drain contacts of the first and second pseudomorphic high electron mobility transistors are coupled to the first cap layer;

wherein each of the first pseudomorphic HEMT and the second pseudomorphic HEMT comprises a gate contact, a first gate metal layer, a gate sinker region, and a gate sinker bottom boundary;

wherein the respective gate contacts of the first and second pseudomorphic HEMTs are coupled to the Schottky layer, wherein the respective first gate metal layers of the first and second pseudomorphic HEMTs are in contact with the first contact layer;

wherein the gate sinker region of the first pseudomorphic high electron mobility transistor and the gate sinker region of the second pseudomorphic high electron mobility transistor are located below the first gate metal layers of the first pseudomorphic high electron mobility transistor and the second pseudomorphic high electron mobility transistor, respectively;

wherein a gate sinker bottom boundary of the first pseudomorphic HEMT is located above the uppermost contact junctionOr belowWithin;

wherein a gate sinker bottom boundary of the second pseudomorphic HEMT is located above one of the junction of the stacking regions of the Schottky layerOr belowWithin.

17. A single crystal integrated circuit device according to claim 16 having gate sinker pseudomorphic hemts, wherein the gate sinker bottom boundary of the first pseudomorphic hemt is at the uppermost contact junction.

18. The single crystal integrated circuit device of claim 16 wherein in any two adjacent stacked regions of said schottky layer, stacked regions of AlGaAs-based semiconductor material comprising at least one of AlGaAs, AlGaAsP and inalgas and another stacked region of InGaP-based semiconductor material comprising at least one of InGaP, InGaPAs and AlInGaP are alternately stacked.

19. The single crystal integrated circuit device of claim 18 wherein the first contact layer comprises at least one of GaAs, AlGaAs, AlGaAsP, inalgas, InGaP, InGaAsP, and InAlGaP, and the first contact layer is of a different material than the uppermost stacked region of the schottky layer.

Technical Field

The present invention relates to a single crystal integrated circuit device comprising one or more pseudomorphic high electron mobility transistors (pHEMTs), and more particularly to a single crystal integrated gate sinker pseudomorphic high electron mobility transistor having a substantially very high threshold voltage uniformity across a wafer or between different wafers.

Background

Gate sinker or gate implant techniques have been widely used to achieve enhancement mode (E-mode/E-mode) pseudomorphic hemts (hereinafter pHEMT) with positive values of the pinch-off voltage or threshold voltage (hereinafter using a pinch-off voltage) due to the shortened gate-to-channel distance. Applications of gate sinker technology when transistor epitaxy structures and processes are properly designed should include, but not be limited to, enhancement mode pHEMT. The gate sinker technique requires careful control of the temperature and time of the thermal treatment process to ensure uniform and global diffusion of the first deposited gate metal into the schottky barrier layer. Therefore, it is a major need in the art for gate sinker pHEMT to have a highly uniform pinch-off voltage across the entire wafer or between different wafers.

In some applications, such as digital and bias circuits, multiple phemts with different pinch-off voltages are required. For example, a normally-off (positive pinch-off) pHEMT and a normally-on (negative pinch-off) pHEMT are epitaxially integrated on the same substrate. FIG. 1 illustrates a conventional single crystal integrated circuit device consisting of a depletion-mode/D-mode pHEMT D1 and an enhancement-mode/E-mode pHEMT E1. The conventional single crystal integrated circuit device includes a compound semiconductor substrate 100 and an epitaxial structure 110. The epitaxial structure 110 grown on the compound semiconductor substrate 100 includes, in order from bottom to top, a buffer layer 111, a channel layer 112, a schottky layer 113, a schottky contact layer 114, a first etch stop layer 115, a first conductive layer 116, a second etch stop layer 117, and a second conductive layer 118. The source electrodes 101/103 and the drain electrodes 102/104 of the depletion/enhancement pHEMT are formed on the second conductive layer 118. A gate recess 108 defined at the bottom by a schottky contact layer 114 is located between the source electrode 101 and the drain electrode 102 of the depletion mode pHEMT. A gate recess 109 defined by a schottky layer 113 at the bottom of the recess is located between the source electrode 103 and the drain electrode 104 of the enhanced pHEMT. A gate electrode 120 of depletion mode pHEMT is deposited on the schottky contact layer 114 in the gate recess 108. The gate electrode 130 of the enhancement mode pHEMT is deposited on the schottky layer 113 in the gate recess 109. As shown in fig. 1, the gate electrodes of depletion and enhancement pHEMT are formed on different semiconductor layers. This means that additional lithography and etching steps are required for both depletion and enhancement mode pHEMT in existing single crystal integrated circuit elements.

FIG. 2 illustrates another conventional single crystal integrated circuit device consisting of a depletion type pHEMT D1 and an enhancement type pHEMT E1. As shown in fig. 2, both depletion and enhancement pHEMT are fabricated with gate-sinker technology. The single crystal integrated circuit device includes a compound semiconductor substrate 200 and an epitaxial structure 210. The epitaxial structure 210 grown on the compound semiconductor substrate 200 includes, in order from bottom to top, a buffer layer 211, a channel layer 212, a first schottky energy barrier layer 213, a first etch stop layer 214, a second schottky energy barrier layer 215, a second etch stop layer 216, and an ohmic contact layer 217. The source electrodes 201/203 and the drain electrodes 202/204 of the depletion/enhancement pHEMT are formed on the ohmic contact layer 217. A gate recess 208 defined at the bottom by a second schottky barrier layer 215 is located between the source electrode 201 and the drain electrode 202 of the depletion mode pHEMT. A gate recess 209 defined at the bottom by a first schottky barrier layer 213 is located between the source electrode 203 and the drain electrode 204 of the enhancement mode pHEMT. A gate electrode 220 of the depletion mode pHEMT is deposited on the second schottky barrier layer 215 in the gate recess 208. A gate electrode 230 of the enhancement mode pHEMT is deposited on the first schottky energy barrier layer 213 in the gate recess 209. A gate sinker 221/231 is located under the gate electrode 220/230 of the depletion/enhancement pHEMT. In the conventional single crystal integrated circuit device shown in FIG. 2, the respective gate electrodes of the depletion type pHEMT and the enhancement type pHEMT are formed on different Schottky layers. This represents the need for additional photolithography and etching steps to form the gate recesses 208, 209 for depletion-type and enhancement-type pHEMT, resulting in additional cost and complexity in the pHEMT process. Most importantly, the etched surfaces of the first and second schottky barrier layers 213, 215 may cause defects and surface states that may degrade transistor characteristics and shift pHEMT clamp voltage from a target value.

In addition, the conventional single crystal integrated circuit device of fig. 2 suffers from serious problems in controlling the respective clamp voltages of depletion type pHEMT and enhancement type pHEMT. It is virtually impossible to perfectly control the bottom boundary of depletion/enhancement mode pHEMT gate sinker region 221/231 within a particular narrow region of the schottky barrier layer. This fact can be attributed to the thickness disparity of the gate electrode within the entire wafer or between different wafers, as well as to the temperature and time of the heat treatment. These undesirable effects cause height differences in the pinch-off voltage of the transistors across the wafer.

Therefore, a new design is highly desirable to achieve single integrated gate sinker pHEMT with very high clamping voltage per se, either across the entire chip or across different chips.

Disclosure of Invention

To achieve a desired clamping voltage uniformity in a single crystal integrated circuit device having more than one gate sinker pHEMT, the present invention implements a compound schottky layer structure stacked from semiconductor layers. By controlling the depth of the gate metal to a specific junction in the semiconductor layer of the schottky layer stack, the difference in clamping voltage across the entire chip or between different chips can be significantly reduced. In addition, the pinch-off voltage of each pHEMT in the single crystal integrated circuit element can be adjusted to any desired value (positive or negative). Accordingly, the present invention providesA single crystal integrated circuit device with a multi-layer structure composed of a low clamping voltage pHEMT and a high clamping voltage pHEMT is provided, wherein the multi-layer structure includes a semiconductor substrate on which a multi-layer epitaxial semiconductor layer shared by the low clamping voltage pHEMT and the high clamping voltage pHEMT is stacked, the multi-layer epitaxial semiconductor layer includes a buffer layer on which a channel layer is stacked, the channel layer is stacked with a Schottky layer, and the Schottky layer is stacked with a first cover layer. The Schottky layer comprises at least three laminated regions of semiconductor materials from bottom to top, wherein each of two adjacent laminated regions is made of a different material from the other laminated region, and a laminated region junction is arranged between the two laminated regions, wherein the distances from any two of the laminated region junctions to the semiconductor substrate are different. The source and drain contacts of the low pinch-off voltage pHEMT and the high pinch-off voltage pHEMT are coupled to the first capping layer. Each of the low pinch-off voltage pHEMT and the high pinch-off voltage pHEMT includes a gate contact, a first gate metal layer, a gate sinker region, and a gate sinker bottom boundary. The respective gate contacts of the low and high clamping voltages pHEMT are coupled to the schottky layer, wherein the respective first gate metal layers of the low and high clamping voltages pHEMT are in contact with the uppermost stacked region of the schottky layer. The gate sinker region of the low pinch-off voltage pHEMT and the gate sinker region of the high pinch-off voltage pHEMT are located below the first gate metal layer of the low pinch-off voltage pHEMT and the high pinch-off voltage pHEMT, respectively. The respective gate landing bottom boundaries of the low and high clamping voltages pHEMT are located within the Schottky layer, wherein the gate landing bottom boundary of the high clamping voltage pHEMT is closer to the semiconductor substrate than the gate landing bottom boundary of the low clamping voltage pHEMT, and the gate landing bottom boundary of the high clamping voltage pHEMT is located above one of the junction of the stacked regions of the Schottky layerOr belowWithin.

In addition to this, the present invention is,the invention provides another single crystal integrated circuit element comprising a low clamping voltage pHEMT and a high clamping voltage pHEMT in a multilayer structure, wherein the multilayer structure comprises a semiconductor substrate, a multilayer epitaxial semiconductor layer shared by the low clamping voltage pHEMT and the high clamping voltage pHEMT is superposed on the semiconductor substrate, the multilayer epitaxial semiconductor layer comprises a buffer layer, a channel layer is superposed on the buffer layer, a Schottky layer is superposed on the channel layer, a first contact layer is superposed on the Schottky layer, and a first covering layer is superposed on the first contact layer. The Schottky layer comprises at least three laminated regions of semiconductor materials from bottom to top, wherein each of two adjacent laminated regions is made of a different material from the other laminated region, and a laminated region junction is arranged between the two laminated regions, wherein the distances from any two of the laminated region junctions to the semiconductor substrate are different. The first contact layer is in contact with an upper surface of the uppermost laminated region of the schottky layer, and an uppermost contact junction surface is arranged between the first contact layer and the uppermost laminated region of the schottky layer. The source and drain contacts of the low pinch-off voltage pHEMT and the high pinch-off voltage pHEMT are coupled to the first capping layer. Each of the low pinch-off voltage pHEMT and the high pinch-off voltage pHEMT includes a gate contact, a first gate metal layer, a gate sinker region, and a gate sinker bottom boundary. The gate contacts of the low and high clamping voltages pHEMT are coupled to the schottky layer, and the first gate metal layer of the low and high clamping voltages pHEMT is in contact with the first contact layer. The gate sinker region of the low pinch-off voltage pHEMT and the gate sinker region of the high pinch-off voltage pHEMT are located below the first gate metal layer of the low pinch-off voltage pHEMT and the high pinch-off voltage pHEMT, respectively. The gate landing bottom boundary of the low clamping voltage pHEMT is located in the Schottky layer or above the uppermost contact junctionOr belowWithin. The gate landing bottom boundary of the high clamping voltage pHEMT is located on the Schottky layerOn one of the laminated region junctionsOr belowWithin. And the gate landing bottom boundary of the high pinch-off voltage pHEMT is closer to the semiconductor substrate than the gate landing bottom boundary of the low pinch-off voltage pHEMT.

In some embodiments, the gate landing bottom boundary of the low pinch-off voltage pHEMT is located above one of the schottky layer's stacked region junctionsOr belowWithin.

In some embodiments, the gate landing bottom boundary of the high pinch-off voltage pHEMT is at one of the schottky layer's stacked region junctions.

In some embodiments, the gate landing bottom boundary of the low pinch-off voltage pHEMT is at one of the junction of the stacked regions of the schottky layer or the uppermost contact junction.

In some embodiments, the first contact layer comprises at least one of GaAs, AlGaAs, AlGaAsP, inalgas, InGaP, InGaAsP, and InAlGaP, and the first contact layer is of a different material than the uppermost stacked region of the schottky layer.

In some embodiments, in any two adjacent stacked regions of the schottky layer, stacked regions composed of an AlGaAs-based semiconductor material including at least one of AlGaAs, AlGaAsP, and inalgas and another stacked region composed of an InGaP-based semiconductor material including at least one of InGaP, InGaPAs, and AlInGaP are alternately stacked.

In some embodiments, the respective first gate metal layers of the low and high pinch-off voltages pHEMT include at least one of molybdenum (Mo), tungsten (W), tungsten silicide (WSi), titanium (Ti), iridium (Ir), palladium (Pd), platinum (Pt), nickel (Ni), cobalt (Co), chromium (Cr), ruthenium (Ru), osmium (Os), rhodium (Rh), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), and rhenium (Re).

In some embodiments, the respective first gate metal layers of the low and high pinch-off voltages pHEMT are made of different materials.

In some embodiments, the respective first gate metal layers of the low and high pinch-off voltages pHEMT are made of the same material.

In some embodiments, the thickness of the first gate metal layer of the high pinch-off voltage pHEMT is greater than the thickness of the first gate metal layer of the low pinch-off voltage pHEMT.

In some embodiments, the multi-layered epitaxial semiconductor layer further includes an etch stop layer formed on the first cap layer and a second cap layer formed on the etch stop layer, and the respective source and drain contacts of the low and high pinch-off voltages pHEMT are formed on the second cap layer.

In some embodiments, the etch stop layer comprises at least one of InGaP, InGaAsP, InAlGaP, and AlAs, and the second capping layer comprises GaAs.

In some embodiments, the first capping layer comprises GaAs, the channel layer comprises at least one of GaAs and InGaAs, the buffer layer comprises at least one of GaAs and AlGaAs, and the compound semiconductor substrate comprises GaAs.

In order to further understand the features and functions of the present invention, the following embodiments are described in detail with reference to the drawings.

Drawings

FIG. 1 is a cross-sectional schematic diagram of a prior art embodiment of a single crystal integrated circuit device.

Figure 2 is a cross-sectional schematic diagram of another prior art embodiment of a single crystal integrated circuit element having a gate sinker pHEMT.

Fig. 3A-3G are schematic side cross-sectional views of a single-crystal integrated circuit device having a gate-sinker pHEMT in accordance with an embodiment of the present invention.

Fig. 4A-4C are schematic side cross-sectional views of a single-crystal integrated circuit device having a gate sinker pHEMT in accordance with an embodiment of the present invention.

Fig. 5-7 are schematic side cross-sectional views of single-crystal integrated circuit devices having gate-sinker pHEMT in accordance with embodiments of the present invention.

[ notation ] to show

1 a single crystal integrated circuit element;

2 a multilayer structure;

5 an insulating region;

10 a semiconductor substrate;

20 buffer layers;

30 channel layers;

35 carrier supply layer;

40 of the schottky layer;

42 a lamination area;

43 a stacked region junction;

44 a lamination area;

45 a stacked region junction;

46 a lamination area;

47 a stacked region junction;

48 a lamination area;

49 uppermost contact junction;

50 a first cover layer;

52 a second cover layer;

60 a first contact layer;

70 etching the stop layer;

91 a grid electrode groove;

92 a gate recess;

100 a compound semiconductor substrate;

101 a source electrode;

102 a drain electrode;

103 a source electrode;

104 a drain electrode;

108 a gate recess;

109 a gate recess;

110 epitaxial structure;

111 a buffer layer;

112 a channel layer;

113 a Schottky layer;

114 Schottky contact layer;

115 a first etch stop layer;

116 a first conductive layer;

117 a second etch stop layer;

118 a second conductive layer;

a 120 gate electrode;

130 a gate electrode;

200 a compound semiconductor substrate;

201 a source electrode;

202 a drain electrode;

203 a source electrode;

204 a drain electrode;

208 a gate recess;

209 a gate recess;

210 an epitaxial structure;

211 a buffer layer;

212 a channel layer;

213 a first Schottky barrier layer;

214 a first etch stop layer;

215 a second Schottky barrier layer;

216 a second etch stop layer;

217 ohmic contact layer;

220 a gate electrode;

a 221 gate sinker region;

230 a gate electrode;

231 a gate sinker region;

d1 depletion pHEMT;

e1 enhanced pHEMT;

h1 high pinch-off voltage pHEMT;

l1 low pinch-off voltage pHEMT;

d1 drain contact;

d2 drain contact;

g1 gate contact;

g11 first gate metal layer;

g12 gate sinker region;

g13 gate sinker bottom boundary;

g14 upper limit;

g15 lower limit;

g2 gate contact;

g21 first gate metal layer;

g22 gate sinker region;

g23 gate sinker bottom boundary;

g24 upper limit;

g25 lower limit;

s1 source contact;

s2 source contact.

Detailed Description

Figure 3A is a side cross-sectional view of a single crystal integrated circuit device having a gate sinker pHEMT in accordance with an embodiment of the present invention. The single crystal integrated circuit element 1 with gate sinker pHEMT comprises a low pinch-off voltage pHEMT L1 and a high pinch-off voltage pHEMT H1 in a multilayer structure 2. The multilayer structure 2 comprises a semiconductor substrate 10 on which are superimposed multilayer epitaxial semiconductor layers common to the low and high pinch-off voltages pHEMT. The multi-layer epitaxial semiconductor layer includes a buffer layer 20, a channel layer 30 stacked on the buffer layer 20, a schottky layer 40 stacked on the channel layer 30, and a first covering layer 50 stacked on the schottky layer 40. The schottky layer 40 comprises, from bottom to top, three stacked regions 42, 44, 46 of semiconductor material, wherein two adjacent stacked regions are each of a different material than the other. A lamination region interface 43 is provided between adjacent lamination regions 42, 44, and a lamination region interface 45 is provided between adjacent lamination regions 44, 46. The laminated region junctions 43 and 45 have different distances to the semiconductor substrate 10. The multilayer epitaxial semiconductor layer comprises an insulating region 5 located between a low pinch-off voltage pHEMT L1 and a high pinch-off voltage pHEMT H1. Each of the low pinch-off voltage pHEMT L1 and the high pinch-off voltage pHEMT H1 is isolated by an insulating region 5. The source contact s1 and the drain contact d1 of the low pinch-off voltage pHEMT L1 are coupled to the first cap layer 50. The source contact s2 and the drain contact d2 of the high pinch-off voltage pHEMT H1 are coupled to the first cap layer 50. The low pinch-off voltage pHEMT L1 includes a gate contact g 1. The gate contact g1 includes a first gate metal layer g 11. The gate contact g1 may further include a second gate metal layer deposited on the first gate metal layer g 11. A gate sinker g12 is located under the first gate metal layer g 11. The gate sinker region g12 has a gate sinker bottom boundary g 13. The high pinch-off voltage pHEMT H1 includes a gate contact g 2. The gate contact g2 includes a first gate metal layer g 21. The gate contact g2 may further include a second gate metal layer deposited on the first gate metal layer g 21. A gate sinker g22 is located under the first gate metal layer g 21. The gate sinker region g22 has a gate sinker bottom boundary g 23. A gate recess 91 of the low pinch-off voltage pHEMT L1 is located between the source electrode s1 and the drain electrode d 1. A gate recess 92 of the high pinch-off voltage pHEMT H1 is located between the source electrode s2 and the drain electrode d 2. The gate contact g1 of the low pinch-off voltage pHEMT L1 is located within the gate recess 91. The gate contact g1 is coupled to the schottky layer 40. The gate contact g2 of the high pinch-off voltage pHEMT H1 is located within the gate recess 92. The gate contact g2 is coupled to the schottky layer 40. The first gate metal layers g11 and g21 of the low pinch-off voltage pHEMT L1 and the high pinch-off voltage pHEMT H1, respectively, contact the uppermost stacked region 46 of the schottky layer 40. The gate sinker region g12 of the low pinch-off voltage pHEMT is located below the first gate metal layer g11 of the low pinch-off voltage pHEMT. The gate sinker region g22 of the high pinch-off voltage pHEMT is located below the first gate metal layer g21 of the high pinch-off voltage pHEMT.

Gate landing boundaries g13 and g23 are located within Schottky layer 40. High-clamping power-offThe gate landing bottom boundary g23 of the voltage pHEMT H1 is closer to the semiconductor substrate 10 than the gate landing bottom boundary g13 of the low pinch-off voltage pHEMT L1. The gate-landing bottom boundary g23 of the high pinch-off voltage pHEMT H1 is between an upper limit g24 and a lower limit g 25. The upper limit g24 is above one of the junction surfaces of the laminated regions of the Schottky layer 40Lower limit g25 below the same lamination region junctionTo (3). In some embodiments, the gate landing bottom boundary g23 of the high pinch-off voltage pHEMT H1 may be located at one of the junction of the stacked regions of the schottky layer 40. In some embodiments, the gate landing bottom boundary g13 of the low pinch-off voltage pHEMT L1 is between an upper limit g14 and a lower limit g 15. The upper limit g14 is above one of the junction surfaces of the laminated regions of the Schottky layer 40Lower limit g15 below the same lamination region junctionTo (3). In some embodiments, the gate landing bottom boundary g13 of the low pinch-off voltage pHEMT L1 may be located at one of the junction of the stacked regions of the schottky layer 40. In the embodiment shown in FIG. 3A, gate landing bottom boundary g13 of low pinch-off voltage pHEMT L1 is located at the stack region junction 45 of the Schottky layer 40, and gate landing bottom boundary g23 of high pinch-off voltage pHEMT H1 is located at the stack region junction 43 of the Schottky layer 40. Fig. 3B-3E show other embodiments of single crystal integrated circuit elements having gate-sinker pHEMT in accordance with the present invention. In fig. 3B to 3E, the upper limit g14 and the lower limit g15 are located above the laminated region junction 45, respectivelyAnd belowUpper limit g24 and lower limitg25 are respectively located above the laminated region junction surfaces 43And belowTo (3). In FIG. 3B, gate landing bottom boundary g13 of low pinch-off voltage pHEMT L1 is located at the stack region junction 45 of the Schottky layer 40, and gate landing bottom boundary g23 of high pinch-off voltage pHEMT H1 is located between upper boundary g24 and the stack region junction 43 of the Schottky layer 40. In FIG. 3C, gate landing bottom boundary g13 of low pinch-off voltage pHEMT L1 is located at the stack region junction 45 of the Schottky layer 40, and gate landing bottom boundary g23 of high pinch-off voltage pHEMT H1 is located between lower boundary g25 and the stack region junction 43 of the Schottky layer 40. In FIG. 3D, gate landing bottom boundary g13 of low pinch-off voltage pHEMT L1 is located between lower limit g15 and stack region junction 45 of Schottky layer 40, and gate landing bottom boundary g23 of high pinch-off voltage pHEMT H1 is located between lower limit g25 and stack region junction 43 of Schottky layer 40. In FIG. 3E, gate landing bottom boundary g13 of low pinch-off voltage pHEMT L1 is located between upper limit g14 and stack region junction 45 of Schottky layer 40, and gate landing bottom boundary g23 of high pinch-off voltage pHEMT H1 is located between lower limit g25 and stack region junction 43 of Schottky layer 40.

In some embodiments, in any two adjacent stacked regions of the schottky layer 40, stacked regions composed of an AlGaAs-based semiconductor material including at least one of AlGaAs, AlGaAsP, and inalgas and another stacked region composed of an InGaP-based semiconductor material including at least one of InGaP, InGaPAs, and AlInGaP are alternately stacked.

In the present invention, the schottky layer may include more than three stacked regions of semiconductor materials, wherein each of two adjacent stacked regions is different from the other stacked region in material, and a stacked region junction is disposed between the two stacked regions, and the distances from any two of the stacked region junctions to the semiconductor substrate are different. FIGS. 3F and 3G show the gate-settled pHEM of the present inventionT, wherein the schottky layer 40 comprises, from bottom to top, four stacked regions 42, 44, 46, 48 of semiconductor material. The laminated region junctions 43, 45, 47 are provided between the laminated regions, respectively. As shown in FIG. 3F, gate landing bottom boundary g13 of low pinch-off voltage pHEMT L1 is located at stack region junction 47 of Schottky layer 40, and gate landing bottom boundary g23 of high pinch-off voltage pHEMT H1 is located at stack region junction 43 of Schottky layer 40. In FIG. 3G, the upper limit G14 and the lower limit G15 are located above the laminated region junction 45, respectivelyAnd belowTo (3). The upper limit g24 and the lower limit g25 are respectively located above the laminated region junction 43And belowTo (3). The gate landing bottom boundary g13 of low pinch-off voltage pHEMT L1 is located between the lower limit g15 and the stacked region junction 45 of the schottky layer 40, and the gate landing bottom boundary g23 of high pinch-off voltage pHEMT H1 is located between the lower limit g25 and the stacked region junction 43 of the schottky layer 40.

Fig. 4A-4C show other embodiments of single crystal integrated circuit elements having gate-sinker pHEMT in accordance with the present invention. In fig. 4A and 4B, the schottky layer 40 includes three stacked regions 42, 44, 46 of semiconductor material from bottom to top, and stacked region junctions 43, 45 are respectively disposed between the stacked regions. As mentioned above, the Schottky layer may comprise more than three stacked regions of semiconductor material. In FIG. 4C, the Schottky layer 40 comprises, from bottom to top, four stacked regions 42, 44, 46, 48 of semiconductor material. The laminated region junctions 43, 45, 47 are provided between the laminated regions, respectively. In FIGS. 4A to 4C, the multi-layered epitaxial semiconductor layer further includes a first contact layer 60 contacting an upper surface of the uppermost stacked region of the Schottky layer. Of the first contact layer 60 and the Schottky layer 40An uppermost contact surface 49 is formed between the uppermost stacked regions. The first capping layer 50 is formed on the first contact layer 60. The respective first gate metals g11 and g21 layers of the low pinch-off voltage pHEMT L1 and the high pinch-off voltage pHEMT H1 are in contact with the first contact layer 60. The gate landing bottom boundary g13 of the low pinch-off voltage pHEMT L1 is between an upper limit g14 and a lower limit g 15. Upper limit g14 above uppermost contact junction 49At or above one of the junction surfaces of the laminated regions of the schottky layer 40Where the lower limit g15 is below the same junction (uppermost contact junction or stacked region junction)To (3). The gate-landing bottom boundary g23 of the high pinch-off voltage pHEMT H1 is between an upper limit g24 and a lower limit g 25. The upper limit g24 is above one of the junction surfaces of the laminated regions of the Schottky layer 40Lower limit g25 below the same lamination region junctionTo (3). As shown in FIG. 4A, gate landing bottom boundary g13 of low pinch-off voltage pHEMT L1 is located at stack region junction 45 of Schottky layer 40, and gate landing bottom boundary g23 of high pinch-off voltage pHEMT H1 is located at stack region junction 43 of Schottky layer 40. In FIG. 4B, the gate landing bottom boundary g13 of the low pinch-off voltage pHEMT L1 is located at the uppermost contact junction 49, while the gate landing bottom boundary g23 of the high pinch-off voltage pHEMT H1 is located at the stack region junction 43 of the Schottky layer 40. In fig. 4C, the gate landing bottom boundary g13 of the low pinch-off voltage pHEMT L1 is located at the uppermost contact junction 49, while the gate landing bottom boundary g23 of the high pinch-off voltage pHEMT H1 is located at the stack region junction 43 of the schottky layer 40.

In some embodiments, the first contact layer 60 comprises at least one of GaAs, AlGaAs, AlGaAsP, inalgas, InGaP, InGaAsP, and InAlGaP, and the first contact layer 60 is of a different material than the uppermost stacked region of the schottky layer 40.

In some embodiments, the respective first gate metal layers of the low and high pinch-off voltages pHEMT include at least one of molybdenum (Mo), tungsten (W), tungsten silicide (WSi), titanium (Ti), iridium (Ir), palladium (Pd), platinum (Pt), nickel (Ni), cobalt (Co), chromium (Cr), ruthenium (Ru), osmium (Os), rhodium (Rh), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), and rhenium (Re). In some embodiments, the respective first gate metal layers of the low and high pinch-off voltages pHEMT are made of different materials. In some embodiments, the respective first gate metal layers of the low and high pinch-off voltages pHEMT are made of the same material. In some embodiments, the thickness of the first gate metal layer of the high pinch-off voltage pHEMT is greater than the thickness of the first gate metal layer of the low pinch-off voltage pHEMT.

Figure 5 shows another embodiment of a single crystal integrated circuit element of the present invention having a gate sinker pHEMT. In this embodiment, the multi-layered epitaxial semiconductor layer further includes an etch stop layer 70 and a second cap layer 52. An etch stop layer 70 is formed on the first capping layer 50 and a second capping layer 52 is formed on the etch stop layer 70. The source contacts s1, s2 and the drain contacts d1, d2 of the low pinch-off voltage pHEMT L1 and the high pinch-off voltage pHEMT H1, respectively, are coupled to the second cap layer 52.

In some embodiments, the etch stop layer 70 comprises at least one of InGaP, InGaAsP, InAlGaP, and AlAs, and the second capping layer 52 comprises GaAs. In some embodiments, first capping layer 50 comprises GaAs. In some embodiments, the channel layer 30 comprises at least one of GaAs and InGaAs. In some embodiments, buffer layer 20 comprises at least one of GaAs and AlGaAs. In some embodiments, the compound semiconductor substrate 10 includes GaAs.

Figure 6 shows another embodiment of a single crystal integrated circuit element of the present invention having a gate sinker pHEMT. In this embodiment, the multi-layered epitaxial semiconductor layer further includes a carrier supply layer 35. The carrier supply layer 35 is formed on the channel layer 30, and the schottky layer 40 is formed on the carrier supply layer 35. The carrier supply layer 35 includes at least one of AlGaAs, AlGaAsP, and inalgas.

Figure 7 shows another embodiment of a single crystal integrated circuit element of the present invention having a gate sinker pHEMT. In this embodiment, the schottky layer 40 comprises four stacked regions 42, 44, 46, 48 of semiconductor material from bottom to top, with stacked region junctions 43, 45, 47 respectively disposed between the stacked regions. The low pinch-off voltage pHEMT L1 and the high pinch-off voltage pHEMT H1 share a pair of source contact s1 and drain contact d 1. The low pinch-off voltage pHEMT L1 includes a gate contact g 1. The gate contact g1 includes a first gate metal layer g11, a gate sinker region g12, and a gate sinker bottom boundary g 13. The high pinch-off voltage pHEMT H1 includes a gate contact g 2. The gate contact g2 includes a first gate metal layer g21, a gate sinker region g22, and a gate sinker bottom boundary g 23. The gate recesses 91 and 92 of the low pinch-off voltage pHEMT L1 and the high pinch-off voltage pHEMT H1, respectively, are located between the source electrode s1 and the drain electrode d 1. The gate contact g1 of the low pinch-off voltage pHEMT L1 coupled to the schottky layer 40 is located within the gate recess 91. The gate contact g2 of the high pinch-off voltage pHEMT H1 coupled to the schottky layer 40 is located within the gate recess 92. The first gate metal layers g11 and g21 of the low pinch-off voltage pHEMT L1 and the high pinch-off voltage pHEMT H1, respectively, are in contact with the uppermost stacked region 48 of the schottky layer 40. The gate sinker region g12 of the low pinch-off voltage pHEMT is located below the first gate metal layer g11 of the low pinch-off voltage pHEMT. The gate sinker region g22 of the high pinch-off voltage pHEMT is located below the first gate metal layer g21 of the high pinch-off voltage pHEMT. In fig. 7, the upper limit g14 and the lower limit g15 are located above the laminated region junction 47, respectivelyAnd belowThe upper limit g24 and the lower limit g25 are respectively located above the laminated region junction 43And belowTo (3). The gate landing bottom boundary g13 of the low pinch-off voltage pHEMT L1 is located at the stack region junction 47 of the schottky layer 40, while the gate landing bottom boundary g23 of the high pinch-off voltage pHEMT H1 is located at the stack region junction 43 of the schottky layer 40.

Thus, the uniformity of the pinch-off voltage and gate-channel distance per pHEMT in a single crystal integrated circuit device is significantly improved. Furthermore, the pinch-off voltage of each pHEMT in the single crystal integrated circuit device can be designed to be any desired value (positive or negative). In addition, the process can be simplified and the economic benefit can be improved.

Although embodiments of the present invention have been described in detail, further modifications and variations can be made by persons skilled in the art in light of the above teachings. Therefore, it should be understood that any modifications and variations equivalent to the spirit of the present invention should be considered to fall within the scope defined by the appended claims.