阅读说明：本技术 高频开关应用中用于噪声滤波的电容器堆栈及运用其的光学子组件模块 (Capacitor stack for noise filtering in high frequency switching applications and optical subassembly module employing same ) 是由 刘翼 李秦 王修哲 陈如如 于 2020-10-09 设计创作，主要内容包括：本发明一般是针对利用以端子到端子的方向安装的电容器堆栈来减少旁路滤波电路的电容器阵列的总体占用面积。在一实施例中,每个电容器堆栈至少包括第一电容器、第二电容器和接地面互连。第一电容器包括相互对置的第一、第二端子。第一端子提供配接面以耦合第二电容器,第二端子耦合接地面。第二电容器包括相互对置的第一、第二端子。第一端子提供一安装面以电性耦合第一电容器并支持第一电容器,第二端子提供一配接面以电性和物理地耦合至接地面。因此,第一电容器可以倒置并安装在第二电容器之上,以消除例如导线键的必要性。(The present invention is generally directed to reducing the overall footprint of a capacitor array bypassing a filter circuit using a capacitor stack mounted in a terminal-to-terminal direction. In an embodiment, each capacitor stack includes at least a first capacitor, a second capacitor, and a ground plane interconnect. The first capacitor includes first and second terminals that are opposed to each other. The first terminal provides a mating face for coupling to the second capacitor and the second terminal couples to the ground plane. The second capacitor includes first and second terminals that face each other. The first terminal provides a mounting surface for electrically coupling and supporting the first capacitor, and the second terminal provides a mating surface for electrically and physically coupling to the ground plane. Thus, the first capacitor can be inverted and mounted on top of the second capacitor to eliminate the necessity of wire bonds, for example.)

1. A capacitor stack for use in a bypass circuit to decouple unwanted high frequency and/or low frequency noise from a signal, said capacitor stack comprising:

a first capacitor having a first terminal disposed opposite a second terminal, the first terminal providing a mating face; and

a second capacitor having a first terminal disposed opposite a second terminal, the first terminal providing a mounting face for coupling with and supporting the first capacitor through the mating face of the first capacitor,

wherein the first capacitor is mounted vertically on the second capacitor in a terminal-to-terminal orientation, wherein the terminal-to-terminal orientation includes the first terminal of the first capacitor being electrically coupled to the first terminal of the second capacitor through the mounting face, and

wherein the mounting face of the second capacitor provides a shelf area to electrically couple the first capacitor and the second capacitor to a power terminal and/or electrode of an associated integrated circuit.

2. The capacitor stack of claim 1 further comprising a ground plane interconnect electrically coupling the second terminal of the first capacitor to a ground plane.

3. The capacitor stack of claim 2 wherein the ground plane interconnect comprises at least one conductive segment disposed along a sidewall of the first and/or second capacitor.

4. The capacitor stack of claim 1 wherein said first capacitor has a first capacitance value and said second capacitor has a second capacitance value, said first and second capacitance values being different.

5. The capacitor stack of claim 4 wherein said first capacitance value is less than said second capacitance value.

6. The capacitor stack of claim 1 wherein said first capacitor has a first package size and said second capacitor has a second package size, wherein said first package size is smaller than said second package size.

7. The capacitor stack of claim 6 wherein the shelf area is provided based at least in part on the first package size being smaller than the second package size.

8. An optical subassembly, comprising:

a submount for coupling to at least one optical component, the submount defining a ground plane;

a voltage source;

an integrated circuit;

at least one capacitor stack disposed on the submount and electrically coupled to the integrated circuit to provide a bypass circuit for a first electrode of the integrated circuit, the at least one capacitor stack comprising at least one first capacitor mounted vertically on a second capacitor, the second capacitor having a first terminal and a second terminal, the first terminal providing a mounting surface coupled to the first capacitor and supporting the first capacitor, the second terminal electrically connected to the ground plane;

a common terminal provided by the mounting face of the second capacitor, the common terminal for electrically coupling the first and second capacitors to each other; and

a first electrical interconnect electrically coupling the common terminal and the voltage source, and a second electrical interconnect electrically coupling the common terminal and the first electrode of the integrated circuit.

9. The optical subassembly of claim 8, further comprising a ground plane interconnect extending from the ground plane to electrically couple a terminal of the first capacitor with the ground plane.

10. The optical subassembly of claim 9, wherein the ground plane interconnect comprises a first conductive segment and a second conductive segment, the second conductive segment extending laterally integrally with respect to the first conductive segment.

11. The optical subassembly of claim 8, wherein the first and second electrical interconnects comprise a first wire bond and a second wire bond, respectively.

12. The optical subassembly of claim 8, further comprising a plurality of capacitor stacks, each capacitor stack of the plurality of capacitor stacks electrically coupled to a respective electrode of the integrated circuit and providing a bypass circuit.

13. The optical subassembly of claim 8, wherein the integrated circuit is implemented as a Laser Diode Driver (LDD) capable of driving N laser configurations.

14. The optical subassembly of claim 8, wherein the optical subassembly is implemented as a multi-channel Transmitter Optical Subassembly (TOSA) module capable of transmitting at least four different channel wavelengths.

Technical Field

The present invention relates to optical communications, and more particularly, to a capacitor stack (capacitor stack) having two or more capacitors mounted to each other to reduce an overall footprint (footprint) and simplify electrical interconnections, and a bypass/filter circuit implemented with the capacitor stack for decoupling unwanted low and/or high frequency noise.

Background

Optical transceivers are used to transmit and receive optical signals for a variety of applications, including but not limited to network data centers, cable television broadband, and Fiber To The Home (FTTH) applications. For example, optical transceivers may provide higher speed and bandwidth over longer distances than copper cable transmissions. The desire to provide higher transmit/receive speeds in increasingly space-constrained optical transceiver modules presents challenges, for example, in terms of thermal management, insertion loss (insertion loss), rf drive signal quality, and manufacturing yield.

Optical transceivers typically include one or more Transmitter Optical Subassembly (TOSA) modules for transmitting channel wavelengths. TOSA modules generally include a laser diode, a Monitor Photodiode (MPD), and a Laser Diode Driver (LDDs). The drive TOSA module includes a high frequency switch. High frequency switching introduces frequency noise and may degrade TOSA performance. The filter circuit, also referred to as a decoupling or bypass circuit, may include one or more capacitors in an array to filter high and/or low frequency noise on the dc bias voltage provided to each TOSA module, for example. This noise on the dc bias has a particularly adverse effect on the performance of the TOSA module.

Filter capacitors of different capacitance and package size can form an array to perform the required filtering. However, the substrates (substrettes)/submounts (submounts) of TOSA modules typically have limited surface area for mounting and routing of wiring components. Such space limitations greatly complicate the introduction of filter configurations/circuits into TOSA modules, as well as other optical subassemblies such as receiver optical subassemblies. The continued development of optical sub-assemblies with transmission speeds up to 400Gb/s and above depends, at least in part, on filter circuits implemented using a small portion of the surface area of existing methods.

Disclosure of Invention

In view of the above, the present invention provides a capacitor stack and an optical subassembly that meet the above needs.

According to one aspect of the present invention, a capacitor stack for use in a bypass circuit to decouple unwanted high and/or low frequency noise from a signal is disclosed. The capacitor stack includes a first capacitor having a first terminal opposite a second terminal, the first terminal providing a mating face, a second capacitor having a first terminal opposite the second terminal, the first terminal providing a mounting face for coupling to and supporting the first capacitor through the mating face of the first capacitor, wherein the first capacitor is mounted on the second capacitor perpendicularly in a terminal-to-terminal orientation. Wherein the terminal-to-terminal orientation includes the first terminal of the first capacitor being electrically coupled to the first terminal of the second capacitor through the mounting face, and the mounting face of the second capacitor providing a shelf area to electrically couple the first and second capacitors to power terminals and/or electrodes of an associated Integrated Circuit (IC).

According to another aspect of the present invention, an optical subassembly is disclosed. The optical subassembly includes a submount for coupling to at least one optical component, the submount defining a ground plane, a voltage source, an Integrated Circuit (IC), at least one capacitor stack on the submount and electrically coupled to the IC to provide bypass circuitry for a first electrode of the IC, the at least one capacitor stack including at least a first capacitor mounted vertically above a second capacitor. The second capacitor has a first terminal providing a mounting face connected to and supporting the first capacitor and a second terminal electrically coupled to the ground plane, the mounting face of the second capacitor providing a common terminal electrically coupling the first and second capacitors to each other, a first electrical interconnect electrically coupling the common terminal to a voltage source and a second electrical interconnect electrically coupling the common terminal to a first electrode of the IC.

The foregoing description of the present disclosure and the following detailed description are presented to illustrate and explain the principles and spirit of the invention and to provide further explanation of the invention as claimed.

Drawings

Fig. 1 shows a block diagram of an example filtering arrangement with horizontally mounted filter capacitors.

Figure 2 illustrates another block diagram of an exemplary filtering configuration with a vertical capacitor stack, according to an embodiment of the invention.

Fig. 3 shows an example of a bypass circuit according to an embodiment of the invention.

Figure 4 illustrates an example of a capacitor stack according to an embodiment of the invention.

Figure 5 illustrates an example of another capacitor stack configuration including a plurality of capacitor stacks according to an embodiment of the present invention.

Figure 6 illustrates another example capacitor stack according to an embodiment of this disclosure.

Figure 7 illustrates a four capacitor stack according to an embodiment of the present invention.

Fig. 8 shows an example of a TO can (can) laser package with one or more integrated capacitor stacks according TO an embodiment of the invention.

Figure 9 shows a schematic diagram of an optical transceiver system according to an embodiment of the invention.

Detailed Description

The detailed features and advantages of the present invention are described in detail in the following embodiments, which are sufficient for anyone skilled in the art to understand the technical contents of the present invention and to implement the present invention, and the related objects and advantages of the present invention can be easily understood by anyone skilled in the art from the disclosure, the claims and the drawings of the present specification. The following examples further illustrate aspects of the invention in detail, but are not intended to limit the scope of the invention in any way.

Existing filtering arrangements, also known as bypass or decoupling circuits, utilize capacitor arrays to bypass/decouple unwanted frequency noise. Fig. 1 shows an example filter configuration comprising a plurality of capacitors connected in parallel with each other. For example, the filter configuration may implement a bypass circuit as shown in fig. 3. As shown, the capacitor includes a first terminal electrically connected to ground and a second terminal electrically coupled to VCC. An electrode of an Integrated Circuit (IC) includes at least one terminal coupled to a terminal of C2. Such a configuration is particularly suitable for providing a filtering/bypass function, but requires a relatively large surface area for installation. This footprint problem is exacerbated by having multiple filter circuits to provide bypass filtering on multiple ICs and/or multiple IC electrodes.

Fig. 2 shows another approach in which the capacitors are stacked on top of each other in a vertical direction. This vertically stacked configuration allows the capacitor to have a smaller footprint. A plurality of wire bonds may electrically couple terminals of the capacitor to VCC and, likewise, couple electrodes of the IC to the capacitor. However, wire bonds add complexity to manufacturing and may introduce time of flight (ToF) and impedance issues. In addition, the wire bonds are easily damaged during the manufacturing process.

Accordingly, the present invention is generally directed to reducing the overall footprint of a capacitor array for a bypass filter circuit (referred to herein simply as a bypass circuit) utilizing a capacitor stack mounted in a terminal-to-terminal orientation. In one embodiment, each capacitor stack includes at least a first capacitor, a second capacitor, and a ground plane interconnect (groundplane interconnect). The first capacitor includes first and second terminals opposite each other. The first terminal provides a mating face to couple to the second capacitor and the second terminal couples to the ground plane. The second capacitor includes first and second terminals opposite each other. The first terminal provides a mounting face to couple to and support the first capacitor (e.g., in a terminal-to-terminal mounting orientation), and the second terminal provides a mating face to electrically and physically couple to the ground plane. The ground plane interconnect extends from the ground plane and includes a segment/portion that is coupled to the second terminal of the first capacitor such that it is electrically coupled to the ground plane. Thus, the first capacitor can be inverted and mounted on top of the second capacitor, and thus the first and second capacitors can be electrically coupled together (e.g., directly through terminal-to-terminal contacts) to eliminate the need for electrical interconnects such as wire bonds.

In one embodiment, the first capacitor includes an overall package size that is smaller than the second capacitor. When the first capacitor is mounted on the second capacitor, a step/shoulder (shoulder) is formed, for example, based on a size difference therebetween (refer to fig. 4). This step allows a single wire bond or other suitable interconnection to electrically couple the first and second capacitors to, for example, the VCC terminal to receive a dc bias voltage.

Thus, the capacitor stack according to the invention greatly reduces the overall footprint required to implement a bypass circuit or any other circuit containing two or more capacitors on a space-constrained submount/substrate. Furthermore, the reduced footprint may allow multiple capacitor stacks to be disposed in close proximity to an associated component (e.g., IC). The circuit layout complexity and number of wire bonds required to implement a circuit using a capacitor stack can be significantly reduced. Furthermore, the capacitor stack according to the invention may be assembled at least partially separately from the optical components and the associated circuitry. The assembled or partially assembled capacitor stack may then be implemented into the required circuitry in a relatively simple manner to allow, for example, an automated pick-and-place (automated pick-and-place) assembly process.

As used herein, "channel wavelength" refers to the wavelength associated with an optical channel and may include a specified band of wavelengths surrounding a center wavelength. In one example, the channel wavelengths may be defined by an International Telecommunication Union (ITU) standard such as an ITU-T Dense Wavelength Division Multiplexing (DWDM) grid. The invention is also suitable for Coarse Wavelength Division Multiplexing (CWDM). In a specific embodiment, the channel wavelengths are implemented in Local Area Network (LAN) Wavelength Division Multiplexing (WDM), which may also be referred to as LWDM. As used herein, the term "coupled" refers to any connection, coupling, link, or the like, and "optically coupled" refers to coupling such that light from one element is transferred to another element. Such "coupled" devices are not necessarily directly connected to each other and may be separated by intermediate components or devices that may manipulate or modify such signals.

The term "substantially" as generally referred to herein refers to a degree of precision within an acceptable tolerance that takes into account and reflects minor real world variations due to material composition, material imperfections, and/or limitations/particularities in the manufacturing process. Such variations may be said to substantially achieve the described characteristics (but not necessarily all). To provide a non-limiting numerical example to quantify "substantially", minor variations may result in deviations from the specified stated masses/characteristics of up to and including ± 5%, unless the present disclosure dictates otherwise.

Fig. 3 illustrates an example of a bypass circuit 300 according to an embodiment. Fig. 3 illustrates the bypass circuit 300 in a highly simplified form for purposes of clarity and not limitation. As shown, the bypass circuit 300 includes a VCC terminal 302 (or VCC electrode), an array of capacitors shown collectively as 304 and individually as 304-1, 304-2, and 304-N, an Integrated Circuit (IC)308, and a ground plane 306. The bypass circuit 300 may be implemented within, for example, TOSAs and other optical subassemblies. In this case, the integrated circuit 308 may be implemented as a Laser Diode Driver (LDD) having N input electrodes for driving N lasers.

VCC terminal 302 is configured to electrically couple to a power/voltage source to provide power, e.g., dc power, to a power rail (power rail)312, which may also be referred to as a dc power rail. Each of the capacitors 304-1 through 304-N are electrically coupled in parallel with each other and each include a first end (end) coupled to the power rail 312 and a second end coupled to the ground plane 306. The IC 308 includes at least a first terminal/input (e.g., V)_IN)，Which is electrically coupled to the power rail 312 through the first electrode 310-1 (or terminal 310-1). IC 308 further includes at least a second terminal/input (e.g., GND) electrically coupled to ground plane 306 through second electrode 310-2 (or terminal 310-2).

The VCC terminal 302 may be configured to receive a dc bias voltage from an external driving circuit (not shown). VCC terminal 302 may then provide a voltage to IC 308 via power rail 312. The array of capacitors 304 is configured to provide a bypass for certain signal components to ensure that the IC 308 receives a relatively stable power signal, such as 5V, at a nominal (nominal) dc level.

For example, in the context of a high frequency radio frequency switch in a TOSA module, each capacitance of the array of capacitors 304 may be selected to ensure that the array of capacitors 304 filters out unwanted frequency noise. TOSA modules typically include components such as Laser Diodes (LDs), Arrayed Waveguide Gratings (AWGs), and Monitor Photodiodes (MPDs). The TOSA module may further include a filter capacitor, such as capacitors 304-1 through 304-N, to filter out frequency noise on a Direct Current (DC) bias. Such noise may appear as high frequency and/or low frequency noise, which, if unfiltered, may negatively impact the performance of the TOSA module.

Accordingly, the array of capacitors 304 may include N capacitors in parallel to ensure that this frequency noise is filtered/decoupled to produce a "clean" dc bias. Based on equation 1, the frequency response of the capacitor is frequency dependent:

thus, a particular value for each of the array of capacitors 304 may be selected to ensure that noise at the target frequency is bypassed/filtered. Low value capacitors tend to bypass/filter high frequency noise, and conversely, relatively high value capacitors tend to bypass/filter low frequencies. In one embodiment, the array of capacitors 304 includes a first capacitor 304-1 having a first capacitance value and a second capacitor 304-2 having a second capacitance value, the first capacitance value being less than the second capacitance value.

For example, the first capacitor 304-1 may comprise a first capacitance value of about 100 picofarads (pF), while the second capacitor 304-2 may comprise a capacitance value of between about 100 and 200 nano-farads (nF). Thus, in this example, the second capacitance value may thus be at least 3 orders of magnitude greater than the first capacitance value. In this example, the relatively small capacitance (capacitance) of the first capacitance 304-1 may bypass/filter unwanted high frequency noise. Preferably, the first capacitor 304-1 is disposed in close physical proximity to a corresponding input/electrode of the IC 308, as shown. On the other hand, the relatively large capacitance of the second capacitor 304-2 may bypass/filter out unwanted low frequency noise.

As discussed in more detail below, the array of capacitors 304 may comprise a stacked configuration in which the capacitors are mounted to each other in a vertical orientation. This stacked configuration advantageously utilizes vertical space, that is, the area away from the mounting surface of the PCB/submount rather than horizontal space, to reduce the overall footprint of the array of capacitors 304. The capacitors in a stacked configuration may generally be referred to herein simply as a vertical capacitor stack, or simply as a capacitor stack.

Furthermore, an embodiment of the present invention includes utilizing capacitor package size differences to reduce wiring complexity and achieve nominal bypass/decoupling coverage. In general terms, the inductance of the capacitor is reduced/increased relative to the package size. For example, as package size increases, inductance generally increases, and vice versa. Accordingly, bypass capacitor arrays typically utilize one or more relatively small packaged capacitors to filter out high frequency noise and one or more relatively large packages to filter out low frequency noise. One layout for such a capacitor array involves placing smaller capacitors near the IC for filtering high frequency noise and larger capacitors near the power supply for filtering low frequency noise. However, the design and implementation of a capacitor stack according to the present invention may include any number of configurations/layouts depending on, for example, layout limitations (e.g., PCB/submount dimensions), targeted decoupling coverage, and other design specific characteristics.

In view of the foregoing, it has been determined by the present invention that a capacitor stack in accordance with the present invention can have a relatively large package of capacitors so as to generally serve as a sub-mount or base for mounting and supporting one or more capacitors having a relatively small package (which may be referred to herein as "top capacitors"). For example, and referring to fig. 4, a capacitor stack 400 (also referred to herein as a capacitor stack configuration) includes a VCC terminal/electrode 402, a first capacitor 404-1, a second capacitor 404-2, a ground plane 406, an IC 408, and a ground plane interconnect 410. The first and second capacitors 404-1, 404-2 may be implemented as surface mount electrolytic capacitors, or any suitable capacitor package. The IC 408 may be implemented, for example, as a Laser Diode Driver (LDD) capable of driving an arrangement of N Laser Diodes (LDs).

As shown, the second capacitor 404-2 includes a first terminal 412-1 provided by a first surface of the second capacitor 404-2 and a second terminal 412-2 provided by a second surface of the second capacitor 404-2, the first surface being disposed opposite the second surface. Thus, second capacitor 404-2 is electrically coupled to VCC through first terminal 412-1 and to ground plane 406 through second terminal 412-2. The first terminal 412-1, and in particular the first surface defining the first terminal 412-1, further provides a mounting area for coupling to and supporting at least the first capacitor 404-1.

The first capacitor 404-1 also includes a first terminal 411-1 for electrically coupling to the VCC terminal 402 and a second terminal 411-2 for electrically coupling to the ground plane 406, the first terminal 411-1 being disposed opposite the second terminal 411-2. The first terminal 411-1 of the first capacitor 404-1 provides a mating interface for coupling with the second capacitor 404-2. Thus, by the first terminal 411-1, in particular defining the mating face of the first terminal 411-1, the first capacitor 404-1 is mounted in, for example, a terminal-to-terminal orientation and electrically coupled to the first terminal 412-1 of the second capacitor 404-2. It is noted that the first capacitor 404-1 and the second capacitor 404-2 may be directly electrically coupled, for example, as shown, or may utilize a conductive material, such as a conductive epoxy, disposed therebetween.

Ground plane interconnects extending from ground plane 406 and disposed along sidewalls of first and second capacitors 404-1, 404-2 as a whole 410 and separately as first and second conductive segments (or portions) 410-1, 410-2, respectively. The ground plane interconnect 410 may be disposed on the sidewalls of the vertical capacitor stack, as shown, or may include a gap (gap)/offset (offset) therebetween, depending on the desired configuration.

The ground plane interconnect 410 may comprise at least one layer of a conductive metallic material, such as copper (Cu) or other suitable conductive material. The first conductive segment 410-1 extends from the ground plane 406 to an overall height that is substantially equal to the overall height of the first and second capacitors 404-1, 404-2 stacked on top of each other. The first and second conductive segments 410-1, 410-2 may be integrally formed as one piece of material or may be formed from multiple pieces of material. Second conductive segment 410-2 extends substantially transversely from first conductive segment 404-1. Thus, the first and second conductive segments 410-1, 410-2 may define an "L" shaped profile.

Second conductive segment 410-2 includes at least a portion disposed on and electrically coupled to second terminal 411-2 of first capacitor 404-1. Additionally, the second conductive segment 410-2 may be implemented as other types of electrical interconnections, such as wire bonds. In this case, the second conductive segment 410-2 may be omitted and the first conductive segment 410-1 may be electrically coupled to the second terminal 411-2 of the first capacitor 404-1 via a wire bond.

In any case, the first terminal 412-1 of the second capacitor 404-2 provides a common terminal for the capacitor stack based on the shoulder/step region 416. The size of the shoulder region 416 may vary depending on the size of the first and second capacitors 404-1, 404-2, but preferably the shoulder region 416 contains at least 100x100 square microns of space for wiring.

Thus, a single electrical interconnect, such as the first wire bond 414-1, may electrically couple both the first terminal 411-1 of the first capacitor 404-1 and the first terminal 412-1 of the second capacitor 404-2 to the VCC terminal 402. Likewise, a single electrical interconnect (single electrical interconnect), such as second wire bond 414-2, may electrically couple both the first terminal 411-1 of the first capacitor 404-1 and the first terminal 412-1 of the second capacitor 404-2 to the IC 408. In addition, the location of the common terminal provided by shoulder region 416 relative to IC 408, and more specifically electrode 418, allows for a relatively short electrical interconnection path by the provision of second wire bond 414-2. Accordingly, the first capacitor 404-1 may be electrically coupled to the electrode 418 of the IC 408 in a relatively short and straightforward manner to ensure nominal decoupling/filtering performance of high frequency noise.

Fig. 5 illustrates another exemplary capacitor stack configuration 500 comprising a capacitor stack array 550 consistent with the invention. The capacitor stack configuration 500 is shown in a highly simplified form for ease of description and clarity. Each capacitor stack in the capacitor stack array 550 may be configured substantially similar to the capacitor stacks shown and discussed above with reference to fig. 4, and the description will not be repeated for the sake of brevity.

The capacitor stack configuration 500 may include one or more associated power supply rails (not shown) and corresponding VCC terminals. Note that each capacitor stack of capacitor stack array 550 may include N number of capacitors, and need not include only two capacitors as shown. Further, each capacitor stack of the capacitor stack array 550 may contain a capacitor having a different capacitance value (capacitor value). For example, the first capacitor 404-1 may have a different capacitance value, package type, and/or package size than the second capacitor 404-2. Each capacitor stack in the array of capacitor stacks 550 may comprise a substantially similar configuration, e.g., the same configuration of top and bottom capacitor values, or each capacitor stack may comprise a different configuration depending on the desired application.

Each capacitor stack of the capacitor stack array 550 may form an independent bypass circuit, for example, with reference to fig. 3. Alternatively, or in addition, two or more capacitor stacks may collectively provide a bypass circuit. Thus, each capacitor stack may be used alone or in combination with other capacitor stacks to provide one or more bypass circuits. Each capacitor stack in the array of capacitor stacks 550 may be coupled to a respective input/electrode of the IC by a wire bond, such as shown. Note that wire bonds 552 are electrically coupled to respective shelves (shelves) provided by each capacitor stack of the capacitor stack array 550.

In one embodiment, the capacitor stack array 550 may thus be utilized to allow N number of electrodes/inputs of the IC 502 to have filtering to ensure nominal performance, e.g., clean/stable dc bias. Furthermore, each capacitor stack of the capacitor stack array 550 advantageously utilizes vertical stacking, e.g., capacitors stacked on top of each other, rather than mounting each individual capacitor horizontally to the same surface of the PCB/substrate (see fig. 1) to reduce the overall footprint. The reduced footprint thereby allows each capacitor stack to be mounted close to the desired component (e.g., IC). Thus, at least a first common level 560-1 may extend through each first capacitance (or top capacitance) C1 of each capacitance stack of the array of capacitor stacks 550, and at least a second common level 560-2 extends through each second capacitance (or base capacitance) C2 of each capacitance stack of the array of capacitor stacks 550.

The capacitor stack array 550 allows each individual capacitor stack to be placed relatively close to the associated electrode/input of the IC 502. In one embodiment, the capacitor stack array 550 allows up to 4, 8, or preferably 10 or more electrodes/inputs of the IC 502 to be electrically coupled to associated capacitor stacks of the capacitor stack array 550. Further, each capacitor stack of the capacitor stack array 550 may be coupled to the IC by a wire bond 552 implemented as a plurality of wire bonds of substantially equal length. By contrast, existing methods of surface mounting each capacitor require a relatively large footprint on the submount/PCB to accommodate the capacitor. For space-constrained applications, such as in the context of TOSA circuitry, this significantly complicates TOSA design and may result in relatively long wire bonds and/or completely limit or eliminate filter capacitors.

Figure 6 illustrates a capacitor stack 600 according to another embodiment of the invention. The capacitor stack 600 is shown in a highly simplified form for ease of description and clarity. The configuration of the capacitor stack 600 may be substantially similar to the configuration of the capacitor stack 400 discussed above and, for the sake of brevity, the description is not repeated.

As shown, the capacitor stack 600 includes a first capacitor 604-1, a second capacitor 604-2, a third capacitor 604-3, a ground plane interconnect 610, and a ground plane 606. In the embodiment of fig. 6, the ground plane interconnect 610 allows the mounting of at least three capacitors. A base/bottom capacitor (e.g., capacitor 604-3) is provided for the first and second capacitors 604-1, 604-2 to the ground plane 606, wherein the ground plane interconnect 610 is electrically coupled to the terminals of the first and second capacitors 604-1, 604-2. As further shown, shelf/shoulders 616 provide a common terminal for each capacitor. As described above, shelf 616 is electrically coupled to first capacitor 604-1 by wire bonding and to second capacitor 604-2 by virtue of the same terminal-to-terminal mounting. The shelves 616 may be further coupled to VCC terminals (not shown) by wire bonds or other suitable interconnects.

Fig. 7 shows a capacitor stack 700 according to a further embodiment of the invention. As shown, the capacitor stack 700 includes a first capacitor 704-1, a second capacitor 704-2, a third capacitor 704-3, a fourth capacitor 704-4, a ground plane 706, and a ground plane interconnect 710 (also referred to herein as a common ground plane interconnect). The embodiment of fig. 7 shows a quad-stack in which two capacitor stack pairs are arranged end-to-end and share a ground plane interconnect 710 as a common ground plane interconnect.

Fig. 8 illustrates an embodiment of a TO can (TO can) laser assembly 800 with one or more capacitor stacks for bypass/filtering, according TO an embodiment. As shown, the TO can laser assembly includes a base 802, a top cap 804, pins 806, a sub-mount 808, a laser configuration 810, and at least one capacitor stack 812. The at least one capacitor stack 812 may include two or more capacitors TO provide filtering and TO decouple/bypass unwanted high and/or low frequency noise from the drive signal (e.g., RF drive signal) or any other signal used during operation of the TO can laser assembly 800, as variously discussed herein. The resulting filtered drive signal may then be used to modulate the laser diodes of the laser arrangement 810.

The capacitor stack with the present invention reduces or otherwise eliminates the alternatives, design complexity and performance tradeoffs associated with horizontally mounted filter/bypass capacitors. The capacitor stack reduces the distance between the capacitor and the associated components, such as the distance between the capacitor for high frequency noise filtering and the electrodes/terminals of the IC, and reduces the number of electrical interconnections, such as wire bonds. Reducing the number of overall wire bonds and wire bond lengths advantageously reduces manufacturing complexity, minimizes or otherwise avoids increasing resistance/impedance (and time of flight (TOF) delays), and generally increases throughput by having fewer fragile and vulnerable wire bonds.

Fig. 9 shows a block diagram of a multi-channel optical transceiver module 900 according to an embodiment of the invention. The multi-channel optical transceiver module 900 includes a housing 901, a substrate 902, a Transmitter Optical Subassembly (TOSA) configuration 904, and a Receiver Optical Subassembly (ROSA) configuration 906. The housing 901 may conform to various housing standards, preferably to the SFF-8661 requirements.

Substrate 902 includes Transmit (TX) connection circuitry (TX circuitry for short) 908-1 and Receive (RX) connection circuitry (RX circuitry for short) 908-2. The TX connection circuit 908-1 and the RX connection circuit 908-2 include a plurality of leads printed/disposed on the first end of the substrate 902 and may also include additional circuitry such as power converters, rectifiers, and the like. A first end of the substrate 902 extends at least partially from the housing 901 to allow external circuitry to electrically couple with the TX connection 908-1 and the RX connection 908-2.

The substrate 902 further includes TX traces 910 having a first end connected to the TX connection 908-1 and a second end electrically coupled to the TOSA arrangement 904. The TOSA configuration can include a sealed housing defining a cavity for receiving and securely housing the plurality of laser configurations 915. Alternatively, multiple laser configurations may be implemented as a housing for receiving and coupling TO a TO can laser assembly, such as the TO can laser assembly of fig. 8. Each laser configuration of the plurality of laser configurations 915 includes passive and/or active components, such as a laser diode, a monitor photodiode, a Laser Diode Driver (LDD) chip, an optical isolator, and/or a focusing lens. In addition, each of the laser arrangements 915 may include one or more various capacitor stacks as disclosed herein. One or more capacitor stacks may be used to bypass/filter unwanted high and/or low frequency noise. To this end, each LDD may include one or more capacitor stacks electrically coupled at one or more input/electrodes of the LDD for filtering. In addition, other Integrated Circuits (ICs) and supporting circuitry for multiple laser assemblies may utilize the disclosed capacitor stack for filtering or other transceiver operations.

An optical multiplexer (multiplexer)914 includes an input port that receives the channel wavelengths from the TOSA configuration 904 and an output port that outputs a multiplexed optical signal 917 having each of the received channel wavelengths. The multiplexed optical signal 917 is transmitted on the external TX fiber through a fiber jack (receptacle)916-1 (also known as an optical coupler-reservoir). The optical multiplexer 914 comprises an Arrayed Waveguide Grating (AWG), although the invention is not intended to be limited in this respect. Furthermore, the optical multiplexer 914 need not be contained within the housing 901, depending on the desired configuration.

In operation, the TX connection 908-1 provides drive signals (TX _ D1 through TX _ D4) to drive the TOSA configuration 904 (e.g., from external drive circuitry). The TOSA arrangement 904 then receives the driving signals (TX _ D1-TX _ D4) (e.g., via TX traces 910) and modulates the plurality of laser arrangements 915 to convert and output four different output optical signals (λ 1- λ 4). The optical multiplexer 914 then combines the output optical signals into a multiplexed optical signal 917. The multiplexed optical signal 917 is then transmitted onto a Transmit (TX) fiber 919 through fiber jack 916-1.

The RX connection circuit 908-2 includes a plurality of traces to electrically couple the multi-channel ROSA configuration 906 to external receiver circuitry. The multi-channel ROSA configuration includes an optical demultiplexer (demultiplexer)920, a Photodiode (PD) array 922 (which may also be referred to herein as a PD array), and a transimpedance amplifier (TIA) 924.

The optical demultiplexer 920 comprises, for example, an Arrayed Waveguide Grating (AWG) or other suitable device. An input of the optical demultiplexer 920 is aligned with the demultiplexing plane to receive the RX optical signal having a plurality of channel wavelengths. An output of the optical demultiplexer 920 outputs the separated channel wavelengths onto corresponding photodetectors (photodetectors) of the PD array 922. The PD array 922 outputs an electrical signal proportional to the detected wavelength. The transimpedance amplifier 924 includes circuitry that amplifies and filters the signal from the PD array 922.

Thus, in operation, an optical signal having multiple channel wavelengths (λ 1.. λ 4) is received by the multi-channel ROSA configuration 906 via the Receive (RX) fiber 921 and the fiber receptacle 916-2. The optical demultiplexer 920 aligns the received optical signal and outputs each separated channel wavelength onto an associated photodiode of the PD array 922. The transimpedance amplifier 924 receives electrical signals from the PD array 922 to provide receive signals (RX _ D1-RX _ D4). The external receive circuitry receives receive signals (RX _ D1 through RX _ D4) through traces and RX connection circuitry 908-2.

Although the present invention has been described with reference to the above embodiments, it is not intended to limit the invention. All changes, substitutions and alterations that come within the spirit and scope of this invention are desired to be protected.

Description of the symbols

C1 first capacitor

C2 second capacitor

CN Nth capacitor

IC integrated circuit

300 bypass circuit

302 VCC terminal

304 capacitor stack

304-1 first capacitor

304-2 second capacitor

304-Nth capacitor

306 ground plane

308 integrated circuit

310-1 first electrode

310-2 second electrode

400 capacitor stack

402 VCC terminal

404-1 first capacitor

404-2 second capacitor

406 ground plane

408 Integrated Circuit (IC)

410 ground plane interconnect

410-1 first conductive segment

410-2 second conductive segment

411-1 first terminal

411-2 second terminal

412-1 first terminal

412-2 second terminal

414-1 first wire bond

414-2 second wire bond

416 shoulder region

418 electrode

500 capacitor stack arrangement

502 Integrated Circuit (IC)

550 capacitor stack array

552 wire bond

560-1 first common horizontal plane

560-2 second common horizontal plane

600 capacitor stack

604-1 first capacitor

604-2 second capacitor

604-3 third capacitor

606 ground plane

610 ground plane interconnect

616 shelf

700 capacitor stack

704-1 first capacitor

704-2 second capacitor

704-3 third capacitor

704-4 fourth capacitor

706 ground plane

710 ground plane interconnect

800 TO can laser assembly

802 base

804 upper cover

806 pin

808 son base

810 laser arrangement

812 capacitor stack

900 multi-channel optical transceiver module

901 outer casing

902 substrate

904 TOSA arrangement

906 multichannel ROSA arrangement

908-1 Transmit (TX) circuit

908-2 Receive (RX) circuit

910 TX trace

914 optical multiplexer

915 laser arrangement

916-1 optical fiber jack

916-2 optical fiber jack

917 multiplexing optical signals

919 Transmit (TX) fiber

920 optical demultiplexer

921 Receive (RX) fiber

922 Photodiode (PD) array

924 transimpedance amplifier