阅读说明：本技术 一种闪存结构、擦除方法、装置和电子设备 (Flash memory structure, erasing method and device and electronic equipment ) 是由 陈纬荣 黄建 冯鹏亮 陈慧 于 2021-06-30 设计创作，主要内容包括：本发明公开了一种闪存结构、擦除方法、装置和电子设备,本发明提供的一种闪存结构,该闪存结构在相邻两个存储块共用P型阱区的接触孔,弃用了深N型接触孔,缩短了绝缘距离,减小了芯片的面积。本发明还提供的一种闪存擦除方法,通过对需要擦除的存储块对应的字线施加的电压为-10V,对不需要擦除的存储块对应的字线施加的电压和P型阱区一致,使得不需要擦除的存储块对应的字线对P型阱区不存在寄生电容,进而减少总电容的大小,提高电压的爬升速度,提高了擦除速度和效率。(The invention discloses a flash memory structure, an erasing method, an erasing device and electronic equipment. According to the flash memory erasing method provided by the invention, the voltage applied to the word line corresponding to the memory block which needs to be erased is-10V, and the voltage applied to the word line corresponding to the memory block which does not need to be erased is consistent with the voltage applied to the P-type well region, so that the word line corresponding to the memory block which does not need to be erased does not have parasitic capacitance to the P-type well region, the size of the total capacitance is reduced, the climbing speed of the voltage is increased, and the erasing speed and the erasing efficiency are improved.)

1. A flash memory structure, comprising:

the semiconductor device comprises a substrate (1), wherein a deep N-type well region (2) and a P-type well region (3) are formed on the substrate (1);

the storage unit array (4) is formed on a P-type well region (3) on the substrate (1), the P-type well region (3) is provided with a contact hole, the storage unit array (4) is divided into a plurality of connected storage blocks, and the contact hole of the P-type well region (3) is shared between every two adjacent storage blocks;

and word lines (5) connecting the memory cells in the memory block.

2. A flash memory structure according to claim 1, characterized in that the substrate (1) is a silicon P-type substrate.

3. A flash memory structure according to claim 1, wherein the contact holes of two adjacent P-well regions (3) are equidistant from each other.

4. A flash memory erasing method is used for erasing a storage block in a flash memory, and the structure of the flash memory comprises the following steps:

the semiconductor device comprises a substrate (1), wherein a deep N-type well region (2) and a P-type well region (3) are formed on the substrate (1);

the storage unit array (4) is formed on a P-type well region (3) on the substrate (1), the P-type well region (3) is provided with a contact hole, the storage unit array (4) is divided into a plurality of connected storage blocks, and the contact hole of the P-type well region (3) is shared between every two adjacent storage blocks;

word lines (5) connecting the memory cells on the memory block;

the flash memory erasing method comprises the following steps:

the voltage applied to the word line (5) corresponding to the memory block needing to be erased is-8 to-10V, and the voltage applied to the word line (5) corresponding to the memory block needing not to be erased is consistent with the P-type well region (3).

5. A flash memory erase method according to claim 4, wherein the voltage applied to the substrate (1) is 0V, the voltage applied to the deep N-well region (2) is 10V, and the voltage applied to the P-well region (3) is 10V.

6. A flash memory erasing method according to claim 4, characterized in that the voltage applied to the word line (5) corresponding to the memory block to be erased is-10V.

7. An erasing method of a flash memory according to claim 5, characterized in that the voltage applied to the word line (5) corresponding to the memory block which does not need to be erased is 10V.

8. An erasing apparatus for a flash memory, configured to erase a memory block in the flash memory, the structure of the flash memory comprising:

the semiconductor device comprises a substrate (1), wherein a deep N-type well region (2) and a P-type well region (3) are formed on the substrate (1);

the storage unit array (4) is formed on a P-type well region (3) on the substrate (1), the P-type well region (3) is provided with a contact hole, the storage unit array (4) is divided into a plurality of connected storage blocks, and the contact hole of the P-type well region (3) is shared between every two adjacent storage blocks;

word lines (5) connecting the memory cells on the memory block;

the flash memory erasing apparatus includes:

the first voltage module is used for applying-10V voltage to a word line corresponding to a memory block needing to be erased;

and the second voltage module is used for applying voltage to the word line corresponding to the memory block which does not need to be erased, and the voltage is consistent with the P-type well region.

9. An electronic device, characterized in that it comprises a processor (61) and a memory (62), a computer program being stored in the memory (62), the processor (61) being adapted to perform the method according to any of claims 4-7 by calling the computer program stored in the memory (62).

Technical Field

The invention belongs to the technical field of memories, and particularly relates to a flash memory structure, an erasing method, an erasing device and electronic equipment.

Background

In the prior art flash memory structure shown in fig. 1, PSUB is a P-type substrate, TPW (Triple P-Well) is a P-type Well region, DNW (Deep N-Well) is a Deep N-Well region, TPW tap is a contact hole of the P-type Well region, and has a width of L1, DNW tap is a contact hole of the Deep N-Well region, and has a width of L2, a distance from the TPW tap to the DNW tap is L3, Diode is a parasitic Diode, and Cap is a parasitic capacitance.

During the NOR flash erase operation, the P-well needs to be added to 10V and the word line needs to be added to-10V, because the area to be erased in practical application is much smaller than the number of the whole NOR flash memory cells, the memory cell array of the practical NOR flash memory is divided into a plurality of unconnected memory blocks as shown in fig. 1.

When a user issues an erasing instruction, the inside of the chip only erases all the memory cells in one memory block or all the memory cells on a part of word lines. Applying positive high voltage (such as 10V) to a P-type well region of a memory block to be erased, applying negative high voltage (such as-10V) to a word line, and setting the voltage difference between the P-type well region and the word line to be 20V so as to achieve the purpose of erasing; the voltages of other memory blocks that do not need to be erased are biased as: the voltage difference between the P-type well region and the word line is 0V, and the P-type well region and the word line cannot be erased.

However, this has the following significant disadvantages: each memory block needs an independent P-type well region, such as P-type well region 0 and P-type well region 1 in fig. one, because each P-type well region needs to be biased to different voltages during an erase operation, the P-type well region to be erased needs to be biased to 10V, and the P-type well region not to be erased needs to be biased to 0V, so different contact holes and voltage driving circuits are needed for the P-type well regions with different voltages.

As shown in fig. 1, there will be a design rule-determined isolation distance between memory blocks:

L＝2L1+2L3+L2

this isolation distance increases as the number of memory blocks increases, greatly consuming chip area. Assuming N memory blocks, there will be N-1 such distances, and thus the distance consumed is:

total of L ═ N-1 ═ L

The deep N-well region contains a large number of free electrons, while the P-well region contains a large number of free holes. A PN junction formed by the deep N-type well region and the P-type well region forms a parasitic diode, and the formation of the PN junction can cause a depletion region to appear on an interface between the P-type well region and the deep N-type well region, wherein the depletion region is a region with depleted free electrons and holes. The depletion regions at two sides of the PN junction are respectively provided with positive charges and negative charges to form an electric field, and the electric field applies external force to electrons or holes passing through the junction to prevent more electrons and holes from passing through the diode, so that the charge distribution in the diode is finally kept in dynamic balance. This is the cause of the parasitic capacitance.

If the whole NOR flash has N memory blocks, the total capacitance to be raised by the positive high voltage applied to the P-well region when erasing one memory block is three types:

1. in the erasing operation of the memory block, the voltage applied to all word lines is-10V, the voltage applied to the P-type well region is 10V, and the parasitic capacitance generated by all word lines to the P-type well region is Cap (WL-TPW);

2. because parasitic diodes of the P-type well region and the deep N-type well region are conducted in the forward direction and have the same potential in the erasing operation, no capacitance exists, the voltage applied to the deep N-type well region is 10V, the voltage applied to the substrate is 0V, and the capacitance generated by the deep N-type well region to a reverse bias parasitic diode of the substrate is Cap (DNW-PSUB);

3. the voltage applied to the deep N-type well region is 10V, the voltage applied to the P-type well region which is not subjected to the erasing operation is OV, and the capacitance generated by the P-type well region to the reverse bias parasitic diode of the deep N-type well region is Cap (TPW-DNW).

The total capacitance of the positive high voltage applied by the P-type well region is the same:

total of C ═ Cap (WL-TPW) + Cap (DNW-PSUB) + N ═ Cap (TPW-DNW)

It can be seen that the positive high voltage on the P-well region is generated by the charge pump, and the larger the total capacitance it is to lift, the slower the positive high voltage of the P-well region climbs, thereby affecting the erase speed.

Accordingly, the prior art is in need of improvement and development.

Disclosure of Invention

Embodiments of the present invention provide a flash memory structure, an erasing method, an erasing apparatus, and an electronic device, which can reduce the area of a chip, reduce the total capacitance, increase the climbing speed of a voltage, and increase the erasing speed and efficiency.

In a first aspect, a flash memory structure provided in an embodiment of the present invention includes:

the semiconductor device comprises a substrate, wherein a P-type well region and a deep N-type well region are formed on the substrate;

the storage unit array is formed on a P-type well region on the substrate, the P-type well region is provided with a contact hole, the storage unit array is divided into a plurality of connected storage blocks, and the contact hole of the P-type well region is shared between every two adjacent storage blocks;

and word lines connected to the memory cells in the memory block.

Optionally, the substrate is a silicon wafer P-type substrate.

Optionally, the distances between two adjacent P-type well region contact holes are equal.

Therefore, according to the flash memory structure provided by the invention, the two adjacent memory blocks share the P-type well region contact hole, the deep N-type well region contact hole is omitted, the insulation distance is shortened, and the area of a chip is reduced.

In a second aspect, a flash memory erasing method provided in an embodiment of the present invention is for erasing a memory block in a flash memory, where the flash memory includes a substrate, a deep N-well region and a P-well region are formed on the substrate, and a memory cell array is formed on the P-well region on the substrate, the P-well region has a contact hole, the memory cell array is divided into a plurality of connected memory blocks, and two adjacent memory blocks share the P-well region contact hole, and a word line is connected to a memory cell on the memory block, and the method includes the following steps:

the voltage applied to the word line corresponding to the memory block needing to be erased is-8 to-10V;

and simultaneously, the voltage applied to the word line corresponding to the memory block which does not need to be erased is consistent with the P-type well region.

Alternatively, the voltage applied to the substrate is 0V, the voltage applied to the deep N-type well region is 10V, and the voltage applied to the P-type well region is 10V.

Optionally, the voltage applied to the word line corresponding to the memory block to be erased is-10V.

Alternatively, the voltage applied to the word line corresponding to the memory block that does not need to be erased is 10V.

From the above, according to the flash memory erasing method provided by the invention, the voltage applied to the word line corresponding to the memory block needing to be erased is-10V, and the voltage applied to the word line corresponding to the memory block not needing to be erased is consistent with the P-type well region, so that the word line corresponding to the memory block not needing to be erased has no parasitic capacitance to the P-type well region, the total capacitance is reduced, the climbing speed of the voltage is increased, and the erasing speed and the erasing efficiency are improved.

In a third aspect, an embodiment of the present invention provides a flash memory erasing apparatus, including:

the first voltage module is used for applying-10V voltage to a word line corresponding to a memory block needing to be erased;

and the second voltage module is used for applying a voltage to a word line corresponding to the memory block which does not need to be erased, and the voltage is consistent with the P-type well region.

In a fourth aspect, an electronic device according to an embodiment of the present invention includes a processor and a memory, where the memory stores a computer program, and the processor is configured to execute any one of the methods described above by calling the computer program stored in the memory.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

FIG. 1 is a diagram of a prior art flash memory structure.

FIG. 2 is a diagram of a flash memory structure according to the present invention.

Fig. 3 is a schematic view of the electronic device of the present invention.

Description of reference numerals: 1. a substrate; 2. a deep N-type well region; 3. a P-type well region; 4. an array of memory cells; 41. a first memory block; 42. a second memory block; 5. a word line; 6. an electronic device; 61. a processor; 62. a memory.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present invention, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

As shown in fig. 2, the present invention provides a flash memory structure, comprising:

the structure comprises a substrate 1, wherein the substrate 1 is a silicon wafer P-type substrate, and a deep N-type well region 2 and a P-type well region 3 are formed on the substrate 1;

the memory cell array 4 is formed on a P-type well region 3 on the substrate 1, the P-type well region 3 is provided with a contact hole, the memory cell array 4 is divided into a plurality of connected memory blocks, and the contact hole of the P-type well region 3 is shared between two adjacent memory blocks;

word lines 5 connect the memory cells in the memory block.

The flash memory structure of the present invention shares the P-well regions of all NOR flash memory cells, and only one contact hole of the P-well region is left between adjacent memory blocks (the first memory block 41 and the second memory block 42 separated by the dotted line in fig. 2), so that if there are N memory blocks, the insulation distance of the design rule is reduced to:

l total ═ (N-1) × L1

The reduced insulation distance is: (N-1) (L1+2L3+ L2)

Therefore, the area of the chip is greatly reduced on the premise that other specifications are not changed.

In order to meet the specification design of a memory and reduce the complexity of the design and application of the flash memory, the distances between the contact holes of two adjacent P-type well regions are equal. The design can also ensure the stable charging and discharging of the parasitic capacitor.

Based on the flash memory structure of the invention, when one memory block is erased, the total capacitance to be raised by the positive high voltage applied to the P-type well region is three types as follows:

1. the voltage applied to all the word lines is-10V, the voltage applied to the P-type well region is 10V, and the parasitic capacitance generated by all the word lines to the P-type well region is Cap (WL-TPW);

2. because parasitic diodes of the P-type well region and the DNW are conducted in the forward direction and have the same potential in the erasing operation, no capacitance exists, the voltage applied to the deep N-type well region is 10V, the voltage applied to the substrate is 0V, and the capacitance generated by the deep N-type well region to a reverse bias parasitic diode of the substrate is Cap (DNW-PSUB);

3. the P-type well region and the word line which are not subjected to the erasing operation are supplied with power by the same voltage source, and no capacitance exists between the P-type well region and the word line.

The total capacitance of the positive high voltage applied by the P-type well region is shared:

c total ═ Cap (WL-TPW) + Cap (DNW-PSUB)

The reduced total capacitance compared to the prior art flash memory structure is: n Cap (TPW-DNW)

In conclusion, the positive high voltage climbing speed is faster after the capacitance is reduced, which brings great speed improvement.

The erasing method according to the structure of the flash memory comprises the following steps: the voltage applied to the word line 5 corresponding to the memory block that needs to be erased is-10V, and the voltage applied to the word line 5 corresponding to the memory block that does not need to be erased is 10V. The voltage applied to substrate 1 is 0V, the voltage applied to deep N-type well region 2 is 10V, and the voltage applied to P-type well region 3 is 10V.

In the embodiment, the voltage applied to the word line 5 corresponding to the block to be erased is-10V, the voltage applied to the P-type well region 3 is 10V, and the voltage difference is 20V, so that the erasing purpose is achieved; meanwhile, the voltage applied to the word line 5 corresponding to the memory block which does not need to be erased is 10V, the voltage applied to the P-type well region is 10V, and the voltage difference is 0V, so that the memory block cannot be erased.

The present invention also provides a flash memory erasing apparatus, comprising:

the first voltage module is used for applying-10V voltage to the word line 5 corresponding to the memory block needing to be erased;

and the second voltage module is used for applying a voltage to the word line 5 corresponding to the memory block which does not need to be erased, and the voltage is consistent with the P-type well region 3.

As shown in fig. 3, the present invention also provides an electronic device 6. The electronic device 6 comprises a processor 61 and a memory 62. The processor 61 is electrically connected to the memory 62. The processor 61 is a control center of the electronic device 6, connects various parts of the entire electronic device 6 by various interfaces and lines, and performs various functions of the electronic device 6 and processes data by running or calling a computer program stored in the memory 62 and calling data stored in the memory 62, thereby performing overall monitoring of the electronic device 6.

In this embodiment, the processor 61 in the electronic device 6 loads instructions corresponding to one or more computer program processes into the memory 62 according to the following steps, and the processor 61 runs the computer program stored in the memory 62, so as to implement various functions: the voltage applied to the word line 5 corresponding to the memory block that needs to be erased is-10V, and the voltage applied to the word line 5 corresponding to the memory block that does not need to be erased is 10V.

The memory 62 may be used to store computer programs and data. The memory 62 stores computer programs containing instructions executable in the processor 61. The computer program may constitute various functional modules. The processor 61 executes various functional applications and data processing by calling a computer program stored in the memory 62.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present invention, and is not intended to limit the scope of the present invention, and it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.