阅读说明：本技术 一种增强型与耗尽型hemt器件的集成芯片及制备方法 (Integrated chip of enhanced and depletion HEMT device and preparation method ) 是由 刘成 田野 何俊蕾 赵杰 郭德霄 叶念慈 于 2020-12-22 设计创作，主要内容包括：本发明涉及一种增强型与耗尽型HEMT器件的集成芯片及制备方法,利用介质层的应力对器件阈值电压的影响与器件栅极线宽的相关性,对P型氮化物栅极层下方的势垒层应力进行调控,改变其极化电场强度,最终实现P型氮化物栅增强型和耗尽型HEMT器件的单片集成。在制备耗尽型半导体器件时,无需刻蚀栅金属下方的P型氮化物层,栅极金属与半导体接触界面不存在刻蚀损伤,可有效降低器件的栅漏电,提升器件开关电流比,降低功耗；本发明制备的增强型半导体器件,与常规P型氮化物栅增强型HEMT相比,P型氮化物栅极层下方的势垒层极化电场强度减弱,异质结界面极化电荷面密度减少,增强型半导体器件的阈值电压得到进一步提升。(The invention relates to an integrated chip of an enhancement type HEMT device and a preparation method thereof, which utilizes the correlation between the influence of the stress of a dielectric layer on the threshold voltage of the device and the line width of a grid electrode of the device to regulate and control the stress of a barrier layer below a P-type nitride grid layer, changes the polarization electric field intensity of the barrier layer, and finally realizes the monolithic integration of the enhancement type HEMT device and the depletion type HEMT device of the P-type nitride grid. When the depletion type semiconductor device is prepared, a P-type nitride layer below the gate metal does not need to be etched, and the contact interface between the gate metal and the semiconductor has no etching damage, so that the gate leakage of the device can be effectively reduced, the on-off current ratio of the device is improved, and the power consumption is reduced; compared with the conventional P-type nitride gate enhanced HEMT, the enhanced semiconductor device prepared by the invention has the advantages that the polarization electric field intensity of the barrier layer below the P-type nitride gate layer is weakened, the heterojunction interface polarization charge surface density is reduced, and the threshold voltage of the enhanced semiconductor device is further improved.)

1. An integrated chip of an enhancement mode HEMT device and a depletion mode HEMT device is characterized by comprising a substrate, a buffer layer, a channel layer, a barrier layer, a first P-type nitride gate layer and a second P-type nitride gate layer, wherein the first P-type nitride gate layer and the second P-type nitride gate layer are arranged at intervals; the grid line width of the first P-type nitride grid layer is larger than that of the second P-type nitride grid layer; a first gate metal is arranged on the first P-type nitride gate layer, and a second gate metal is arranged on the second P-type nitride gate layer; the first P-type nitride grid layer and a certain range of area around the first P-type nitride grid layer are defined as an enhancement area, and the second P-type nitride grid layer and a certain range of area around the second P-type nitride grid layer are defined as a depletion area; the enhancement region and the depletion region cover the tensile stress dielectric layer, the enhancement region is provided with a first source metal and a first drain metal to form an enhancement type semiconductor device, and the depletion region is provided with a second source metal and a second drain metal to form a depletion type semiconductor device.

2. The integrated chip of the enhancement mode and depletion mode HEMT device of claim 1, wherein the first P-type nitride gate layer has a gate line width of 1 to 2 μm and the second P-type nitride gate layer has a gate line width of 0.1 to 0.6 μm; the threshold voltage of the enhancement type semiconductor device is 0.5V-2.5V, and the threshold voltage of the depletion type semiconductor device is-0.5V-1V.

3. The integrated chip of the enhancement mode and depletion mode HEMT device according to claim 1 or 2, wherein the enhancement region and the depletion region cover a passivation layer, and a tensile stress dielectric layer covers the passivation layer; the stress value of the passivation layer is lower than that of the tensile stress dielectric layer.

4. The integrated chip of the enhancement mode and depletion mode HEMT device according to claim 3, wherein the stress value of the tensile stress dielectric layer is 200MPa to 3GPa, and the stress value of the passivation layer is-250 MPa to 150 MPa; the thickness of the tensile stress dielectric layer is 30nm-1000nm, and the thickness of the passivation layer is less than 20 nm.

5. The integrated chip of the enhancement mode and depletion mode HEMT device as claimed in claim 1, wherein the stress dielectric of the tensile stress dielectric layer is one or more of silicon nitride, silicon oxide or silicon oxynitride, and the passivation layer is one or more of silicon nitride, silicon oxide, aluminum nitride or aluminum oxide.

6. A preparation method of an integrated chip of an enhancement mode HEMT device and a depletion mode HEMT device is characterized by comprising the following steps:

1) preparing a nitride epitaxial structure on a substrate, wherein the nitride epitaxial structure comprises a buffer layer, a channel layer, a barrier layer and a P-type nitride layer; etching the P-type nitride layer of the nitride epitaxial structure to form a first P-type nitride gate layer and a second P-type nitride gate layer; preparing a first gate metal on the first P-type nitride gate layer and a first gate metal on the second P-type nitride gate layer; the first P-type nitride grid layer and a certain range of area around the first P-type nitride grid layer are defined as an enhancement area, and the second P-type nitride grid layer and a certain range of area around the second P-type nitride grid layer are defined as a depletion area; the grid line width of the first P-type nitride grid layer is larger than that of the second P-type nitride grid layer;

2) depositing a tensile stress medium layer on the surface of the nitride epitaxial structure, wherein the tensile stress medium layer covers the enhancement region and the depletion region;

3) preparing a first source electrode metal and a first drain electrode metal in the enhancement region to form an enhancement type semiconductor device; and preparing a second source metal and a second drain metal in the depletion region to form the depletion type semiconductor device.

7. The method of claim 6, wherein the first P-type nitride gate layer has a gate line width of 1 μm to 2 μm, and the second P-type nitride gate layer has a gate line width of 0.1 μm to 0.6 μm.

8. The method for preparing the integrated chip of the enhancement mode HEMT device or the depletion mode HEMT device according to the claim 6 or 7, wherein between the step 1) and the step 2), the method further comprises the following steps:

depositing a stress medium on the surface of the nitride epitaxial structure to form a passivation layer, wherein the passivation layer covers the enhancement region and the depletion region; the stress value of the passivation layer is lower than that of the tensile stress dielectric layer.

9. The method for preparing an integrated chip of an enhancement mode and depletion mode HEMT device according to claim 8, wherein the thickness of the tensile stress dielectric layer is 30nm-1000nm, and the stress value is 200 MPa-3 GPa; the thickness of the passivation layer is less than 20nm, and the stress value is-250 MPa-150 MPa.

10. The method for manufacturing an integrated chip of an enhancement mode and depletion mode HEMT device according to claim 8, wherein the stress medium of the tensile stress medium layer is one or a combination of silicon nitride, silicon oxide or silicon oxynitride, and the passivation layer is one or a combination of silicon nitride, silicon oxide, aluminum nitride or aluminum oxide.

Technical Field

The invention relates to the technical field of semiconductors, in particular to an integrated chip of an enhanced HEMT device and a depletion HEMT device and a preparation method of the integrated chip of the enhanced HEMT device and the depletion HEMT device.

Background

The silicon-based GaN HEMT has a wide development prospect in the field of power switches due to the excellent characteristics of the silicon-based GaN HEMT, wherein the commercial power GaN HEMT is mainly a P-type nitride gate enhanced HEMT device. However, the P-type nitride gate enhancement type HEMT device has the problems of low threshold voltage, small gate swing and the like, and in order to fully exert the advantages of GaN materials, a gate drive circuit and a power GaN HEMT need to be monolithically integrated.

In the prior art, a common method for realizing monolithic integration of an enhancement type and depletion type semiconductor device based on a p-GaN/AlGaN/GaN epitaxial structure is as follows: and selectively etching or completely etching the surface P-type nitride layer by using a dry etching process to obtain the enhancement type or depletion type GaN HEMT device.

However, in the above method, when the depletion-mode GaN HEMT device is prepared by completely etching the P-type nitride layer, dry etching damage exists on the surface of the AlGaN layer below the gate region, and the damage causes a large number of defects on the surface of the AlGaN layer, which results in uneven distribution of threshold voltage of the device and large gate leakage current. Meanwhile, the enhancement type HEMT device prepared by the method for selectively etching the P-type nitride layer has lower threshold voltage, and has the risk of mistaken opening in practical circuit application, thereby influencing the circuit safety.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides an integrated chip of an enhanced HEMT device and a preparation method thereof, wherein the monolithic integration of the enhanced HEMT device and a depletion HEMT device of the depletion semiconductor device is realized by utilizing the correlation between the influence of the stress of a dielectric layer on the threshold voltage of the device and the line width of a grid electrode of the device, the contact interface of grid metal and a semiconductor has no etching damage, the grid leakage of the device can be effectively reduced, the on-off current ratio of the device is improved, and the power consumption is reduced; and simultaneously, the threshold voltage of the enhancement type semiconductor device is further improved.

The technical scheme of the invention is as follows:

an integrated chip of an enhancement mode HEMT device and a depletion mode HEMT device comprises a substrate, a buffer layer, a channel layer, a barrier layer, a first P-type nitride gate layer and a second P-type nitride gate layer, wherein the first P-type nitride gate layer and the second P-type nitride gate layer are arranged at intervals; the grid line width of the first P-type nitride grid layer is larger than that of the second P-type nitride grid layer; a first gate metal is arranged on the first P-type nitride gate layer, and a second gate metal is arranged on the second P-type nitride gate layer; the first P-type nitride grid layer and a certain range of area around the first P-type nitride grid layer are defined as an enhancement area, and the second P-type nitride grid layer and a certain range of area around the second P-type nitride grid layer are defined as a depletion area; the enhancement region and the depletion region cover the tensile stress dielectric layer, the enhancement region is provided with a first source metal and a first drain metal to form an enhancement type semiconductor device, and the depletion region is provided with a second source metal and a second drain metal to form a depletion type semiconductor device.

Preferably, the gate line width of the first P-type nitride gate layer is 1 μm to 2 μm, and the gate line width of the second P-type nitride gate layer is 0.1 μm to 0.6 μm; the threshold voltage of the enhancement type semiconductor device is 0.5V-2.5V, and the threshold voltage of the depletion type semiconductor device is-0.5V-1V.

Preferably, the enhancement region and the depletion region cover the passivation layer, and the tensile stress dielectric layer covers the passivation layer; the stress value of the passivation layer is lower than that of the tensile stress dielectric layer.

Preferably, the stress value of the tensile stress dielectric layer is 200MPa to 3GPa, and the stress value of the passivation layer is-250 MPa to 150 MPa; the thickness of the tensile stress dielectric layer is 30nm-1000nm, and the thickness of the passivation layer is less than 20 nm.

Preferably, the stress medium of the tensile stress medium layer is one or a combination of more than one of silicon nitride, silicon oxide or silicon oxynitride, and the passivation layer is one or a combination of more than one of silicon nitride, silicon oxide, aluminum nitride or aluminum oxide.

A preparation method of an integrated chip of an enhancement mode HEMT device and a depletion mode HEMT device comprises the following steps:

1) preparing a nitride epitaxial structure on a substrate, wherein the nitride epitaxial structure comprises a buffer layer, a channel layer, a barrier layer and a P-type nitride layer; etching the P-type nitride layer of the nitride epitaxial structure to form a first P-type nitride gate layer and a second P-type nitride gate layer; preparing a first gate metal on the first P-type nitride gate layer and a first gate metal on the second P-type nitride gate layer; the first P-type nitride grid layer and a certain range of area around the first P-type nitride grid layer are defined as an enhancement area, and the second P-type nitride grid layer and a certain range of area around the second P-type nitride grid layer are defined as a depletion area; the grid line width of the first P-type nitride grid layer is larger than that of the second P-type nitride grid layer;

2) depositing a tensile stress medium layer on the surface of the nitride epitaxial structure, wherein the tensile stress medium layer covers the enhancement region and the depletion region;

3) preparing a first source electrode metal and a first drain electrode metal in the enhancement region to form an enhancement type semiconductor device; and preparing a second source metal and a second drain metal in the depletion region to form the depletion type semiconductor device.

Preferably, the first P-type nitride gate layer has a gate line width of 1 μm to 2 μm, and the second P-type nitride gate layer has a gate line width of 0.1 μm to 0.6 μm.

Preferably, between step 1) and step 2), the following steps are further included:

depositing a stress medium on the surface of the nitride epitaxial structure to form a passivation layer, wherein the passivation layer covers the enhancement region and the depletion region; the stress value of the passivation layer is lower than that of the tensile stress dielectric layer.

Preferably, the thickness of the tensile stress dielectric layer is 30nm-1000nm, and the stress value is 200 MPa-3 GPa; the thickness of the passivation layer is less than 20nm, and the stress value is-250 MPa-150 MPa.

Preferably, the stress medium of the tensile stress medium layer is one or a combination of more than one of silicon nitride, silicon oxide or silicon oxynitride, and the passivation layer is one or a combination of more than one of silicon nitride, silicon oxide, aluminum nitride or aluminum oxide.

The invention has the following beneficial effects:

according to the integrated chip of the enhancement type and depletion type HEMT device, the stress of the barrier layer below the P type nitride gate layer is regulated and controlled by utilizing the influence of the stress of the dielectric layer on the threshold voltage of the device and the correlation of the line width of the gate of the device, the polarization electric field intensity of the barrier layer is changed, and finally the monolithic integration of the enhancement type and depletion type HEMT device of the P type nitride gate is realized. The contact interface of the grid metal and the semiconductor has no etching damage, so that the grid leakage of the device can be effectively reduced, the on-off current ratio of the device is improved, and the power consumption is reduced; according to the enhanced semiconductor device, the polarization electric field intensity of the barrier layer below the P-type nitride gate layer is weakened, the density of the heterojunction interface polarization charge surface is reduced, and the threshold voltage of the enhanced semiconductor device is further improved.

The preparation method of the integrated chip of the enhancement mode and depletion mode HEMT device is used for preparing the integrated chip of the enhancement mode and depletion mode HEMT device, when the depletion mode semiconductor device is prepared, a P-type nitride layer below a grid metal does not need to be etched, the contact interface of the grid metal and a semiconductor does not have etching damage, the grid leakage of the device can be effectively reduced, the on-off current ratio of the device is improved, and the power consumption is reduced; compared with the conventional P-type nitride gate enhanced HEMT, the enhanced semiconductor device prepared by the invention has the advantages that the polarization electric field intensity of the barrier layer below the P-type nitride gate layer is weakened, the heterojunction interface polarization charge surface density is reduced, and the threshold voltage of the enhanced semiconductor device is further improved.

Drawings

FIG. 1 is a schematic structural view of example 1;

FIG. 2 is a schematic structural view of example 6;

in the figure: 10 is a substrate, 11 is a buffer layer, 12 is a barrier layer, 131 is a first P-type nitride gate layer, 132 is a second P-type nitride gate layer, 141 is a first source metal, 142 is a second source metal, 151 is a first drain metal, 152 is a second drain metal, 161 is a first gate metal, 162 is a second gate metal, 20 is a tensile stress dielectric layer, and 30 is a passivation layer.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples.

The integrated chip of the enhancement type and depletion type HEMT device realizes the monolithic integration of the enhancement type and depletion type HEMT device of the depletion type semiconductor device by utilizing the influence of the stress of the dielectric layer on the threshold voltage of the device and the correlation of the grid line width of the device.

The invention is realized by the following principle: due to the fact that the tensile stress medium layer enables crystal lattices of the barrier layer below the P-type nitride gate layer to be subjected to plane biaxial tensile stress, the spontaneous polarization direction of the barrier layer below the P-type nitride gate layer is the same as the piezoelectric polarization direction, the total polarization strength is enhanced, the polarization charge surface density of the heterojunction interface of the channel layer and the barrier layer is increased, the two-dimensional electron gas concentration of the heterojunction interface of the channel layer and the barrier layer is further increased, and the threshold voltage of the P-type nitride gate HEMT device is reduced. And the crystal lattices of the barrier layer below the P-type nitride gate layer are mainly concentrated in the edge regions of the gate by plane biaxial tensile stress, namely the crystal lattices at the edge regions of the gate are stronger than those at the center of the gate by the plane biaxial tensile stress. Therefore, the smaller the grid line width of the P-type nitride grid layer is, the more obvious the effect of the crystal lattice of the barrier layer below the P-type nitride grid layer under the action of plane biaxial tensile stress is, the lower the threshold voltage of the P-type nitride grid HEMT device is, and the enhancement type semiconductor device is converted into a depletion type semiconductor device.

Example 1

An integrated chip of an enhancement mode and depletion mode HEMT device is shown in FIG. 1, and comprises a substrate 10, a buffer layer 11, a channel layer, a barrier layer 12, a first P-type nitride gate layer 131 and a second P-type nitride gate layer 132, wherein the first P-type nitride gate layer 131 and the second P-type nitride gate layer 132 are arranged at intervals; a first gate metal 161 is disposed on the first P-type nitride gate layer 131, and a second gate metal 162 is disposed on the second P-type nitride gate layer 132; a region of the first P-nitride gate layer 131 and its periphery is defined as an enhancement region, and a region of the second P-nitride gate layer 132 and its periphery is defined as a depletion region. The enhancement region typically includes the first P-nitride gate layer 131, the first gate metal 161, a peripheral metal region and a metal-free region; the depletion region typically includes the second P-nitride gate layer 132, the second gate metal 162, and a peripheral metal region and a metal-free region.

Because the influence of the stress of the dielectric layer on the threshold voltage of the device is related to the line width of the gate of the device, in the invention, the line width of the gate of the first P-type nitride gate layer 131 is greater than the line width of the gate of the second P-type nitride gate layer 132; the reinforced area and the depletion area are covered with a tensile stress medium layer 20; further, the first source metal 141 and the first drain metal 151 are provided in the enhancement region to form an enhancement semiconductor device, and the second source metal 142 and the second drain metal 152 are provided in the depletion region to form a depletion semiconductor device.

In specific implementation, the integrated chip comprises a substrate 10, a GaN buffer layer 11, a channel layer, an AlGaN barrier layer 12 and a P-type nitride gate layer; the P-type nitride gate layer is made of P-GaN, P-AlGaN, P-InGaN or P-InAlGaN; the stress medium of the tensile stress medium layer 20 is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride. In this embodiment, the thickness of the tensile stress dielectric layer 20 is 30nm to 1000nm, and the stress value of the tensile stress dielectric layer 20 is 200MPa to 3 GPa.

In order to make the size difference between first P-type nitride gate layer 131 and second P-type nitride gate layer 132 better interact with the stress of tensile stress dielectric layer 20, and have an influence on the threshold voltage of the device, the gate line width of first P-type nitride gate layer 131 is usually set to be large, such as 1 μm or more, and the gate line width of second P-type nitride gate layer 132 is set to be small, such as 1 μm or less. In this embodiment, the first P-type nitride gate layer has a gate line width of 1 μm to 2 μm, and the second P-type nitride gate layer has a gate line width of 0.1 μm to 0.6 μm.

Based on the structure of the invention, the threshold voltage of the enhancement type semiconductor device is 0.5V-2.5V, and the threshold voltage of the depletion type semiconductor device is-0.5V-1V.

Example 2

The embodiment provides a method for manufacturing an integrated chip of an enhancement mode HEMT device and a depletion mode HEMT device, which is used for manufacturing the integrated chip (such as the integrated chip described in embodiment 1), and comprises the following steps:

1) a nitride epitaxial structure is prepared on a substrate 10, and in the embodiment, the nitride epitaxial structure is a P-type nitride HEMT epitaxial structure and comprises a substrate 10, a GaN buffer layer 11, a channel layer, an AlGaN barrier layer 12 and a P-type nitride gate layer.

2) Selectively etching the P-type nitride layer to form a first P-type nitride gate layer 131 and a second P-type nitride gate layer 132; the gate line width of first P-type nitride gate layer 131 is greater than the gate line width of second P-type nitride gate layer 132. In this embodiment, the first P-type nitride gate layer has a gate line width of 1 μm to 2 μm, and the second P-type nitride gate layer has a gate line width of 0.1 μm to 0.6 μm.

In the embodiment, gate patterns of the enhancement type semiconductor device and the depletion type semiconductor device are defined through a photolithography process, and redundant P-type nitride is etched by using a selective etching technology to form the gate patterns of the enhancement type semiconductor device and the depletion type semiconductor device, namely, a first P-type nitride gate layer 131 and a second P-type nitride gate layer 132; in specific implementation, dry etching (such as ICP, RIE, ECR, etc.) may be used. Wherein, the material of the P-type nitride layer is P-GaN, P-AlGaN, P-InGaN or P-InAlGaN.

3) Preparing a first gate metal 161 on the first P-type nitride gate layer 131, and preparing the first gate metal 161 on the second P-type nitride gate layer 132; in specific implementation, the metal system can be prepared by evaporation, sputtering or the like, and the metal system can include Ti, Al, Ni, Au, Ta or the like, and an alloy containing the metal system or a compound of the metal system.

A region of the first P-nitride gate layer 131 and its periphery is defined as an enhancement region, and a region of the second P-nitride gate layer 132 and its periphery is defined as a depletion region.

4) And depositing a tensile stress medium layer 20 on the surface (whole surface) of the nitride epitaxial structure, wherein the tensile stress medium layer 20 covers the enhancement region and the depletion region. In one embodiment, the tensile stress dielectric layer 20 may be deposited by PECVD, LPCVD, or the like. Wherein, the stress medium of the tensile stress medium layer 20 is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride; the whole thickness of the tensile stress dielectric layer 20 is 30nm-1000nm, and the stress value is 200 MPa-3 GPa.

5) Preparing a first source metal 141 and a first drain metal 151 in the enhancement region to form an enhancement semiconductor device; and preparing a second source metal 142 and a second drain metal 152 in the depletion region to form a depletion type semiconductor device. Specifically, openings are respectively formed in the compressive stress dielectric layer 20, and a first source metal 141 and a first drain metal 151 are respectively prepared on the compressive stress dielectric layer 20 at the positions corresponding to the openings; opening the tensile stress dielectric layer 20, and preparing a second source metal 142 and a second drain metal 152 on the tensile stress dielectric layer 20 at the opening positions.

Example 3

As shown in fig. 2, the present embodiment is different from embodiment 1 in that the enhancement region and the depletion region cover the passivation layer 30, and the tensile stress dielectric layer 20 covers the passivation layer 30; when the PECVD is used for depositing the tensile stress dielectric layer 20, the plasma bombardment can avoid damaging the surface of the non-gate region, a large number of traps can be generated on the surface, and the dynamic characteristic of the device can be reduced.

In this embodiment, the thickness of the passivation layer 30 is smaller than that of the tensile stress dielectric layer 20; the passivation layer 30 has a tensile stress value lower than that of the tensile stressed dielectric layer 20. In specific implementation, the stress value of the passivation layer 30 is-250 MPa-150 MPa; the thickness of the passivation layer 30 is less than 20 nm. The passivation layer 30 is one or a combination of silicon nitride, silicon oxide, aluminum nitride or aluminum oxide.

The other portions are the same as in example 1.

Example 4

This embodiment provides a method for manufacturing an integrated chip of an enhancement mode HEMT device, which is used to manufacture the integrated chip (e.g., the integrated chip described in embodiment 3). This embodiment is substantially the same as embodiment 2.

Corresponding to the passivation layer 30, compared with embodiment 2, this embodiment further includes the following steps between step 3) and step 4):

depositing a stress medium on the surface (whole surface) of the nitride epitaxial structure to form a passivation layer 30, wherein the stress value of the passivation layer 30 is lower than that of the tensile stress medium layer 20; the passivation layer 30 covers the enhancement region, the depletion region. In specific implementation, a layer of low stress dielectric, i.e., the passivation layer 30, may be deposited over the entire surface by using a thin film growth process such as ALD, LPCVD, PECVD, PVD, etc.

In this embodiment, the passivation layer 30 is one or a combination of silicon nitride, silicon oxide, aluminum nitride, or aluminum oxide. The thickness of the passivation layer 30 is less than 20nm, and the stress value is-250 MPa-150 MPa.

The other portions are the same as in example 2.

The above examples are provided only for illustrating the present invention and are not intended to limit the present invention. Changes, modifications, etc. to the above-described embodiments are intended to fall within the scope of the claims of the present invention as long as they are in accordance with the technical spirit of the present invention.