阅读说明：本技术 一种增强型与耗尽型hemt集成器件及制备方法 (Enhanced and depletion HEMT integrated device and preparation method thereof ) 是由 蔡文必 田野 刘成 何俊蕾 赵杰 郭德霄 叶念慈 于 2020-12-22 设计创作，主要内容包括：本发明涉及一种增强型与耗尽型HEMT集成器件及制备方法,通过在P型氮化物栅极层上沉积不同应力的介质,对P型氮化物栅极层下方的势垒层应力进行调控,改变其极化电场强度,最终实现P型氮化物栅增强型和耗尽型HEMT器件的单片集成。在制备耗尽型半导体器件时,无需刻蚀栅金属下方的P型氮化物层,栅极金属与半导体接触界面不存在刻蚀损伤,可有效降低器件的栅漏电,提升器件开关电流比,降低功耗；本发明制备的增强型半导体器件,与常规P型氮化物栅增强型HEMT相比,P型氮化物栅极层下方的势垒层极化电场强度减弱,异质结界面极化电荷面密度减少,增强型半导体器件的阈值电压得到进一步提升。(The invention relates to an enhancement type and depletion type HEMT integrated device and a preparation method thereof. When the depletion type semiconductor device is prepared, a P-type nitride layer below the gate metal does not need to be etched, and the contact interface between the gate metal and the semiconductor has no etching damage, so that the gate leakage of the device can be effectively reduced, the on-off current ratio of the device is improved, and the power consumption is reduced; compared with the conventional P-type nitride gate enhanced HEMT, the enhanced semiconductor device prepared by the invention has the advantages that the polarization electric field intensity of the barrier layer below the P-type nitride gate layer is weakened, the heterojunction interface polarization charge surface density is reduced, and the threshold voltage of the enhanced semiconductor device is further improved.)

1. An enhancement mode and depletion mode HEMT integrated device is characterized by comprising a substrate, a buffer layer, a channel layer, a barrier layer, a first P-type nitride gate layer and a second P-type nitride gate layer, wherein the first P-type nitride gate layer and the second P-type nitride gate layer are arranged at intervals; a first gate metal is arranged on the first P-type nitride gate layer, and a second gate metal is arranged on the second P-type nitride gate layer; the first P-type nitride grid layer and a certain range of area around the first P-type nitride grid layer are defined as an enhancement area, and the second P-type nitride grid layer and a certain range of area around the second P-type nitride grid layer are defined as a depletion area; the enhancement region covers the compressive stress dielectric layer, and is provided with a first source electrode metal and a first drain electrode metal to form an enhancement type semiconductor device; the depletion region covers the tensile stress dielectric layer, and is provided with a second source metal and a second drain metal to form a depletion type semiconductor device.

2. The enhancement mode and depletion mode HEMT integrated device of claim 1, wherein the enhancement region and the depletion region cover different kinds of passivation layers, and the compressive stress dielectric layer and the tensile stress dielectric layer respectively correspond to the enhancement region and the depletion region and cover the passivation layers; the compressive stress value of the passivation layer is lower than that of the compressive stress dielectric layer, and the tensile stress value of the passivation layer is lower than that of the tensile stress dielectric layer.

3. The enhancement mode and depletion mode HEMT integrated device according to claim 2, wherein the stress value of the compressive stress dielectric layer is-250 MPa to-3 GPa, the stress value of the tensile stress dielectric layer is 200MPa to 3GPa, and the stress value of the passivation layer is-250 MPa to 150 MPa; the thickness of the compressive stress dielectric layer is 30nm-1000nm, the thickness of the tensile stress dielectric layer is 30nm-1000nm, and the thickness of the passivation layer is less than 20 nm; the threshold voltage of the enhancement type semiconductor device is 0.5V-2.5V, and the threshold voltage of the depletion type semiconductor device is-0.5V-1V.

4. The monolithic integrated circuit of enhancement mode and depletion mode HEMT device as claimed in claim 2 or 3, wherein the stress dielectric of the compressive stress dielectric layer is one or more of silicon nitride, silicon oxide or silicon oxynitride, the stress dielectric of the tensile stress dielectric layer is one or more of silicon nitride, silicon oxide or silicon oxynitride, and the passivation layer is one or more of silicon nitride, silicon oxide, aluminum nitride or aluminum oxide.

5. A preparation method of an enhancement mode and depletion mode HEMT integrated device is characterized by comprising the following steps:

1) preparing a nitride epitaxial structure on a substrate, wherein the nitride epitaxial structure comprises a buffer layer, a channel layer, a barrier layer and a P-type nitride layer; etching the P-type nitride layer of the nitride epitaxial structure to form a first P-type nitride gate layer and a second P-type nitride gate layer; preparing a first gate metal on the first P-type nitride gate layer and a first gate metal on the second P-type nitride gate layer; the first P-type nitride grid layer and a certain range of area around the first P-type nitride grid layer are defined as an enhancement area, and the second P-type nitride grid layer and a certain range of area around the second P-type nitride grid layer are defined as a depletion area;

2) depositing a compressive stress medium layer on the surface of the nitride epitaxial structure, wherein the compressive stress medium layer covers the enhancement region and the depletion region;

or depositing a tensile stress dielectric layer on the surface of the nitride epitaxial structure, wherein the tensile stress dielectric layer covers the enhancement region and the depletion region;

3) removing the compressive stress dielectric layer covering the depletion region;

or removing the tensile stress medium layer covering the enhanced region;

4) depositing a tensile stress medium layer on the surface of the nitride epitaxial structure, wherein the tensile stress medium layer covers the compressive stress medium layer and the depletion region; removing the tensile stress medium layer covering the compressive stress medium layer;

or depositing a compressive stress dielectric layer on the surface of the nitride epitaxial structure, wherein the compressive stress dielectric layer covers the tensile stress dielectric layer and the enhanced region; removing the compressive stress dielectric layer covering the tensile stress dielectric layer;

the thickness of the compressive stress dielectric layer is 30nm-1000nm, and the stress value is-250 MPa-3 GPa;

the thickness of the tensile stress dielectric layer is 30nm-1000nm, and the stress value is 200 MPa-3 GPa;

5) preparing a first source electrode metal and a first drain electrode metal in the enhancement region to form an enhancement type semiconductor device; preparing a second source electrode metal and a second drain electrode metal in the depletion region to form a depletion type semiconductor device;

or preparing a second source metal and a second drain metal in the depletion region to form a depletion type semiconductor device; and preparing a first source metal and a first drain metal in the enhancement region to form the enhancement type semiconductor device.

6. The method for preparing an enhancement mode and depletion mode HEMT integrated device according to claim 5, wherein between step 1) and step 2), the method further comprises the following steps:

depositing a stress medium on the surface of the nitride epitaxial structure to form a passivation layer, wherein the passivation layer covers the enhancement region and the depletion region;

the thickness of the passivation layer is less than 20nm, and the stress value is-250 MPa-150 MPa.

7. The method according to claim 6, wherein the stress dielectric of the compressive stress dielectric layer is one or a combination of silicon nitride, silicon oxide or silicon oxynitride, the stress dielectric of the tensile stress dielectric layer is one or a combination of silicon nitride, silicon oxide or silicon oxynitride, and the passivation layer is one or a combination of silicon nitride, silicon oxide, aluminum nitride or aluminum oxide.

8. A preparation method of an enhancement mode and depletion mode HEMT integrated device is characterized by comprising the following steps:

1) preparing a nitride epitaxial structure on a substrate, wherein the nitride epitaxial structure comprises a buffer layer, a channel layer, a barrier layer and a P-type nitride layer; etching the P-type nitride layer of the nitride epitaxial structure to form a first P-type nitride gate layer and a second P-type nitride gate layer; preparing a first gate metal on the first P-type nitride gate layer and a first gate metal on the second P-type nitride gate layer; the first P-type nitride grid layer and a certain range of area around the first P-type nitride grid layer are defined as an enhancement area, and the second P-type nitride grid layer and a certain range of area around the second P-type nitride grid layer are defined as a depletion area;

2) depositing a compressive stress medium layer on the surface of the nitride epitaxial structure, wherein the compressive stress medium layer covers the enhancement region and the depletion region;

or depositing a tensile stress dielectric layer on the surface of the nitride epitaxial structure, wherein the tensile stress dielectric layer covers the current depletion region of the enhancement region;

3) performing high-temperature annealing to convert the compressive stress dielectric layer into a tensile stress dielectric layer;

or, carrying out high-temperature annealing to convert the tensile stress dielectric layer into a compressive stress dielectric layer;

4) removing the tensile stress medium layer covering the enhanced area;

or removing the compressive stress dielectric layer covering the depletion region;

5) depositing a compressive stress dielectric layer on the surface of the nitride epitaxial structure, wherein the compressive stress dielectric layer covers the enhancement region and the tensile stress dielectric layer; removing the compressive stress dielectric layer covering the tensile stress dielectric layer;

or depositing a tensile stress dielectric layer on the surface of the nitride epitaxial structure, wherein the tensile stress dielectric layer covers the compressive stress dielectric layer and the depletion region; removing the tensile stress medium layer covering the compressive stress medium layer;

the thickness of the compressive stress dielectric layer is 30nm-1000nm, and the stress value is-250 MPa-3 GPa;

the thickness of the tensile stress dielectric layer is 30nm-1000nm, and the stress value is 200 MPa-3 GPa;

6) preparing a second source electrode metal and a second drain electrode metal in the depletion region to form a depletion type semiconductor device; preparing a first source electrode metal and a first drain electrode metal in the enhancement region to form an enhancement type semiconductor device;

or preparing a first source electrode metal and a first drain electrode metal in the enhancement region to form an enhancement type semiconductor device; and preparing a second source metal and a second drain metal in the depletion region to form the depletion type semiconductor device.

9. The method for preparing an enhancement mode and depletion mode HEMT integrated device according to claim 8, wherein between step 1) and step 2), the method further comprises the following steps:

depositing a stress medium on the surface of the nitride epitaxial structure to form a passivation layer, wherein the passivation layer covers the enhancement region and the depletion region;

the thickness of the passivation layer is less than 20nm, and the stress value is-250 MPa-150 MPa;

the stress medium of the compressive stress medium layer is one or a combination of more than one of silicon nitride, silicon oxide or silicon oxynitride, the stress medium of the tensile stress medium layer is one or a combination of more than one of silicon nitride, silicon oxide or silicon oxynitride, and the passivation layer is one or a combination of more than one of silicon nitride, silicon oxide, aluminum nitride or aluminum oxide.

10. The method as claimed in claim 8, wherein the annealing temperature in step 2) is 700-1000 ℃ and the annealing time is 1-5 hours.

Technical Field

The invention relates to the technical field of semiconductors, in particular to an enhanced HEMT integrated device and a depletion HEMT integrated device and a preparation method of the enhanced HEMT integrated device and the depletion HEMT integrated device.

Background

The silicon-based GaN HEMT has a wide development prospect in the field of power switches due to the excellent characteristics of gallium nitride materials, wherein the commercial power GaN HEMT is mainly a P-type nitride gate enhanced HEMT device. However, the P-type nitride gate enhancement type HEMT device has the problems of low threshold voltage, small gate swing and the like, and in order to fully exert the advantages of GaN materials, a gate drive circuit and a power GaN HEMT need to be monolithically integrated.

In the prior art, based on a p-GaN/AlGaN/GaN epitaxial structure, a common method for realizing monolithic integration of enhancement and depletion devices is as follows: and selectively etching or completely etching the surface P-type nitride layer by using a dry etching process to obtain the enhancement type or depletion type GaN HEMT device.

However, in the above method, when the depletion-mode GaN HEMT device is prepared by completely etching the P-type nitride layer, dry etching damage exists on the surface of the AlGaN layer below the gate region, and the damage causes a large number of defects on the surface of the AlGaN layer, which results in uneven distribution of threshold voltage of the device and large gate leakage current. Meanwhile, the enhancement type HEMT device prepared by the method for selectively etching the P-type nitride layer has lower threshold voltage, and has the risk of mistaken opening in practical circuit application, thereby influencing the circuit safety.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides an enhanced HEMT integrated device and a preparation method thereof, wherein monolithic integration of the enhanced HEMT device and the depletion HEMT device of the depletion semiconductor device is realized by applying different stresses, and the contact interface of grid metal and a semiconductor has no etching damage, so that grid leakage of the device can be effectively reduced, the on-off ratio of the device is improved, and the power consumption is reduced; and simultaneously, the threshold voltage of the enhancement type semiconductor device is further improved.

The technical scheme of the invention is as follows:

an enhancement mode and depletion mode HEMT integrated device comprises a substrate, a buffer layer, a channel layer, a barrier layer, a first P-type nitride gate layer and a second P-type nitride gate layer, wherein the first P-type nitride gate layer and the second P-type nitride gate layer are arranged at intervals; a first gate metal is arranged on the first P-type nitride gate layer, and a second gate metal is arranged on the second P-type nitride gate layer; the first P-type nitride grid layer and a certain range of area around the first P-type nitride grid layer are defined as an enhancement area, and the second P-type nitride grid layer and a certain range of area around the second P-type nitride grid layer are defined as a depletion area; the enhancement region covers the compressive stress dielectric layer, and is provided with a first source electrode metal and a first drain electrode metal to form an enhancement type semiconductor device; the depletion region covers the tensile stress dielectric layer, and is provided with a second source metal and a second drain metal to form a depletion type semiconductor device.

Preferably, the enhancement region and the depletion region are covered with different types of passivation layers, and the compressive stress dielectric layer and the tensile stress dielectric layer respectively correspond to the enhancement region and the depletion region and cover the passivation layers; the compressive stress value of the passivation layer is lower than that of the compressive stress dielectric layer, and the tensile stress value of the passivation layer is lower than that of the tensile stress dielectric layer.

Preferably, the stress value of the compressive stress dielectric layer is-250 MPa to-3 GPa, the stress value of the tensile stress dielectric layer is 200MPa to 3GPa, and the stress value of the passivation layer is-250 MPa to 150 MPa; the thickness of the compressive stress dielectric layer is 30nm-1000nm, the thickness of the tensile stress dielectric layer is 30nm-1000nm, and the thickness of the passivation layer is less than 20 nm; the threshold voltage of the enhancement type semiconductor device is 0.5V-2.5V, and the threshold voltage of the depletion type semiconductor device is-0.5V-1V.

Preferably, the stress medium of the compressive stress medium layer is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride, the stress medium of the tensile stress medium layer is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride, and the passivation layer is one or a combination of several of silicon nitride, silicon oxide, aluminum nitride or aluminum oxide.

A preparation method of an enhancement mode and depletion mode HEMT integrated device comprises the following steps:

1) preparing a nitride epitaxial structure on a substrate, wherein the nitride epitaxial structure comprises a buffer layer, a channel layer, a barrier layer and a P-type nitride layer; etching the P-type nitride layer of the nitride epitaxial structure to form a first P-type nitride gate layer and a second P-type nitride gate layer; preparing a first gate metal on the first P-type nitride gate layer and a first gate metal on the second P-type nitride gate layer; the first P-type nitride grid layer and a certain range of area around the first P-type nitride grid layer are defined as an enhancement area, and the second P-type nitride grid layer and a certain range of area around the second P-type nitride grid layer are defined as a depletion area;

2) depositing a compressive stress medium layer on the surface of the nitride epitaxial structure, wherein the compressive stress medium layer covers the enhancement region and the depletion region;

or depositing a tensile stress dielectric layer on the surface of the nitride epitaxial structure, wherein the tensile stress dielectric layer covers the enhancement region and the depletion region;

3) removing the compressive stress dielectric layer covering the depletion region;

or removing the tensile stress medium layer covering the enhanced region;

4) depositing a tensile stress medium layer on the surface of the nitride epitaxial structure, wherein the tensile stress medium layer covers the compressive stress medium layer and the depletion region; removing the tensile stress medium layer covering the compressive stress medium layer;

or depositing a compressive stress dielectric layer on the surface of the nitride epitaxial structure, wherein the compressive stress dielectric layer covers the tensile stress dielectric layer and the enhanced region; removing the compressive stress dielectric layer covering the tensile stress dielectric layer;

the thickness of the compressive stress dielectric layer is 30nm-1000nm, and the stress value is-250 MPa-3 GPa;

the thickness of the tensile stress dielectric layer is 30nm-1000nm, and the stress value is 200 MPa-3 GPa;

5) preparing a first source electrode metal and a first drain electrode metal in the enhancement region to form an enhancement type semiconductor device; preparing a second source electrode metal and a second drain electrode metal in the depletion region to form a depletion type semiconductor device;

or preparing a second source metal and a second drain metal in the depletion region to form a depletion type semiconductor device; and preparing a first source metal and a first drain metal in the enhancement region to form the enhancement type semiconductor device.

Preferably, between step 1) and step 2), the following steps are further included:

depositing a stress medium on the surface of the nitride epitaxial structure to form a passivation layer, wherein the passivation layer covers the enhancement region and the depletion region;

the thickness of the passivation layer is less than 20nm, and the stress value is-250 MPa-150 MPa.

Preferably, the stress medium of the compressive stress medium layer is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride, the stress medium of the tensile stress medium layer is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride, and the passivation layer is one or a combination of several of silicon nitride, silicon oxide, aluminum nitride or aluminum oxide.

A preparation method of an enhancement mode and depletion mode HEMT integrated device comprises the following steps:

1) preparing a nitride epitaxial structure on a substrate, wherein the nitride epitaxial structure comprises a buffer layer, a channel layer, a barrier layer and a P-type nitride layer; etching the P-type nitride layer of the nitride epitaxial structure to form a first P-type nitride gate layer and a second P-type nitride gate layer; preparing a first gate metal on the first P-type nitride gate layer and a first gate metal on the second P-type nitride gate layer; the first P-type nitride grid layer and a certain range of area around the first P-type nitride grid layer are defined as an enhancement area, and the second P-type nitride grid layer and a certain range of area around the second P-type nitride grid layer are defined as a depletion area;

2) depositing a compressive stress medium layer on the surface of the nitride epitaxial structure, wherein the compressive stress medium layer covers the enhancement region and the depletion region;

or depositing a tensile stress dielectric layer on the surface of the nitride epitaxial structure, wherein the tensile stress dielectric layer covers the current depletion region of the enhancement region;

3) performing high-temperature annealing to convert the compressive stress dielectric layer into a tensile stress dielectric layer;

or, carrying out high-temperature annealing to convert the tensile stress dielectric layer into a compressive stress dielectric layer;

4) removing the tensile stress medium layer covering the enhanced area;

or removing the compressive stress dielectric layer covering the depletion region;

5) depositing a compressive stress dielectric layer on the surface of the nitride epitaxial structure, wherein the compressive stress dielectric layer covers the enhancement region and the tensile stress dielectric layer; removing the compressive stress dielectric layer covering the tensile stress dielectric layer;

or depositing a tensile stress dielectric layer on the surface of the nitride epitaxial structure, wherein the tensile stress dielectric layer covers the compressive stress dielectric layer and the depletion region; removing the tensile stress medium layer covering the compressive stress medium layer;

the thickness of the compressive stress dielectric layer is 30nm-1000nm, and the stress value is-250 MPa-3 GPa;

the thickness of the tensile stress dielectric layer is 30nm-1000nm, and the stress value is 200 MPa-3 GPa;

6) preparing a second source electrode metal and a second drain electrode metal in the depletion region to form a depletion type semiconductor device; preparing a first source electrode metal and a first drain electrode metal in the enhancement region to form an enhancement type semiconductor device;

or preparing a first source electrode metal and a first drain electrode metal in the enhancement region to form an enhancement type semiconductor device; and preparing a second source metal and a second drain metal in the depletion region to form the depletion type semiconductor device.

Preferably, between step 1) and step 2), the following steps are further included:

depositing a stress medium on the surface of the nitride epitaxial structure to form a passivation layer, wherein the passivation layer covers the enhancement region and the depletion region;

the thickness of the passivation layer is less than 20nm, and the stress value is-250 MPa-150 MPa;

the stress medium of the compressive stress medium layer is one or a combination of more than one of silicon nitride, silicon oxide or silicon oxynitride, the stress medium of the tensile stress medium layer is one or a combination of more than one of silicon nitride, silicon oxide or silicon oxynitride, and the passivation layer is one or a combination of more than one of silicon nitride, silicon oxide, aluminum nitride or aluminum oxide.

Preferably, in the step 2), the annealing temperature is 700-1000 ℃, and the annealing time is 1-5 hours.

The invention has the following beneficial effects:

according to the enhancement type and depletion type HEMT integrated device, the stress of the barrier layer below the P-type nitride gate layer is regulated and controlled by depositing media with different stresses on the P-type nitride gate layer, the polarization electric field intensity of the barrier layer is changed, and finally the monolithic integration of the enhancement type and depletion type HEMT device of the P-type nitride gate is realized. The contact interface of the grid metal and the semiconductor has no etching damage, so that the grid leakage of the device can be effectively reduced, the on-off current ratio of the device is improved, and the power consumption is reduced; according to the enhanced semiconductor device, the polarization electric field intensity of the barrier layer below the P-type nitride gate layer is weakened, the density of the heterojunction interface polarization charge surface is reduced, and the threshold voltage of the enhanced semiconductor device is further improved.

The preparation method of the enhancement mode and depletion mode HEMT integrated device is used for preparing the enhancement mode and depletion mode HEMT integrated device, when the depletion mode semiconductor device is prepared, a P-type nitride layer below a gate metal does not need to be etched, and the contact interface of the gate metal and a semiconductor does not have etching damage, so that the gate leakage of the device can be effectively reduced, the on-off current ratio of the device is improved, and the power consumption is reduced; compared with the conventional P-type nitride gate enhanced HEMT, the enhanced semiconductor device prepared by the invention has the advantages that the polarization electric field intensity of the barrier layer below the P-type nitride gate layer is weakened, the heterojunction interface polarization charge surface density is reduced, and the threshold voltage of the enhanced semiconductor device is further improved.

Drawings

FIG. 1 is a schematic structural view of example 1;

FIG. 2 is a schematic structural view of example 6;

in the figure: 10 is a substrate, 11 is a buffer layer, 12 is a barrier layer, 131 is a first P-type nitride gate layer, 132 is a second P-type nitride gate layer, 141 is a first source metal, 142 is a second source metal, 151 is a first drain metal, 152 is a second drain metal, 161 is a first gate metal, 162 is a second gate metal, 20 is a compressive stress dielectric layer, 30 is a tensile stress dielectric layer, and 40 is a passivation layer.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples.

According to the enhancement type and depletion type HEMT integrated device, the stress of the barrier layer below the P-type nitride gate layer is regulated and controlled by depositing media with different stresses on the P-type nitride gate layer, the polarization electric field intensity of the barrier layer is changed, and finally the monolithic integration of the enhancement type and depletion type HEMT device of the P-type nitride gate is realized.

The invention is realized by the following principle: on one hand, a compressive stress medium is deposited on the enhanced semiconductor device, so that the barrier layer below the P-type nitride gate layer is subjected to plane biaxial compressive stress, the piezoelectric polarization direction of the barrier layer is opposite to the spontaneous polarization direction due to the plane biaxial compressive stress, the total polarization strength of crystal lattices is weakened, the heterojunction interface polarization charge density below the P-type nitride gate layer is reduced, the energy level of a conduction band is integrally moved upwards, the concentration of two-dimensional electron gas at the heterojunction interface of the channel layer and the barrier layer is reduced, and the threshold voltage of the enhanced device is improved; on the other hand, a tensile stress medium is deposited on the enhancement type semiconductor device, so that the barrier layer below the P-type nitride gate layer is subjected to plane biaxial tensile stress, the piezoelectric polarization direction of the barrier layer is the same as the spontaneous polarization direction, the total polarization strength of crystal lattices is enhanced, the heterojunction interface polarization charge density below the P-type nitride gate layer is increased, the energy level of a conduction band is integrally moved downwards, the concentration of two-dimensional electron gas at the heterojunction interface of the channel layer and the barrier layer is increased, the threshold value of the device is moved from positive to negative to be smaller than zero, and finally the enhancement type semiconductor device is converted into a depletion type semiconductor device.

Example 1

An enhancement mode and depletion mode HEMT integrated device, as shown in FIG. 1, comprises a substrate 10, a buffer layer 11, a channel layer, a barrier layer 12, a first P-type nitride gate layer 131, a second P-type nitride gate layer 132, wherein the first P-type nitride gate layer 131 and the second P-type nitride gate layer 132 are arranged at intervals; a first gate metal 161 is disposed on the first P-type nitride gate layer 131, and a second gate metal 162 is disposed on the second P-type nitride gate layer 132; a region of the first P-nitride gate layer 131 and its periphery is defined as an enhancement region, and a region of the second P-nitride gate layer 132 and its periphery is defined as a depletion region. The enhancement region typically includes the first P-nitride gate layer 131, the first gate metal 161, a peripheral metal region and a metal-free region; the depletion region typically includes the second P-nitride gate layer 132, the second gate metal 162, and a peripheral metal region and a metal-free region. The enhanced region covers the compressive stress dielectric layer 20, and is provided with a first source metal 141 and a first drain metal 151 to form an enhanced semiconductor device; the depletion region covers the tensile stress dielectric layer 30, and the second source metal 142 and the second drain metal 152 are disposed to form a depletion type semiconductor device.

In specific implementation, the monolithic integrated circuit includes a substrate 10, a GaN buffer layer 11, a channel layer, an AlGaN barrier layer 12, and a P-type nitride gate layer; the P-type nitride gate layer is made of P-GaN, P-AlGaN, P-InGaN or P-InAlGaN; the stress medium of the compressive stress medium layer 20 is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride, and the stress medium of the tensile stress medium layer 30 is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride.

The thickness of the compressive stress dielectric layer 20 is 30nm-1000nm, and the stress value of the compressive stress dielectric layer 20 is-250 MPa-3 GPa; the thickness of the tensile stress medium layer 30 is 30nm-1000nm, and the stress value of the tensile stress medium layer 30 is 200 MPa-3 GPa.

Based on the structure of the invention, the threshold voltage of the increasing type semiconductor device is 0.5V-2.5V, and the threshold voltage of the depletion type semiconductor device is-0.5V-1V.

Example 2

The embodiment provides a method for manufacturing an enhancement mode HEMT integrated device and a depletion mode HEMT integrated device, which is used for manufacturing a monolithic integrated circuit (such as the monolithic integrated circuit described in embodiment 1), and takes a manufacturing method for manufacturing an enhancement mode semiconductor device first and then a depletion mode semiconductor device as an example, and includes the following steps:

1) preparing a nitride epitaxial structure on a substrate 10, wherein in the embodiment, the nitride epitaxial structure is a P-type nitride HEMT epitaxial structure and comprises the substrate 10, a GaN buffer layer 11, a channel layer, an AlGaN barrier layer 12 and a P-type nitride gate layer; wherein the substrate comprises one of silicon, gallium nitride, silicon carbide, sapphire and the like.

2) Selectively etching the P-type nitride layer to form a first P-type nitride gate layer 131 and a second P-type nitride gate layer 132; in this embodiment, gate patterns of the enhancement type semiconductor device and the depletion type semiconductor device are defined through a photolithography process, and redundant P-type nitride is etched by using a selective etching technique to form gate patterns of the enhancement type semiconductor device and the depletion type semiconductor device, that is, a first P-type nitride gate layer 131 and a second P-type nitride gate layer 132; in specific implementation, dry etching (such as ICP, RIE, ECR, etc.) may be used. Wherein, the material of the P-type nitride layer is P-GaN, P-AlGaN, P-InGaN or P-InAlGaN.

3) Preparing a first gate metal 161 on the first P-type nitride gate layer 131, and preparing the first gate metal 161 on the second P-type nitride gate layer 132; in specific implementation, the metal system can be prepared by evaporation, sputtering or the like, and the metal system can include Ti, Al, Ni, Au, Ta or the like, and an alloy containing the metal system or a compound of the metal system.

A region of the first P-nitride gate layer 131 and its periphery is defined as an enhancement region, and a region of the second P-nitride gate layer 132 and its periphery is defined as a depletion region.

4) And depositing a compressive stress medium layer 20 on the surface (whole surface) of the nitride epitaxial structure, wherein the compressive stress medium layer 20 covers the enhancement region and the depletion region. In one embodiment, the compressive dielectric layer 20 may be deposited by PECVD, LPCVD, or the like. And coating photoresist in a spinning mode, exposing and developing to enable the enhancement region to be covered by the photoresist and enable the depletion region to be exposed. The compressive stress dielectric layer 20 covering the depletion region is selectively removed by using a dry etching (e.g., ICP, RIE) or wet etching process. Wherein, the stress medium of the compressive stress medium layer 20 is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride; the whole thickness of the compressive stress medium layer 20 is 30nm-1000nm, and the stress value is-250 MPa to-3 GPa ("-" represents compressive stress).

5) And depositing a tensile stress medium layer 30 on the surface (whole surface) of the nitride epitaxial structure, wherein the tensile stress medium layer 30 covers the compressive stress medium layer 20 and the depletion region. In a specific implementation, the tensile stress dielectric layer 30 may be deposited by PECVD, LPCVD, or the like. And coating photoresist in a spinning mode, exposing and developing to enable the depletion region to be covered by the photoresist, and exposing the compressive stress dielectric layer 20 in the enhancement region. The tensile stress dielectric layer 30 covering the compressive stress dielectric layer 20 is selectively removed by using a dry etching (such as ICP, RIE, ECR) or wet etching process. Wherein, the stress medium of the tensile stress medium layer 30 is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride; the whole thickness of the tensile stress medium layer 30 is 30nm-1000nm, and the stress value is 200 MPa-3 GPa.

6) Preparing a first source metal 141 and a first drain metal 151 in the enhancement region to form an enhancement type semiconductor device; and preparing a second source metal 142 and a second drain metal 152 in the depletion region to form a depletion type semiconductor device. Specifically, openings are respectively formed in the compressive stress dielectric layer 20, and a first source metal 141 and a first drain metal 151 are respectively prepared on the compressive stress dielectric layer 20 at the positions corresponding to the openings; the tensile stress dielectric layer 30 is opened, and a second source metal 142 and a second drain metal 152 are respectively prepared on the tensile stress dielectric layer 30 at the positions corresponding to the openings.

Example 3

The difference between this embodiment and embodiment 2 is that this embodiment prepares a depletion-type semiconductor device first and then prepares an enhancement-type semiconductor device, and correspondingly, step 4) and step 5) of this embodiment are as follows:

4) and depositing a tensile stress medium layer 30 on the surface (whole surface) of the nitride epitaxial structure, wherein the tensile stress medium layer 30 covers the enhancement region and the depletion region. In particular, the tensile stress dielectric layer 30 may be deposited by PECVD, LPCVD, or the like. And coating photoresist in a spinning mode, exposing and developing to enable the depletion region to be covered by the photoresist and enable the enhancement region to be exposed. The tensile-stressed dielectric layer 30 covering the enhancement region is selectively removed using a dry etching (e.g., ICP, RIE, ECR) or wet etching process. Wherein, the stress medium of the tensile stress medium layer 30 is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride; the whole thickness of the tensile stress medium layer 30 is 30nm-1000nm, and the stress value is 200 MPa-3 GPa.

5) And depositing a compressive stress dielectric layer 20 on the surface (whole surface) of the nitride epitaxial structure, wherein the compressive stress dielectric layer 20 covers the tensile stress dielectric layer 30 and the enhancement region. In particular, the tensile stress dielectric layer 30 may be deposited by PECVD or the like. And coating photoresist in a spinning mode, exposing and developing to enable the enhancement region to be covered by the photoresist, and exposing the tensile stress dielectric layer 30 in the depletion region. And selectively removing the compressive stress dielectric layer 20 covering the tensile stress dielectric layer 30 by adopting a dry etching (such as ICP, RIE) or wet etching process. Wherein, the stress medium of the compressive stress medium layer 20 is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride; the whole thickness of the compressive stress medium layer 20 is 30nm-1000nm, and the stress value is-250 MPa to-3 GPa ("-" represents compressive stress).

The other portions are the same as in example 2.

Example 4

The difference between this embodiment and embodiments 2 and 3 is that the preparation processes of the compressive stress dielectric layer 20 and the tensile stress dielectric layer 30 are different, in this embodiment, by using the stress characteristic of the transition stress dielectric, the compressive stress dielectric layer 20 on the whole surface is deposited first, then the compressive stress dielectric layer 20 is transformed into the tensile stress dielectric layer 30 by high temperature annealing, and then the compressive stress dielectric layer 20 is deposited, so as to obtain the combination of the compressive stress dielectric layer 20 and the tensile stress dielectric layer 30 in different regions. Compared with the embodiments 2 and 3, the preparation method of the embodiment can achieve more optimized effects in the aspects of the process steps, the process window and the like than the preparation method of the embodiments 2 and 3, namely, the process steps are simplified, and the precision requirement of the process window is lower.

Specifically, the method for manufacturing the enhancement mode and depletion mode HEMT integrated device according to the embodiment includes the following steps:

1) a nitride epitaxial structure is prepared on a substrate 10, and in the embodiment, the nitride epitaxial structure is a P-type nitride HEMT epitaxial structure and comprises a substrate 10, a GaN buffer layer 11, a channel layer, an AlGaN barrier layer 12 and a P-type nitride gate layer.

2) Selectively etching the P-type nitride layer to form a first P-type nitride gate layer 131 and a second P-type nitride gate layer 132; in this embodiment, gate patterns of the enhancement type semiconductor device and the depletion type semiconductor device are defined through a photolithography process, and redundant P-type nitride is etched by using a selective etching technique to form gate patterns of the enhancement type semiconductor device and the depletion type semiconductor device, that is, a first P-type nitride gate layer 131 and a second P-type nitride gate layer 132; in specific implementation, dry etching (such as ICP, RIE, ECR, etc.) may be used. Wherein, the material of the P-type nitride layer is P-GaN, P-AlGaN, P-InGaN or P-InAlGaN.

3) Preparing a first gate metal 161 on the first P-type nitride gate layer 131, and preparing the first gate metal 161 on the second P-type nitride gate layer 132; in specific implementation, the metal system can be prepared by evaporation, sputtering or the like, and the metal system can include Ti, Al, Ni, Au, Ta or the like, and an alloy containing the metal system or a compound of the metal system.

A region of the first P-nitride gate layer 131 and its periphery is defined as an enhancement region, and a region of the second P-nitride gate layer 132 and its periphery is defined as a depletion region.

4) And depositing a compressive stress medium layer 20 on the surface (whole surface) of the nitride epitaxial structure, wherein the compressive stress medium layer 20 covers the enhancement region and the depletion region. In one embodiment, the compressive dielectric layer 20 may be deposited by PECVD, LPCVD, or the like.

5) Performing high-temperature annealing to convert the compressive stress dielectric layer 20 into a tensile stress dielectric layer 30; in this embodiment, the annealing temperature is 700-1000 deg.C, and the annealing time is 1-5 hours. Wherein, the stress medium of the tensile stress medium layer 30 is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride; the whole thickness of the tensile stress medium layer 30 is 30nm-1000nm, and the stress value is 200 MPa-3 GPa.

6) And selectively removing the tensile stress medium layer 30 covering the enhancement region by etching or other removal methods.

7) And depositing a compressive stress dielectric layer 20 on the surface (whole surface) of the nitride epitaxial structure, wherein the compressive stress dielectric layer 20 covers the enhancement region and the tensile stress dielectric layer 30. Wherein, the stress medium of the compressive stress medium layer 20 is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride; the whole thickness of the compressive stress medium layer 20 is 30nm-1000nm, and the stress value is-250 MPa to-3 GPa ("-" represents compressive stress).

8) And selectively removing the compressive stress dielectric layer 20 covering the tensile stress dielectric layer 30 by etching or other removal methods.

9) Preparing a first source metal 141 and a first drain metal 151 in the enhancement region to form an enhancement type semiconductor device; and preparing a second source metal 142 and a second drain metal 152 in the depletion region to form a depletion type semiconductor device. Specifically, openings are respectively formed in the compressive stress dielectric layer 20, and a first source metal 141 and a first drain metal 151 are respectively prepared on the compressive stress dielectric layer 20 at the positions corresponding to the openings; the tensile stress dielectric layer 30 is opened, and a second source metal 142 and a second drain metal 152 are respectively prepared on the tensile stress dielectric layer 30 at the positions corresponding to the openings.

Example 5

The difference between this embodiment and embodiment 4 is that a tensile stress dielectric layer 30 is deposited, the tensile stress dielectric layer 30 is converted into a compressive stress dielectric layer 20, and then the tensile stress dielectric layer 30 is deposited, so as to obtain the combination of the compressive stress dielectric layer 20 and the tensile stress dielectric layer 30 in different regions. Correspondingly, steps 4) to 8) of this embodiment are specifically as follows:

4) and depositing a tensile stress medium layer 30 on the surface (whole surface) of the nitride epitaxial structure, wherein the tensile stress medium layer 30 covers the enhancement region and the depletion region. In particular, the tensile stress dielectric layer 30 may be deposited by PECVD, LPCVD, or the like.

5) Performing high-temperature annealing to convert the tensile stress dielectric layer 30 into the compressive stress dielectric layer 20; in this embodiment, the annealing temperature is 700-1000 deg.C, and the annealing time is 1-5 hours. Wherein, the stress medium of the compressive stress medium layer 20 is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride; the whole thickness of the compressive stress medium layer 20 is 30nm-1000nm, and the stress value is-250 MPa to-3 GPa ("-" represents compressive stress).

6) And selectively removing the compressive stress dielectric layer 20 covering the depletion region by etching or other removal methods.

7) And depositing a tensile stress medium layer 30 on the surface (whole surface) of the nitride epitaxial structure, wherein the tensile stress medium layer 30 covers the depletion region and the compressive stress medium layer 20. Wherein, the stress medium of the tensile stress medium layer 30 is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride; the whole thickness of the tensile stress medium layer 30 is 30nm-1000nm, and the stress value is 200 MPa-3 GPa.

8) And selectively removing the tensile stress medium layer 30 covering the compressive stress medium layer 20 by etching or other removal methods.

The other portions are the same as in example 4.

Example 6

As shown in fig. 2, the difference between this embodiment and embodiment 1 is that the enhancement region and the depletion region cover different kinds of passivation layers 40, and the compressive stress dielectric layer 20 and the tensile stress dielectric layer 30 respectively correspond to the enhancement region and the depletion region and cover the passivation layers 40; when the compressive stress dielectric layer 20 and the tensile stress dielectric layer 30 are deposited by using PECVD, the AlGaN layer in the non-gate region is prevented from being damaged, and a large number of surface states are introduced.

In this embodiment, the thickness of the passivation layer 40 is smaller than the thickness of the compressive stress dielectric layer 20 and the tensile stress dielectric layer 30; the compressive stress value of the passivation layer 40 is lower than that of the compressive stress dielectric layer 20, and the tensile stress value of the passivation layer 40 is lower than that of the tensile stress dielectric layer 30. The stress value of the passivation layer 40 is-250 MPa-150 MPa; the thickness of the passivation layer 40 is less than 20 nm. The passivation layer 40 is one or a combination of silicon nitride, silicon oxide, aluminum nitride or aluminum oxide.

The other portions are the same as in example 1.

Example 7

This embodiment provides a method for manufacturing an enhancement mode HEMT integrated device and a depletion mode HEMT integrated device, which is used for manufacturing the monolithic integrated circuit (such as the monolithic integrated circuit described in embodiment 6). This example is substantially the same as examples 2, 3, 4, and 5.

Corresponding to the passivation layer 40, compared with embodiments 2 and 3, the present embodiment further includes the following steps between step 3) and step 4), compared with embodiments 4 and 5, between step 3) and step 4):

and depositing a stress medium on the surface (whole surface) of the nitride epitaxial structure to form a passivation layer 40, wherein the passivation layer 40 covers the enhancement region and the depletion region. Wherein the enhancement region and the depletion region cover different kinds of passivation layers 40. In specific implementation, a layer of low stress dielectric, i.e., the passivation layer 40, may be deposited over the entire surface by using a thin film growth process such as ALD, LPCVD, PECVD, PVD, etc.

In this embodiment, the passivation layer 40 is one or a combination of silicon nitride, silicon oxide, aluminum nitride, or aluminum oxide. The thickness of the passivation layer 40 is less than 20nm, and the stress value is-250 MPa-150 MPa.

The other portions are the same as those in examples 2, 3, 4 and 5.

The above examples are provided only for illustrating the present invention and are not intended to limit the present invention. Changes, modifications, etc. to the above-described embodiments are intended to fall within the scope of the claims of the present invention as long as they are in accordance with the technical spirit of the present invention.