阅读说明：本技术 单调计数器及其操作方法 (Monotonic counter and method of operating the same ) 是由 卢中舟 于 2020-12-11 设计创作，主要内容包括：本发明提供了一种单调计数器,包括控制器以及多个存储块,且每个存储块包括特殊位以及用于存储计数数据的数据位,其中,控制器包括：用于判断特殊位的有效性,以从多个存储块中确定当前存储块的当前存储块判断模块；以及用于在多个存储块的特殊位均无效时,比较多个存储块中各特殊位中的被擦除位的数量,并对数量多的存储块进行擦除修补的擦除修补模块,从而在有异常情况发生而导致单调计数器出现过度擦除的情况时,单调计数器可以对其存储块进行修补,并找到当前时刻进行存储计数的当前存储块。(The invention provides a monotonic counter, which comprises a controller and a plurality of storage blocks, wherein each storage block comprises a special bit and a data bit for storing counting data, and the controller comprises: a current memory block judgment module for judging validity of the special bit to determine a current memory block from the plurality of memory blocks; and the erasure repairing module is used for comparing the number of the erased bits in each special bit in the plurality of storage blocks and performing erasure repairing on the storage blocks with large number when the special bits of the plurality of storage blocks are invalid, so that when the monotonic counter is excessively erased due to abnormal conditions, the monotonic counter can repair the storage blocks and find the current storage block for performing storage counting at the current moment.)

1. A monotonic counter comprising a controller and a plurality of memory blocks including special bits and data bits for storing count data, wherein the controller comprises:

a current storage block judgment module, configured to judge validity of the special bit to determine a current storage block from the plurality of storage blocks;

and the erasure repairing module is used for comparing the number of the erased bits in each special bit in the plurality of storage blocks and performing erasure repairing on the storage blocks with a large number of the erased bits when the special bits of the plurality of storage blocks are invalid.

2. The monotonic counter of claim 1, wherein the current memory block determining module further comprises a re-determination submodule configured to re-determine validity of the special bit of the plurality of memory blocks after the erasure patch.

3. The monotonic counter of claim 2, wherein the re-determination sub-module is further configured to determine that the memory block not undergoing erase repair is a current memory block when the re-determination sub-module determines that a special bit of the memory block not undergoing erase repair is valid.

4. The monotonic counter of claim 3, wherein after determining the current memory block, the controller is further configured to write data in a first data bit of the current memory block that does not store count data for counting.

5. The monotonic counter of claim 4, wherein after the controller writes data in a first data bit of the current memory block that does not store counting data for counting, the controller is further configured to read a counting value of the current memory block, wherein the counting value is a sum of the data bit of the current memory block and data recorded in a counting base bit.

6. The monotonic counter of claim 1, wherein the parity bit of the special bit is used to determine validity.

7. The monotonic counter of claim 1, wherein the special bits comprise at least one of a count base bit, an identification bit, and a check bit of the memory block.

8. The monotonic counter of claim 1, wherein the plurality of memory blocks are in a same P-type doped well.

9. The monotonic counter of claim 1, wherein the number of memory blocks is two or four.

10. An operation method of a monotonic counter, applied to a monotonic counter, the monotonic counter including a plurality of memory blocks including special bits and data bits for storing count data, the operation method comprising:

a judging step of judging the validity of the special bit;

comparing, when all the special bits of the plurality of memory blocks are invalid, the number of erased bits in each of the special bits in the plurality of memory blocks;

and an erasing and repairing step, namely erasing and repairing the memory block with a large number of erased bits.

11. The method of claim 10, wherein the parity bits of the special bits are used to determine validity.

12. The method of claim 10, wherein the special bits comprise at least one of a count base bit, an identification bit, and a check bit of the memory block.

13. The method of operation of claim 10, further comprising, after the step of erase repairing:

a re-judgment step, which returns to execute the judgment step;

and a determining step, namely determining the storage block which is not subjected to the erasure repair as the current storage block when the special bit of the storage block which is not subjected to the erasure repair is valid.

14. The method of operation of claim 13, further comprising, after the determining step:

counting, namely writing data in a first data bit which does not store counting data in the current storage block for counting;

reading, namely reading a count value of the current storage block, wherein the count value is the sum of the data bit of the current storage block and the data recorded by the counting base bit.

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a monotonic counter and an operation method thereof.

Background

The Replay Protection Monotonic Counter (RPMC) is a Counter having a Monotonic counting function, and the Replay Protection Monotonic Counter is only monotonically increased along with a change in a count value after data counted in the Replay Protection Monotonic Counter is replied. Usually, the response protection monotonic counter is combined with FLASH (FLASH memory) to ensure confidentiality and integrity of read and write data during data storage. For example, the response protection monotonic counter is combined with the FLASH to determine the storage times of the memory, and when the FLASH reads and writes data once, a count value is added to the monotonic counter, so that a complete data record is provided for the read and write data times of the FLASH; for another example, in the data sending process, the data is counted monotonously, so that the non-repeatability of the data is ensured, and the confidentiality of data sending can be improved.

However, in the response protection monotonic counter in the prior art, when an abnormal condition occurs (such as abnormal power down, reset, unstable voltage, etc.), the monotonic counter may have an over-erase phenomenon, so that check bits of all storage blocks in the monotonic counter are invalid, and finally the monotonic counter cannot find a current storage block.

Disclosure of Invention

The invention provides a monotonic counter and an operation method thereof, which effectively solve the problem that the monotonic counter is excessively erased due to abnormal conditions, so that check bits of all storage blocks in the monotonic counter are invalid, and the current storage block cannot be found by the monotonic counter.

In order to solve the above problem, the present invention provides a monotonic counter comprising a controller and a plurality of memory blocks including special bits and data bits for storing count data, wherein the controller comprises:

a current storage block judgment module, configured to judge validity of the special bit to determine a current storage block from the plurality of storage blocks;

and the erasure repairing module is used for comparing the number of the erased bits in each special bit in the plurality of storage blocks and performing erasure repairing on the storage blocks with a large number of the erased bits when the special bits of the plurality of storage blocks are invalid.

Further preferably, the current storage block determination module further includes a re-determination submodule, configured to re-determine validity of the special bits of the plurality of storage blocks after the erasure patch.

Further preferably, when the re-judgment sub-module judges that the special bit of the memory block which is not subjected to the erasure correction is valid, the re-judgment sub-module is further configured to determine that the memory block which is not subjected to the erasure correction is the current memory block.

Further preferably, after determining the current memory block, the controller is further configured to write data in a first data bit of the current memory block, where the count data is not stored, for counting.

Further preferably, after the controller writes data in the first data bit of the current storage block, where the count data is not stored, for counting, the controller is further configured to read a count value of the current storage block, where the count value is a sum of the data bit of the current storage block and data recorded in a count base bit.

Further preferably, the check bit in the special bit is used for being judged to be valid.

Further preferably, the special bit includes at least one of a count base bit, an identification bit, and a check bit of the memory block.

Further preferably, the plurality of memory blocks are in the same P-type doped well.

Further preferably, the number of the memory blocks is two or four.

In another aspect, the present invention further provides an operation method of a monotonic counter, which is applied to the monotonic counter, wherein the monotonic counter includes a plurality of memory blocks, and each memory block includes a special bit and a data bit for storing count data, and the operation method includes:

a judging step of judging the validity of the special bit;

comparing, when all the special bits of the plurality of memory blocks are invalid, the number of erased bits in each of the special bits in the plurality of memory blocks;

and an erasing and repairing step, namely erasing and repairing the memory block with a large number of erased bits.

Further preferably, the check bit in the special bit is used for being judged to be valid.

Further preferably, the special bit includes at least one of a count base bit, an identification bit, and a check bit of the memory block.

Further preferably, after the step of erasing and repairing, the method further comprises:

a re-judgment step, which returns to execute the judgment step;

and a determining step, namely determining the storage block which is not subjected to the erasure repair as the current storage block when the special bit of the storage block which is not subjected to the erasure repair is valid.

Further preferably, after the determining step, the method may further include:

counting, namely writing data in a first data bit which does not store counting data in the current storage block for counting;

reading, namely reading a count value of the current storage block, wherein the count value is the sum of the data bit of the current storage block and the data recorded by the counting base bit.

The invention has the beneficial effects that: the invention provides a monotonic counter, which comprises a controller and a plurality of storage blocks, wherein each storage block comprises a special bit and a data bit for storing counting data, and the controller comprises: a current memory block judgment module for judging validity of the special bit to determine a current memory block from the plurality of memory blocks; and the erasure repairing module is used for comparing the number of the erased bits in each special bit in the plurality of memory blocks and performing erasure repairing on the memory blocks with large number when the special bits of the plurality of memory blocks are invalid, so that when the monotonic counter is excessively erased due to abnormal conditions, the monotonic counter can repair the memory blocks, and the monotonic counter can correctly perform subsequent operations. In order to further improve the stability of the system and ensure that the repair operation completes the error correction, as an optimal scheme, special bits of a memory block which is not subjected to erasure repair are checked, and when the special bits are valid, the memory block which is not subjected to erasure repair is determined to be the current memory block.

Drawings

In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the description of the embodiments according to the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without inventive effort.

Fig. 1 is a schematic diagram illustrating the relationship between memory cells in different operating states and corresponding voltages in a monotonic counter according to an embodiment of the present invention.

Fig. 2 is a schematic structural diagram of a memory block in the same P-type doped well in the monotonic counter according to the embodiment of the present invention.

Fig. 3 is a schematic structural diagram of a monotonic counter according to an embodiment of the present invention.

Fig. 4 is another schematic structural diagram of the monotonic counter according to the embodiment of the present invention.

Fig. 5 is a flow chart illustrating an operation method of the monotonic counter according to an embodiment of the present invention.

Fig. 6 is a schematic flow chart of a further method for operating a monotonic counter according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Flash memory (Flash) is the most common type of non-volatile memory at present, is a reliable data retention method, and is characterized in that data can be repeatedly read for a long time by once writing, and is not influenced by chip reset or power failure. The Replay Protection Monotonic Counter (RPMC) refers to a Counter having a Monotonic counting function. The response protection monotonic counter is combined with Flash, so that confidentiality and integrity of read-write data of the memory can be guaranteed.

Referring to fig. 1, fig. 1 is a schematic diagram illustrating a relationship between memory cells in different operating states and corresponding voltages in a monotonic counter according to an embodiment of the present invention. As shown in fig. 1, the threshold voltage (Vt) of the NOR Flash memory cell is a characteristic value of a state in which the NOR Flash is located. The NOR Flash cell structure determines that the operations for writing data into Flash include two steps of erasing (Erase) and programming (Program), wherein erasing is to lower the voltage of the memory cell to a certain positive voltage threshold range, and programming is to raise the voltage of the memory cell to a higher positive voltage threshold range according to the written value based on the erased voltage. The voltage threshold range of NOR Flash can be divided into 2 types according to the operation state: (1) writing a 1 state, which is embodied as that the voltage of the memory cell is within a certain positive voltage threshold range, and the reading value is '1'; (2) the write 0 state is characterized by the memory cell having a voltage within a voltage threshold range higher than the "write 1 state" and a read value of "0".

The memory cell is over-erased (over erase), which means that the voltage of the NOR Flash memory cell is erased to a certain voltage range that is too low, and specifically, as shown in fig. 2, the voltage threshold range that characterizes the memory cell in the "over-erased state" is lower than the voltage threshold range that characterizes the memory cell in the "write 1 state".

In Flash, a plurality of memory blocks (each having a plurality of memory cells) are usually configured in the same P-type doped well, and as shown in fig. 2, two memory blocks are configured in the same P-type doped well: when Flash performs an erase operation, voltage needs to be supplied to the P-type doped well, so that if a memory cell in the memory block 1 is over-erased, for example, the threshold voltage of the memory cell is pulled down to a too low negative value, so that a Bit Line (BL) where the memory cell is located generates leakage current, and reading of other memory cells on the Bit Line BL is in error. Since a plurality of memory blocks are disposed in the same P-type doped well, and memory cells on the same bit Line BL and on different Word Lines (WL) belong to different memory blocks, when the memory cells of the memory block 1 are over-erased, the reading of the memory cells in the memory block 2 is disturbed. If the memory cells in the same P-type doped well that are used to determine the validity of each memory block (i.e., memory block 1 and memory block 2) are disturbed, the current memory block that is performing the counting operation cannot be found by the response protection monotonic counter.

The invention aims at the problem that the monotone counter in the prior art is over-erased due to abnormal conditions, so that check bits of all storage blocks in the monotone counter are invalid, and the monotone counter cannot find a current storage block.

Referring to fig. 3, fig. 3 is a schematic structural diagram of the monotonic counter 100 according to the embodiment of the present invention, and it can be seen from fig. 3 that the components and the relative positions of the components according to the embodiment of the present invention are shown.

As shown in fig. 3, the monotonic counter 100 includes a controller 110 and a plurality of memory blocks 120, and each memory block 120 includes a plurality of special bits 121 and a plurality of data bits 122 for storing count data, wherein the controller 110 specifically includes:

a current memory block judgment module 111, the current memory block judgment module 111 being configured to judge validity of the special bit 121 to determine a current memory block from the plurality of memory blocks 120; and the number of the first and second groups,

an erase patch module 112, where the erase patch module 112 is configured to compare the number of erased bits in each of the special bits 121 in the plurality of memory blocks 120 when all the special bits 121 in the plurality of memory blocks 120 are invalid, and perform erase patch on the memory block 120 with the large number of erased bits.

Please refer to fig. 1, when an over erase phenomenon occurs in a memory cell of the memory block 1 due to an abnormal condition, the threshold voltage of the memory cell is lower than the threshold voltage of the memory cell in the erase state, and the erase repair is performed on the memory block 1 to raise the threshold voltage of the memory cell in the memory block 1 to the threshold voltage of the memory cell in the erase state.

After the memory block 1 is erased and repaired, the memory block 2 in the same P-type doped well is not affected by leakage current generated by overerasing of the memory block 1, and when the memory block 2 is read again, the read data is not abnormal.

Specifically, referring to fig. 4, fig. 4 is another schematic structural diagram of the monotonic counter 100 according to the embodiment of the present invention, as shown in fig. 4:

the special bits 121 include at least one of a count base bit 1211, an identification bit 1212, and check bits 1213 of the memory block 120, wherein the check bits 1213 are used to determine the validity of the special bits 121.

Further, because the count data is monotonically incremented due to the monotonicity of the Replay Protection Monotonic Counter (RPMC), when the memory block is switched to count, the data of the memory block before switching must be stored in the memory block after switching to be used as the basis for counting the memory block after switching, and the count base 1211 is used for recording the data counted when the previous memory block is fully written;

further, the data recorded in the flag bit 1212 is used to indicate whether the memory block 120 needs to be erased and programmed, specifically, the flag bit 1212 has only two data states, one data state indicates that the memory block 120 needs to be erased and programmed (e.g., 00), and one data state indicates that the memory block 120 has been erased and programmed and does not need to be erased and programmed (e.g., FF);

the validity of check bits 1213 is used to characterize whether the data in special bits 121 of memory block 120 is valid. Specifically, the count base 1211 and the flag bit 1212 generate a value through some check operation (such as an addition operation, a parity operation, an exclusive-or operation, or a cyclic redundancy check (cyclic redundancy check) operation), and then compare the value with the value in the check bit 1213, if the two values are equal, the flag bit 1213 is valid, that is, the data in the storage block 120 corresponding to the check bit 1213 is valid and has no exception; if the two values are not equal, the representation check bit 1213 is invalid, that is, the data in the storage block 120 corresponding to the check bit 1213 is invalid and an exception occurs;

the data bit 122 is a unit for storing count data, and generally, in order to increase the storage amount of the storage block 120 and reduce the number of times of erasing, each storage block 120 includes a plurality of data bits 122, and each time Flash corresponding to the monotonic counter 100 performs one data read/write operation, one data bit 122 of the storage block 120 in the monotonic counter 100 is written to be 1.

Referring to fig. 4, as shown in fig. 4, the current block determining module 111 further includes a re-determining sub-module 1111 for re-determining the validity of the special bits 121 of the plurality of memory blocks 120 after the erase repair.

Specifically, when the re-judgment sub-module 1111 judges that the special bit 121 of the memory block 120 not subjected to erase repair is valid, the re-judgment sub-module 1111 determines that the memory block 120 not subjected to erase repair is the current memory block.

Further, after performing the erasure correction and the redetermination operation once, the redetermination sub-module 1111 still does not find the storage block 120 with the valid special bit 121 from the storage block 120 without erasure correction, then the erasure correction module 112 will perform erasure correction on the storage block 120 with the largest number of erased bits, and then perform the redetermination operation until finding the storage block 120 with the valid special bit 121 as the current storage block.

Specifically, after determining the current storage block, the controller 110 is further configured to perform a counting step of the monotonic counter 100, that is, writing data into the first data bit 122 of the current storage block that does not store the counting data for counting, and then, the controller 110 is further configured to read a counting value of the current storage block of the monotonic counter 100, where the counting value is a sum of the data recorded in the data bit 122 and the counting base 1211 of the current storage block.

The counting value is the sum of the data recorded by the data bit 122 of the current memory block and the counting base 1211, which means that the value of the data bit 122 of the previous memory block is summed with the values in all the data bits.

In practical applications, the monotonic counter 100 is often used with a flash memory, and each time data is read or written by the flash memory, a 1 is written in the data bit in the current memory block of the monotonic counter 100, so that the value of all the data bits 122 plus the count base 1211 in one memory block 120 is equal to the count value at the current time. For example, the data bits 122 may represent n 0's by adding 1 to the count value of the monotonic counter 100 (n is an integer greater than or equal to 1), and when the count base bit of the monotonic counter 100 is 1000, n is 8, and the data bit has 0 of 3 bytes, then the count value of the monotonic counter 100 is 1003 at the current time.

Specifically, the plurality of memory blocks 120 in the monotonic counter 100 are in the same P-type doped well (i.e., the region doped with P-type impurities (e.g., B, Ga) in the substrate), and because the plurality of memory blocks 120 are in the same P-type doped well, when an over-erase (over-erase) occurs in a memory block 120 due to an interrupt, a leakage current may be generated in each region in the P-type doped well, thereby affecting the performance of the data reading operation of other memory blocks 120, for example, when an over-erase occurs in the P-type doped well corresponding to the check bit 1213, an error may occur in reading the check bit 1213 in the memory block 120, thereby causing the monotonic counter 100 to fail to find the current memory block, in this embodiment, since the erase repair module 112 performs erase repair on the over-erased memory block 120, the memory block 120 in the same P-type doped well may be recovered to be normal, thereby improving the problem that the monotonic counter 100 can not find the current memory block due to the occurrence of over-erase.

Preferably, the number of memory blocks 120 is 2 or 4.

Different from the prior art, the present invention provides a monotonic counter 100, which comprises a controller 110 and a plurality of memory blocks 120, wherein each memory block 120 comprises a plurality of special bits 121 and a plurality of data bits 122 for storing count data, wherein the controller 110 comprises: a current memory block judgment module 111 for judging validity of the special bit 121 to determine a current memory block from the plurality of memory blocks 120; and an erasure patch module 112 for comparing the number of erased bits in each special bit 121 of the plurality of memory blocks 120 and performing erasure patch on the memory block 120 with the large number of erased bits when all the special bits 121 of the plurality of memory blocks 120 are invalid, so that when an abnormal condition occurs and the monotonic counter 100 is excessively erased, the monotonic counter 100 can patch the memory block 120 and find the current memory block which performs storage counting at the current time, so that the monotonic counter 100 can correctly perform subsequent operations. In order to further improve the stability of the system and ensure that the repair operation has completed correcting the error, it is preferable to check the special bit 121 of the memory block 120 that is not erase-repaired, and when the special bit 121 is valid, determine that the memory block 120 that is not erase-repaired is the current memory block.

Referring to fig. 5, fig. 5 is a schematic flowchart of an operation method of the monotonic counter 100 according to the embodiment of the present invention, the operation method is applied to the monotonic counter 100, and the monotonic counter 100 includes a plurality of memory blocks, each memory block includes a plurality of special bits and a plurality of data bits for storing count data, and the specific flow of the operation method can be as follows:

a judging step S1O1, judging the validity of the special bit;

a comparison step S1O2, when the special bits of the plurality of memory blocks are invalid, comparing the number of the erased bits in each special bit of the plurality of memory blocks;

the erase repair step s1o3 performs erase repair on the memory block having the large number of erased bits.

Specifically, the comparison step S1O2 and the erase repair step S1O3 are performed by the erase repair module 112 in the controller 110 of the monotonic counter 100.

Referring to fig. 6, fig. 6 is a schematic flow chart of a further operation method of the monotonic counter 100 according to the embodiment of the present invention, as shown in fig. 6, after the erase repairing step S1O3, the method further includes:

a re-judgment step S1O4. returning to the execution judgment step;

step S1O5 is determined, when the special bit of the memory block which is not subjected to the erasure repairing is valid, the memory block which is not subjected to the erasure repairing is determined to be the current memory block.

Specifically, after performing the erase-patch step S1O3 and returning to the step S1O4 once, if the monotonic counter 100 still does not find the memory block with valid special bits from the memory block without erase-patch, the monotonic counter 100 will perform the comparison step S1O2, the erase-patch step S1O3 and returning to the step S1O4 once again until the memory block with valid special bits is found as the current memory block in the step S1O5.

Further, the special bit includes at least one of a count base bit, an identification bit and a check bit of the memory block, and the check bit is used for judging the validity of the special bit. Furthermore, the counting base bit is used for recording data counted when the last current storage block is fully written, the check bit is used for verifying whether data reading in the storage block is correct, and the data bit is a unit for storing the counting data.

With continuing reference to fig. 6, after determining step S1O5, the method may further include:

a counting step S1O6, writing data into a first data bit which does not store counting data in the current storage block for counting;

reading step S1O7, reading the count value of the current storage block, wherein the count value is the sum of the data bit of the current storage block and the data recorded by the counting base bit.

The count value is the sum of the data bits of the current memory block and the data recorded in the count base bit, which means that the value of the data bits of the previous memory block is summed with the values in all the data bits. In practical applications, the monotonic counter is often used with a flash memory, and each time the flash memory reads and writes data, 1 is written in a data bit in a current storage block of the monotonic counter, so that the value of all data bits in one storage block plus a count base bit is equal to a count value at the current time. For example, the data bits may represent n 0's for the count value of the monotonic counter 100 plus 1, and when the count base bit of the monotonic counter 100 is 1000, n is 8, and the data bits have 0's of 3 bytes, then the count value of the monotonic counter 100 is 1003 at the current time.

Preferably, the number of memory blocks 120 is 2 or 4.

Different from the prior art, the present invention provides an operation method of a monotonic counter 100, the operation method is applied to the monotonic counter 100, and the monotonic counter 100 includes a plurality of memory blocks, each memory block includes a plurality of special bits and a plurality of data bits for storing count data, the operation method includes: judging the validity of the special bits, comparing the number of erased bits in each special bit in the plurality of memory blocks when the special bits of the plurality of memory blocks are invalid, and then performing erase repair on the memory blocks with the large number of erased bits, so that when the monotonic counter 100 is excessively erased due to an abnormal condition, the monotonic counter 100 can repair the memory blocks and find the current memory block which performs memory counting at the current time, so that the monotonic counter 100 can correctly perform subsequent operations. In order to further improve the stability of the system and ensure that the repair operation has completed correcting the error, it is preferable to check the special bit 121 of the memory block 120 that is not erase-repaired, and when the special bit 121 is valid, determine that the memory block 120 that is not erase-repaired is the current memory block.

In addition to the above embodiments, the present invention may have other embodiments. All technical solutions formed by using equivalents or equivalent substitutions fall within the protection scope of the claims of the present invention.

In summary, although the preferred embodiments of the present invention have been described above, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.