阅读说明：本技术 电子装置 (Electronic device ) 是由 陈巍中 郭文瑜 冯捷威 王泰瑞 于 2020-09-22 设计创作，主要内容包括：本发明提供一种电子装置,包括像素阵列结构、重布线结构以及多个导电通孔结构。像素阵列结构包括多条信号线。重布线结构与像素阵列结构重叠设置且包括多条导线。多个导电通孔结构将像素阵列结构的多条信号线与重布线结构的多条导线电连接。多个导电通孔结构中的至少一个与像素阵列结构共用至少一层导电层。(The invention provides an electronic device which comprises a pixel array structure, a rewiring structure and a plurality of conductive through hole structures. The pixel array structure includes a plurality of signal lines. The rewiring structure is overlapped with the pixel array structure and comprises a plurality of wires. The plurality of conductive via structures electrically connect the plurality of signal lines of the pixel array structure with the plurality of conductive lines of the rewiring structure. At least one of the plurality of conductive via structures shares at least one conductive layer with the pixel array structure.)

1. An electronic device, comprising:

a pixel array structure including a plurality of signal lines;

a rewiring structure overlapping with the pixel array structure and including a plurality of wires; and

and a plurality of conductive via structures electrically connecting the plurality of signal lines of the pixel array structure and the plurality of conductive lines of the rewiring structure, wherein at least one of the plurality of conductive via structures shares at least one conductive layer with the pixel array structure.

2. The electronic device of claim 1, wherein the pixel array structure further comprises a plurality of sub-pixels, and two adjacent rows of sub-pixels share a signal line, and the signal line is electrically connected to at least one conductive via structure.

3. The electronic device of claim 1, further comprising at least one of a data demultiplexer, a shift register unit, and a gate drive circuit.

4. The electronic device of claim 1, further comprising:

the pixel array structure comprises a plurality of simulation conductive through hole structures, wherein at least one of the simulation conductive through hole structures and the pixel array structure share at least one conductive layer, the pixel array structure further comprises a plurality of sub-pixels, and each sub-pixel is provided with at least one of one conductive through hole structure and one simulation conductive through hole structure.

5. The electronic device of claim 1, wherein the pixel array structure further comprises a plurality of sub-pixels and a plurality of stretchable electrodes, at least one of the stretchable electrodes being located at an interface of two adjacent sub-pixels and connecting two portions of a same signal line located in the two adjacent sub-pixels.

6. The electronic device of claim 1, further comprising:

a substrate, wherein the pixel array structure and the rewiring structure are disposed on the substrate; and

and the element layer is arranged on the substrate and is overlapped with the pixel array structure and the rewiring structure.

7. The electronic device according to claim 6, wherein the element layer comprises a display medium layer or a photoelectric conversion layer.

8. The electronic device of claim 6, wherein the pixel array structure and the redistribution structure are disposed on opposite surfaces of the substrate, respectively, and the plurality of conductive via structures extend through the substrate to electrically connect the plurality of signal lines of the pixel array structure with the plurality of conductive lines of the redistribution structure, wherein the element layer is disposed on a side of the pixel array structure away from the substrate.

9. The electronic device of claim 6, wherein the pixel array structure is located between the redistribution structure and the substrate, and

wherein the element layer is located between the redistribution structure and the pixel array structure, or the redistribution structure is located between the element layer and the pixel array structure, or the substrate is located between the element layer and the pixel array structure.

10. The electronic device of claim 1, wherein the electronic device comprises a plurality of the pixel array structures, the plurality of the pixel array structures comprises a first pixel array structure and a second pixel array structure, and the first pixel array structure is located between the second pixel array structure and the redistribution structure,

wherein the multiple wires of the rewiring structure include multiple first wires and multiple second wires, the multiple conductive via structures include multiple first conductive via structures and multiple second conductive via structures, and

wherein a plurality of signal lines in the first pixel array structure are electrically connected to the plurality of first conductive lines of the redistribution structure through the plurality of first conductive via structures, and a plurality of signal lines in the second pixel array structure are electrically connected to the plurality of second conductive lines of the redistribution structure through the plurality of second conductive via structures.

11. The electronic device of claim 1, wherein the at least one of the plurality of conductive via structures shares a first conductive layer and a second conductive layer in the pixel array structure with the pixel array structure.

12. The electronic device of claim 1, wherein each signal line in the pixel array structure is electrically connected to a corresponding one of the conductive lines in the redistribution structure through at least one conductive via structure.

13. The electronic device of claim 1, wherein the plurality of conductive lines of the rewiring structure at least partially overlap the plurality of signal lines of the pixel array structure.

14. The electronic device of claim 1, further comprising:

and the driving circuit is overlapped with the pixel array structure and the rewiring structure and is electrically connected with the signal wires of the pixel array structure through the wires of the rewiring structure and the conductive through hole structures.

15. The electronic device of claim 1, wherein at least one of the plurality of conductive via structures satisfies:

S1≤S≤S2；

s1 ═ 2 × d × cot θ + a 1; and

S2＝(25400/PPI]-a2，

wherein S is the maximum dimension of the at least one conductive via structure, d is the thickness of the conductive via with the maximum thickness in the at least one conductive via structure, θ is the included angle between the side wall surface of the conductive via at the narrow end and the contact surface at the narrow end outside the conductive via with the maximum thickness, a1 is the contact width of the conductive via at the narrow end, PPI is pixel density, and a2 is the pitch of the conductive lines of the rewiring structure.

Technical Field

The present invention relates to an electronic device.

Background

The driving circuit in the electronic device is generally disposed at the periphery of the active region, and the signal line in the active region is electrically connected to the driving circuit through a peripheral line disposed at the periphery of the active region. The peripheral circuits occupy a certain layout area, so that the electronic device cannot easily achieve a narrow frame design. In addition, as the size or resolution of the electronic device is increased, the problem of resistance-capacitance loading (RC loading) is easily caused by the overlong peripheral circuit, and the uniformity of performance of the electronic device is affected, for example, the uniformity of brightness or electrical performance is not good.

Disclosure of Invention

An embodiment of the invention provides an electronic device, which is helpful for realizing the design of a narrow frame or improving the problem of resistance-capacitance load.

An electronic device according to an embodiment of the invention includes a pixel array structure, a redistribution structure, and a plurality of conductive via structures. The pixel array structure includes a plurality of signal lines. The rewiring structure is overlapped with the pixel array structure and comprises a plurality of wires. The plurality of conductive via structures electrically connect the plurality of signal lines of the pixel array structure with the plurality of conductive lines of the rewiring structure. At least one of the plurality of conductive via structures shares at least one conductive layer with the pixel array structure.

In order to make the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

Fig. 1 to fig. 3 are a partial perspective view, a partial cross-sectional view and a partial top view of an electronic device according to a first embodiment of the invention;

fig. 4 to 6 are schematic partial top views of electronic devices according to second to fourth embodiments of the invention, respectively;

FIGS. 7A-7C are circuit diagrams of the shift register unit SR 1-SR 3 in FIG. 6, respectively;

fig. 8 and 9 are a partial top view and a partial cross-sectional view of an electronic device according to a fifth embodiment of the invention;

fig. 10 is a schematic partial top view of an electronic device according to a sixth embodiment of the invention;

fig. 11 to 13 are schematic partial cross-sectional views of electronic devices according to seventh to ninth embodiments of the invention, respectively;

fig. 14 and fig. 15 are a partial perspective view and a partial cross-sectional view of an electronic device according to a tenth embodiment of the invention;

fig. 16 and 17 are a partial cross-sectional view and a partial top view of an electronic device according to an eleventh embodiment of the invention.

Description of the reference numerals

1. 1A-1J: an electronic device;

10. 10G, 10J: a pixel array structure;

10-1: a first pixel array structure;

10-2: a second pixel array structure;

100. 120, 120G: a buffer layer;

101: a semiconductor layer;

102: a gate insulating layer;

103: a first conductive layer;

104. 121: a first insulating layer;

105: an intermediate conductive layer;

106. 123: a second insulating layer;

107: a second conductive layer;

108: a third insulating layer;

109: a fourth insulating layer;

109G: an insulating layer;

110: a third conductive layer;

110G, 110H: a conductive layer;

111: a stretchable electrode;

12. 12G: a rewiring structure;

122: a first rewiring conductive layer;

124: a second redistribution conductive layer;

1220. 1240 and CL: a wire;

13. 13A-13G: a conductive via structure;

13-1: a first conductive via structure;

13-2: a second conductive via structure;

13X: simulating a conductive through hole structure;

16. 26: a substrate;

18. 28: an element layer;

20: a drive circuit;

22: a data demultiplexer;

24: a gate drive circuit;

30: a bonding layer;

AE. AD 1: an active element;

BE: a lower electrode;

c: a capacitor;

CH: a channel pattern;

CL-1: a first conductive line;

CL-2: a second conductive line;

CLK, XCLK, INPUT, OUTPUT, VGH, VGL: a signal line;

CP1, CP 2: a conductive pattern;

CT: a connecting member;

CV1-CV4, CV1A, CV1G, CV1H, CV4F, CV 4G: a conductive via;

d1: a first direction;

d2: a second direction;

d3: a third direction;

DE. DE 1: a drain electrode;

DL: a data line;

GE. GE 1: a gate electrode;

MP: an intermediate pattern;

PL: a power line;

PE, PEG, PEH: a pixel electrode;

SE, SE 1: a source electrode;

SL: scanning a line;

SP: a sub-pixel;

SR1, SR2, SR 3: a shift register unit;

TE: an upper electrode;

TP: an upper layer pattern;

θ: and (4) an included angle.

Detailed Description

Directional phrases used herein include, for example: "upper", "lower", "front", "rear", "left", "right", etc., refer only to the orientation of the figures. Accordingly, the directional terminology is used for purposes of illustration and is in no way limiting.

In the drawings, which illustrate general features of methods, structures, and/or materials used in certain embodiments. These drawings, however, should not be construed as defining or limiting the scope or nature encompassed by these embodiments. For example, the relative sizes, thicknesses, and locations of various layers, regions, or structures may be reduced or exaggerated for clarity, and/or portions of elements or layers may be omitted.

The terms "first", "second", and the like in the description or in the claims are only used for naming different elements or distinguishing different embodiments or ranges, and are not used for limiting the upper limit or the lower limit of the number of the elements, nor are they used for limiting the manufacturing sequence or the arrangement sequence of the elements. Further, an element/layer being disposed on (or over) another element/layer can encompass instances where the element/layer is disposed directly on (or over) the other element/layer, and the two elements/layers are in direct contact; and where the element/layer is disposed indirectly on (or over) the other element/layer, and one or more elements/layers are present between the two elements/layers.

Fig. 1 to fig. 3 are a partial perspective view, a partial cross-sectional view, and a partial top view of an electronic device according to a first embodiment of the invention. Referring to fig. 1, the electronic device 1 may include, but is not limited to, a pixel array structure 10, a redistribution structure 12, and a plurality of conductive via structures 13.

The pixel array structure 10 includes a plurality of signal lines, such as a plurality of scan lines SL and a plurality of data lines DL, but is not limited thereto. The scan lines SL and the data lines DL intersect with each other to define a plurality of sub-pixels SP. Each sub-pixel SP may include a scan line SL and a data line DL. However, the relative arrangement relationship of the scan lines SL, the data lines DL and the sub-pixels SP or the number of the scan lines SL and the data lines DL included in each sub-pixel SP may be changed as required.

The rewiring structure 12 is provided to overlap the pixel array structure 10. In other words, the redistribution structure 12 and the pixel array structure 10 overlap each other in the thickness direction of the electronic device 1 (e.g., the third direction D3). The rerouting structure 12 may include a plurality of conductive lines CL. In some embodiments, as shown in fig. 1, the conductive lines CL of the rewiring structure 12 may at least partially overlap the signal lines (e.g., the data lines DL and the scan lines SL) of the pixel array structure 10, so as to maintain the aperture ratio or the light transmittance of the electronic device 1. Any of the embodiments of the present invention may combine the technical means described herein (i.e., the plurality of conductive lines CL may at least partially overlap the plurality of signal lines) without conflict, and will not be repeated below.

The plurality of conductive via structures 13 electrically connect a plurality of signal lines (e.g., a plurality of data lines DL) of the pixel array structure 10 with a plurality of conductive lines CL of the rewiring structure 12. Specifically, the conductive via structure 13 may include a plurality of conductive structures stacked in a thickness direction (e.g., the third direction D3) of the electronic device 1. One of the conductive structures of the conductive via structures 13 may be connected with a corresponding signal line, and the other of the conductive structures of the conductive via structures 13 may be connected with a corresponding conductive line CL. In some embodiments, at least one of the conductive via structures 13 and at least one of the conductive structures in the pixel array structure 10 may be patterned from the same conductive layer. In other words, at least one of the plurality of conductive via structures 13 may share at least one conductive layer with the pixel array structure 10.

In some embodiments, the electronic device 1 may further include a driving circuit 20. The driving circuit 20 overlaps the pixel array structure 10 and the redistribution structure 12, and the driving circuit 20 can be electrically connected to a plurality of signal lines (e.g., a plurality of data lines DL) of the pixel array structure 10 through the plurality of conductive lines CL of the redistribution structure 12 and the plurality of conductive via structures 13.

The signal lines of the pixel array structure 10 can receive signals from the driving circuit 20 through the conductive lines CL of the redistribution structure 12 and the conductive via structures 13, and the electronic device 1 does not need to provide peripheral lines around the active region (the region where the sub-pixels SP are located), thereby facilitating the design of a full-narrow frame. In addition, as the size or resolution of the electronic device is increased, a proper signal transmission path can be provided by the design (such as size, number or position) of at least one of the conductive via structure 13, the conductive line CL and the driving circuit 20, which further helps to improve the rc loading problem. In some embodiments, the electronic device 1 may be applied to a borderless mobile phone, a borderless tablet, or an ultra-narrow-sided desktop display. In some embodiments, when the electronic device 1 has a requirement of high light transmittance (e.g., for a transparent display), a miniature driving circuit 20 may be used to reduce the visibility of the driving circuit 20. In some embodiments, the electronic device 1 may also be applied to replaceable display modules of large-sized tiled displays.

Fig. 1 schematically illustrates the conductive via structures 13 in rectangular boxes, wherein each data line DL can be electrically connected to the driving circuit 20 through more than one conductive via structures 13 (the upper and lower layers can be the same conductive via or different conductive vias) and more than one conductive line CL. In the structure in which one data line DL is electrically connected to a plurality of conductive via structures 13, two conductive via structures 13 electrically connected to the same data line DL may be respectively located in the sub-pixels SP at opposite ends of the data line DL. However, the top view shape of the conductive via structures 13, the number of the conductive via structures 13 electrically connected to each signal line, the number of the conductive lines CL electrically connected to each signal line, or the positions of the conductive via structures 13 in the sub-pixel array may be changed as required, and other signal lines (e.g., the scan lines SL) in the pixel array structure 10 may also be electrically connected to the driving circuit 20 through the conductive via structures 13 and the conductive lines CL.

In some embodiments, as shown in fig. 2, the electronic device 1 may further include a substrate 16 and an element layer 18. However, the electronic device 1 may further include other elements/layers or omit at least one of the above elements/layers according to different requirements.

The substrate 16 is used for carrying components, for example, and the substrate 16 may be a rigid substrate or a flexible substrate. For example, the material of the rigid substrate may be glass, wafer, quartz or other hard materials, and the flexible substrate may be polyethylene terephthalate (PET), Polyimide (PI), Polycarbonate (PC), Polyamide (PA), polyethylene naphthalate (PEN), Polyethyleneimine (PEI), Polyurethane (PU), Polydimethylsiloxane (PDMS), acrylic (acrylic) polymer such as polymethyl methacrylate (PMMA), etc., ether (ether) polymer such as polyether sulfone (PES) or polyether ether ketone (PEEK), polyolefin (polyeffesin), thin glass or other flexible materials, but not limited thereto.

The pixel array structure 10 may be disposed on a substrate 16. In some embodiments, as shown in fig. 2, the pixel array structure 10 may include a buffer layer 100, a semiconductor layer 101, a gate insulating layer 102, a first conductive layer 103, a first insulating layer 104, an intermediate conductive layer 105, a second insulating layer 106, a second conductive layer 107, a third insulating layer 108, a fourth insulating layer 109, and a third conductive layer 110. However, according to different requirements, the pixel array structure 10 can adjust the relative position relationship between the elements/layers, or further include other elements/layers or omit at least one of the elements/layers.

A buffer layer 100, a semiconductor layer 101, a gate insulating layer 102, a first conductive layer 103, a first insulating layer 104, an intermediate conductive layer 105, a second insulating layer 106, a second conductive layer 107, a third insulating layer 108, a fourth insulating layer 109, and a third conductive layer 110 are formed on the substrate 16, for example, in this order. The manufacturing method, materials and relative arrangement relationship of the above-mentioned multiple layers can be configured according to the requirement, and are not limited herein.

In fig. 2, the pixel array structure 10 may include four conductive layers, such as a first conductive layer 103, an intermediate conductive layer 105, a second conductive layer 107, and a third conductive layer 110. In some embodiments, the materials of the first conductive layer 103, the intermediate conductive layer 105, and the second conductive layer 107 may include metals, but are not limited thereto, based on conductivity or signal transmission efficiency considerations. In addition, the material of the third conductive layer 110 may include a light-transmitting conductive material, based on consideration of an aperture ratio or light transmittance, but is not limited thereto. The pixel array structure 10 can increase or decrease the number of conductive layers according to different requirements. For example, the pixel array structure 10 may not include the intermediate conductive layer 105, and the second conductive layer 107 may be disposed on the second insulating layer 106 (as shown in fig. 11).

In fig. 2, the semiconductor layer 101 may be a patterned semiconductor layer and include a plurality of channel patterns CH (one channel pattern CH is schematically illustrated in fig. 2). The first conductive layer 103 may BE a patterned conductive layer and include a plurality of scan lines SL (refer to fig. 3), a plurality of gate electrodes GE (one gate electrode GE is schematically illustrated in fig. 2), a plurality of lower electrodes BE (one lower electrode BE is schematically illustrated in fig. 2), and a plurality of intermediate patterns MP (one intermediate pattern MP is schematically illustrated in fig. 2). In other words, the plurality of scan lines SL, the plurality of gate electrodes GE, the plurality of lower electrodes BE, and the plurality of intermediate patterns MP belong to the same layer. The intermediate conductive layer 105 may be a patterned conductive layer and includes a plurality of upper electrodes TE (one upper electrode TE is schematically illustrated in fig. 2). The second conductive layer 107 may be a patterned conductive layer and include a plurality of data lines DL (refer to fig. 3), a plurality of power lines PL (refer to fig. 3), a plurality of source electrodes SE (fig. 2 schematically illustrates one source electrode SE), a plurality of drain electrodes DE (fig. 2 schematically illustrates one drain electrode DE), and a plurality of upper patterns TP (fig. 2 schematically illustrates one upper pattern TP). In other words, the plurality of data lines DL, the plurality of power lines PL, the plurality of source electrodes SE, the plurality of drain electrodes DE, and the plurality of upper patterns TP belong to the same layer. In other embodiments, the plurality of data lines DL and the plurality of power lines PL may belong to different layers, for example, the plurality of power lines PL may be fabricated together with the plurality of upper electrodes TE, i.e., the plurality of power lines PL may belong to the same layer as the plurality of upper electrodes TE. The third conductive layer 110 may be a patterned conductive layer and includes a plurality of pixel electrodes PE (one pixel electrode PE is schematically illustrated in fig. 2).

The pixel array structure 10 may include a plurality of active elements AE (one active element AE is schematically illustrated in fig. 2). Each active element AE may include, but is not limited to, a channel pattern CH, a gate electrode GE, a source electrode SE, and a drain electrode DE. As shown in fig. 2, the source electrode SE may be electrically connected to the corresponding channel pattern CH through a conductive via CV1 passing through the gate insulating layer 102, the first insulating layer 104, and the second insulating layer 106. In addition, the drain electrode DE may be electrically connected to the corresponding channel pattern CH through another conductive via CV 1. In addition, the drain electrode DE may be electrically connected to the corresponding pixel electrode PE through a conductive via CV1A penetrating through the third insulating layer 108 and the fourth insulating layer 109. However, the type of the active element AE and the relative arrangement relationship of each element in the active element AE may be changed according to the requirement, and is not limited to the illustration in fig. 2. For example, the active element AE may be an amorphous Silicon thin film transistor (a-Si TFT), a Low Temperature Polysilicon (LTPS) TFT, a High Temperature Polysilicon (HTPS) TFT, or an oxide TFT, but is not limited thereto.

The pixel array structure 10 may further include a plurality of capacitors C (one capacitor C is schematically shown in fig. 2). Each capacitor C may comprise a lower electrode BE and an upper electrode TE. In some embodiments, the upper electrode TE may be electrically connected with the corresponding source electrode SE through a conductive via CV2 passing through the second insulating layer 106.

Fig. 3 schematically shows the relative arrangement relationship of a plurality of signal lines (e.g., a plurality of scan lines SL, a plurality of data lines DL, and a plurality of power lines PL) and a plurality of sub-pixels SP in the pixel array structure 10. As shown in fig. 3, each scan line SL may extend in the first direction D1, and a plurality of scan lines SL may be arranged in the second direction D2. The first direction D1 and the second direction D2 intersect each other and are perpendicular to the thickness direction of the electronic device 1 (e.g., the third direction D3). The first direction D1 and the second direction D2 may be perpendicular to each other, but are not limited thereto. Each data line DL may extend in the second direction D2, and a plurality of data lines DL may be arranged in the first direction D1. Each power line PL may extend in the second direction D2, and a plurality of power lines PL may be arranged in the first direction D1. As shown in fig. 3, the plurality of data lines DL and the plurality of power lines PL may be alternately arranged in the first direction D1, but are not limited thereto. In other embodiments, the plurality of signal lines may further include traces for other purposes, such as, but not limited to, repair lines (not shown) or common electrode lines (not shown).

Fig. 3 schematically shows nine sub-pixels SP in a thick solid line. The nine sub-pixels SP are arranged in a rectangular array in the first direction D1 and the second direction D2. However, the number of the sub-pixels SP and the arrangement thereof may vary according to the requirement (e.g. the shape of the active area of the electronic device 1). For example, the plurality of sub-pixels SP may be arranged in a non-rectangular array (e.g., a circle, other polygon, irregular shape, etc.). In some embodiments, each sub-pixel SP may include a scan line SL, a data line DL, and a power line PL. However, the number of scan lines SL, the number of data lines DL, and the number of power lines PL in each sub-pixel SP or the relative arrangement relationship between each sub-pixel SP and the corresponding signal lines may be changed as required.

Referring to fig. 2 again, the device layer 18 may be disposed on the substrate 16 and overlap the pixel array structure 10 and the redistribution structure 12. In some embodiments, as shown in fig. 2, the element layer 18 may be disposed on a side of the pixel array structure 10 away from the substrate 16, such as on the third conductive layer 110, but is not limited thereto. In some embodiments, the device layer 18 may include a display medium layer, such as, but not limited to, a liquid crystal layer or an electrophoretic layer. Correspondingly, the electronic device 1 may provide a display function. In other embodiments, the element layer 18 may include a photoelectric conversion layer. For example, the element layer 18 may include an Organic Light Emitting Diode (OLED), a sub-millimeter Light Emitting Diode (mini LED), a micro Light Emitting Diode (micro LED), or a photo sensing element (PD), but is not limited thereto. Correspondingly, the electronic device 1 may provide an illumination function, a display function, or a light sensing function.

The redistribution structure 12 may be disposed on a substrate 16. In some embodiments, the pixel array structure 10 and the redistribution structure 12 are disposed on opposite surfaces of the substrate 16, respectively, but are not limited thereto. In some embodiments, as shown in fig. 2, the redistribution structure 12 may include a buffer layer 120, a first insulating layer 121, a first redistribution conductive layer 122, a second insulating layer 123, and a second redistribution conductive layer 124. However, the redistribution structure 12 may further include other elements/layers or omit at least one of the above elements/layers according to different requirements.

The buffer layer 120, the first insulating layer 121, the first redistribution conductive layer 122, the second insulating layer 123, and the second redistribution conductive layer 124 are, for example, sequentially formed on the substrate 16. For example, after the pixel array structure 10 and the element layer 18 are formed, the substrate 16 may be inverted, and the buffer layer 120, the first insulating layer 121, the first redistribution conductive layer 122, the second insulating layer 123, and the second redistribution conductive layer 124 are sequentially formed. The manufacturing method, materials and relative arrangement relationship of the above-mentioned multiple layers can be configured according to the requirement, and are not limited herein.

In fig. 2, the redistribution structure 12 may include two conductive layers, such as a first redistribution conductive layer 122 and a second redistribution conductive layer 124. In some embodiments, the material of the first and second redistribution conductive layers 122 and 124 may include a metal, but is not limited thereto, based on considerations of conductivity or signal transmission efficiency. The redistribution structure 12 may increase or decrease the number of conductive layers according to different requirements.

The first redistribution layer 122 may be a patterned conductive layer and includes a plurality of conductive lines 1220 (one conductive line 1220 is schematically illustrated in fig. 2). The second redistribution conductive layer 124 may be a patterned conductive layer and includes a plurality of wires 1240 (one wire 1240 is schematically illustrated in fig. 2). In some embodiments, the conductive line 1220 is electrically connected to the corresponding middle pattern MP by passing through the first insulating layer 121, the buffer layer 120, the substrate 16, the buffer layer 100 and the conductive via CV4 of the gate insulating layer 102. The method for manufacturing the conductive via CV4 may include, for example, drilling (such as, but not limited to, laser drilling), wet etching, dry etching, or dry-wet hybrid etching, to form a via penetrating through the first insulating layer 121, the buffer layer 120, the substrate 16, the buffer layer 100, and the gate insulating layer 102, and then filling the material of the first redistribution conductive layer 122 into the via when forming the first redistribution conductive layer 122. In addition, the conductive lines 1240 may be electrically connected to the corresponding conductive lines 1220 through the conductive vias CV5 penetrating the second insulating layer 123.

In some embodiments, as shown in fig. 2, at least one conductive via structure 13 of the plurality of conductive via structures 13 of the electronic device 1 may include, but is not limited to, an upper pattern TP, a conductive via CV3, an intermediate pattern MP, and a conductive via CV 4. In other embodiments, the conductive via structure 13 may not include the middle pattern MP and the conductive via CV3, and the conductive via CV4 may further penetrate through the first insulating layer 104 and the second insulating layer 106. In the configuration where the conductive via structure 13 includes the middle pattern MP and the conductive via CV3, the conductive via CV4 may not further penetrate the first insulating layer 104 and the second insulating layer 106, thereby helping to reduce the size of the conductive via CV4 (e.g., the thickness of the conductive via CV4 in the third direction D3) or reduce the manufacturing time, material usage, or manufacturing difficulty of the conductive via CV 4.

In some embodiments, the upper pattern TP and the conductive via CV3 in the conductive via structure 13 may BE fabricated together with the source electrode SE, the drain electrode DE, the conductive via CV1 and the conductive via CV2 in the pixel array structure 10, and the middle pattern MP in the conductive via structure 13 may BE fabricated together with the gate electrode GE and the lower electrode BE in the pixel array structure 10, that is, the conductive via structure 13 may share at least one conductive layer (e.g., the first conductive layer 103 and the second conductive layer 107) with the pixel array structure 10. On the other hand, the conductive via CV4 in the conductive via structure 13 can be fabricated together with the conductive line 1220 of the redistribution structure 12, and therefore, the conductive via structure 13 can also share at least one conductive layer (e.g., the first redistribution conductive layer 122) with the redistribution structure 12.

The driving circuit 20 may be disposed on the second redistribution conductive layer 124 of the redistribution structure 12 and connected to the corresponding wire 1240. The driving circuit 20 may include an integrated circuit, but is not limited thereto.

In each sub-pixel SP, the maximum dimension S of the conductive via structure 13 is determined by, for example, the conductive via (e.g., the conductive via CV4) with the largest thickness in the conductive via structure 13. In some embodiments, the maximum dimension S of the conductive via structure 13 (e.g., the maximum width of the conductive via CV4 in the first direction D1) may be greater than or equal to S1 and less than or equal to S2, i.e., S1 ≦ S2. S1 ═ 2 × d × cot θ + a1, and S2 ═ (25400/PPI) -a 2. In the above equation, D is the thickness of the conductive via (e.g., the thickness of the conductive via CV4 in the third direction D3), θ is the angle between the sidewall surface of the conductive via at the narrow end and the contact surface at the narrow end outside the conductive via (see fig. 2), a1 is the contact width of the conductive via at the narrow end (e.g., the maximum contact width of the conductive via CV4 in the first direction D1), PPI is the sub-pixel density (sub-pixel pitch), and a2 is the CL pitch of the conductive lines of the redistribution structure 12 (e.g., the maximum pitch in the first direction D1). In some embodiments, a1 is ≧ 2 μm, and a2 is ≧ 2 μm.

Other embodiments of the electronic device of the present invention are described below with reference to other drawings. In the following embodiments, the same or similar elements will be denoted by the same or similar reference numerals, and the detailed description thereof will be omitted. Furthermore, the features of the different exemplary embodiments may be combined with each other without conflict and simple equivalent changes and modifications made in the present specification or claims may still fall within the scope of the present patent.

Fig. 4 is a schematic partial top view of an electronic device according to a second embodiment of the invention. Referring to fig. 4, in the electronic device 1A, two adjacent rows of sub-pixels SP (e.g., the left six sub-pixels SP in fig. 4) share one signal line (e.g., the middle power line PL in fig. 4), and the one signal line (e.g., the middle power line PL in fig. 4) is electrically connected to at least one conductive via structure 13. By the design of the common signal line, the number of the conductive via structures 13 is reduced, and the aperture ratio or the light transmittance of the electronic device 1A is improved. In some embodiments, the conductive via structure 13 may be disposed between adjacent four sub-pixels SP (as indicated by the thick dashed line frame) to reduce the shielding rate of each of the four sub-pixels SP, but not limited thereto. In other embodiments, a plurality of signal lines (e.g., a plurality of power lines PL or a plurality of common electrode lines not shown) may also share one or more conductive via structures 13, and the plurality of signal lines may be electrically connected to each other through a connection line (not shown) to reduce the number of conductive via structures 13, thereby improving the aperture ratio or light transmittance of the electronic device 1A. Any embodiment of the present invention may be combined with any of the technical means described herein without conflict and will not be repeated hereinafter.

Fig. 5 is a schematic partial top view of an electronic device according to a third embodiment of the invention. Referring to fig. 5, the electronic device 1B may utilize the circuit design of the data demultiplexer 22 to reduce the number of the conductive via structures 13, thereby improving the aperture ratio or the light transmittance of the electronic device 1B. For example, the gates GE1 of a plurality of (three shown schematically in fig. 5) active devices AD1 in the data demultiplexer 22 are electrically connected to the conductive via structures 13A, respectively, so as to electrically connect the conductive via structures 13A to corresponding driving circuits (not shown), so that the active devices AD1 are sequentially turned on (or sequentially turned off). The sources SE1 of the active elements AD1 are electrically connected to the same conductive via structure 13 to receive data signals from a driving circuit (not shown) through the conductive via structure 13. The drains DE1 of the active devices AD1 are electrically connected to the data lines DL, respectively, for transmitting data signals to the data lines DL. The number and the configuration position of the data demultiplexers 22 can be determined according to the requirement, and are not limited herein.

Fig. 6 is a schematic partial top view of an electronic device according to a fourth embodiment of the invention. Fig. 7A to 7C are circuit diagrams of the shift register units SR1 to SR3 in fig. 6, respectively. Referring to fig. 6 to 7C, the electronic device 1C further includes a Gate Driver on Array (GOA) 24. By disposing the gate driving circuit 24 in the active region and electrically connecting it to the driving circuit (not shown) through the conductive via structure 13B to the conductive via structure 13F, it is helpful to implement a design of a full narrow bezel, compared to disposing the gate driving circuit 24 at the periphery of the active region (where the plurality of sub-pixels SP are located). In some embodiments, the gate driving circuit 24 may include shift register units SR1 to SR 3. Each of the shift register units SR1 through SR3 includes a signal line CLK, a signal line XCLK, a signal line INPUT, a signal line OUTPUT, a signal line VGH, and a signal line VGL. The signal line INPUT in the shift register unit SR1 is electrically connected to a driving circuit (not shown) through the conductive via structure 13B. The signal line VGL and the signal line XCLK in the shift register unit SR2 are electrically connected to a driving circuit (not shown) through the conductive via structure 13C and the conductive via structure 13D, respectively. The signal line CLK and the signal line VGH in the shift register unit SR3 are electrically connected to a driving circuit (not shown) through the conductive via structure 13E and the conductive via structure 13F, respectively. The number and the arrangement position of the shift register units can be determined according to the requirement, and are not limited herein.

Fig. 8 and 9 are a partial top view and a partial cross-sectional view of an electronic device according to a fifth embodiment of the invention. Referring to fig. 8 and 9, in the electronic device 1D, in consideration of the processing uniformity or the visual effect uniformity of the electronic device 1D, the electronic device 1D may further include a plurality of dummy conductive via structures 13X. At least one of one conductive via structure 13 and one dummy conductive via structure 13X may be disposed in each sub-pixel SP, for example. As shown in fig. 8, assuming that each sub-pixel SP is designed to include two conductive via structures, the two conductive via structures may be two conductive via structures 13, a combination of one conductive via structure 13 and one dummy conductive via structure 13X, or two dummy conductive via structures 13X (not shown).

In some embodiments, as shown in fig. 9, at least one of the plurality of dummy conductive via structures 13X may include one upper pattern TP, one conductive via CV3, and one middle pattern MP, i.e., at least one of the plurality of dummy conductive via structures 13X may share at least one conductive layer (e.g., the first conductive layer 103 and the second conductive layer 107) with the pixel array structure 10. Further, the plurality of dummy conductive via structures 13X may not be electrically connected to the plurality of conductive lines CL of the re-routing structure 12.

Fig. 10 is a schematic partial top view of an electronic device according to a sixth embodiment of the invention. Referring to fig. 10, in the electronic device 1E, the pixel array structure further includes a plurality of stretchable electrodes 111. A portion of the signal line (e.g., the scan line SL or the data line DL) may be formed of the stretchable electrode 111, for example, at least one of the stretchable electrodes 111 may be located at an interface of two adjacent sub-pixels SP and connect two portions of the same signal line (e.g., the scan line SL or the data line DL) located in the two adjacent sub-pixels SP. In other embodiments, the whole of the signal line (e.g., the scan line SL or the data line DL) may also be formed of the stretchable electrode 111. The stretchable electrode 111 has high stretchability and electrical conductivity. For example, the material of the stretchable electrode 111 may include carbon-based nanomaterials, metal nanomaterials, or a combination thereof, but is not limited thereto.

Fig. 11 is a schematic partial cross-sectional view of an electronic device according to a seventh embodiment of the invention. Referring to fig. 11, in the electronic device 1F, the pixel array structure 10 is located between the redistribution structure 12 and the substrate 16, and the device layer 18 is located between the redistribution structure 12 and the pixel array structure 10. For example, the buffer layer 120 of the rewiring structure 12 may be disposed on the element layer 18, the third conductive layer 110 and the fourth insulating layer 109. In addition, in the conductive via structure 13, the conductive via CV4F penetrates through the first insulating layer 121, the buffer layer 120, the fourth insulating layer 109 and the third insulating layer 108, and two opposite ends of the conductive via CV4F are connected to the conductive line 1220 and the upper pattern TP, respectively. The electronic device 1F can be applied to an embedded sensing display apparatus, but not limited thereto.

Fig. 11 does not show the intermediate conductive layer 105 and the capacitor C. Depending on different requirements, the pixel array structure 10 of the electronic device 1F may or may not include the intermediate conductive layer 105 or the capacitor C. Any embodiment of the present invention may be combined with any of the technical means described herein without conflict and will not be repeated hereinafter.

Fig. 12 is a schematic partial cross-sectional view of an electronic device according to an eighth embodiment of the invention. Referring to fig. 12, in the electronic device 1G, the rewiring structure 12G is located between the element layer 18 and the pixel array structure 10G.

In some embodiments, as shown in fig. 12, after the buffer layers 100 to the third insulating layers 108 of the pixel array structure 10G are sequentially formed on the substrate 16, the first insulating layer 121 to the second redistribution conductive layer 124 of the redistribution structure 12G may be sequentially formed, and then the driving circuit 20, the insulating layer 109G, the conductive layer 110G, the device layer 18, and the buffer layer 120G are sequentially formed. Under this structure, the pixel array structure 10G may not include the fourth insulating layer 109 and the third conductive layer 110, and the redistribution structure 12G may not include the buffer layer 120. Further, the first insulating layer 121 of the re-wiring structure 12G is disposed on the third insulating layer 108 of the pixel array structure 10G. In the conductive via structure 13G, the conductive via CV4G penetrates through the first insulating layer 121 and the third insulating layer 108, and two opposite ends of the conductive via CV4G are respectively connected to the conductive line 1220 and the upper pattern TP. The insulating layer 109G of the electronic device 1G is provided over the driver circuit 20 and the second insulating layer 123. The conductive layer 110G of the electronic device 1G is provided on the insulating layer 109G. The conductive layer 110G may be a patterned conductive layer and includes a plurality of pixel electrodes PEG (one pixel electrode PEG is schematically illustrated in fig. 12). The pixel electrode PEG may be electrically connected to the conductive line 1220 through a conductive via CV1G penetrating the insulating layer 109G and the second insulating layer 123. The buffer layer 120G of the electronic device 1G is provided on the element layer 18 and the conductive layer 110G.

Fig. 13 is a schematic partial cross-sectional view of an electronic device according to a ninth embodiment of the invention. Referring to fig. 13, in the electronic device 1H, the substrate 16 is located between the element layer 18 and the pixel array structure 10G. For example, the electronic device 1H may not include the insulating layer 109G, and the conductive layer 110H, the element layer 18 and the buffer layer 120G of the electronic device 1H may be sequentially disposed on the surface of the substrate 16 away from the pixel array structure 10G, wherein the pixel electrode PEH of the conductive layer 110H is electrically connected to the corresponding middle pattern MP by the conductive via CV1H penetrating through the substrate 16, the buffer layer 100 and the gate insulating layer 102.

Fig. 14 and fig. 15 are a partial perspective view and a partial cross-sectional view of an electronic device according to a tenth embodiment of the invention. Referring to fig. 14 and 15, the electronic device 1I includes a plurality of pixel array structures, such as a first pixel array structure 10-1 and a second pixel array structure 10-2. The first pixel array structure 10-1 is located between the second pixel array structure 10-2 and the re-routing structure 12. The plurality of conductive lines of the rewiring structure 12 include a plurality of first conductive lines CL-1 and a plurality of second conductive lines CL-2. For convenience of distinction, fig. 14 shows first conductive line CL-1 and second conductive line CL-2 as solid lines of different line widths. The plurality of conductive via structures includes a plurality of first conductive via structures 13-1 and a plurality of second conductive via structures 13-2. For convenience of distinction, the areas of the first conductive via structure 13-1 and the second conductive via structure 13-2 are marked with different ground colors. The plurality of signal lines (e.g., the plurality of data lines DL) in the first pixel array structure 10-1 are electrically connected to the plurality of first conductive lines CL1 of the redistribution structure 12 through the plurality of first conductive via structures 13-1, and the plurality of signal lines (e.g., the plurality of data lines DL) in the second pixel array structure 10-2 are electrically connected to the plurality of second conductive lines CL2 of the redistribution structure 12 through the plurality of second conductive via structures 13-2. Fig. 14 schematically shows that the plurality of first conductive lines CL1 and the plurality of second conductive lines CL2 are electrically connected to one driving circuit 20. Alternatively, the plurality of first conductive lines CL1 and the plurality of second conductive lines CL2 may be electrically connected to the plurality of driving circuits 20 (as shown in fig. 15).

Referring to fig. 15, the elements/layers of the first pixel array structure 10-1 and the redistribution structure 12 and their relative arrangement relationship are referred to above, and will not be described again here. The second pixel array structure 10-2 is disposed on the substrate 26 and may have a substantially similar structure to the first pixel array structure 10-1. The second pixel array structure 10-2 of fig. 15 does not show the intermediate conductive layer 105, the second insulating layer 106, and the capacitor C. However, the pixel array structure 10-2 may or may not include the middle conductive layer 105, the second insulating layer 106 or the capacitor C according to different requirements. The element layer 28 is disposed on the pixel electrode PE of the second pixel array structure 10-2. The device layer 28 and the device layer 18 can be used to provide different functions, such as two of an illumination function, a display function, and a light sensing function, but not limited thereto. For example, one of the device layer 28 and the device layer 18 may include a sub-millimeter light emitting diode array or a micro light emitting diode array, for example, to provide an illumination function, and the other of the device layer 28 and the device layer 18 may include a liquid crystal layer, for example, to provide a display function. Alternatively, one of the device layers 28 and 18 may include a liquid crystal layer, an electrophoretic layer, an organic light emitting diode array, a sub-millimeter light emitting diode array, or a micro light emitting diode array to provide a display function, and the other of the device layers 28 and 18 may include a light sensing device array to provide a light sensing function.

In some embodiments, as shown in fig. 15, the first conductive via structure 13-1 may have a structure similar to the conductive via structure 13 of fig. 2, i.e., the first conductive via structure 13-1 may include, but is not limited to, an upper pattern TP, a conductive via CV3, a middle pattern MP, and a conductive via CV 4. On the other hand, the second conductive via structure 13-2 may further include a conductive via CV1A, a conductive pattern CP2, a connector CT, and a conductive pattern CP1 in addition to one upper pattern TP, one conductive via CV3, one middle pattern MP, and one conductive via CV 4. The conductive pattern CP2 may be formed together with the pixel electrode PE in the first pixel array structure 10-1, and the conductive pattern CP2 may be electrically connected with the upper pattern TP through the conductive via CV 1A. The conductive pattern CP1 may be formed together with the pixel electrode PE of the second pixel array structure 10-2. After the second pixel array structure 10-2 and the element layer 28 are disposed on the substrate 26, the substrate 26 may be turned over such that the second pixel array structure 10-2 faces the first pixel array structure 10-1, and the first pixel array structure 10-1 and the second pixel array structure 10-2 are joined by the adhesion layer 30, and the conductive pattern CP1 is electrically connected to the conductive pattern CP2 by the connection CT. The connection CT includes, for example, a conductive paste or a solder, but is not limited thereto.

Fig. 16 and 17 are a partial cross-sectional view and a partial top view of an electronic device according to an eleventh embodiment of the invention. Referring to fig. 16 and 17, in the electronic device 1J, the pixel array structure 10J is a passive pixel array structure, for example. In addition, the pixel array structure 10J may not include the power line PL, the active device AD, the capacitor C, the semiconductor layer 101, and the intermediate conductive layer 105, but is not limited thereto.

In an embodiment of the invention, the signal lines of the pixel array structure may be connected to the conductive lines of the redistribution structure through the conductive via structures, and then connected to the driving system (e.g., the driving circuit) through the conductive lines of the redistribution structure. In addition, as the size or resolution of the electronic device is increased, a proper signal transmission path can be provided by the design (such as size, number or position) of at least one of the conductive via structure, the conductive line and the driving circuit, thereby contributing to the improvement of the rc loading problem.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention. Therefore, the scope of the present invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.