阅读说明：本技术 一种背板组件、制程方法和显示装置 (Backboard component, manufacturing method and display device ) 是由 罗传宝 于 2020-12-08 设计创作，主要内容包括：本申请提供一种背板组件、制程方法和显示装置,背板组件包括基板、第一金属层、透明金属氧化层、缓冲层以及有源层,基板具有相对设置的第一面和第二面,第一金属层设置在所述第一面,透明金属氧化层设置在所述第一金属层远离所述基板的一面,所述透明金属氧化层和所述第一金属层形成源漏极、遮光层以及焊盘,缓冲层设置在透明金属氧化层远离所述基板的一面,且覆盖所述第一面,所述缓冲层设有过孔,所述过孔位置与所述源漏极对应,有源层设置在缓冲层远离所述基板的一面,所述有源层包括沟道区以及沟道区两侧的非沟道区,所述沟道区通过所述过孔与所述源漏极连接。本申请实施例能够节省至少一道掩膜工艺,降低生产成本。(The application provides a backboard component, a manufacturing method and a display device, wherein the backboard component comprises a substrate, a first metal layer, a transparent metal oxide layer, a buffer layer and an active layer, the substrate is provided with a first surface and a second surface which are oppositely arranged, the first metal layer is arranged on the first surface, the transparent metal oxide layer is arranged on one surface of the first metal layer far away from the substrate, the transparent metal oxide layer and the first metal layer form a source drain electrode, a shading layer and a bonding pad, the buffer layer is arranged on one surface of the transparent metal oxide layer far away from the substrate, and covers the first surface, the buffer layer is provided with via holes, the positions of the via holes correspond to the source and drain electrodes, the active layer is arranged on one surface of the buffer layer far away from the substrate, the active layer comprises a channel region and non-channel regions on two sides of the channel region, and the channel region is connected with the source and the drain through the through hole. According to the embodiment of the application, at least one mask process can be saved, and the production cost is reduced.)

1. A backplane assembly, comprising:

the substrate is provided with a first surface and a second surface which are oppositely arranged;

a first metal layer disposed on the first surface;

the transparent metal oxide layer is arranged on one surface, far away from the substrate, of the first metal layer, and the transparent metal oxide layer and the first metal layer form a source drain electrode, a shading layer and a bonding pad;

the buffer layer is arranged on one surface, far away from the substrate, of the transparent metal oxide layer and covers the first surface, a through hole is formed in the buffer layer, and the position of the through hole corresponds to the source drain electrode;

the active layer is arranged on one surface, far away from the substrate, of the buffer layer and comprises a channel region and non-channel regions on two sides of the channel region, and the channel region is connected with the source and the drain through the through hole.

2. The backplane assembly of claim 1, further comprising an insulating layer disposed on a side of the active layer remote from the substrate and a second metal layer disposed on a side of the insulating layer remote from the substrate.

3. The backplane assembly of claim 2, further comprising a first passivation layer and a third metal layer, the first passivation layer disposed on a side of the second metal layer remote from the substrate and covering the active layer and the buffer layer, the first passivation layer having a contact hole, the third metal layer disposed on a side of the first passivation layer remote from the substrate, the third metal layer connected to the non-channel region of the active layer through the contact hole.

4. A backplate assembly according to claim 3, further comprising a chip, wherein the surface of the third metal layer remote from the substrate is provided with a recess, the recess is located in the contact hole, and the chip is disposed on the surface of the third metal layer remote from the substrate and located in the recess.

5. A backplate assembly according to claim 4, further comprising a second passivation layer disposed on the side of the first passivation layer remote from the substrate, the second passivation layer partially covering the third metal layer, and a black matrix disposed on the side of the second passivation layer remote from the substrate.

6. The backplate assembly of claim 1, wherein the transparent metal oxide layer is indium zinc oxide or indium tin oxide.

7. A method of fabricating a backplane assembly, comprising:

providing a substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged;

arranging a first metal layer on the first surface;

arranging a transparent metal oxide layer on one surface of the first metal layer, which is far away from the substrate;

forming a source drain electrode, a shading layer and a bonding pad by patterning the transparent metal oxide layer and the first metal layer;

arranging a buffer layer on one surface of the transparent metal oxide layer, which is far away from the substrate, wherein the buffer layer covers the first surface, the buffer layer is provided with a via hole, and the via hole corresponds to the source and drain electrode;

and an active layer is arranged on one surface of the buffer layer, which is far away from the substrate, the active layer comprises a channel region and non-channel regions on two sides of the channel region, and the channel region is connected with the source and the drain through the through hole.

8. The method of claim 7, wherein disposing a buffer layer on a surface of the transparent metal oxide layer away from the substrate comprises:

depositing a buffer transition layer on one surface of the transparent metal oxide layer, which is far away from the substrate;

patterning the buffer transition layer;

and annealing the buffer transition layer after the patterning treatment to form a buffer layer, wherein the annealing temperature is 300-400 ℃, and the annealing time is 2-3 hours.

9. The method of claim 7, wherein the step of disposing the source layer on the surface of the buffer layer away from the substrate comprises:

arranging a first passivation layer on one surface, far away from the substrate, of the active layer, wherein the first passivation layer is provided with a contact hole;

arranging a third metal layer on one surface of the first passivation layer, which is far away from the substrate, wherein the third metal layer is connected with the active layer through a contact hole;

and arranging a chip on one surface of the third metal layer far away from the substrate.

10. A display device comprising the backplane assembly of any of claims 1 to 6.

Technical Field

The application relates to the technical field of display, in particular to a back plate assembly, a manufacturing process method and a display device.

Background

Min and MicroLED (collectively: MLED) display technologies enter an accelerated development stage in the last two years and can be used in the field of small and medium-sized high-added-value display applications. Compared to OLED screens, MLED displays can exhibit better performance in terms of cost, contrast, high brightness, and thin profile. In the MLED display technology, the backplane technology is a key technology. The existing Micro-LED backboard technology is complex in process, the backboard cost is greatly increased, and the mass production of the Micro-LED display technology is not facilitated.

Disclosure of Invention

The embodiment of the application provides a backboard component, a manufacturing method and a display device, which can reduce the procedures of a backboard and reduce the production cost of the backboard.

The present application provides a backplane assembly comprising:

the substrate is provided with a first surface and a second surface which are oppositely arranged;

a first metal layer disposed on the first surface;

the transparent metal oxide layer is arranged on one surface, far away from the substrate, of the first metal layer, and the transparent metal oxide layer and the first metal layer form a source drain electrode, a shading layer and a bonding pad;

the buffer layer is arranged on one surface, far away from the substrate, of the transparent metal oxide layer and covers the first surface, the buffer layer is provided with a through hole, and the position of the through hole corresponds to the source drain electrode;

the active layer is arranged on one surface, far away from the substrate, of the buffer layer and comprises a channel region and non-channel regions on two sides of the channel region, and the channel region is connected with the source and the drain through the through hole.

In some embodiments, the semiconductor device further comprises an insulating layer and a second metal layer, wherein the insulating layer is arranged on one side of the active layer far away from the substrate, and the second metal layer is arranged on one side of the insulating layer far away from the substrate.

In some embodiments, the device further comprises a first passivation layer and a third metal layer, the first passivation layer is disposed on a side of the second metal layer far away from the substrate and covers the active layer and the buffer layer, the first passivation layer has a contact hole, the third metal layer is disposed on a side of the first passivation layer far away from the substrate, and the third metal layer is connected with the non-channel region of the active layer through the contact hole.

In some embodiments, the chip further includes a recess disposed on a surface of the third metal layer away from the substrate, the recess is located in the contact hole, and the chip is disposed on a surface of the third metal layer away from the substrate and located in the recess.

In some embodiments, the display device further comprises a second passivation layer and a black matrix, wherein the second passivation layer is arranged on one side, far away from the substrate, of the first passivation layer, the second passivation layer partially covers the third metal layer, and the black matrix is arranged on one side, far away from the substrate, of the second passivation layer.

In some embodiments, the transparent metal oxide layer is indium zinc oxide or indium tin oxide.

The embodiment of the present application further provides a method for manufacturing a backplane assembly, including:

providing a substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged;

arranging a first metal layer on the first surface;

arranging a transparent metal oxide layer on one surface of the first metal layer, which is far away from the substrate;

forming a source drain electrode, a shading layer and a bonding pad by patterning the transparent metal oxide layer and the first metal layer;

arranging a buffer layer on one surface of the transparent metal oxide layer, which is far away from the substrate, wherein the buffer layer covers the first surface, the buffer layer is provided with a via hole, and the via hole corresponds to the source and drain electrode;

and an active layer is arranged on one surface of the buffer layer, which is far away from the substrate, the active layer comprises a channel region and non-channel regions on two sides of the channel region, and the channel region is connected with the source and the drain through the through hole.

In some embodiments, the disposing a buffer layer on a side of the transparent metal oxide layer away from the substrate includes:

depositing a buffer transition layer on one surface of the transparent metal oxide layer, which is far away from the substrate;

patterning the buffer transition layer;

and annealing the buffer transition layer after the patterning treatment to form a buffer layer, wherein the annealing temperature is 300-400 ℃, and the annealing time is 2-3 hours.

In some embodiments, after the source layer is disposed on a side of the buffer layer away from the substrate, the method includes:

arranging a first passivation layer on one surface, far away from the substrate, of the active layer, wherein the first passivation layer is provided with a contact hole;

arranging a third metal layer on one surface of the first passivation layer, which is far away from the substrate, wherein the third metal layer is connected with the active layer through a contact hole;

and arranging a chip on one surface of the third metal layer far away from the substrate.

The embodiment of the application also provides a display device, which comprises the back plate assembly in the embodiment.

The backboard component, the manufacturing method and the display device provided by the embodiment of the application comprise a substrate, a first metal layer, a transparent metal oxide layer, a buffer layer and an active layer, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged, the first metal layer is arranged on the first surface, the transparent metal oxide layer is arranged on the surface of the first metal layer far away from the substrate, the transparent metal oxide layer and the first metal layer form a source drain electrode, a shading layer and a bonding pad, the buffer layer is arranged on one surface of the transparent metal oxide layer far away from the substrate, and covers the first surface, the buffer layer is provided with via holes, the positions of the via holes correspond to the source and drain electrodes, the active layer is arranged on one surface of the buffer layer far away from the substrate, the active layer comprises a channel region and non-channel regions on two sides of the channel region, and the channel region is connected with the source and the drain through the through hole. According to the embodiment of the application, the transparent metal oxide layer and the first metal layer serve as the source drain electrode and the shading layer at the same time, a mask process can be saved, meanwhile, the contact resistance of the non-channel region and the source drain electrode in a lap joint mode can be reduced through the transparent metal oxide layer, the transparent metal oxide layer serves as a pad, and a subsequent anode mask process can be further saved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a backplane assembly according to an embodiment of the present disclosure.

Fig. 2 is another schematic structural diagram of a backplane assembly according to an embodiment of the present disclosure.

Fig. 3 is a flowchart illustrating a method for manufacturing a backplane assembly according to an embodiment of the present disclosure.

Fig. 4 is a schematic view illustrating a manufacturing method of a backplane assembly according to an embodiment of the present disclosure.

Fig. 5 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that in the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be configured in a specific orientation, and operate, and thus, should not be construed as limiting the present application.

The embodiment of the application provides a backboard assembly, a manufacturing method and a display device, and the backboard assembly is described in detail below.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a backplane assembly according to an embodiment of the present disclosure. The backplane assembly 10 comprises a substrate 11, a first metal layer 12, a transparent metal oxide layer 13, a buffer layer 14 and an active layer 15, wherein the substrate 11 is provided with a first surface 11a and a second surface 11b which are oppositely arranged, the first metal layer 12 is arranged on the first surface 11a, the transparent metal oxide layer 13 is arranged on one surface of the first metal layer 12 far away from the substrate 11, the transparent metal oxide layer 13 and the first metal layer 12 form a source/drain electrode 101, a shading layer 102 and a bonding pad 103, the buffer layer 14 is arranged on one surface of the transparent metal oxide layer 13 far away from the substrate 11 and covers the first surface 11a, the buffer layer 14 is provided with a via hole 141, the position of the via hole 141 corresponds to the source/drain electrode 101, the active layer 15 is arranged on one surface of the buffer layer 14 far away from the substrate 11, and the active layer 15 comprises a channel region 151 and a non-channel region 152, the channel region 151 is connected to the source and drain 101 through the via hole 141.

The material of the substrate 11 may be glass, but other materials may be used for the substrate 11. The first surface 11a may be an upper surface of the substrate 11, and the second surface 11b may be a lower surface of the substrate 11. In some embodiments, the first side 11a may also be a lower surface of the substrate 11, and the second side 11b may be an upper surface of the substrate 11.

Specifically, the material of the first metal layer 12 is copper or molybdenum. Of course, other materials may be used for the first metal layer 12. Redundant description is not provided in the embodiments of the present application.

In addition, the material of the transparent metal oxide layer 13 may be indium zinc oxide or indium tin oxide. Of course, the transparent metal oxide layer 13 may be made of other materials.

Specifically, the first metal layer 12 and the transparent metal oxide layer 13 may form a composite layer, and at the same time, the first metal layer 12 and the transparent metal oxide layer 13 together form the source and drain electrodes 101 of the thin film transistor, the light shielding layer 102, and the pad 103 through a patterning process. More specifically, the light-shielding layer 102 is located between the source-drain 101 and the pad 103.

The material of the buffer layer 14 may be silicon oxide, silicon nitride, or the like. Of course, other materials may be used for buffer layer 14. In addition, buffer layer 14 may be formed of one or more layers.

Specifically, the material of the active layer 15 may be any one of Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO), Indium Gallium Zinc Tin Oxide (IGZTO), Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Aluminum Zinc Oxide (IAZO), Indium Gallium Tin Oxide (IGTO), or Antimony Tin Oxide (ATO). The above materials have good conductivity and transparency, and are small in thickness, and do not affect the overall thickness of the display panel 10. Meanwhile, the electronic radiation and ultraviolet and infrared light which are harmful to human bodies can be reduced. The thickness of the semiconductor layer 13 isToSpecifically, the thickness of the active layer 15 layer is OrThe active layer 15 is formed through a patterning process. The active layer 15 includes a channel region 151 and non-channel regions 152 on two sides of the channel region 151, and the channel region 151 is connected to the source and drain 101 through the via hole 141. This arrangement makes it possible to connect the light-shielding layer 102 and the source/drain 101. In addition, the channel region 151 and the non-channel region 152 of the thin film transistor are formed by plasma processing the active layer 15 region, and the non-channel region 152 is formed in both the regions where the active layer 15 is made conductive.

It can be understood that in the embodiment of the present application, the transparent metal oxide layer 13 and the first metal layer 12 serve as the source/drain 101 and the light shielding layer 102 at the same time, a masking process can be saved, and meanwhile, the transparent metal oxide layer 13 can reduce the contact resistance of the non-channel region 152 and the source/drain 101, and serve as the pad 103, so that a subsequent masking process of the anode can be further saved.

Referring to fig. 2, fig. 2 is another schematic structural diagram of a backplane assembly according to an embodiment of the present disclosure. The backplane assembly 10 further includes an insulating layer 16 and a second metal layer 17, wherein the insulating layer 16 is disposed on a side of the active layer 15 away from the substrate 11, and the second metal layer 17 is disposed on a side of the insulating layer 16 away from the substrate 11.

Specifically, the material of the second metal layer 17 is copper or molybdenum. Of course, other materials may be used for the second metal layer 17. Redundant description is not provided in the embodiments of the present application.

Specifically, the insulating layer 16 is made of a silicon oxide compound, a silicon nitride compound, or a combination thereof. For example, in the multilayer structure of the insulating layer 16, a multilayer structure of a layer of a silicon oxide compound and a layer of a silicon nitride compound may be employed.

The backplane assembly 10 further includes a first passivation layer 18 and a third metal layer 19, the first passivation layer 18 is disposed on a side of the second metal layer 17 away from the substrate 11 and covers the active layer 15 and the buffer layer 14, the first passivation layer 18 has a contact hole 181, the third metal layer 19 is disposed on a side of the first passivation layer 18 away from the substrate 11, and the third metal layer 19 is connected to the non-channel region 152 of the active layer 15 through the contact hole 181.

Specifically, the material of the third metal layer 19 is copper or molybdenum. Of course, other materials may be used for the second metal layer 17. Redundant description is not provided in the embodiments of the present application.

In addition, the first passivation layer 18 may have a single-layer or multi-layer structure, and the material used for the first passivation layer 18 is a silicon oxide compound, a silicon nitride compound, or a combination thereof. For example, in the multilayer structure of the first passivation layer 18, a multilayer structure of a layer of a silicon oxide compound and a layer of a silicon nitride compound may be employed.

The back plate assembly 10 further includes a chip 104, a recess 191 is disposed on a surface of the third metal layer 19 away from the substrate 11, the recess 191 is located in the contact hole 181, and the chip 104 is disposed on a surface of the third metal layer 19 away from the substrate 11 and located in the recess 191.

It should be noted that the chip 104 may be a micro light emitting diode. The light emission of the backplate assembly 10 can be achieved by placing micro light emitting diodes in the recesses 191.

The backplane assembly 10 further includes a second passivation layer 105 and a black matrix 106, the second passivation layer 105 is disposed on a side of the first passivation layer 18 away from the substrate 11, the second passivation layer 105 partially covers the third metal layer 19, and the black matrix 106 is disposed on a side of the second passivation layer 105 away from the substrate 11.

Specifically, the second passivation layer 105 may have a single-layer or multi-layer structure, and the material used for the second passivation layer 105 is a silicon-oxygen compound, a silicon-nitrogen compound, or a combination thereof. For example, in the multilayer structure of the second passivation layer 105, a multilayer structure of a layer of a silicon oxide compound and a layer of a silicon nitride compound may be employed.

The black matrix 106 is made of a light-shielding resist material.

The backboard component 10 of the embodiment of the application comprises a substrate 11, a first metal layer 12, a transparent metal oxide layer 13, a buffer layer 14 and an active layer 15, wherein the substrate 11 is provided with a first surface 11a and a second surface 11b which are oppositely arranged, the first metal layer 12 is arranged on the first surface 11a, the transparent metal oxide layer 13 is arranged on the first metal layer 12 far away from one surface of the substrate 11, the transparent metal oxide layer 13 and the first metal layer 12 form a source drain 101, a shading layer 102 and a pad 103, the buffer layer 14 is arranged on the transparent metal oxide layer 13 far away from one surface of the substrate 11 and covers the first surface 11a, the buffer layer 14 is provided with a via hole 141, the position of the via hole 141 corresponds to the source drain 101, the active layer 15 is arranged on the buffer layer 14 far away from one surface of the substrate 11, the active layer 15 comprises a channel region 151 and a non-channel region 152 on two sides, the channel region 151 is connected to the source and drain 101 through the via hole 141. According to the embodiment of the application, the transparent metal oxide layer 13 and the first metal layer 12 serve as the source and drain electrodes 101 and the light shielding layer 102 at the same time, a mask process can be saved, meanwhile, the contact resistance of the non-channel region 152 and the source and drain electrodes 101 in a lap joint can be reduced through the transparent metal oxide layer 13, and the transparent metal oxide layer serves as the bonding pad 103, so that a subsequent anode mask process can be further saved.

Referring to fig. 3 and 4, fig. 3 is a flow chart illustrating a method for manufacturing a backplane assembly according to an embodiment of the present disclosure. Fig. 4 is a schematic view illustrating a manufacturing method of a backplane assembly according to an embodiment of the present disclosure. The manufacturing method of the backboard component comprises the following steps:

201. providing a substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged.

The material of the substrate 11 may be glass, but other materials may be used for the substrate 11. The first surface 11a may be an upper surface of the substrate 11, and the second surface 11b may be a lower surface of the substrate 11. In some embodiments, the first side 11a may also be a lower surface of the substrate 11, and the second side 11b may be an upper surface of the substrate 11.

202. And arranging a first metal layer on the first surface.

The material of the first metal layer 12 is copper or molybdenum. Of course, other materials may be used for the first metal layer 12. Redundant description is not provided in the embodiments of the present application.

203. And arranging a transparent metal oxide layer 13 on one surface of the first metal layer far away from the substrate.

Note that the material of the transparent metal oxide layer 13 may be indium zinc oxide or indium tin oxide. Of course, the transparent metal oxide layer 13 may be made of other materials.

204. And forming a source drain electrode, a shading layer and a bonding pad by patterning the transparent metal oxide layer and the first metal layer.

Note that the first metal layer 12 and the transparent metal oxide layer 13 are patterned together to form the light shielding layer 102 and the source/drain 101. The composite structure of the first metal layer 12 and the transparent metal oxide layer 13 can be used as the bonding pad 103, the first metal layer 12 can use H2O2 series chemical liquid as an etchant, and the transparent metal oxide layer 13 can use oxalic acid series chemical liquid as an etchant.

205. The buffer layer is arranged on one surface, far away from the substrate, of the transparent metal oxide layer and covers the first surface 10a, the buffer layer is provided with via holes, and the via holes correspond to the source and drain electrodes in position.

The buffer layer 14 is formed by chemical vapor deposition, and the material of the film layer may be silicon oxide, silicon nitride, or the like.

In some embodiments, the method for disposing the buffer layer 14 on the surface of the transparent metal oxide layer 13 away from the substrate 11 specifically includes the steps of:

(1) and depositing a buffer transition layer on one surface of the transparent metal oxide layer, which is far away from the substrate.

Note that the transition layer is buffered by chemical vapor deposition.

(2) And patterning the buffer transition layer.

The buffer transition layer is patterned by an etching solution to form a pattern of the buffer layer 14.

(3) And annealing the buffer transition layer after the patterning treatment to form the buffer layer 14, wherein the annealing temperature is 300-400 ℃, and the annealing time is 2-3 hours.

It should be noted that the electrode of the first metal layer 12 can be prevented from being oxidized due to the transparent metal oxide layer 13, and the high-temperature thermal annealing will reduce the contact resistance between the first metal layer 12 and the active layer 15.

206. An active layer is arranged on one surface, far away from the substrate, of the buffer layer, the active layer comprises a channel region and non-channel regions on two sides of the channel region, and the channel region is connected with the source and the drain electrodes through the through holes 141.

The material of the active layer 15 may be any one of Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO), Indium Gallium Zinc Tin Oxide (IGZTO), Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Aluminum Zinc Oxide (IAZO), Indium Gallium Tin Oxide (IGTO), or Antimony Tin Oxide (ATO). The active layer 15 is formed by patterning. The active layer 15 includes a channel region 151 and non-channel regions 152 on two sides of the channel region 151, and the channel region 151 is connected to the source and drain 101 through the via hole 141. This arrangement makes it possible to connect the light-shielding layer 102 and the source/drain 101. In addition, the channel region 151 and the non-channel region 152 of the thin film transistor are formed by plasma processing the active layer 15 region, and the region where the active layer 15 is made conductive is the non-channel region 152.

In some embodiments, after the source layer is disposed on a surface of the buffer layer away from the substrate, the method specifically includes:

(1) and arranging a first passivation layer on one surface of the active layer, which is far away from the substrate, wherein the first passivation layer is provided with a contact hole.

The first passivation layer 18 may have a single-layer or multi-layer structure, and the material used for the first passivation layer 18 is a silicon oxide, a silicon nitride, or a combination thereof. For example, in the multilayer structure of the first passivation layer 18, a multilayer structure of a layer of a silicon oxide compound and a layer of a silicon nitride compound may be employed.

(2) And arranging a third metal layer on one surface of the first passivation layer, which is far away from the substrate, wherein the third metal layer is connected with the active layer through the contact hole.

It should be noted that a recess 191 is formed in a surface of the third metal layer 19 away from the substrate 11, the recess 191 is located in the contact hole 181, and the chip 104 is disposed on a surface of the third metal layer 19 away from the substrate 11 and is located in the recess 191.

In some embodiments, after disposing the third metal layer 19 on the side of the first passivation layer 18 away from the substrate 11, the following steps may be included:

a second passivation layer 105 is disposed on a side of the first passivation layer 18 away from the substrate 11, the second passivation layer 105 partially covers the third metal layer 19, and a black matrix 106 is disposed on a side of the second passivation layer 105 away from the substrate 11.

(3) And arranging a chip on one surface of the third metal layer far away from the substrate.

It should be noted that the chip 104 may be a micro light emitting diode. The light emission of the backplate assembly 10 can be achieved by placing micro light emitting diodes in the recesses 191.

According to the embodiment of the application, the transparent metal oxide layer 13 and the first metal layer 12 serve as the source and drain electrodes 101 and the light shielding layer 102 at the same time, a mask process can be saved, meanwhile, the contact resistance of the non-channel region 152 and the source and drain electrodes 101 in a lap joint can be reduced through the transparent metal oxide layer 13, and the transparent metal oxide layer serves as the bonding pad 103, so that a subsequent anode mask process can be further saved.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. The display device 100 includes a backplane assembly 10 and a display assembly 20, the display assembly 20 is disposed on the backplane assembly 10, and the display assembly 20 is described in the related embodiments, so that the display assembly 20 is not described in detail in this embodiment. The back plate assembly 10 is the back plate assembly 10 described in the above embodiments. Since the above embodiments have been described in detail. Therefore, the backplate assembly 10 will not be described in detail in the embodiments of the present application.

Since the display device 100 of the embodiment of the present application employs the backplane assembly 10 of the above-described embodiment. Therefore, according to the embodiment of the application, the transparent metal oxide layer and the first metal layer serve as the source/drain electrode and the shading layer at the same time, a masking process can be omitted, meanwhile, the contact resistance of the non-channel region and the source/drain electrode in a lap joint can be reduced through the transparent metal oxide layer, and the transparent metal oxide layer serves as a bonding pad, so that a subsequent masking process of an anode can be further omitted.

The backplane assembly, the manufacturing method and the display device provided in the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are described herein using specific examples, which are provided only to help understanding of the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.