阅读说明：本技术 显示面板和显示装置 (Display panel and display device ) 是由 樊勇 于 2020-12-10 设计创作，主要内容包括：本发明公开了一种显示面板和显示装置,通过将绑定层设置于薄膜晶体管层和衬底基板之间,并使薄膜晶体管层的金属走线通过过孔与绑定引线电性连接,能减少外围区的范围,从而能实现窄bonding,实现了降低边框的目的。(The invention discloses a display panel and a display device.A binding layer is arranged between a thin film transistor layer and a substrate, and metal wires of the thin film transistor layer are electrically connected with binding leads through via holes, so that the range of a peripheral area can be reduced, narrow bonding can be realized, and the aim of reducing a frame is fulfilled.)

1. A display panel, has display area and is located the peripheral binding area in display area, display panel includes array substrate and set up in on the array substrate and be located at least a light emitting device of display area, its characterized in that, array substrate includes in proper order in its orientation in the thickness direction of light emitting device: substrate base plate, binding layer and thin-film transistor layer, wherein:

the binding layer comprises at least one binding lead positioned in the display area and at least one binding electrode positioned in the binding area, the binding lead is electrically connected with the thin film transistor layer, and the binding electrode is electrically connected with the corresponding binding lead and is configured to be at least used for binding the driving chip.

2. The display panel of claim 1, wherein the thin-film transistor layer comprises a multi-layer insulating layer and a plurality of metal traces formed on the multi-layer insulating layer, wherein:

the multilayer insulating layer comprises at least one through hole positioned in the display area and at least one first opening positioned in the peripheral area;

the via hole extends from the surface of the metal wire to the surface of the binding layer and is configured as a place for electrically connecting the metal wire and the binding lead;

the first opening penetrates through the thickness direction of the multilayer insulating layer, and an orthographic projection of the first opening on the binding layer covers the binding electrode.

3. The display panel of claim 2, wherein an orthographic projection of the first opening on the array substrate covers the bonding region.

4. The display panel of claim 2, wherein the plurality of metal traces include Data lines, Gate lines, VDD lines, and VSS lines;

the binding lead comprises a first binding lead, a second binding lead, a third binding lead and a third binding lead which are respectively and electrically connected with the Data line, the Gate line, the VDD line and the VSS line.

5. The display panel of claim 1, wherein a layer of solder material is disposed on a surface of the bonding electrode facing away from the substrate base plate; the material of the welding material layer is at least one of indium, tin, bismuth, silver or gold.

6. The display panel of claims 1-5, wherein an interlayer insulating layer is disposed between the bonding layer and the thin-film transistor layer, the interlayer insulating layer having a via hole and a second opening penetrating upper and lower surfaces thereof, wherein:

the through hole is positioned in the display area and communicated with the through hole so as to expose the binding lead;

the second opening is located in the peripheral region, and an orthographic projection of the first opening on the interlayer insulating layer falls into the second opening.

7. A display device characterized in that it comprises a display panel according to any one of claims 1 to 6.

8. The display device according to claim 7, wherein the display device further comprises a flip-chip film vertically disposed on a side of the bonding region away from the display region;

the chip on film is provided with a first binding end facing the light emitting device, and the first binding end bends and extends into the first opening and is electrically connected with the binding electrode.

9. The display apparatus of claim 8, further comprising a printed circuit board on a side of the substrate base plate facing away from the light emitting device;

the chip on film is provided with a second binding end opposite to the first binding end, and the second binding end is bent to the surface of the substrate base plate, which is far away from the light-emitting device, and is electrically connected with the printed circuit board.

10. The display device according to claim 9, wherein a eutectic conductive layer is provided between the bonding electrode of the display panel and the bonding electrode of the first bonding terminal.

11. The display apparatus of claim 8, wherein the display panel further comprises an encapsulation adhesive layer disposed on the light emitting device and covering the thin-film transistor layer and a portion of the flip-chip film bonded to the array substrate.

Technical Field

The invention relates to the technical field of display, in particular to a display panel and a display device.

Background

Fig. 1 is a schematic structural diagram of a conventional display device. As shown in fig. 1, in the conventional display device, it is necessary to use an upper glass substrate 10 and a lower glass substrate 20, in which a TFT layer 30 is provided on the upper surface of the upper glass substrate 10 and a Fanout wiring 40 is formed on the lower surface of the lower glass substrate 10, and thus it is necessary to connect the TFT layer 30 and the Fanout wiring 40 via a side-printed wiring 50; meanwhile, the connection between the chip on film 60 and the printed circuit board 70 is realized by a backside bonding technology.

In the display device, the side printed circuit 50 and the double-sided circuit are required to be protected, the manufacturing process is complex, the cost of related equipment is high, precise grinding is required before the side printed circuit 50 is printed, the required time is long, the capacity is limited, and after the side printed circuit is printed, the packaging glue at the edge of the circuit is not easy to level, so that the splicing effect of the display panel is influenced.

Therefore, it is desirable to provide a display panel and a display device capable of realizing seamless splicing to solve the above technical problems.

Disclosure of Invention

In order to solve the above problems, the invention provides a display panel and a display device, wherein a bonding layer is arranged between a thin film transistor layer and a substrate, and a metal wire of the thin film transistor layer is electrically connected with a bonding lead through a via hole, so that the range of a peripheral area can be reduced, narrow bonding can be realized, and the purpose of reducing a frame is realized.

In order to achieve the above object, the display panel and the display device of the present invention adopt the following technical solutions.

The invention provides a display panel, which is provided with a display area and a binding area positioned on the periphery of the display area, wherein the display panel comprises an array substrate and at least one light-emitting device arranged on the array substrate and positioned in the display area, and the array substrate sequentially comprises the following components in the thickness direction facing the light-emitting device: substrate base plate, binding layer and thin-film transistor layer, wherein: the binding layer comprises at least one binding lead positioned in the display area and at least one binding electrode positioned in the binding area, the binding lead is electrically connected with the thin film transistor layer, and the binding electrode is electrically connected with the corresponding binding lead and is configured to be at least used for binding the driving chip.

Further, the thin film transistor layer includes a plurality of insulating layers and a plurality of metal traces formed on the insulating layers, wherein: the multilayer insulating layer comprises at least one through hole positioned in the display area and at least one first opening positioned in the peripheral area; the via hole extends from the surface of the metal wire to the surface of the binding layer and is configured as a place for electrically connecting the metal wire and the binding lead; the first opening penetrates through the thickness direction of the multilayer insulating layer, and an orthographic projection of the first opening on the binding layer covers the binding electrode.

Further, the orthographic projection of the first opening on the array substrate covers the binding region.

Further, the metal routing lines comprise a Data line, a Gate line, a VDD line and a VSS line; the binding lead comprises a first binding lead, a second binding lead, a third binding lead and a third binding lead which are respectively and electrically connected with the Data line, the Gate line, the VDD line and the VSS line.

Further, a welding material layer is arranged on the surface of the binding electrode, which is far away from the substrate base plate; the material of the welding material layer is at least one of indium, tin, bismuth, silver or gold.

Further, an interlayer insulating layer is arranged between the binding layer and the thin film transistor layer, and the interlayer insulating layer is provided with a through hole and a second opening which penetrate through the upper surface and the lower surface of the interlayer insulating layer, wherein: the through hole is positioned in the display area and communicated with the through hole so as to expose the binding lead; the second opening is located in the peripheral region, and an orthographic projection of the first opening on the interlayer insulating layer falls into the second opening.

The present invention also provides a display device comprising the display panel of any one of claims 1 to 6.

Furthermore, the display device also comprises a chip on film vertically arranged on one side of the binding area far away from the display area; the chip on film is provided with a first binding end facing the light emitting device, and the first binding end bends and extends into the first opening and is electrically connected with the binding electrode.

Further, the display device also comprises a printed circuit board, wherein the printed circuit board is positioned on one side of the substrate base plate, which is far away from the light-emitting device; the chip on film is provided with a second binding end opposite to the first binding end, and the second binding end is bent to the surface of the substrate base plate, which is far away from the light-emitting device, and is electrically connected with the printed circuit board.

Furthermore, a eutectic conducting layer is arranged between the binding electrode of the display panel and the binding electrode of the first binding end.

Furthermore, the display panel further comprises a packaging adhesive layer, wherein the packaging adhesive layer is arranged on the light-emitting device and covers the thin-film transistor layer and the part of the flip chip film, which is bound to the array substrate.

The display panel and the display device have the following beneficial effects:

(1) the binding layer is arranged between the thin film transistor layer and the substrate, so that the wiring range of the binding area can be reduced, the purpose of reducing the frame is realized, and the problems that the side printing circuit needs to be precisely ground before printing, and the packaging glue at the edge of the circuit is not easy to level and the splicing effect of the display panel is influenced can be solved;

(2) the metal wires of the thin film transistor layer are electrically connected to the binding layer through the via holes, so that the number of wires in the binding area or the peripheral area can be further reduced, and the purpose of reducing the frame is facilitated;

(3) the binding lead and the binding electrode are arranged in the same layer, so that the manufacturing process can be greatly saved;

(4) by arranging the welding material layer on the binding electrode, compared with ACF glue, the resistance can be reduced, and the length in a binding area can be effectively shortened; meanwhile, the welding material layer and the binding electrode material on the driving chip or the chip on film can form eutectic materials, so that the binding strength can be effectively improved;

(5) by extending the packaging adhesive to the binding region, the packaging adhesive can cover the flip chip film in the binding region, so that the binding strength can be effectively improved, and the binding metal is prevented from being oxidized.

Drawings

The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.

FIG. 1 is a schematic diagram of a conventional display device;

FIG. 2 is a schematic structural diagram of a display panel according to the present invention;

FIG. 3 is a schematic structural diagram of a display device according to the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.

Fig. 2 is a schematic structural diagram of a display panel according to the present invention. As shown in fig. 2, the present invention provides a display panel, which includes a display area 101 and a binding area 102 located at the periphery of the display area 101.

As shown in fig. 2, the display panel includes an array substrate 10 and at least one light emitting device 20 disposed on the array substrate 10 and located in the display region 101.

As shown in fig. 2, the array substrate 10 includes a substrate 11, a bonding layer 12, and a thin film transistor layer 13, which are sequentially stacked in a thickness direction thereof toward the light emitting device 20.

Specifically, the substrate base plate 11 material may include polyimide, polysiloxane, epoxy-based resin, acrylic resin, polyester, and/or the like. In one embodiment, the substrate base plate 11 may include polyimide.

As shown in fig. 2, the binding layer 12 is disposed on a surface of the substrate 11 facing the light emitting device 20 and covers the substrate 11.

As shown in fig. 2, the bonding layer 12 includes at least one bonding wire 121 located in the display region and at least one bonding electrode 122 located in the bonding region 102, the bonding wire 121 is electrically connected to the corresponding bonding electrode 122, and the bonding electrode 122 is configured for bonding a driver chip or a chip on film.

In a specific use, the bonding electrode 122 receives a current signal from a driver chip or a chip on film and transmits the current signal to the thin film transistor layer 13 through the bonding wire 121.

By arranging the bonding layer 12 between the thin film transistor layer 13 and the substrate 11, the display panel of the invention can reduce the number of wires or the range of the wire area on the periphery of the display area 101, thereby reducing the width of the bonding area 102 and achieving the purpose of reducing the frame.

Specifically, the bonding wires 121 include a first bonding wire, a second bonding wire, a third bonding wire, and a third bonding wire.

It should be noted that the present invention does not limit the routing manner, shape, width or extension tendency of the bonding wire 121. For example, the plurality of bonding wires 121 may be disposed on the same layer or may be disposed on different film layers. In a specific implementation, each of the bonding wires 121 may extend linearly, or may extend in a serpentine shape.

Specifically, the bonding electrode 122 is made of copper or at least one of copper and gold. For example, in the present embodiment, the bonding electrode 122 is made of copper.

It should be noted that the present invention does not limit the arrangement, shape, size or material of the binding electrode 122.

In one implementation, the binding layer 12 can be fabricated independently through a separate mask. Specifically, the bonding wire 121 and the bonding electrode 122 are obtained for the same film layer. By adopting the design, the bonding wires 121 and the bonding electrodes 122 can be formed simultaneously through one-time composition process, so that the process steps for manufacturing the display substrate and the use number of mask plates are reduced, the time for manufacturing the display substrate can be saved, and the cost is saved.

In other embodiments, the bonding wire 121 and the bonding electrode 122 can be made of the same or different materials independently. The invention is not limited in this regard.

Specifically, a surface of the bonding electrode 122 facing away from the substrate base plate 11 is provided with a solder material layer.

Specifically, the layer of solder material has an ambient melting temperature that is lower than the ambient melting temperature of the bonded electrode 122. Or, the welding material layer adopts low-temperature metal.

In a specific implementation, the material of the soldering material layer is at least one of indium, tin, bismuth, silver or gold. For example, the material of the soldering material layer is at least one of In, Sn, AuSn, SnBi, SnAgBi or Au/In.

In a specific implementation, the bonding electrode of the driving chip 20 is bonded to the bonding electrode 122 through the bonding material layer.

It should be noted that the present invention is not limited to the film structure or shape of the solder material layer. For example, in the present embodiment, the welding material layer has a single-layer structure. In other embodiments, the welding material layer may be a multilayer laminate structure.

By arranging the welding material layer, the resistance can be reduced when the driving chip is welded on the bonding electrode 122, and compared with an ACF adhesive, the length of the bonding area 102 can be effectively shortened, which is beneficial to realizing a narrow frame. On the other hand, by configuring the materials of the bonding electrode 122 and the welding material layer, a eutectic material can be formed after bonding, and the bonding strength is effectively improved.

Specifically, an interlayer insulating layer having a through hole and a second opening penetrating through a thickness direction of the interlayer insulating layer is disposed on a surface of the binding layer 12 facing the light emitting device 20, wherein the through hole is located in the display region 101 to expose the binding wire 121, the second opening is located in the peripheral region 10b, and an orthographic projection of the second opening on the binding layer 12 covers the binding electrode 122.

By providing the interlayer insulating layer, the bonding layer 12 and the thin film transistor layer 13 can be separated, and the function of protecting the bonding layer 12 can also be achieved.

In specific implementation, the interlayer insulating layer can be made of silicon oxide, silicon nitride, silicon oxynitride and/or the like. The interlayer insulating layer may also be an organic material such as polyimide, epoxy-based resin, acrylic resin, polyester, and/or the like.

It should be noted that the present invention is not limited to the structure or material of the interlayer insulating layer. In a specific implementation, the interlayer insulating layer may have a single-layer film structure or a multi-layer film combination structure. Moreover, each film layer in the film layer combination can independently select the same or different material processes.

In addition, in other embodiments, a buffer layer or other insulating functional layer of the thin-film transistor layer 13 itself may also be used as the interlayer insulating layer. The invention is not limited in this regard.

As shown in fig. 2, the thin-film transistor layer 13 is disposed on a surface of the bonding layer 12 facing the light emitting device 20.

As shown in fig. 2, the thin-film transistor layer 13 includes a multi-layer insulating layer 131 and a plurality of metal traces (not shown) formed in the multi-layer insulating layer 131.

As shown in fig. 2, the multi-layered insulating layer 131 includes a via 1311 at the display region 101 and a first opening 1312 at the binding region 102.

As shown in fig. 2, the via 1311 extends from the surface of the metal trace to the surface of the bonding layer 12 and is configured as a place for electrically connecting the metal trace and the bonding wire 121. In other words, the via 1311 is a place where a conductive path between the metal trace and the bonding wire 121 is formed.

By providing the via 1311 on the thin-film transistor layer 13, the via 1311 allows a metal trace, a conductive material, or an electrical connection with other device components to pass through, forming an electrical connection through the via 1311 of the thin-film transistor layer 13, which may help reduce the number of circuits or traces in the bonding area 102 or the peripheral area, and thus reduce the required width of the bonding area 102.

For example, as shown in fig. 2, the via 1311 is in communication with the through hole of the interlayer insulating layer, so that the two together constitute a place for forming a conductive path between the metal trace and the bonding wire 121.

In the present embodiment, a via 1311 is formed at a portion of the multi-layered insulating layer 131 corresponding to the bonding wire 121 and the electrode of the thin film transistor, and the via 1311 penetrates at least a portion of the thickness of the multi-layered insulating layer 131 in a thickness direction of the multi-layered insulating layer 131. Of course, in other embodiments, three or more of the vias 1311 may be prepared. It is to be understood that the present invention is not limited to the specific structure of the via 1311, as long as the via 1311 can be used to form an electrical connection channel between the bonding wire 121 and the electrode of the tft.

Specifically, a conductive material is filled in the via hole 1311 and the bonding wire 121 and the thin film transistor are connected through the conductive material. In this embodiment, the via hole 1311 is filled with a material for manufacturing the thin film transistor in a process of manufacturing a subsequent thin film transistor, that is, a conductive material for manufacturing the thin film transistor is filled in the via hole 1311, so that the bonding wire 121 and the thin film transistor are connected, and this manufacturing method is simple, convenient, and easy to operate; in other embodiments, the via 1311 may also be filled separately, that is, the conductive material of the via 1311 may also be different from the material of the conductive material for manufacturing the thin film transistor, and may be set as needed.

As shown in fig. 2, the first opening 1312 penetrates a partial region (partial thickness region) in the thickness direction of the multilayer insulating layer 131, and an orthogonal projection of the first opening 131 on the binding layer 13 covers the binding electrode 122. Alternatively, thin-film transistor layer 13 is disposed away from bonding area 102.

The first opening 1312 extends to an edge of the bonding region 102 away from the display region 101 and exposes at least a portion of the edge of the array substrate 10.

In a preferred embodiment, an orthographic projection of the first opening 1312 on the array substrate 10 covers the bonding region 102 and exposes a portion of the edge of the bonding layer 12. That is, the multi-layered insulating layer 131 has an end point at the border of the display area 101 and the binding area 102 to escape from the binding area 102.

By providing the first opening 1312 on the thin-film transistor layer 13, the first opening 1312 allows the flip-chip film to enter the first opening 1312 and be directly bonded to the bonding electrode 122. In other words, the first opening 1312 is configured as a place for the bonding of the flip chip film and the bonding electrode 122. It can be seen that the first opening 1312 may help reduce the number of circuits or traces in the bonding area 102 or the peripheral area, thereby also reducing the required width of the bonding area 102.

Openings in the thin-film-transistor layer 13, such as the first opening 1312, may be formed using any suitable method (e.g., mechanical drilling, laser drilling, inserting a thermal element, etc.) and may have any suitable shape (circular, linear, other suitable shapes, etc.).

Specifically, the multi-layered insulating layer 131 may be one or a combination of a buffer layer, a gate insulating layer, an interlayer dielectric layer, a passivation layer, and a planarization layer. In other embodiments, the multi-layered insulating layer may further include a pixel defining layer or a spacer layer.

Specifically, the metal traces include a Data line, a Gate line, a VDD line, and a VSS line. The Data line, the Gate line, the VDD line and the VSS line are electrically connected to the first bonding lead, the second bonding lead, the third bonding lead and the third bonding lead through vias 1311, respectively.

In specific implementation, the gate insulating layer or the interlayer dielectric layer may be independently silicon oxide, silicon nitride, silicon oxynitride, and/or the like, respectively. These may be used alone or in combination thereof. The passivation layer, the buffer layer, or the planarization layer may each independently include an organic material, such as polyimide, epoxy-based resin, acrylic resin, polyester, and/or the like.

Specifically, the thin-film transistor layer 13 further includes a plurality of at least one thin-film transistor formed in the multi-layer insulating layer 131.

Specifically, the thin film transistor includes an active layer, a gate electrode, a drain electrode, and a source electrode. Here, the phrase "at least one thin film transistor formed in the multilayer insulating layer 131" is at least understood to mean that a plurality of metal layers and semiconductor layers constituting the thin film transistor are provided between the plurality of insulating layers. Correspondingly, the multilayer metal layer includes a gate metal layer and a source/drain metal layer, and in other embodiments, the multilayer metal layer may further include a pixel electrode layer.

In a specific implementation, the material of the semiconductor layer may be a silicon compound of polysilicon or an oxide semiconductor. The oxide semiconductor may be, but is not limited to, Indium Gallium Zinc Oxide (IGZO), Zinc Tin Oxide (ZTO), Indium Tin Zinc Oxide (ITZO), and/or the like.

The gate, the drain, and the source may include a metal, an alloy, or a metal nitride. For example, the gate electrode 1123 may include a metal such as aluminum (Al), silver (Ag), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), and neodymium (Nd), an alloy thereof, and/or a nitride thereof. These may be used alone or in combination thereof.

It should be noted that the present invention does not limit the type or structure of the thin film transistor. In specific implementation, the thin-film transistor layer may be configured to implement a driving or switching function of the light emitting device 20. For example, the thin film transistor may be a polysilicon transistor, an amorphous silicon transistor, an organic thin film transistor, a metal oxide transistor, a carbon nanotube or graphene transistor, other nanoparticle-based transistors, and the like.

In other embodiments, interconnect lines, integrated circuits, driver integrated circuits, other conductive structures, or combinations of these conductive structures associated with thin film transistors or other image pixel arrays may also be provided within the multilayer insulating layer 131.

As shown in fig. 2, the light emitting device 20 is disposed on the array substrate 10 and located in the display region 101, and the light emitting device 20 is electrically connected to the array substrate 10.

Optionally, in this embodiment, the light emitting device 20 is a Micro light emitting diode (Micro LED) or an organic light emitting device, and the structure of the light emitting device 20 may be changed in real time according to different display requirements.

For example, as shown in fig. 2, in the present embodiment, the light emitting device 20 is a micro light emitting diode, and the micro light emitting diode is bound to the array substrate 10 through its bonding electrode and is electrically connected to the thin film transistor.

In specific implementation, the thin film transistor drives or controls the light emitting device 20 to emit light or display according to the current signal received from the bonding wire 121.

FIG. 3 is a schematic structural diagram of a display device according to the present invention. As shown in fig. 3, the present invention further provides a display device, which includes the display panel of the present invention. For the specific structure of the display panel, please refer to the above, which is not described herein again.

As shown in fig. 3, the printed circuit board 50 is disposed on a surface of the display panel facing away from the light emitting device 20.

In particular implementations, the printed circuit board 50 may be formed from a rigid printed circuit board material (e.g., glass fiber filled epoxy), a sheet of flexible material (such as a polymer), or a combination of rigid and flexible materials (sometimes referred to as a "rigid-flex" printed circuit board). Flexible printed circuits ("flex circuits") may be formed, for example, from flexible polyimide sheets.

As shown in fig. 3, the display device further includes a chip on film 40, and the chip on film 40 is vertically disposed on one side of the bonding region 102 away from the display region 101.

As shown in fig. 3, the chip on film 40 has a first bonding end 41 facing the light emitting device 20 and a second bonding end 42 opposite to the first bonding end 41.

As shown in fig. 3, the first binding end 41 is bent and extended into the first opening 1312 to bind with the binding electrode 122 located in the first opening 1312. The second binding end 42 is bent to extend to a side of the display panel facing away from the light emitting device 20 and is bound with the printed circuit board 50.

In practical implementation, a eutectic conductive layer is disposed between the bonding electrode 122 of the display panel and the bonding electrode of the first bonding terminal 41.

In a specific implementation, the bonding electrode of the flip chip 40 is at least one of copper or gold. By using copper or gold as the bonding electrode material of the chip on film 40, the eutectic conductive layer can be formed between the bonding electrode of the chip on film 40 and the bonding electrode 122 of the display panel, so as to improve the bonding strength.

As shown in fig. 3, the display panel further includes an encapsulation adhesive layer 30, and the encapsulation adhesive layer 30 is disposed on the light emitting device 20 and covers the light emitting device 20, the array substrate 10, and the first bonding end 41 extending into the first opening 1312.

By providing the encapsulating adhesive layer 30, not only the light emitting device 20 and the display panel can be protected, but also the first opening 1312 can be filled.

In specific implementation, the encapsulation adhesive layer 30 is formed by melting a thermoplastic adhesive film.

According to the display panel and the display device, the binding layer 12 is arranged between the thin film transistor layer 13 and the substrate 11, and meanwhile, the metal wiring of the thin film transistor layer 13 is electrically connected to the binding layer 12 through the through hole 1311, so that the range of the binding region 102 can be reduced, the purpose of reducing a frame is achieved, and the problems that precision grinding is needed before printing and the packaging glue at the edge of a circuit is not easy to level and the splicing effect is influenced existing in a side printing circuit can be solved; by arranging the welding material layer on the bonding electrode 122, compared with the ACF adhesive, the resistance can be reduced, and the length in the bonding region 102 can be effectively shortened; meanwhile, the welding material layer and the binding electrode material on the driving chip can form an eutectic material, so that the binding strength can be effectively improved; by extending the packaging adhesive 40 to the binding region, the packaging adhesive 40 can cover the binding region 102, so that the binding strength can be effectively improved, and the bound metal can be prevented from being oxidized.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The display panel and the display device provided by the embodiment of the present invention are described in detail above, and the principle and the embodiment of the present invention are explained in the present document by applying specific examples, and the description of the above embodiments is only used to help understanding the technical scheme and the core idea of the present invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.