阅读说明：本技术 阵列基板及其制备方法、显示面板 (Array substrate, preparation method thereof and display panel ) 是由 蔡振飞 于 2020-12-14 设计创作，主要内容包括：本发明提供的一种阵列基板及其制备方法、显示面板,该阵列基板通过在所述双栅极薄膜晶体管设置过孔,所述双栅极薄膜晶体管的顶栅和底栅通过所述过孔电连接,所述GOA电路通过所述扫描线与所述顶栅或底栅电连接,使得所述顶栅将扫描信号传递至所述底栅,或者将所述底栅的扫描信号传递至所述顶栅,从而实现单根扫描线驱动所述双栅极薄膜晶体管,进而减少所述GOA电路的数量,达到缩窄显示面板边框的效果。(According to the array substrate, the double-gate thin film transistor is provided with the through hole, the top gate and the bottom gate of the double-gate thin film transistor are electrically connected through the through hole, the GOA circuit is electrically connected with the top gate or the bottom gate through the scanning line, so that the top gate transmits a scanning signal to the bottom gate or transmits the scanning signal of the bottom gate to the top gate, the double-gate thin film transistor is driven by a single scanning line, the number of the GOA circuits is reduced, and the effect of narrowing the frame of the display panel is achieved.)

1. An array substrate, comprising:

a substrate;

the plurality of sub-pixels are arranged on the substrate and are arranged in an array;

the GOA circuit is arranged outside the area where the plurality of sub-pixels are located; and

a plurality of scanning lines electrically connected with the sub-pixels and the GOA circuit;

the sub-pixels comprise at least one double-gate thin film transistor, the double-gate thin film transistor is provided with a through hole, the top gate and the bottom gate of the double-gate thin film transistor are electrically connected through the through hole, and the GOA circuit is electrically connected with the top gate or the bottom gate through the scanning line.

2. The array substrate of claim 1, wherein the dual-gate thin film transistor is a dual-gate oxide semiconductor thin film transistor.

3. The array substrate of claim 1, wherein the sub-pixels further comprise at least one polysilicon thin film transistor.

4. The array substrate of claim 1, wherein the circuit of the sub-pixel comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor and 1 capacitor, and at least two of the thin film transistors of the sub-pixel are double-gate oxide semiconductor thin film transistors.

5. The array substrate of claim 1, wherein a connection electrode is disposed in the via hole, and the top gate and the bottom gate of the dual-gate thin film transistor are electrically connected through the connection electrode in the via hole.

6. A display panel comprising the array substrate according to any one of claims 1 to 5.

7. A preparation method of an array substrate is characterized by comprising the following steps:

preparing a plurality of sub-pixels, a GOA circuit and a plurality of scanning lines on a substrate, wherein the sub-pixels comprise at least one double-gate thin film transistor;

and forming a through hole on the double-gate thin film transistor, so that the top gate and the bottom gate of the double-gate thin film transistor are electrically connected through the through hole, and the GOA circuit is electrically connected with the top gate or the bottom gate through the scanning line.

8. The method of claim 7, wherein the method of fabricating the sub-pixel comprises:

forming a polycrystalline silicon semiconductor layer on the substrate;

forming a first grid electrode insulating layer, a first grid electrode, a second grid electrode insulating layer and a second grid electrode on the polycrystalline silicon semiconductor layer in sequence, wherein the second grid electrode is used as a bottom grid of the double-grid electrode thin film transistor;

forming a first interlayer dielectric layer on the second grid electrode, and forming a first interlayer dielectric layer hole on the first interlayer dielectric layer;

forming an oxide semiconductor layer on the interlayer dielectric layer;

depositing a third gate insulating layer and a third gate in sequence on the semiconductor layer, wherein the third gate is used as a top gate of the double-gate thin film transistor;

forming a second interlayer dielectric layer on the third gate electrode, forming a second interlayer dielectric layer hole on the second interlayer dielectric layer, wherein the first interlayer dielectric layer hole and the second interlayer dielectric layer hole are used as through holes of the double-gate thin film transistor;

and forming a first source drain layer on the second interlayer dielectric layer, wherein the first source drain layer comprises a connecting electrode, and the top gate and the bottom gate of the dual-gate thin film transistor are electrically connected through the connecting electrode in the through hole.

9. The method of claim 8, wherein the method of preparing the sub-pixel further comprises:

sequentially forming a passivation layer, a first flat layer, a second source drain layer and a second flat layer on the first source drain layer;

depositing an anode on the second planar layer;

a pixel defining layer is formed on the anode, and a support pillar is disposed on the pixel defining layer.

10. The method according to claim 8, wherein the oxide semiconductor layer material is at least one of indium gallium zinc oxide, indium tin zinc oxide or indium gallium zinc tin oxide.

Technical Field

The application relates to the technical field of display, in particular to an array substrate, a preparation method of the array substrate and a display panel.

Background

The flat display device has many advantages such as thin body, power saving, no radiation, etc., and is widely used. The conventional flat panel Display devices mainly include Liquid Crystal Displays (LCDs) and Organic Light Emitting Diodes (OLEDs). Thin Film Transistors (TFTs) are important components of flat panel display devices. TFTs may be formed on a glass substrate or a plastic substrate, and are generally used as switching parts and driving parts on flat display devices such as LCDs, OLEDs, and the like.

Currently, most OLED devices adopt a panel technology of LTPS (Low Temperature Poly-silicon) TFT (Thin Film Transistor). After the improvement of the past years, the LTPS display panel has the advantages of high resolution, high response speed, high brightness, high aperture ratio, etc., so that it becomes the most mature and mainstream TFT panel technology in the market today. Although being popular in the market, LTPS display panels have disadvantages of high production cost and large required power consumption. Therefore, a Low Temperature Polycrystalline Oxide (LTPO) display panel technology, that is, an LTPO display panel obtained by combining the LTPS display panel technology and the Oxide display panel technology, has been developed by technical personnel, and the LTPO display panel not only has the advantages of high resolution, high reaction speed, high brightness, high aperture ratio and the like of the LTPS display panel, but also has the advantages of Low production cost and Low power consumption.

However, the LTPO technology may cause an increase in leakage current of the tft, so the oxide semiconductor tft is usually used to replace a part of the LTPO circuit that is prone to leakage current, but in the actual development process, the oxide semiconductor tft is prone to threshold voltage shift, which causes an increase in leakage current, or even fails to be normally turned off, so a dual-gate design is introduced in the existing design, that is, one tft is controlled by upper and lower layers of scan lines, and the scan lines are connected to the same gate driving signal, so as to reduce leakage current. However, this technique can cause some side effects: the introduction of the dual gate signal causes a problem of an additional parasitic capacitance increase in the circuit, thereby causing an increase in RC Loading of the gate driving signal. In order to reduce the RC Loading, a group of GOA driving circuits needs to be additionally added to the right side of the AA area (display area), and the added group of GOA driving circuits may increase the frame of the display panel.

Disclosure of Invention

In order to solve the above problems, the present application provides an array substrate, a manufacturing method thereof, and a display panel, and aims to solve the problem that the number of GOA driving circuits is increased and the frame of the display panel is increased due to the introduction of dual-gate signals into a circuit.

In one aspect, the present invention provides an array substrate, including: a substrate; the plurality of sub-pixels are arranged on the substrate and are arranged in an array; the GOA circuit is arranged outside the area where the plurality of sub-pixels are located; the plurality of scanning lines are electrically connected with the sub-pixels and the GOA circuit;

the sub-pixels comprise at least one double-gate thin film transistor, the double-gate thin film transistor is provided with a through hole, the top gate and the bottom gate of the double-gate thin film transistor are electrically connected through the through hole, and the GOA circuit is electrically connected with the top gate or the bottom gate through the scanning line to transmit scanning driving signals of the GOA circuit.

In some embodiments, the double-gate thin film transistor is a double-gate oxide semiconductor thin film transistor.

In some embodiments, the sub-pixel further comprises at least one polysilicon thin film transistor.

In some embodiments, the circuit of the sub-pixel includes a first thin film transistor (T1), a second thin film transistor (T2), a third thin film transistor (T3), a fourth thin film transistor (T4), a fifth thin film transistor (T5), a sixth thin film transistor (T6), a seventh thin film transistor (T7), and 1 capacitor (C1), and at least two of the thin film transistors of the sub-pixel are double-gate oxide semiconductor thin film transistors.

In some embodiments, a connection electrode is disposed in the via hole, and the top gate and the bottom gate of the dual-gate thin film transistor are electrically connected through the connection electrode in the via hole.

In some embodiments, the material of the connection electrode is a transparent conductive material.

In another aspect, the present invention provides a display panel, including the array substrate according to the first aspect.

In another aspect, the present invention provides a method for manufacturing an array substrate, including:

preparing a plurality of sub-pixels, a GOA circuit and a plurality of scanning lines on a substrate, wherein the sub-pixels comprise at least one double-gate thin film transistor;

and forming a through hole on the dual-gate thin film transistor, so that a top gate and a bottom gate of the dual-gate thin film transistor are electrically connected through the through hole, and the GOA circuit is electrically connected with the top gate or the bottom gate through the scanning line, so that the top gate scanning signal is transmitted to the bottom gate, or the bottom gate scanning signal is transmitted to the top gate, thereby realizing that a single scanning driving line simultaneously drives the dual-gate thin film transistor.

In some embodiments, a method of making the sub-pixel comprises:

forming a polycrystalline silicon semiconductor layer on the substrate;

forming a first grid electrode insulating layer, a first grid electrode, a second grid electrode insulating layer and a second grid electrode on the polycrystalline silicon semiconductor layer in sequence, wherein the second grid electrode is used as a bottom grid of the double-grid electrode thin film transistor;

forming a first interlayer dielectric layer on the second grid electrode, and forming a first interlayer dielectric layer hole on the first interlayer dielectric layer;

forming an oxide semiconductor layer on the interlayer dielectric layer;

depositing a third gate insulating layer and a third gate in sequence on the semiconductor layer, wherein the third gate is used as a top gate of the double-gate thin film transistor;

forming a second interlayer dielectric layer on the third gate electrode, forming a second interlayer dielectric layer hole on the second interlayer dielectric layer, wherein the first interlayer dielectric layer hole and the second interlayer dielectric layer hole are used as through holes of the double-gate thin film transistor;

and forming a first source drain layer on the second interlayer dielectric layer, wherein the first source drain layer comprises a connecting electrode, and the top gate and the bottom gate of the dual-gate thin film transistor are electrically connected through the connecting electrode in the through hole.

In some embodiments, the method of manufacturing a sub-pixel further comprises:

sequentially forming a passivation layer, a first flat layer, a second source drain layer and a second flat layer on the first source drain layer;

depositing an anode on the second planar layer;

a pixel defining layer is formed on the anode, and a support pillar is disposed on the pixel defining layer.

In some embodiments, the oxide semiconductor layer material employs at least one of indium gallium zinc oxide, indium tin zinc oxide, or indium gallium zinc tin oxide.

In some embodiments, the polysilicon semiconductor layer is of a thickness of。

According to the array substrate provided by the invention, the through holes are formed in the dual-gate thin film transistor, the top gate and the bottom gate of the dual-gate thin film transistor are electrically connected through the through holes, the GOA circuit is electrically connected with the top gate or the bottom gate through the scanning lines, so that the scanning signals of the top gate are transmitted to the bottom gate, or the scanning signals of the bottom gate are transmitted to the top gate, and therefore, the dual-gate thin film transistor is driven by a single scanning line, the number of GOA driving circuits is further reduced, and the effect of narrowing the frame of a display panel is achieved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below.

FIG. 1 is a schematic diagram of a 7T1C circuit provided in the prior art;

FIG. 2 is a schematic diagram of a 7T1C planar structure provided in the prior art;

FIG. 3 is a schematic cross-sectional view of an array substrate provided in the prior art;

FIG. 4 is a schematic diagram of a planar structure of an array substrate provided in the prior art;

FIG. 5 is a schematic view of a 7T1C planar structure provided in an embodiment of the present invention;

FIG. 6 is a schematic diagram of a planar structure of an array substrate provided in an embodiment of the present invention;

fig. 7 is a schematic cross-sectional structure diagram of an array substrate provided in an embodiment of the invention.

Wherein the reference numbers indicate:

11. 21-bottom gate; 12. 22-top gate; 23-a via hole; 24-a first flexible substrate layer; 25-a first buffer layer; 26-a second flexible substrate layer; 27-a second buffer layer; 28-an insulating layer; 29-a polysilicon semiconductor layer; 210-a first gate insulation layer; 211-a first gate; 212-a second gate insulation layer; 213-first interlayer dielectric layer; 214-an oxide semiconductor layer; 215-third gate insulation layer; 216-a second interlayer dielectric layer; 217-first source drain; 218-a passivation layer; 219 — first flat layer; 220-a second source drain layer; 221-a second planar layer; 222-an anode; 223-a pixel definition layer; 224-support column.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first," "second," etc. may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

The LTPO technique may cause an increase in leakage current of the tft, so that the oxide semiconductor tft is usually used to replace a portion of the LTPO circuit which is prone to leakage, for example, a 7T1C circuit is shown in fig. 1, where T1, T2, T3, T4, T5, T6, and T7 are respectively a first tft, a second tft, a third tft, a fourth tft, a fifth tft, a sixth tft, and a seventh tft, Data is a Data signal input terminal, Vdd is a power source terminal, Vss is a common voltage terminal, EM is a control signal terminal, C1 is a storage capacitor, Xscan is a first Scan signal terminal, Scan vth is a second Scan signal terminal, Scan Data is a Data voltage terminal, Reset is a Reset signal terminal, and VI is a reference voltage terminal.

T3 and T4 in fig. 1 are oxide semiconductor thin film transistors, and other thin film transistors, for example, T1, T2, T5, T6, and T7 are semiconductor thin film transistors manufactured by LTPO technology. The arrangement of the oxide semiconductor thin film transistor can prevent the electric charge of the grid electrode of the driving thin film transistor T1 from being leaked, and low-frequency driving is easy to realize, so that the power consumption of the panel is reduced; however, in the actual development process, the problem of threshold voltage shift of the oxide semiconductor thin film transistor is easily caused, which causes the problem that the leakage current of T3 and T4 is increased, and even the normal shutdown is not realized.

Referring to fig. 2 and fig. 3, a double-gate design (bottom gate 11, top gate 12) is introduced into the conventional design, i.e., one tft is controlled by upper and lower layers of scan lines, and the scan lines are connected to the same gate driving signal, so as to reduce the leakage current. In fig. 2, Vdd is a power supply terminal, Vdata is a Data signal input terminal (i.e., Data), Scan1 is a Reset signal terminal (i.e., Reset), Scan Data is a Data voltage terminal, Xscan is a first Scan signal terminal, Scan vth is a second Scan signal terminal, and Emit is a control signal terminal (i.e., EM). However, this technique can cause some side effects: the introduction of the dual gate signal results in additional parasitic capacitance added to the 1, 2, and 3 portions as shown in fig. 2, thereby resulting in an increase in RC Loading of the gate driving signal. As shown in fig. 4, one row of P-scan, one row of N-scan, and one row of EMIT represent a group of GOA (Gate Driver on Array) circuits, the AA area (display area) includes a plurality of sub-pixels, the plurality of sub-pixels includes a plurality of sub-pixel circuits and pixel electrodes, in order to reduce the RC Loading, an additional group of GOA driving circuits needs to be added to the right side of the AA area, and the additional group of GOA driving circuits may increase the frame of the display panel.

In order to solve the above problems, embodiments of the present invention provide an array substrate, a method for manufacturing the array substrate, and a display panel, which are described in detail below.

First, referring to fig. 5 to 7, an embodiment of the invention provides an array substrate, including:

a substrate, a plurality of sub-pixels, a GOA circuit, and a plurality of scan lines (not shown). The plurality of sub-pixels are arranged on the substrate and are arranged in an array, the GOA circuit is arranged on the outer side of the area where the plurality of sub-pixels are located, and the plurality of scanning lines are electrically connected with the sub-pixels and the GOA circuit.

In one embodiment, the sub-pixel comprises at least one double-gate thin film transistor comprising a semiconductor layer 214, a top gate 22 and a bottom gate 21; two ends of the semiconductor layer are respectively electrically connected with the source electrode and the drain electrode; the top gate 22 and the bottom gate 21 are respectively arranged on the upper side and the lower side of the semiconductor layer and used for reducing the leakage current of the double-gate thin film transistor.

In one embodiment, the sub-pixel further comprises at least one polysilicon thin film transistor.

Specifically, the double-gate thin film transistor further includes, between the substrate and the bottom gate, a first flexible substrate layer (PI)24, a first buffer layer 25(buf), a second flexible substrate layer 26, a second buffer layer 27, an insulating layer 28, a polysilicon semiconductor layer 29, a first gate insulating layer (GI)210, and a first Gate Electrode (GE) 211.

In particular, the substrate may be made of a transparent insulating material, such as glass, quartz or other suitable materials.

Specifically, the material of the first gate insulating layer 210 may include silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiNxOy), or other suitable materials, such as organic resin materials.

Specifically, the material of the polysilicon semiconductor layer 29 is low-temperature polysilicon, or low-temperature polysilicon oxide, and in a preferred embodiment, is low-temperature polysilicon oxide.

The bottom gate 21 serves as a second gate, a first interlayer dielectric layer 213(ILD) is further arranged between the second gate and the semiconductor layer, and a first interlayer dielectric layer hole is formed in the first interlayer dielectric layer 213.

The top gate 22 serves as a third gate, and the source and the drain serve as a first source and drain 217. A second interlayer dielectric layer 216 is further disposed between the third gate and the source and the drain, a second interlayer dielectric layer hole is formed in the second interlayer dielectric layer 216, the first interlayer dielectric layer hole and the second interlayer dielectric layer hole are used as a via hole 23 of the dual-gate thin film transistor, and the via hole 23 can be used as a through hole to realize signal transmission between the top gate 22 and the bottom gate 21.

The top gate 22 and the bottom gate 21 of the dual-gate thin film transistor are electrically connected through the via hole 23, and the GOA circuit is electrically connected with the top gate 22 or the bottom gate 21 through the scanning line to transmit a scanning driving signal of the GOA circuit.

Specifically, the material of the first gate electrode 211, the top gate 22 and the bottom gate 21 may be formed of one or more selected from molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti) or an alloy formed by any combination of the above metals, or other suitable materials. In addition, the first gate electrode 211, the top gate 22 and the bottom gate 21 may also have a single-layer or multi-layer structure.

The double-gate thin film transistor provided by the embodiment may further include a passivation layer 218(PV), where the passivation layer 218 is disposed on the source and drain electrodes, and may cover the entire thin film transistor to provide protection. A Planarization Layer (PLN) and a second source/drain electrode, an anode 222, and a pixel defining layer 223(PDL) are further disposed on the passivation layer 218, and a support pillar 224(PS) is further disposed on the pixel defining layer 223.

The material of the passivation layer 218 may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), or other suitable materials. For example, the passivation layer 218 may have a single-layer structure of silicon nitride or silicon oxide, or a multi-layer structure of silicon nitride and silicon oxide.

The double-gate thin film transistor is a double-gate oxide semiconductor thin film transistor.

Specifically, the oxide semiconductor material of the double-gate oxide semiconductor thin film transistor may be Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO), Indium Gallium Zinc Tin Oxide (IGZTO), or the like, and may have a single-layer structure or a multi-layer structure.

In some embodiments, as shown in fig. 5, the circuit of the sub-pixel has a 7T1C structure, including a first thin film transistor (T1), a second thin film transistor (T2), a third thin film transistor (T3), a fourth thin film transistor (T4), a fifth thin film transistor (T5), a sixth thin film transistor (T6), a seventh thin film transistor (T7), a capacitor (C1), a power supply terminal (Vdd), a Data signal input terminal (Vdata, i.e., Data), a Reset signal terminal (scan1, i.e., Reset), a Data voltage terminal (scan Data), a first scan signal terminal (Xscan), a second scan signal terminal (scan vth), and a control signal terminal (Emit, i.e., EM).

Specifically, at least two of the thin film transistors of the sub-pixels are double-gate oxide semiconductor thin film transistors.

As shown in fig. 7, cross-sectional views of a semiconductor thin film transistor and a dual gate oxide semiconductor thin film transistor fabricated using LTPO or LTPS technology in a 7T1C circuit are shown, respectively. The third thin film transistor and the fourth thin film transistor are double-gate oxide semiconductor thin film transistors. The first thin film transistor (T1), the second thin film transistor (T2), the fifth thin film transistor (T5), the sixth thin film transistor (T6) and the seventh thin film transistor (T7) are semiconductor thin film transistors manufactured by LTPO or LTPS technology. Through holes 23 are formed in the third thin film transistor and the fourth thin film transistor.

It should be noted that, in the embodiment of the present invention, only the circuit structure of 7T1C is listed, and it is understood that, in some other embodiments of the present invention, structures such as 6T1C, 7T2C, etc. may also be used, and the specific details are not limited herein.

In some embodiments, a connection electrode is disposed in the via 23, and the top gate 22 and the bottom gate 21 of the dual-gate thin film transistor are electrically connected through the connection electrode in the via 23.

Specifically, the material of the connection electrode is a transparent conductive material, such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Gallium Oxide (IGO), Gallium Zinc Oxide (GZO), or a carbon nanotube.

According to the array substrate provided by the invention, the through hole 23 is formed in the dual-gate thin film transistor, the top gate 22 and the bottom gate 21 of the dual-gate thin film transistor are electrically connected through the through hole 23, and the GOA circuit is electrically connected with the top gate 22 or the bottom gate 21 through the scanning line, so that the scanning signal of the top gate 22 is transmitted to the bottom gate 21, or the scanning signal of the bottom gate 21 is transmitted to the top gate 22, and thus the dual-gate thin film transistor is driven by a single scanning driving line, as shown in FIG. 6, the number of the GOA driving circuits is reduced, and the effect of narrowing the frame of the display panel is achieved.

Based on the same inventive concept, an embodiment of the present invention provides a display panel, including the array substrate provided in the embodiment of the present invention. The display panel can be applied to any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

For example, one example of the display panel is a liquid crystal display panel including an array substrate and an opposite substrate, which are opposite to each other to form a liquid crystal cell in which a liquid crystal material is filled. The counter substrate is, for example, a color filter substrate. The pixel electrode of each sub-pixel of the array substrate is used for applying an electric field to control the rotation degree of the liquid crystal material so as to perform display operation. In general, a liquid crystal display panel includes a backlight which is disposed on the rear side of an array substrate with respect to a counter substrate, for example.

Another example of the display panel is an Organic Light Emitting Diode (OLED) display panel, wherein organic light emitting diodes are formed on the array substrate, and a pixel electrode of each of the sub-pixels may serve as an anode 222 or a cathode of the organic light emitting diode or may be electrically connected to the anode 222 or the cathode of the organic light emitting diode for driving the organic light emitting diode to emit light for a display operation.

Still another example of the display panel is an electronic paper display panel, wherein an electronic ink layer is formed on the array substrate, and a pixel electrode of each of the sub-pixels serves as a voltage for applying a voltage for driving charged microparticles in the electronic ink to move for a display operation.

In another aspect, the present invention provides a method for manufacturing an array substrate, including:

preparing a plurality of sub-pixels, a GOA circuit and a plurality of scanning lines on a substrate, wherein the sub-pixels comprise at least one double-gate thin film transistor;

forming a via hole 23 on the dual-gate thin film transistor, so that a top gate 22 and a bottom gate 21 of the dual-gate thin film transistor are electrically connected through the via hole 23, and the GOA circuit is electrically connected with the top gate 22 or the bottom gate 21 through the scanning line, so that a scanning signal of the top gate 22 is transmitted to the bottom gate 21, or a scanning signal of the bottom gate 21 is transmitted to the top gate 22, thereby realizing that a single scanning driving line simultaneously drives the dual-gate thin film transistor.

In some embodiments, a method of making the sub-pixel comprises:

s1, forming a polycrystalline silicon semiconductor layer 29(poly-si) on the substrate, and forming a polycrystalline silicon semiconductor pattern through a photoetching process;

s2, sequentially forming a first grid electrode insulating layer 210, a first grid electrode 211, a second grid electrode insulating layer 212 and a second grid electrode on the polycrystalline silicon semiconductor layer 29, forming corresponding patterns through a photoetching process, wherein the second grid electrode is used as a bottom grid electrode 21 of the double-grid electrode thin film transistor, and the bottom grid electrode 21 is connected with the GOA circuit to receive scanning driving signals;

s3, forming a first interlayer dielectric layer 213 on the second grid electrode, and forming a first interlayer dielectric layer hole on the first interlayer dielectric layer 213 by utilizing photoetching and dry etching;

s4, forming an oxide semiconductor layer 214 on the first interlayer dielectric layer 213, and forming an oxide semiconductor layer 214 pattern through a photoetching process;

s5, sequentially depositing a third grid electrode insulating layer 215 and a third grid electrode on the semiconductor layer, and forming a third grid electrode pattern through photoetching, wherein the third grid electrode is used as a top grid 22 of the double-grid-electrode thin film transistor;

s6, forming a second interlayer dielectric layer 216 on the third grid electrode, forming a second interlayer dielectric layer hole on the second interlayer dielectric layer 216 by utilizing photoetching and dry etching, wherein the first interlayer dielectric layer hole and the second interlayer dielectric layer hole are used as through holes 23 of the double-grid thin film transistor;

and S7, forming a first source drain 217 layer on the second interlayer dielectric layer 216, forming corresponding patterns and connecting electrodes by utilizing photoetching and wet etching, wherein the top gate 22 and the bottom gate 21 of the double-gate thin film transistor are electrically connected through the connecting electrodes in the through holes 23, and the scanning signal of the bottom gate 21 is supplied to the top gate 22.

Specifically, a first flexible substrate layer 24, a first buffer layer 25, a second flexible substrate layer 26, and a second buffer layer 27 may be formed in this order between the substrate and the polycrystalline silicon semiconductor layer 29.

The present invention further provides an embodiment, which is different from the above embodiment, in that the top gate 22 is connected to the GOA circuit to receive the scan driving signal, so that the scan signal of the top gate 22 is supplied to the bottom gate 21, other steps are the same, and repeated parts are not described again.

In some embodiments, the method of manufacturing a sub-pixel further comprises:

s8, forming a passivation layer 218 on the first source drain 217 layer, and forming a passivation hole through photoetching and dry etching;

s9, forming a first flat layer 219 on the passivation layer 218, and forming a first flat layer hole by utilizing photoetching;

s10, forming a second source drain layer 220 on the first flat layer 219, and forming patterns by utilizing photoetching and wet etching;

s11, forming a second flat layer 221 on the second source drain layer 220, and forming a second flat layer hole by utilizing photoetching;

s12, depositing an ITO/Ag/ITO anode 222 on the second flat layer 221;

s13. a pixel defining layer 223 is formed on the anode 222, and a supporting column 224 is disposed on the pixel defining layer 223.

In some embodiments, the oxide semiconductor layer 214 is at least one of indium gallium zinc oxide, indium tin zinc oxide, or indium gallium zinc tin oxide.

In some embodiments, the polysilicon semiconductor layer 29 is as thick as。

According to the preparation method of the array substrate, the through hole 23 penetrating through the first interlayer dielectric layer 213 and the second interlayer dielectric layer 216 is obtained through photoetching and dry etching, and the connecting electrode is arranged in the through hole 23, so that only one of the bottom gate 21 and the top gate 22 is needed to be connected with the GOA circuit, the scanning signal of the top gate 22 is supplied to the bottom gate 21, or the scanning signal of the bottom gate 21 is supplied to the top gate 22, and the bottom gate 21 and the top gate 22 can both receive the scanning driving signal of the GOA circuit, and further the manufacturing process of the GOA driving circuit can be reduced.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and a part which is not described in detail in a certain embodiment may refer to the detailed descriptions in the other embodiments, and is not described herein again.

In a specific implementation, each unit or structure may be implemented as an independent entity, or may be combined arbitrarily to be implemented as one or several entities, and the specific implementation of each unit or structure may refer to the foregoing method embodiment, which is not described herein again.

The array substrate, the manufacturing method thereof, and the display panel provided in the embodiments of the present application are described in detail above, and the principles and embodiments of the present invention are explained herein by applying specific examples, and the description of the embodiments above is only used to help understanding the method and the core concept of the present invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.