阅读说明：本技术 显示面板及其制作方法 (Display panel and manufacturing method thereof ) 是由 彭浩 朴宇成 赵慧慧 何家庆 于 2020-12-15 设计创作，主要内容包括：本申请提出了一种显示面板及其制作方法。该显示面板包括位于显示区内通过第一过孔与第一有源层电连接的第一源漏极层,与第一源漏极层同层的第二源漏极层,第二源漏极层通过第二过孔与第二有源层电连接；绑定区内的开口至少包括远离衬底的第一子开口以及靠近衬底的第二子开口,第一子开口贯穿的膜层数量与第一过孔和/或第二过孔贯穿的膜层数量相同。本申请通过设置位于绑定区内的第一子开口贯穿的膜层与第一过孔和/或第二过孔贯穿的膜层相同,使第一子开口可以与第一过孔和/或第二过孔在同一工序中、使用同一光罩形成,减少了制程中用于形成过孔和开口的光罩的数量,降低了显示面板的生产成本,提高了显示面板的产品良率。(The application provides a display panel and a manufacturing method thereof. The display panel comprises a first source drain layer and a second source drain layer, wherein the first source drain layer is positioned in the display area and electrically connected with the first active layer through a first through hole; the openings in the binding region at least comprise first sub-openings far away from the substrate and second sub-openings close to the substrate, and the number of the film layers penetrated by the first sub-openings is the same as that of the film layers penetrated by the first via holes and/or the second via holes. The film layer that this application runs through setting up the first sub-opening that is located the binding area is the same with the film layer that first via hole and/or second via hole run through, makes first sub-opening can be in same process with first via hole and/or second via hole, uses same light cover to form, has reduced the quantity that is used for forming via hole and open-ended light cover in the processing procedure, has reduced display panel's manufacturing cost, has improved display panel's product yield.)

1. A display panel is characterized by comprising a display area and a binding area positioned on one side of the display area, wherein a substrate and a thin film transistor layer positioned on the substrate are arranged in the display area;

the thin film transistor layer comprises a first thin film transistor positioned in the display area and a second thin film transistor electrically connected with the first thin film transistor, a first source drain layer of the first thin film transistor and a second source drain layer of the second thin film transistor are arranged on the same layer, the first source drain layer is electrically connected with the first active layer through a first through hole, and the second source drain layer is electrically connected with the second active layer through a second through hole;

the bonding region is internally provided with an opening penetrating through a film layer between the first source drain layer and the substrate, the opening at least comprises a first sub-opening far away from the substrate and a second sub-opening close to the substrate, and the number of the film layers penetrating through the first sub-opening is the same as that of the film layers penetrating through the first via hole and/or the second via hole.

2. The display panel according to claim 1, wherein the first active layer and the second active layer are disposed in different layers, and a film layer through which the first sub-opening penetrates is the same as a film layer through which the first via hole or the second via hole penetrates.

3. The display panel according to claim 2, wherein the first via hole comprises a first sub-via hole at a side away from the substrate and a second sub-via hole at a side close to the substrate; alternatively, the first and second electrodes may be,

the second via hole comprises a third sub-via hole at one side far away from the substrate and a fourth sub-via hole at one side close to the substrate;

wherein the depth of the first sub-opening is the same as the depth of the first sub-via; alternatively, the first and second electrodes may be,

the depth of the first sub-opening is the same as the depth of the third sub-via.

4. The display panel according to claim 3, wherein the opening further comprises a third sub-opening located between the first sub-opening and the second sub-opening, and a film layer through which the third sub-opening passes is the same as a film layer through which the second sub-via passes; alternatively, the first and second electrodes may be,

the film layer penetrated by the third sub-opening is the same as the film layer penetrated by the fourth sub-via hole.

5. The display panel according to claim 4, wherein the first thin film transistor further comprises a first gate electrode on the first active layer and a third gate electrode on the first gate electrode, wherein the second thin film transistor further comprises a second gate electrode on the second active layer and a fourth gate electrode between the second active layer and the substrate, and wherein the first gate electrode and the fourth gate electrode are disposed on the same layer;

the thin film transistor layer further comprises a first insulating layer positioned between the first active layer and the first grid electrode, a second insulating layer positioned between the first grid electrode and the third grid electrode, a third insulating layer positioned between the fourth grid electrode and the second active layer, a fourth insulating layer positioned between the second active layer and the second grid electrode, and a fifth insulating layer positioned between the second grid electrode and the second source drain layer;

the first sub-opening penetrates through the fourth insulating layer and the fifth insulating layer, and the third sub-opening penetrates through the first insulating layer, the second insulating layer and the third insulating layer.

6. The display panel according to claim 5, wherein the display panel further comprises a buffer layer on the substrate and a protective layer between the buffer layer and the first active layer, and the second sub-opening penetrates through the buffer layer and the protective layer.

7. The display panel according to claim 4, wherein the opening areas of the first sub opening, the third sub opening and the second sub opening decrease sequentially.

8. The display panel according to claim 4, wherein the first sub-opening comprises a first side close to one side of the display region, the second sub-opening comprises a second side close to one side of the display region, the third sub-opening comprises a third side close to one side of the display region, and obtuse angles formed by the first side, the third side and the second side with the substrate decrease in sequence.

9. The display panel according to claim 1, wherein the first sub-opening is filled with a first filling layer, the second sub-opening is filled with a second filling layer, and an elastic modulus of the first filling layer is different from an elastic modulus of the second filling layer.

10. A method for manufacturing a display panel is characterized by comprising the following steps:

forming a first active layer and a second active layer on the substrate in the display region;

forming a first sub-opening in a bonding region while forming a first via on the first active layer and/or forming a second via on the second active layer;

forming a second sub-opening between the first sub-opening and the substrate;

wherein, the film layer penetrated by the first sub-opening is the same as the film layer penetrated by the first via hole and/or the second via hole.

Technical Field

The present disclosure relates to display technologies, and particularly to a display panel and a manufacturing method thereof.

Background

With the increase of the demand of people for the display panel, how to reduce the production cost of the display panel and improve the yield of the display panel is a great improvement direction of the display panel.

In the existing LTPO (Low Temperature Polycrystalline Oxide) display panel manufacturing process, a source drain layer of a thin film transistor in a display area is electrically connected with an active layer through a via hole, and since openings in the via hole and a binding area need to be formed by using a photomask process respectively, the manufacturing process is complex, the product yield is difficult to improve, and the production cost is difficult to reduce.

Therefore, a display panel and a method for fabricating the same are needed to solve the above-mentioned problems.

Disclosure of Invention

The application provides a display panel, which is used for solving the problems that the product yield of an LTPO display panel is difficult to improve and the production cost is difficult to reduce due to the complex process of the LTPO display panel.

In order to solve the technical problem, the technical scheme provided by the application is as follows:

the application provides a display panel, which comprises a display area and a binding area positioned on one side of the display area, wherein a substrate and a thin film transistor layer positioned on the substrate are arranged in the display area;

the thin film transistor layer comprises a first thin film transistor positioned in the display area and a second thin film transistor electrically connected with the first thin film transistor, a first source drain layer of the first thin film transistor and a second source drain layer of the second thin film transistor are arranged on the same layer, the first source drain layer is electrically connected with the first active layer through a first through hole, and the second source drain layer is electrically connected with the second active layer through a second through hole;

the bonding region is internally provided with an opening penetrating through a film layer between the first source drain layer and the substrate, the opening at least comprises a first sub-opening far away from the substrate and a second sub-opening close to the substrate, and the number of the film layers penetrating through the first sub-opening is the same as that of the film layers penetrating through the first via hole and/or the second via hole.

In the display panel provided by the application, the first active layer and the second active layer are arranged in different layers, and the film layer penetrated by the first sub-opening is the same as the film layer penetrated by the first via hole or the second via hole.

In the display panel provided by the application, the first via hole comprises a first sub-via hole at one side far away from the substrate and a second sub-via hole at one side close to the substrate; alternatively, the first and second electrodes may be,

the second via hole comprises a third sub-via hole at one side far away from the substrate and a fourth sub-via hole at one side close to the substrate;

wherein the depth of the first sub-opening is the same as the depth of the first sub-via; alternatively, the first and second electrodes may be,

the depth of the first sub-opening is the same as the depth of the third sub-via.

In the display panel provided by the application, the opening further includes a third sub-opening located between the first sub-opening and the second sub-opening, and a film layer penetrated by the third sub-opening is the same as a film layer penetrated by the second sub-via hole; alternatively, the first and second electrodes may be,

the film layer penetrated by the third sub-opening is the same as the film layer penetrated by the fourth sub-via hole.

In the display panel provided by the present application, the first thin film transistor further includes a first gate electrode on the first active layer and a third gate electrode on the first gate electrode, the second thin film transistor further includes a second gate electrode on the second active layer and a fourth gate electrode between the second active layer and the substrate, and the first gate electrode and the fourth gate electrode are disposed on the same layer;

the thin film transistor layer further comprises a first insulating layer positioned between the first active layer and the first grid electrode, a second insulating layer positioned between the first grid electrode and the third grid electrode, a third insulating layer positioned between the fourth grid electrode and the second active layer, a fourth insulating layer positioned between the second active layer and the second grid electrode, and a fifth insulating layer positioned between the second grid electrode and the second source drain layer;

the first sub-opening penetrates through the fourth insulating layer and the fifth insulating layer, and the third sub-opening penetrates through the first insulating layer, the second insulating layer and the third insulating layer.

In the display panel provided by the application, the display panel further comprises a buffer layer located on the substrate and a protective layer located between the buffer layer and the first active layer, and the second sub-opening penetrates through the buffer layer and the protective layer.

In the display panel provided by the application, the opening areas of the first sub-opening, the third sub-opening and the second sub-opening are sequentially decreased progressively.

In the display panel that this application provided, first sub-opening includes and is close to the first side of display area one side, the second sub-opening includes and is close to the second side of display area one side, the third sub-opening includes and is close to the third side of display area one side, first side the third side and the second side with the obtuse angle that the substrate formed diminishes in proper order.

In the display panel provided by the application, the first sub-opening is filled with a first filling layer, the second sub-opening is filled with a second filling layer, and the elastic modulus of the first filling layer is different from that of the second filling layer.

The application also provides a manufacturing method of the display panel, which comprises the following steps:

forming a first active layer and a second active layer on the substrate in the display region;

forming a first sub-opening in a bonding region while forming a first via on the first active layer and/or forming a second via on the second active layer;

forming a second sub-opening between the first sub-opening and the substrate;

wherein, the film layer penetrated by the first sub-opening is the same as the film layer penetrated by the first via hole and/or the second via hole.

Has the advantages that: the film layer that this application runs through setting up the first sub-opening that is located the binding area is the same with the film layer that first via hole and/or second via hole run through, makes first sub-opening can be in same process with first via hole and/or second via hole, uses same light cover to form, has reduced the quantity that is used for forming via hole and open-ended light cover in the processing procedure, has reduced display panel's manufacturing cost, has improved display panel's product yield.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a first structural schematic diagram of a display panel according to the present application.

Fig. 2 is a second structural diagram of the display panel of the present application.

Fig. 3 is a third structural diagram of the display panel of the present application.

Fig. 4 is a fourth structural diagram of the display panel of the present application.

Fig. 5 is a schematic diagram of a fifth structure of the display panel of the present application.

Fig. 6 is a flowchart of a method for manufacturing a display panel according to the present application.

Fig. 7a to 7d are process flow diagrams of a manufacturing method of a display panel according to the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The conventional LTPO display panel has the problems that the manufacturing process is complex, the production cost is difficult to reduce, and the product yield is difficult to improve because the via hole for electrically connecting the source drain layer and the active layer of the thin film transistor in the display area and the opening in the binding area are respectively formed by using a photomask process. Based on this, the application provides a display panel and a manufacturing method thereof.

Referring to fig. 1 to 5, the display panel 100 includes a display area and a bonding area located at one side of the display area, and a substrate 101 and a thin film transistor layer located on the substrate 101 are disposed in the display area.

The thin film transistor layer comprises a first thin film transistor located in the display area and a second thin film transistor electrically connected with the first thin film transistor, a first source drain layer 102 of the first thin film transistor and a second source drain layer 105 of the second thin film transistor are arranged on the same layer, the first source drain layer 102 is electrically connected with a first active layer 104 through a first through hole 103, and the second source drain layer 105 is electrically connected with a second active layer 107 through a second through hole 106.

An opening 108 penetrating through a film layer between the first source drain layer 102 and the substrate 101 is arranged in the bonding region, the opening 108 at least comprises a first sub-opening 109 far away from the substrate 101 and a second sub-opening 110 close to the substrate 101, and the number of the film layers penetrating through the first sub-opening 109 is the same as that of the film layers penetrating through the first via hole 103 and/or the second via hole 106.

The film layer penetrated by the first sub-opening 109 in the binding area is the same as the film layer penetrated by the first via hole 103 and/or the second via hole 106, so that the first sub-opening 109 and the first via hole 103 and/or the second via hole 106 can be formed in the same process by using the same photomask, the number of photomasks for forming the via hole and the opening in the manufacturing process is reduced, the production cost of the display panel 100 is reduced, and the product yield of the display panel 100 is improved.

In the present application, the first thin film transistor may be a low-temperature polysilicon thin film transistor or a metal oxide thin film transistor, and the second thin film transistor may be one of the low-temperature polysilicon thin film transistor or the metal oxide thin film transistor different from the first thin film transistor. The first thin film transistor is a low temperature polysilicon thin film transistor, and the second thin film transistor is a metal oxide thin film transistor.

The technical solution of the present application will now be described with reference to specific embodiments.

Example one

Referring to fig. 1 to 5, the present embodiment is the same as or similar to the first embodiment, except that:

the first active layer 104 and the second active layer 107 are arranged in a different layer, and a film layer through which the first sub-opening 109 penetrates is the same as a film layer through which the first via hole 103 or the second via hole 106 penetrates.

In this embodiment, the first via 103 includes a first sub-via 128 at a side far from the substrate 101 and a second sub-via 129 at a side close to the substrate 101.

Alternatively, the second via 106 includes a third sub-via on a side far from the substrate 101 and a fourth sub-via on a side close to the substrate 101.

Wherein the depth of the first sub opening 109 is the same as the depth of the first sub via 128.

Alternatively, the depth of the first sub opening 109 is the same as the depth of the third sub via.

In this embodiment, the opening 108 further includes a third sub-opening 120 located between the first sub-opening 109 and the second sub-opening 110, and a film layer through which the third sub-opening 120 passes is the same as a film layer through which the second sub-via 129 passes.

Alternatively, the film layer through which the third sub-opening 120 penetrates is the same as the film layer through which the fourth sub-via penetrates.

In this embodiment, through the same arrangement of the third sub-opening 120 and the second sub-via 129 or the film layer through which the fourth sub-via penetrates, the third sub-opening 120 and the second sub-via 129 or the fourth sub-via can be formed in the same process by using the same photomask, and the third sub-opening 120 is formed without additionally increasing the number of photomasks, which is beneficial to simplifying the process of the display panel 100, reducing the production cost of the display panel 100, and improving the product yield of the display panel 100.

Meanwhile, through the arrangement of the third sub-opening 120, the opening 108 is formed through three etching processes, which is beneficial to avoiding film residues in the opening 108, and improving the product quality of the display panel 100.

In this embodiment, when the first via hole 103 includes the first sub-via hole 128 and the second sub-via hole 129, the first thin film transistor further includes a first gate 111 located on the first active layer and a third gate 113 located on the first gate 111, the second thin film transistor further includes a second gate 112 located on the second active layer and a fourth gate 114 located between the second active layer and the substrate 101, and the first gate 111 and the fourth gate 114 are disposed at the same layer.

At this time, the first gate 111 and the third gate 113 are located on the same side of the first active layer 104, and the dielectrics between the first gate 111 and the third gate 113 of different first thin film transistors are easy to be kept consistent, so that the storage capacitance values of different first thin film transistors are kept consistent, which is beneficial to keeping the stability of the performance of the first thin film transistor; meanwhile, the fourth gate 114 is located between the second active layer 107 and the substrate 101, and the fourth gate 114 functions to block light from the substrate 101 side to the second active layer 107 of the second thin film transistor, so as to prevent the light from the substrate 101 side from affecting the working performance of the second active layer 107; the third gate 113 and the fourth gate 114 are disposed on the same layer, so that the third gate and the fourth gate can be formed in the same process and by using the same material, which is beneficial to simplifying the process; finally, since the first active layer 104 and the second active layer 107 are separated by a plurality of layers, it is beneficial to reduce the mutual influence between the two layers to the maximum extent.

The thin film transistor layer includes a first insulating layer 115 between the first active layer 104 and the first gate 111, a second insulating layer 116 between the first gate 111 and the third gate 113, a third insulating layer 117 between the fourth gate 114 and the second active layer 107, a fourth insulating layer 118 between the second active layer 107 and the second gate 112, and a fifth insulating layer 119 between the second gate 112 and the second source drain layer 105.

In this embodiment, the first insulating layer 115, the second insulating layer 116, the third insulating layer 117, the fourth insulating layer 118, and the fifth insulating layer 119 extend into the bonding region.

In this embodiment, the first sub-opening 109 penetrates through the fourth insulating layer 118 and the fifth insulating layer 119, and the third sub-opening 120 penetrates through the first insulating layer 115, the second insulating layer 116, and the third insulating layer 117.

In this embodiment, the display panel 100 further includes a buffer layer 127 located on the substrate 101 and a protection layer 126 located between the buffer layer 127 and the first active layer 104, where the protection layer 126 is used to keep the temperature of each place on the first active layer 104 consistent in the manufacturing process of the display panel 100, so as to avoid that the temperature distribution of each place on the first active layer 104 in the manufacturing process affects the working performance of the first active layer 104.

In this embodiment, the second sub-opening 110 penetrates through the buffer layer 127 and the protection layer 126.

In this embodiment, when the first via hole 103 includes the first sub-via hole 128 and the second sub-via hole 129, a distance between the first active layer 104 and the first source drain layer 102 is farther than a distance between the second active layer 107 and the second source drain, and the first via hole 103 includes the first sub-via hole 128 and the second sub-via hole 129, so that the first via hole 103 is formed by two etching processes, and compared with the case where the first via hole 103 is formed by one etching process, the formed first via hole 103 has a more regular structure without a film layer residue, and is more favorable for electrically connecting the first source drain layer 102 and the first active layer 104; in addition, the first sub-opening 109, the first sub-via 128 and the second via 106 have the same layer, and both can be formed in the same process using the same mask, so that the number of masks is not increased by forming the first via 103 through two etching processes, which is beneficial to reducing the production cost of the display panel 100.

Referring to fig. 3, in the present embodiment, a source or a drain of the first thin film transistor may have a first portion extending to the first gate 111 and/or the third gate 113, and the first portion may form a storage capacitor with the first gate 111 and/or the third gate 113 to increase a storage capacitance of the first thin film transistor.

Referring to fig. 4, in the present embodiment, the first active layer 104 of the first thin film transistor may extend to a position below the second thin film transistor, at this time, an orthographic projection of the second active layer 107 on the substrate 101 is located in the first active layer 104, the first active layer 104 functions as a light shielding layer for blocking light from the second active layer 107, and at this time, the fourth gate electrode 114 may be omitted to simplify the manufacturing process.

Referring to fig. 5, in the present embodiment, when the first gate 111, the third gate 113, and the first active layer 104 are formed, a first conductor layer 131, a second conductor layer 132, and a third conductor layer 133 that are electrically connected to each other are simultaneously formed between the first via hole 103 and the first active layer 104 and at a position corresponding to the first via hole 103, and by the arrangement of the first conductor layer 131, the second conductor layer 132, and the third conductor layer 133, the depth of the first via hole 103 is reduced, the process is simplified, and the occurrence of poor electrical connection between the first active layer 104 and the first source/drain layer 102 due to the excessive depth of the first via hole 103 is avoided.

In this embodiment, the first thin film transistor further includes a fifth gate disposed on the same layer as the second gate 112, and the fifth gate may be formed in the same process and the same material as the second gate 112, so as to increase the storage capacitance of the first thin film transistor.

In this embodiment, the opening areas of the first sub-opening 109, the third sub-opening 120 and the second sub-opening 110 are sequentially decreased, that is, the areas of the first sub-opening 109, the second sub-opening 110 and the third sub-opening 120 on the first plane are sequentially the second sub-opening 110, the third sub-opening 120 and the first sub-opening 109. Wherein the first plane is a plane parallel to the substrate 101.

Therefore, a step structure is formed between the first sub-opening 109 and the third sub-opening 120 and between the third sub-opening 120 and the second sub-opening 110, which is beneficial to increase the contact area of the filling layer in the opening 108 and the plurality of film layers between the first source drain layer 102 and the substrate 101, enhance the adhesion between the filling layer and the plurality of film layers between the first source drain layer 102 and the substrate 101, avoid the separation between the filling layer and the plurality of film layers between the first source drain layer 102 and the substrate 101, and improve the packaging effect of the filling layer on the plurality of film layers between the first source drain layer 102 and the substrate 101.

In this embodiment, the first sub-opening 109 includes a first side close to one side of the display region, the second sub-opening 110 includes a second side close to one side of the display region, the third sub-opening 120 includes a third side close to one side of the display region, and obtuse angles formed by the first side, the third side, and the second side and the substrate 101 decrease in sequence.

In this embodiment, the first sub-opening 109 further includes a fourth side far away from one side of the display area, the second sub-opening 110 further includes a fifth side far away from one side of the display area, and the third sub-opening 120 further includes a sixth side far away from one side of the display area, where the first side and the fourth side, the second side and the fifth side, and the third side and the sixth side are all symmetric about a first axis of symmetry of the opening in the first direction. Wherein the first direction is a direction perpendicular to the substrate 101.

Through the arrangement that the obtuse angles formed by the first side, the third side and the second side and the substrate 101 are sequentially increased, the filling layer positioned in the opening 108 is enabled to be unparallel with different contact surfaces formed by a plurality of film layers between the first source drain layer 102 and the substrate 101 in different sub-openings, the separation of the filling layer and the plurality of film layers between the first source drain layer 102 and the substrate 101 is favorably avoided, and the packaging effect of the filling layer on the plurality of film layers between the first source drain layer 102 and the substrate 101 is improved.

In this embodiment, the film layer through which the first sub-opening 109 passes is the same as the film layer through which the first via hole 103 or the second via hole 106 passes, so that the first sub-opening 109 and the first via hole 103 or the second via hole 106 are formed in the same process by using the same photomask, the number of the through holes connecting the source layer and the source drain layer in the display area and the number of the photomasks forming the opening in the bonding area in the process of forming the display panel 100 are reduced, the process of forming the display panel 100 is simplified, the process cost is reduced, and the product yield of the display panel 100 is improved.

In the foregoing embodiments, the source and drain of the first thin film transistor are electrically connected to the source and drain of the second thin film transistor, so that the first thin film transistor and the second thin film transistor are electrically connected.

In the above embodiments, the display panel 100 may be an OLED display panel, in this case, the display panel 100 further includes a planarization layer 121 located on the first source drain layer 102, a pixel definition layer 122 located on the planarization layer 121, and the pixel definition layer 122 includes a plurality of spacers; the display panel 100 further includes a light emitting device layer between the spacers, the light emitting device layer including an anode layer 123, and a light emitting material layer 124 and a cathode layer on the anode layer 123, the anode layer 123 being electrically connected to the drain of the first thin film transistor; the display panel 100 further includes a support 125 on the pixel defining layer.

In the above embodiments, the first sub-opening 109 is filled with a first filling layer, the second sub-opening 110 is filled with a second filling layer, and the elastic modulus of the first filling layer is different from the elastic modulus of the second filling layer. Through the elastic modulus of first filling layer with the elastic modulus of second filling layer is different, works as bind in the district display panel 100 takes place to buckle when, first filling layer with the second filling layer causes deformation between them to have the difference because elastic modulus is different, is favorable to external stress to transmit and release step by step between the two, protects other retes of display panel 100.

In the above embodiments, the display panel 100 further includes a barrier layer located in the opening 108, and the barrier layer covers the film layer through which the opening 108 penetrates. The barrier layer is located between the film layer through which the opening 108 penetrates and the filling layer in the opening 108, and the material of the barrier layer may be an inorganic material, and is used to block water and oxygen from invading the thin film transistor layer from the opening 108, so as to enhance the packaging effect of the display panel 100 in the opening 108 and prolong the service life of the display panel 100.

Referring to fig. 1 to 6 and fig. 7a to 7d, the present application further provides a method for manufacturing a display panel 100, including:

s100, a first active layer 104 and a second active layer 107 are formed on the substrate 101 in the display region.

S200, forming a first via hole 103 on the first active layer 104 and/or forming a first sub-opening 109 in the bonding region at the same time of forming a second via hole 106 on the second active layer 107.

S300, forming a second sub-opening 110 between the first sub-opening 109 and the substrate 101.

Wherein, the film layer through which the first sub-opening 109 penetrates is the same as the film layer through which the first via 103 and/or the second via 106 penetrates.

According to the manufacturing method of the display panel 100, the film layer penetrating through the first sub-opening 109 and the film layer penetrating through the first via hole 103 and/or the second via hole 106 in the binding region are the same, so that the first sub-opening 109 and the first via hole 103 and/or the second via hole 106 can be formed in the same process by using the same photomask, the number of photomasks used for forming the via hole and the opening in the manufacturing process is reduced, the production cost of the display panel 100 is reduced, and the product yield of the display panel 100 is improved.

The technical solution of the present application will now be described with reference to specific embodiments.

Example two

Referring to fig. 1 to 6 and fig. 7a to 7d, the method for manufacturing the display panel 100 includes:

s100, a first active layer 104 and a second active layer 107 are formed on the substrate 101 in the display region.

In this embodiment, the material of the first active layer 104 may be a low temperature polysilicon material, and the material of the second active layer 107 may be a metal oxide material, such as indium gallium zinc oxide, and the like.

In this embodiment, step S100 may include:

s110, forming the first active layer 104 on the substrate 101 in the display region.

S120, forming a first gate 111 on the first active layer 104.

S130, forming a second gate 112 and a third gate 113 on the first gate 111.

S140, forming a second active layer 107 on the second gate 112.

S150, forming a fourth gate 114 on the second active layer 107.

S200, forming a first via hole 103 on the first active layer 104 and/or forming a second via hole 106 on the second active layer 107 and simultaneously forming a first sub-opening 109 on the substrate 101 in a binding region.

In this embodiment, step S200 may include:

s210, forming the first sub-opening 109 in the bonding region while forming the second via hole 106 on the second active layer 107 and the first sub-via hole 128 on the first active layer 104.

In this embodiment, the film layer penetrated by the first sub-opening 109 is the same as the film layer penetrated by the second via 106 and the first sub-via 128, and the depth of the first sub-opening 109 is the same as the depth of the first sub-via 128.

S300, forming a second sub-opening 110 between the first sub-opening 109 and the substrate 101.

In this embodiment, step S300 may include:

s310, forming a third sub-opening 120 between the first sub-opening 109 and the substrate 101 while forming a second sub-via 129 between the first active layer 104 and the first sub-via 128.

In this embodiment, the film layer through which the third sub-opening 120 passes is the same as the film layer through which the second sub-via 129 passes.

S320, forming the second sub-opening 110 between the third sub-opening 120 and the substrate 101.

In this embodiment, the first sub-via 128 and the second sub-via 129 form the first via 103.

In this embodiment, the first sub-opening 109, the second sub-opening 110, and the third sub-opening 120 form an opening 108 located in a bonding region and penetrating through a film layer between the first source/drain layer 102 and the substrate 101.

In the embodiment, the film layer through which the first sub-opening 109 located in the bonding region passes is the same as the film layer through which the first via 103 and/or the second via 106 passes, so that the first sub-opening 109 and the first via 103 and/or the second via 106 can be formed in the same process by using the same photomask, the number of photomasks used for forming the via and the opening in the manufacturing process is reduced, the production cost of the display panel 100 is reduced, and the product yield of the display panel 100 is improved.

The application provides a display panel and a manufacturing method thereof. The display panel comprises a first source drain layer and a second source drain layer, wherein the first source drain layer is positioned in the display area and electrically connected with the first active layer through a first through hole; the openings in the binding region at least comprise first sub-openings far away from the substrate and second sub-openings close to the substrate, and the number of the film layers penetrated by the first sub-openings is the same as that of the film layers penetrated by the first via holes and/or the second via holes. The film layer that this application runs through setting up the first sub-opening that is located the binding area is the same with the film layer that first via hole and/or second via hole run through, makes first sub-opening can be in same process with first via hole and/or second via hole, uses same light cover to form, has reduced the quantity that is used for forming via hole and open-ended light cover in the processing procedure, has reduced display panel's manufacturing cost, has improved display panel's product yield.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The display panel and the manufacturing method thereof provided by the embodiment of the present application are described in detail above, and a specific example is applied in the description to explain the principle and the implementation manner of the present application, and the description of the embodiment is only used to help understanding the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.