阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 李熙烈 郑在馥 于 2020-10-10 设计创作，主要内容包括：提供一种半导体装置,该半导体装置包括：第一组,其包括多个第一存储器块；第二组,其包括多个第二存储器块；第一公共源极线,其连接到第一组；第二公共源极线,其连接到第二组；源极线电压提供电路,其提供源极线电压；第一开关,其控制第一公共源极线与源极线电压提供电路之间的连接；以及第二开关,其控制第二公共源极线与源极线电压提供电路之间的连接。当选择第一组的多个第一存储器块中的一个第一存储器块时,第一开关可以接通并且第二开关可以断开。(Provided is a semiconductor device including: a first bank comprising a plurality of first memory blocks; a second group including a plurality of second memory blocks; a first common source line connected to the first group; a second common source line connected to the second group; a source line voltage supply circuit that supplies a source line voltage; a first switch that controls connection between the first common source line and the source line voltage supply circuit; and a second switch that controls connection between the second common source line and the source line voltage supply circuit. When one of the first memory blocks of the first group of the plurality of first memory blocks is selected, the first switch may be turned on and the second switch may be turned off.)

1. A semiconductor device, comprising:

a first bank comprising a plurality of first memory blocks;

a second group comprising a plurality of second memory blocks;

a first common source line connected to the first group;

a second common source line connected to the second group;

a source line voltage providing circuit that provides a source line voltage;

a first switch that controls a connection between the first common source line and the source line voltage supply circuit; and

a second switch that controls a connection between the second common source line and the source line voltage supply circuit,

wherein, when one of the plurality of first memory blocks of the first group is selected, the first switch is turned on and the second switch is turned off.

2. The semiconductor device according to claim 1, wherein when one of the plurality of second memory blocks of the second group is selected, the second switch is turned on and the first switch is turned off.

3. The semiconductor device of claim 1, wherein the first common source line and the second common source line are electrically isolated from each other.

4. The semiconductor device according to claim 1, wherein the source line voltage supply circuit supplies a positive voltage in a programming operation.

5. The semiconductor device according to claim 1, wherein the source line voltage supply circuit supplies a ground voltage or a positive voltage in a read operation.

6. The semiconductor device according to claim 1, wherein the source line voltage supply circuit supplies an erase voltage in an erase operation.

7. The semiconductor device according to claim 1, wherein the second common source line is floated when the second switch is off.

8. The semiconductor device according to claim 1, further comprising:

a third group comprising a plurality of third memory blocks;

a third common source line connected to the third group; and

a third switch that controls a connection between the third common source line and the source line voltage providing circuit.

9. The semiconductor device according to claim 8, wherein when one of the plurality of first memory blocks of the first group is selected, the first switch is turned on, and the second switch and the third switch are turned off.

10. The semiconductor device according to claim 8, wherein when one of the plurality of second memory blocks of the second group is selected, the second switch is turned on, and the first switch and the third switch are turned off.

11. The semiconductor device according to claim 1, wherein the first group and the second group belong to the same plane.

12. A semiconductor device, comprising:

a plurality of first memory blocks;

a plurality of second memory blocks;

a first common source line commonly connected to the plurality of first memory blocks;

a second common source line commonly connected to the plurality of second memory blocks, the second common source line electrically isolated from the first common source line; and

a source line voltage supply circuit that supplies a source line voltage,

wherein the first common source line is electrically connected to the source line voltage supply circuit when one of the plurality of first memory blocks is selected.

13. The semiconductor device according to claim 12, wherein the second common source line is electrically disconnected from the source line voltage supply circuit when the one first memory block is selected.

14. The semiconductor device according to claim 12, wherein when one of the plurality of second memory blocks is selected, the second common source line is electrically connected to the source line voltage supply circuit, and the first common source line is electrically disconnected from the source line voltage supply circuit.

Technical Field

The present disclosure relates generally to an electronic device, and more particularly, to a semiconductor device.

Background

The semiconductor device may include a memory device configured to store data or output stored data. The memory device may be a volatile memory device in which stored data disappears when power is interrupted. Alternatively, the memory device may be a nonvolatile memory device that retains stored data even when power is interrupted. Examples of memory devices may include static ram (sram), dynamic ram (dram), synchronous dram (sdram), Read Only Memory (ROM), programmable ROM (prom), electrically programmable ROM (eprom), electrically erasable programmable ROM (eeprom), flash memory, phase change ram (pram), magnetic ram (mram), resistive ram (rram), and ferroelectric ram (fram), among others.

The memory device may include a memory cell array configured to store data, peripheral circuits configured to perform various operations such as a program operation, a read operation, and an erase operation, and control logic configured to control the peripheral circuits. The memory device may be implemented as a structure in which memory cells are two-dimensionally arranged over a substrate or a structure in which memory cells are three-dimensionally stacked over a substrate.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a semiconductor device including: a first bank comprising a plurality of first memory blocks; a second group including a plurality of second memory blocks; a first common source line connected to the first group; a second common source line connected to the second group; a source line voltage supply circuit that supplies a source line voltage; a first switch that controls connection between the first common source line and the source line voltage supply circuit; and a second switch that controls a connection between the second common source line and the source line voltage supply circuit, wherein when one of the plurality of first memory blocks of the first group is selected, the first switch is turned on and the second switch is turned off.

According to another aspect of the present disclosure, there is provided a semiconductor device including: a first memory block; a second memory block; a first common source line commonly connected to the respective first memory blocks; second common source lines commonly connected to the respective second memory blocks, the second common source lines being electrically isolated from the first common source lines; and a source line voltage supply circuit that supplies a source line voltage, wherein when one of the respective first memory blocks is selected, the first common source line is electrically connected to the source line voltage supply circuit.

These and other features and advantages of the present disclosure will become apparent to those of ordinary skill in the art to which the present invention pertains from the following drawings and detailed description.

Drawings

Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings; this invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

Like reference numerals refer to like elements throughout.

Fig. 1 is a block diagram showing a configuration of a semiconductor device according to one embodiment of the present disclosure.

Fig. 2 and 3 are circuit diagrams illustrating a cell array structure of a semiconductor device according to one embodiment of the present disclosure.

Fig. 4 is a diagram showing a configuration of a semiconductor device according to one embodiment of the present disclosure.

Fig. 5 is a diagram illustrating an operation of a semiconductor device according to one embodiment of the present disclosure.

Fig. 6 is a diagram illustrating an operation of a semiconductor device according to one embodiment of the present disclosure.

Fig. 7 is a diagram illustrating a memory system according to one embodiment of the present disclosure.

Fig. 8 is a diagram illustrating a memory system according to one embodiment of the present disclosure.

Fig. 9 is a diagram illustrating a memory system according to one embodiment of the present disclosure.

Fig. 10 is a diagram illustrating a memory system according to one embodiment of the present disclosure.

Fig. 11 is a diagram illustrating a memory system according to one embodiment of the present disclosure.

Detailed Description

Various embodiments relate to a semiconductor device having improved operating characteristics.

The specific structural or functional descriptions disclosed herein are merely illustrative for the purposes of describing embodiments of the present disclosure. Embodiments may be embodied in various other forms and should not be construed as limited to the embodiments set forth herein.

The figures are schematic illustrations of various embodiments (and intermediate structures). Accordingly, deviations in the illustrated configurations and shapes, for example due to manufacturing techniques and/or tolerances, may be expected. Accordingly, the described embodiments should not be construed as limited to the particular configurations and shapes shown herein but are to include deviations in configurations and shapes that do not depart from the spirit and scope of the invention as defined in the appended claims.

In the drawings, the size may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. It should be understood that the figures are simplified schematic illustrations of the described apparatus and may not include well-known details or components.

It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly on, connected or coupled to the other element or one or more intervening elements may be present. Further, the connections/couplings may not be limited to physical connections but may also include non-physical connections, such as wireless connections.

As used herein, the singular forms also are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be further understood that the terms "comprises," "comprising," "has," "having," and "containing," when used in this specification, specify the presence of stated elements, and do not preclude the presence or addition of one or more other elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It should also be noted that features present in one embodiment may be used with one or more features of another embodiment without departing from the scope of the invention.

Fig. 1 is a block diagram showing a configuration of a semiconductor device according to one embodiment of the present disclosure.

Referring to fig. 1, a semiconductor apparatus 100 may include a cell array 110 and a peripheral circuit 120. Peripheral circuitry 120 may include address decoder 121, read and write circuitry 123, input/output (I/O) circuitry 124, control logic 125, and source line voltage supply circuitry 126. The semiconductor device 100 may be a memory device. In one embodiment, the semiconductor device 100 may be a volatile memory device. In another embodiment, the semiconductor device 100 may be a nonvolatile memory device. For example, the semiconductor device 100 may be a flash memory device.

The cell array 110 may be connected to an address decoder 121 through row lines RL and to a read-write circuit 123 through column lines CL. The row lines RL may be word lines and the column lines CL may be bit lines. However, word lines and bit lines are relative concepts. The row lines may be bit lines and the column lines may be word lines.

The cell array 110 may be connected to the source line voltage supply circuit 126 through a common source line CSL. The switch may be connected between the common source line CSL and the source line voltage supply circuit 126. The electrical connection between the common source line CSL and the source line voltage supply circuit 126 may be controlled by a switch, and the switch may be controlled by the control logic 125.

The cell array 110 may include at least one plane. A plane may include a plurality of memory blocks BLK, and the memory blocks BLK may be grouped into a plurality of groups GR. Each group GR may comprise a plurality of memory blocks BLK. The common source line CSL may be connected to the group GR. The respective common source lines CSL may be respectively connected to the respective groups GR in one-to-one correspondence. In addition, the common source lines CSL connected to different groups GR may be independently driven. Each memory block BLK may include a plurality of memory strings. Further, each memory block BLK may include a plurality of pages.

Control logic 125 may be connected to address decoder 121, read and write circuitry 123, I/O circuitry 124, and source line voltage supply circuitry 126. Control logic 125 may receive commands CMD and addresses ADDR from I/O circuitry 124. In accordance with the received command CMD, the control logic 125 may control the address decoder 121, the read/write circuit 123, and the source line voltage supply circuit 126 to perform internal operations.

Address decoder 121 may be connected to cell array 110 by row lines RL. For example, the address decoder 121 may be connected to the cell array 110 through a word line, a dummy word line, a source select line, and a drain select line. In addition, address decoder 121 may control row line RL under the control of control logic 125. For example, the address decoder 121 may receive an address ADDR from the control logic 125 and select one group GR among the respective groups GR of the cell array 110. As another example, the address decoder 121 may select one block BLK among the respective memory blocks BLK of the cell array 110 according to the received address ADDR.

The program operation and the read operation of the semiconductor device 100 may be performed in units of pages. For example, in a program operation and a read operation, the address ADDR may include a block address and a row address. The address decoder 121 may decode a block address in the received address ADDR. The address decoder 121 may generate a block selection signal according to the decoded block address and select one memory block BLK according to the block selection signal. In addition, the address decoder 121 may generate a group selection signal according to the decoded block address or block selection signal. The address decoder 121 may select one group GR according to a group selection signal.

The address decoder 121 may decode a row address in the received address ADDR and select any one page of the selected memory block BLK according to the decoded row address.

The erase operation of the semiconductor apparatus 100 may be performed in units of memory blocks. For example, in an erase operation, the address ADDR may include a block address. The address decoder 121 may decode a block address in the received address ADDR. The address decoder 121 may select one memory block BLK according to the decoded block address and select the group GR to which the corresponding memory block belongs.

The source line voltage supply circuit 126 supplies a source line voltage to the common source line CSL. The source line voltage supply circuit 126 may supply a source line voltage for a program operation, a read operation, or an erase operation in response to a command CMD. The group GR may be selected according to a group selection signal, and a common source line of the selected group GR may be electrically connected to the source line voltage supply circuit 126. The unselected group GR may be electrically disconnected from the source line voltage supply circuit 126 and floated. The source line voltage may be applied only to the common source line CSL of the selected group GR, and not to the common source line CSL of the unselected group GR. The source line voltage may include an erase voltage, a power supply voltage, a ground voltage, a precharge voltage, and the like.

The read and write circuit 123 may be connected to the cell array 110 through column lines CL. The read-write circuit 123 may include a plurality of page buffers. The page buffer may access the cell array 110 through the column line CL.

In a program operation, the read and write circuit 123 may transfer the DATA received from the I/O circuit 124, and the memory cells of the selected page may be programmed according to the transferred DATA. The DATA may be multi-bit DATA to be programmed to the respective memory cells, respectively. In a read operation, the read-write circuit 123 may read DATA from the memory cells of the selected page through the column lines CL and output the read DATA to the I/O circuit 124. In an erase operation, the read and write circuitry 123 may float the column line CL. A verifying operation may be included in the program operation and the erase operation. The verify operation may be performed in a manner similar to that of a read operation.

Fig. 2 and 3 are circuit diagrams illustrating a cell array structure of a semiconductor device according to one embodiment of the present disclosure.

Referring to fig. 2, the cell array may include a plurality of memory blocks BLK. The memory blocks BLK may be arranged in a first direction I, in a second direction II intersecting the first direction I, or in the first and second directions I and II. Further, the memory blocks BLK may be stacked in the third direction III. The third direction III may be a direction protruding from a plane defined by the first direction I and the second direction II. The third direction III may be perpendicular to the plane.

Each memory block BLK may include a plurality of memory strings MS11 through MS1m and MS21 through MS2 m. Each of the memory strings MS 11-MS 1m and MS 21-MS 2m may extend in the third direction III. The third direction III may be a direction in which the memory cells MC are stacked. In this embodiment, m may be an integer of 2 or more.

The first memory block BLK1 may include memory strings MS11 to MS1m and MS21 to MS2m connected between bit lines BL1 to BLm and a common source line CSL. Memory strings arranged on the same line in the second direction II among the memory strings MS11 to MS1m and MS21 to MS2m may share a corresponding one of the bit lines BL1 to BLm.

Each of the memory strings MS11 through MS1m and MS21 through MS2m may include at least one source select transistor SST, a plurality of memory cells MC, and at least one drain select transistor DST. Each of the memory strings MS11 through MS1m and MS21 through MS2m may further include at least one source side dummy memory cell connected between the source select transistor SST and the memory cell MC. Each of the memory strings MS11 through MS1m and MS21 through MS2m may further include at least one drain-side dummy memory cell connected between the drain select transistor DST and the memory cell MC.

At least one source select transistor SST included in each of the memory strings MS11 through MS1m and MS21 through MS2m may be connected in series between the memory cells MC and the common source line CSL. The gate electrode of the source selection transistor SST may be connected to at least one source selection line SSL. In addition, the source selection transistors SST at the same level may be connected to the same source selection line SSL.

The memory cells MC included in each of the memory strings MS11 through MS1m and MS21 through MS2m may be connected in series between the source select transistor SST and the drain select transistor DST. The gate electrodes of the memory cells MC may be connected to a word line WL, and the memory cells MC at the same level may be connected to the same word line WL. Word line voltages (a program bias, a pre-program bias, a read bias, and the like) required to drive the memory cells MC may be applied to each word line WL.

At least one drain select transistor DST included in each of the memory strings MS11 through MS1m and MS21 through MS2m may be connected in series between a corresponding one of the bit lines BL1 through BLm and the memory cell MC. The gate electrode of the drain select transistor DST may be connected to at least one drain select line DSL. Drain select transistors DST at the same level among drain select transistors DST of memory strings (MS11 to MS1m or MS21 to MS2m) arranged on the same row (first direction I) may be connected to the same drain select line DSL. Further, the drain select transistors SST arranged in different rows (first direction I) may be connected to different drain select lines DSL.

The memory strings MS11 to MS1m and MS21 to MS2m belonging to the same memory block BLK share a common source line CSL. Further, the plurality of memory blocks BLK may share a common source line, and the memory blocks sharing the common source line CSL may constitute one group. The common source lines CSL connected to different groups may be independently driven.

Referring to fig. 3, the memory block BLK may include memory strings MS11 to MS1m and MS21 to MS2m connected between a common source line CSL and bit lines BL1 to BLm. Each of the memory strings MS11 through MS1m and MS21 through MS2m may include at least one source select transistor SST, a plurality of memory cells MC, at least one pipe transistor PT, a plurality of memory cells MC, and at least one drain select transistor DST connected in series. Each of the memory strings MS11 through MS1m and MS21 through MS2m may be arranged in a "U" shape.

The pipe transistor PT may connect the drain side memory cell MC and the source side memory cell MC. Further, the gate of the pipe transistor PT of each of the memory strings MS11 to MS1m and MS21 to MS2m may be connected to the line PL. The rest of the structure is similar to the structure described with reference to fig. 2, and, for example, a repetitive description will be omitted.

Fig. 4 is a diagram showing a configuration of a semiconductor device according to one embodiment of the present disclosure.

Referring to fig. 4, the semiconductor device may include memory blocks BLK1 through BLKx, common source lines CSL1 through CSLx, and a source line voltage supply circuit SSC. Further, the semiconductor device may further include switches SW1 to SWx. Here, x is an integer of 2 or more.

One plane PL may include a plurality of memory blocks BLK1 through BLKx. The memory blocks BLK1 through BLKx may be grouped into a plurality of groups GR1 through GRx. The numbers of memory blocks BLK1 through BLKx belonging to the groups GR1 through GRx may be equal to or different from each other. The first group GR1 may include respective first memory blocks BLK 1. The second group GR2 may include respective second memory blocks BLK 2. The third set GR3 may include respective third memory blocks BLK 3. The xth group GRx may include respective xth memory blocks.

One plane PL may include a plurality of common source lines CSL1 to CSLx. The common source lines CSL 1-CSLx may be electrically isolated from each other. The common power source lines CSL1 to CSLx may be electrically connected to the source line voltage supply circuit SSC through switches SW1 to SWx, respectively.

The common source lines CSL1 through CSLx may be connected to the groups GR1 through GRx, respectively. The first common source line CSL1 may be connected to the first group GR 1. The first common source line CSL1 is commonly connected to the respective first memory blocks BLK 1. The second common source line CSL2 may be connected to a second group GR 2. The second common source line CSL2 may be commonly connected to the respective second memory blocks BLK 2. The third common source line CSL3 may be connected to a third group GR 3. The third common source line CSL3 may be commonly connected to the respective third memory blocks BLK 3. The xth common source line CSLx may be connected to the xth group GRx. The xth common source line CSLx may be commonly connected to the respective xth memory blocks BLKx.

The source line voltage supply circuit SSC supplies a source line voltage. The source line voltage supply circuit SSC supplies a source line voltage according to the received command. The source line voltage may be an erase voltage, a power supply voltage, a ground voltage, a precharge voltage, and the like. The source line voltage supply circuit SSC may supply a positive voltage in a program operation. For example, the source line voltage supply circuit SSC may supply a power supply voltage as a source line voltage. In a read operation, the source line voltage supply circuit SSC may supply a ground voltage or supply a positive voltage. In the erase operation, the source line voltage supply circuit SSC may supply an erase voltage.

The connections between the common source lines CSL1 to CSLx and the source line voltage supply circuit SSC may be controlled by switches SW1 to SWx. The switches SW1 to SWx may be turned on or off. Switches SW1 through SWx may be controlled by control logic 125. The switch corresponding to the group to which the selected memory block belongs may be turned on, and the other switches may be turned off. Accordingly, a source line voltage may be supplied to the common source line of the selected group, and the common source line of the unselected group may be floated. Meanwhile, in some cases, at least one unselected switch may be turned on together with the selected switch. In these cases, the source line voltage may be provided to at least one unselected group.

When one first memory block BLK1 among the respective first memory blocks BLK1 is selected, the first switch SW1 may be turned on by the group selection signal, and the other switches SW2 to SWx may be turned off. The first common source line CSL1 may be electrically connected to the source line voltage supply circuit SSC. In addition, the other common source lines CSL2 to CSLx may be electrically disconnected from the source line voltage supply circuit SSC.

When one second memory block BLK2 among the respective second memory blocks BLK2 is selected, the second switch SW2 may be turned on by the group selection signal, and the other switches SW1 and SW3 to SWx may be turned off. The second common source line CSL2 may be electrically connected to the source line voltage supply circuit SSC. In addition, the other common source lines CSL1 and CSL3 to CSLx may be electrically disconnected from the source line voltage supply circuit SSC and may be floated.

Similarly, when one third memory block BLK3 among the respective third memory blocks BLK3 is selected, the third switch SW3 may be turned on by the group selection signal, and the other switches SW1, SW2, and SW4 to SWx may be turned off. The third common source line CSL3 may be electrically connected to the source line voltage supply circuit SSC. In addition, the other common source lines CSL1, CSL2, and CSLs 4 to CSLx may be electrically disconnected from the source line voltage supply circuit SSC and may be floated.

According to the above configuration, the operating characteristics of the semiconductor device can be improved. In the programming operation, a load capacitance (loading capacitance) of the common source line can be reduced, and the common source line can be charged quickly. In addition, the leakage current of the bit line can be reduced. In the read operation, the leakage current of the bit line can be reduced, and a read margin (read margin) can be secured by reducing the sense current. In the erase operation, stress of the unselected group can be reduced, and read fail (read fail) of the first page can be reduced.

Fig. 5 is a diagram illustrating an operation of a semiconductor device according to one embodiment of the present disclosure, which illustrates a program operation condition of a program-inhibited memory string.

Referring to fig. 5, at a first time t1, a program voltage Vpgm is applied to a selected word line sel _ WL and a pass voltage Vpass is applied to an unselected word line unsel _ WL. The voltage of the selected word line sel _ WL may reach the pass voltage Vpass and then increase to the program voltage Vpgm. The source selection transistor and the drain selection transistor are turned off, so that the channel of the unselected memory string can be boosted. Therefore, the channel voltage CH _ potential of the unselected memory string increases, and the unselected memory string is inhibited from programming.

The common source line sel _ CSL corresponding to the selected group is electrically connected to the source line voltage supply circuit, and the source line voltage Vsl is applied to the selected common source line sel _ CSL. The unselected common source lines corresponding to the unselected groups may be floated.

At a second time t2, the selected word line sel _ WL, the unselected word lines unsel _ WL, and the selected common source line sel _ CSL are discharged. The selected word line sel _ WL may discharge earlier than the unselected word line unsel _ WL.

According to the above-described operating method, the respective common source lines included in one plane are independently controlled, so that a program operating characteristic can be improved. When memory blocks included in the same plane share one common source line, the common source line may be slowly charged (see dotted line) due to a capacitor existing between the common source line and the source select line of the unselected memory block. On the other hand, according to the embodiment of the present disclosure, since the source line voltage Vsl is applied only to the selected common source line sel _ CSL, the selected common source line sel _ CSL can be rapidly charged.

Fig. 6 is a diagram illustrating an operation of a semiconductor device according to one embodiment of the present disclosure, which illustrates a program operation condition of a program-inhibited memory string.

Referring to fig. 6, at a first time t1, a common source line sel _ CSL corresponding to a selected group is electrically connected to a source line voltage supply circuit, and a source line voltage Vsl is applied to the selected common source line sel _ CSL. The unselected common source lines corresponding to the unselected groups may be floated. The memory string is connected to the selected source line sel _ CSL by turning on the source select transistor. Thus, the channels of the memory strings are precharged.

At a second time t2, the program voltage Vpgm is applied to the selected word line sel _ WL and the pass voltage Vpass is applied to the unselected word line unsel _ WL. The voltage of the selected word line sel _ WL may reach the pass voltage Vpass and then increase to the program voltage Vpgm. The source select transistor and the drain select transistor are turned off, thereby enabling boosting of the channel of the unselected memory string. Therefore, the channel voltage CH _ potential of the unselected memory string increases.

At a third time t3, the selected word line sel _ WL, the unselected word lines unsel _ WL, and the selected common source line sel _ CSL are discharged. The selected word line sel _ WL may discharge earlier than the unselected word line unsel _ WL.

According to the above-described operation method, the channel regions of the memory strings are precharged by using the selected common source line sel _ CSL. Therefore, even when the pass voltage Vpass having a level lower than that of the pass voltage Vpass shown in fig. 5 is employed, the channel region can be sufficiently boosted, and the pass disturb (pass disturb) can be minimized. Further, since the source line voltage Vsl is applied only to the selected common source line sel _ CSL, the selected common source line sel _ CSL can be quickly charged.

Fig. 7 is a diagram illustrating a memory system according to one embodiment of the present disclosure.

Referring to fig. 7, a memory system 1000 may include a memory device 1200 configured to store data and a memory controller 1100 configured to communicate between the memory device 1200 and a host 2000.

The host 2000 may be a device or system that stores data in the memory system 1000 or retrieves data from the memory system 1000. The host 2000 may generate request RQ for various operations and output the generated request RQ to the memory system 1000. The request RQ may include a program request for a program operation, a read request for a read operation, an erase request for an erase operation, and so on. Host 2000 may communicate with memory system 1000 through various interfaces such as peripheral component interconnect express (PCI-E), Advanced Technology Attachment (ATA), serial ATA (sata), parallel ATA (pata), serial attached scsi (sas), non-volatile memory express (NVMe), Universal Serial Bus (USB), multimedia card (MMC), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

The host 2000 may include at least one of a computer, a portable digital device, a tablet, a digital camera, a digital audio player, a television, a wireless communication device, and a cellular phone, but embodiments of the present disclosure are not limited thereto.

The memory controller 1100 may control the overall operation of the memory system 1000. The memory controller 1100 controls the memory device 1200 according to a request RQ of the host 2000. The memory controller 1100 may control the memory device 1200 to perform a program operation, a read operation, an erase operation, and the like according to a request of the host 2000. Alternatively, the memory controller 1100 may perform background operations to improve the performance of the memory system 1000 without any request by the host 2000.

The memory controller 1100 may transmit control signals CTRL and data signals DQ to the memory device 1200 to control the operation of the memory device 1200. The control signal CTRL and the data signal DQ may be transmitted to the memory device 1200 through different input/output lines. The DATA signal DQ may include a command CMD, an address ADD, or DATA. The control signal CTRL may be used to distinguish a period of the input data signal DQ.

The memory device 1200 may perform a program operation, a read operation, an erase operation, and the like under the control of the memory controller 1100. In one embodiment, the memory device 1200 may be implemented by a volatile memory device in which stored data disappears when power is interrupted. In one embodiment, memory device 1200 may be implemented by a non-volatile memory device that retains stored data even when power is interrupted. In one embodiment, the memory device 1200 may be the semiconductor device 100 described above. Memory device 1200 may be a flash memory device.

When a program operation, a read operation, or an erase operation is requested from the host 2000, the memory controller 1100 commands the memory device 1200 to perform the program operation, the read operation, or the erase operation, so that a memory block is selected by using the method described with reference to fig. 1 to 6.

Fig. 8 is a diagram illustrating a memory system according to one embodiment of the present disclosure.

Referring to fig. 8, the memory system 30000 may be implemented as a cellular phone, a smart phone, a tablet PC, a Personal Digital Assistant (PDA), or a wireless communication device. The memory system 30000 may include a memory device 2200 and a memory controller 2100 capable of controlling the operation of the memory device 2200.

The memory controller 2100 may control data access operations of the memory device 2200, such as program operations, erase operations, read operations, or the like, under the control of the processor 3100.

Data programmed in the memory device 2200 may be output through the display 3200 under the control of the memory controller 2100.

The radio transceiver 3300 may transmit/receive a radio signal through an antenna ANT. For example, the radio transceiver 3300 may change a radio signal received through the antenna ANT into a signal that can be processed by the processor 3100. For example, the processor 3100 may process a signal output from the radio transceiver 3300 and transmit the processed signal to the memory controller 2100 or the display 3200. The memory controller 2100 may transmit signals processed by the processor 3100 to the memory device 2200. Further, the radio transceiver 3300 may change a signal output from the processor 3100 into a radio signal and output the changed radio signal to an external device through an antenna ANT. The input device 3400 is a device capable of inputting a control signal for controlling the operation of the processor 3100 or data to be processed by the processor 3100, and may be implemented as a pointing device such as a touch panel, a computer mouse, a keypad, or a keyboard. The processor 3100 may control the operation of the display 3200 so that data output from the memory controller 2100, data output from the radio transceiver 3300, or data output from the input device 3400 can be output through the display 3200.

In some embodiments, the memory controller 2100 capable of controlling the operation of the memory device 2200 may be implemented as part of the processor 3100 or as a separate chip from the processor 3100.

Fig. 9 is a diagram illustrating a memory system according to one embodiment of the present disclosure.

Referring to fig. 9, the memory system 40000 may be implemented as a Personal Computer (PC), a tablet PC, a netbook, an e-reader, a Personal Digital Assistant (PDA), a Portable Multimedia Player (PMP), an MP3 player, or an MP4 player.

The memory system 40000 may include a memory device 2200 and a memory controller 2100 capable of controlling data processing operations of the memory device 2200.

The processor 4100 may output data stored in the memory device 2200 through the display 4300 according to data input through the input device 4200. For example, the input device 4200 may be implemented as a pointing device such as a touch pad, computer mouse, keypad, or keyboard.

The processor 4100 may control the overall operation of the memory system 40000 and control the operation of the memory controller 2100. In some embodiments, the memory controller 2100 capable of controlling the operation of the memory device 2200 may be implemented as part of the processor 4100 or as a separate chip from the processor 4100.

Fig. 10 is a diagram illustrating a memory system according to one embodiment of the present disclosure.

Referring to fig. 10, the memory system 50000 may be implemented as an image processing apparatus such as a digital camera, a mobile terminal having a digital camera attached thereto, a smart phone having a digital camera attached thereto, or a tablet PC having a digital camera attached thereto.

The memory system 50000 may include a memory device 2200 and a memory controller 2100 capable of controlling data processing operations (e.g., program operations, erase operations, or read operations) of the memory device 2200.

The image sensor 5200 of the memory system 50000 may convert the optical image into a digital signal and may transmit the converted digital signal to the processor 5100 or the memory controller 2100. The converted digital signal may be output through the display 5300 or may be stored in the memory device 2200 through the memory controller 2100 under the control of the processor 5100. In addition, data stored in the memory device 2200 may be output through the display 5300 under the control of the processor 5100 or the memory controller 2100.

In some embodiments, the memory controller 2100 capable of controlling the operation of the memory device 2200 may be implemented as part of the processor 5100 or as a separate chip from the processor 5100.

Fig. 11 is a diagram illustrating a memory system according to one embodiment of the present disclosure.

Referring to fig. 11, the memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 2200, a memory controller 2100, and a card interface 7100.

The memory controller 2100 may control data exchange between the memory device 2200 and the card interface 7100. In some embodiments, the card interface 7100 may be a Secure Digital (SD) card interface or a multimedia card (MMC) interface, although the disclosure is not limited thereto.

The card interface 7100 may interface data exchanges between the host 60000 and the memory controller 2100 according to the protocol of the host 60000. In some embodiments, card interface 7100 may support the Universal Serial Bus (USB) protocol and the inter-chip (IC) -USB protocol. The card interface 7100 may comprise hardware, software embedded in hardware, or a signaling scheme suitable for supporting the protocols used by the host 60000.

When the memory system 70000 is connected to a host interface 6200 of a host 60000 (e.g., a PC, a tablet PC, a digital video camera, a digital audio player, a cellular phone, console video game hardware, or a digital set-top box), the host interface 6200 can perform data communication with the memory device 2200 through the card interface 7100 and the memory controller 2100 under the control of the microprocessor 6100.

According to the present disclosure, a semiconductor device having improved operating characteristics and enhanced reliability is provided.

While the present disclosure has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. For example, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined not only by the appended claims but also by their equivalents.

In the above embodiment, all operations may be selectively performed. In each embodiment, the operations need not be performed in the order described, and may be rearranged. The embodiments disclosed in the present specification and drawings are examples for assisting understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it is apparent to those skilled in the art that various modifications can be made in the technical scope of the present disclosure.

Furthermore, embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are employed herein, they are used only to describe embodiments of the disclosure. For example, the present disclosure is not limited to the above-described embodiments, and various modifications may be made within the spirit and scope of the present disclosure. It is apparent to those skilled in the art that various modifications other than the embodiments disclosed herein are possible based on the technical scope of the present disclosure.

Cross Reference to Related Applications

This application claims priority to korean patent application No.10-2020-0041734, filed on 6/4/2020, which is hereby incorporated by reference in its entirety.