阅读说明：本技术 薄膜晶体管基板及显示面板 (Thin film transistor substrate and display panel ) 是由 黄建龙 于 2020-08-31 设计创作，主要内容包括：本申请提供一种薄膜晶体管及显示面板,在薄膜晶体管基板中,有源层包括第一部分、第二部分和连接在第一部分与第二部分之间的中间部分,第一部分的延伸方向与中间部分的延伸方向重合；第一栅极和第二栅极分别与中间部分重叠设置；源极连接于第一部分,漏极连接于第二部分。本申请通过变更有源层的形状,以压缩有源层在垂直方向或水平方向的宽度,进而提高开口率。(In a thin film transistor substrate, an active layer includes a first portion, a second portion, and a middle portion connected between the first portion and the second portion, and an extending direction of the first portion coincides with an extending direction of the middle portion; the first grid and the second grid are respectively arranged in an overlapping way with the middle part; the source is connected to the first portion and the drain is connected to the second portion. The active layer is compressed in the width in the vertical direction or the horizontal direction by changing the shape of the active layer, and the aperture opening ratio is further improved.)

1. A thin film transistor substrate, comprising:

a plurality of scanning lines extending along a first direction;

the data lines extend along a second direction, and the extending direction of the data lines and the extending direction of the scanning lines are crossed to form a cross part; and

a plurality of thin film transistors disposed near the intersections;

the thin film transistor includes:

an active layer including a first portion, a second portion, and an intermediate portion connected between the first portion and the second portion, an extending direction of the first portion coinciding with an extending direction of the intermediate portion;

the first grid electrode is connected to the scanning line and is overlapped with the middle part;

the second grid electrode is connected to the scanning line and is arranged in an overlapping mode with the middle part;

a source electrode connected to the data line, the source electrode being electrically connected to the first portion; and

a drain electrically connected to the second portion.

2. The thin film transistor substrate according to claim 1, wherein an extending direction of the intermediate portion is parallel to an extending direction of the scan line.

3. The thin film transistor substrate according to claim 2, wherein an extending direction of the second portion coincides with an extending direction of the intermediate portion.

4. The thin film transistor substrate according to claim 3, wherein the first gate electrode extends in a direction perpendicular to the direction in which the scanning lines extend, and the second gate electrode extends in a direction perpendicular to the direction in which the scanning lines extend.

5. The thin film transistor substrate according to claim 1, wherein an extending direction of the second portion intersects an extending direction of the intermediate portion.

6. The thin film transistor substrate of claim 1, wherein an extending direction of the intermediate portion is parallel to an extending direction of the data line.

7. The thin film transistor substrate according to claim 6, wherein the data lines are respectively disposed to overlap the first gate electrode and the second gate electrode.

8. The thin film transistor substrate according to claim 7, wherein an extending direction of the first gate electrode is perpendicular to an extending direction of the data line, and an extending direction of the second gate electrode is perpendicular to an extending direction of the data line, in a plan view of the thin film transistor substrate.

9. The thin film transistor substrate according to claim 7, wherein the data line is disposed to overlap the intermediate portion.

10. The thin film transistor substrate of claim 7, wherein the scan line comprises a first segment and a second segment arranged at intervals, and the first gate is arranged opposite to the second gate;

the first gate is connected on the same side of the first segment and the second segment and is located between the first segment and the second segment; the second gate is connected on the other same side of the first segment and the second segment and is located between the first segment and the second segment.

11. A display panel, comprising:

the thin film transistor substrate according to any one of claims 1 and 5 to 8;

the color film substrate is arranged opposite to the thin film transistor substrate and comprises a black matrix, and the black matrix covers the scanning lines, the data lines and the thin film transistors.

12. The display panel according to claim 11, further comprising spacers disposed between the thin film transistor substrate and the color filter substrate, the spacers being disposed at intersections between the scan lines and the data lines;

the data line is arranged to be overlapped with the middle part; the spacer is arranged to overlap the intermediate portion.

13. The display panel according to claim 12, wherein the scan line includes a first segment and a second segment arranged at an interval, and the first gate electrode is arranged opposite to the second gate electrode;

the first gate is connected on the same side of the first segment and the second segment and is located between the first segment and the second segment; the second gate is connected to the other same side of the first segment and the second segment and is located between the first segment and the second segment;

the orthographic projection of the spacing column on the plane of the first metal layer is located between the first section and the second section.

Technical Field

The present disclosure relates to display technologies, and particularly to a thin film transistor substrate and a display panel.

Background

In the panel industry, the aperture ratio is an important index for measuring the panel, and refers to the ratio of the area of one sub-pixel transmitting light to the area of the whole sub-pixel. With the increasing demands of the market on resolution, how to design panels with high aperture ratio is the direction of the development of each enterprise.

In the current pixel design, the factors affecting the aperture ratio are mainly the line widths of the scan lines and the data lines. And the width in the scan line direction is mainly affected by the width in the vertical direction of the portion of the active layer corresponding to the sub-pixel. The conventional active layer corresponding to the sub-pixel is generally U-shaped, which results in an excessively large width of the active layer corresponding to the thin film transistor in the vertical direction, thereby causing a low aperture ratio of the sub-pixel.

Disclosure of Invention

The embodiment of the application provides a thin film transistor substrate and a display panel, and aims to solve the technical problem that the opening ratio of a sub-pixel is low due to the fact that the width of a part, corresponding to a thin film transistor, of an active layer of the existing display panel in the vertical direction is too large.

An embodiment of the present application provides a thin film transistor substrate, the thin film transistor substrate includes:

a plurality of scanning lines extending along a first direction;

the data lines extend along a second direction, and the extending direction of the data lines and the extending direction of the scanning lines are crossed to form a cross part; and

a plurality of thin film transistors disposed near the intersections;

the thin film transistor includes:

an active layer including a first portion, a second portion, and an intermediate portion connected between the first portion and the second portion, an extending direction of the first portion coinciding with an extending direction of the intermediate portion;

the first grid electrode is connected to the scanning line and is overlapped with the middle part;

the second grid electrode is connected to the scanning line and is arranged in an overlapping mode with the middle part;

a source electrode connected to the data line, the source electrode being electrically connected to the first portion; and

a drain electrically connected to the second portion.

In the thin film transistor substrate according to the embodiment of the present application, an extending direction of the second portion coincides with an extending direction of the intermediate portion.

In the thin film transistor substrate according to the embodiment of the present application, an extending direction of the middle portion is parallel to an extending direction of the scan line.

In the thin film transistor substrate according to the embodiment of the present application, an extending direction of the first gate electrode is perpendicular to an extending direction of the scan line, and an extending direction of the second gate electrode is perpendicular to the extending direction of the scan line.

In the thin film transistor substrate according to another embodiment of the present application, an extending direction of the second portion intersects an extending direction of the intermediate portion.

In the thin film transistor substrate according to another embodiment of the present application, an extending direction of the middle portion is parallel to an extending direction of the data line.

In the thin film transistor substrate according to another embodiment of the present application, the data lines are respectively overlapped with the first gate and the second gate.

In another embodiment of the thin film transistor substrate, in a top view of the thin film transistor substrate, an extending direction of the first gate electrode is perpendicular to an extending direction of the data line, and an extending direction of the second gate electrode is perpendicular to the extending direction of the data line.

In the thin film transistor substrate according to another embodiment of the present application, the data line overlaps with the middle portion.

In the thin film transistor substrate according to another embodiment of the present application, the scan line includes a first segment and a second segment that are disposed at an interval, and the first gate is disposed opposite to the second gate;

the first gate is connected on the same side of the first segment and the second segment and is located between the first segment and the second segment; the second gate is connected on the other same side of the first segment and the second segment and is located between the first segment and the second segment.

The embodiment of the present application further relates to a display panel, which includes:

the thin film transistor substrate according to the another embodiment;

the color film substrate is arranged opposite to the thin film transistor substrate and comprises a black matrix, and the black matrix covers the scanning lines, the data lines and the thin film transistors.

In the display panel of this embodiment, the display panel further includes a spacer disposed between the thin film transistor substrate and the color film substrate, where the spacer is disposed at an intersection of an extending direction of the scan line and an extending direction of the data line;

the data line is arranged to be overlapped with the middle part; the spacer is arranged to overlap the intermediate portion.

In the display panel of this embodiment, the scan line includes a first segment and a second segment that are disposed at an interval, and the first gate is disposed opposite to the second gate;

the first gate is connected on the same side of the first segment and the second segment and is located between the first segment and the second segment; the second gate is connected on the other same side of the first segment and the second segment and is located between the first segment and the second segment.

The orthographic projection of the spacing column on the plane of the first metal layer is located between the first section and the second section.

According to the thin film transistor substrate and the display panel, the width of the active part in the vertical direction or the horizontal direction is reduced by changing the shape of the active layer, and the aperture opening ratio is further improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required in the embodiments are briefly described below. The drawings in the following description are only some embodiments of the present application, and it will be obvious to those skilled in the art that other drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a schematic cross-sectional structural diagram of a display panel according to a first embodiment of the present application;

FIG. 2 is a schematic top view of a thin film transistor substrate portion of a display panel according to a first embodiment of the present application;

FIG. 3 is a schematic top view of a thin film transistor substrate portion of a display panel according to a second embodiment of the present application;

fig. 4 is a schematic cross-sectional structural diagram of a display panel according to a third embodiment of the present application;

fig. 5 is a schematic top view of a thin film transistor portion of a display panel according to a third embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "width," "upper," "lower," "vertical," "horizontal," "top," "bottom," and the like, as used herein, are defined based on the orientation or positional relationship shown in the drawings, and are used merely for convenience in describing the present application and for simplicity in description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be considered limiting of the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "connected" and "connected" are to be interpreted broadly, e.g., as being fixed or detachable or integrally connected; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Referring to fig. 1 and fig. 2, fig. 1 is a schematic cross-sectional structure view of a display panel according to a first embodiment of the present application; fig. 2 is a schematic top view of a thin film transistor substrate portion of a display panel according to a first embodiment of the present application.

The display panel 100 according to the first embodiment of the present application includes a thin film transistor substrate 10 and a color filter substrate 20. The color film substrate 20 is arranged opposite to the thin film transistor substrate 10.

The color film substrate 20 includes a first substrate 21, a black matrix 22, and a planarization layer 23. The black matrix 22 is disposed on the first substrate 21. The flat layer 23 is disposed on the black matrix 22.

The thin film transistor substrate 10 includes a plurality of sub-pixel regions. The thin film transistor substrate 10 includes a second substrate 11, an active layer 12, a first insulating layer 13, a first metal layer 14, a second insulating layer 15, a second metal layer 16, and a protective layer 17.

The thin film transistor substrate 10 further includes a pixel electrode layer (not shown). The thin film transistor in the thin film transistor substrate 10 may be a bottom gate type or a top gate type. The display panel 100 of the first embodiment is illustrated by taking a top gate thin film transistor as an example, but is not limited thereto.

Specifically, an active layer 12, a first insulating layer 13, a first metal layer 14, a second insulating layer 15, a second metal layer 16, and a protective layer 17 are sequentially disposed on the second substrate 11.

The active layer 12 includes a first portion 12a, a second portion 12b, and an intermediate portion 12c connected between the first portion 12a and the second portion 12 b. The extension direction of the first portion 12a coincides with the extension direction of the intermediate portion 12 c.

The first metal layer 14 is disposed in a different layer from the active layer 12. The first metal layer 14 includes a scan line 141, a first gate 142, and a second gate 143. The scan lines 141 extend along a first direction. The first gate 142 and the second gate 143 are spaced apart from each other and are connected to the scan line 141. The first gate 142 and the second gate 143 are respectively disposed to overlap the middle portion 12 c.

The second metal layer 16 is disposed in a different layer from the active layer 12 and the first metal layer 14, respectively. The second metal layer 16 includes a data line 161, a source electrode 162, and a drain electrode 163. The source electrode 162 is connected to the data line 161. The data line 161 extends along a second direction. The extending direction of the data line 161 and the extending direction of the scan line 141 are arranged to intersect to form an intersection. The source 162 is electrically connected to the first portion 12 a. The drain electrode 163 is electrically connected to the second portion 12 b.

Specifically, the source 162 is connected to the first portion 12a through a first via. The drain electrode 163 is connected to the second portion 12b through a second via hole.

Specifically, the thin film transistor TFT is disposed in the vicinity of the intersection. The thin film transistor TFT includes an active layer 12, a first gate electrode 142, a second gate electrode 143, a source electrode 162, and a drain electrode 163.

Alternatively, as shown in fig. 2, the extending direction of the data line 161 is perpendicular to the extending direction of the scan line 141. I.e. the first direction is perpendicular to the second direction.

The black matrix 22 covers the scan line 141, the data line 161, and the thin film transistor TFT.

The display panel 100 of the first embodiment of the present application changes the shape of the active layer 12 to reduce the occupied area of the active layer, thereby improving the aperture ratio. Specifically, the first portion 12a and the middle portion 12c of the active layer 12 extend and are connected in the same direction to reduce the occupied area of the active layer 12, thereby increasing the aperture ratio.

In the display panel 100 of the present first embodiment, the extending direction of the middle portion 12c is parallel to the extending direction of the scan line 141. Therefore, the width of the active layer 12 in the vertical direction is shortened, and the aperture opening ratio is improved; note that the vertical direction is a direction perpendicular to the extending direction of the scanning line 141; in the present embodiment, since the first direction is perpendicular to the second direction, the vertical direction is equivalent to the second direction, and the horizontal direction is equivalent to the first direction.

In addition, the extending direction of the second portion 12b coincides with the extending direction of the intermediate portion 12 c. This makes the active layer 12 linear, and the width of the active layer 12 in the vertical direction is further reduced.

Optionally, the extending direction of the first gate 142 is perpendicular to the extending direction of the scan line 141. The extending direction of the second gate electrode 143 is perpendicular to the extending direction of the scan line 141. Thereby simplifying the lap joint structure of the first and second gate electrodes 142 and 143, respectively, with the intermediate portion 12 c.

Referring to fig. 3, the display panel 200 of the second embodiment is different from the display panel 100 of the first embodiment in that the extending direction of the second portion 12b intersects with the extending direction of the middle portion 12 c.

Optionally, the extending direction of the second portion 12b is perpendicular to the extending direction of the middle portion 12 c.

Embodiments of the present application also relate to a thin film transistor substrate, which is the thin film transistor substrate 10 of the display panel 100 of the first embodiment or the thin film transistor substrate 10 of the display panel 200 of the second embodiment. The thin film transistor substrate can be applied to an OLED display panel, and can also be applied to a liquid crystal display panel or a Mini-LED display panel and the like.

Referring to fig. 4 and 5, a display panel 300 according to a third embodiment of the present disclosure includes a thin film transistor substrate 10, a color filter substrate 20, and spacers 30. The color film substrate 20 is arranged opposite to the thin film transistor substrate 10. The spacers 30 are disposed between the thin film transistor substrate 10 and the color filter substrate 20.

The color film substrate 20 includes a first substrate 21, a black matrix 22, and a planarization layer 23. The black matrix 22 is disposed on the first substrate 21. The flat layer 23 is disposed on the black matrix 22.

The thin film transistor substrate 10 includes a plurality of sub-pixel regions. The thin film transistor substrate 10 includes a second substrate 11, an active layer 12, a first insulating layer 13, a first metal layer 14, a second insulating layer 15, a second metal layer 16, and a protective layer 17.

The thin film transistor substrate 10 may further include a pixel electrode layer (not shown). The thin film transistor in the thin film transistor substrate 10 may be a bottom gate type or a top gate type. The display panel 300 of the third embodiment is illustrated by taking a top gate thin film transistor as an example, but is not limited thereto.

Specifically, an active layer 12, a first insulating layer 13, a first metal layer 14, a second insulating layer 15, a second metal layer 16, and a protective layer 17 are sequentially disposed on the second substrate 11.

The active layer 12 includes a first portion 12a, a second portion 12b, and an intermediate portion 12c connected between the first portion 12a and the second portion 12 b. The extension direction of the first portion 12a coincides with the extension direction of the intermediate portion 12 c.

The first metal layer 14 is disposed in a different layer from the active layer 12. The first metal layer 14 includes a scan line 141, a first gate 142, and a second gate 143. The scan lines 141 extend along a first direction. The first gate 142 and the second gate 143 are spaced apart from each other and are connected to the scan line 141. The first gate 142 and the second gate 143 are respectively disposed to overlap the middle portion 12 c.

The second metal layer 16 is disposed in a different layer from the active layer 12 and the first metal layer 14, respectively. The second metal layer 16 includes a data line 161, a source electrode 162, and a drain electrode 163. The source electrode 162 is connected to the data line 161. The data line 161 extends along a second direction. The extending direction of the data line 161 and the extending direction of the scan line 141 are arranged to intersect to form an intersection. The source 162 is electrically connected to the first portion 12 a. The drain electrode 163 is electrically connected to the second portion 12 b.

Specifically, the source 162 is connected to the first portion 12a through a first via. The drain electrode 163 is connected to the second portion 12b through a second via hole.

Alternatively, as shown in fig. 4, the extending direction of the data line 161 is perpendicular to the extending direction of the scan line 141.

The black matrix 22 covers the scan line 141, the data line 161, and the thin film transistor TFT.

The display panel 300 according to the third embodiment of the present application changes the shape of the active layer 12 to reduce the occupied area of the active layer 12, thereby improving the aperture ratio. Specifically, the first portion 12a and the middle portion 12c of the active layer 12 extend and are connected in the same direction to reduce the occupied area of the active layer 12, thereby increasing the aperture ratio.

Wherein the extension direction of the second portion 12b intersects the extension direction of the intermediate portion 12 c. The extending direction of the middle portion 12c is parallel to the extending direction of the data line 161. Thereby shortening the width of the active layer 12 in the horizontal direction. The horizontal direction is perpendicular to the vertical direction.

In the display panel 300 according to the third embodiment, the data lines 161 are respectively overlapped with the first gate electrodes 142 and the second gate electrodes 143. Thus, the portion of the data line 161 overlapping the first gate electrode 142 shares the portion of the black matrix 22, and the portion of the data line 161 overlapping the second gate electrode 142 shares the portion of the black matrix 22. That is, the portion of the black matrix 22 simultaneously blocks the portion of the data line 161 overlapping the first gate electrode 142 and the portion of the data line 161 overlapping the second gate electrode 142 to improve the aperture ratio.

In the display panel 300 according to the third embodiment, in a top view (fig. 5) of the thin film transistor substrate 10, an extending direction of the first gate electrode 142 is perpendicular to an extending direction of the data line 161, and an extending direction of the second gate electrode 143 is perpendicular to the extending direction of the data line 161. Meanwhile, the extending direction of the first gate 142 is perpendicular to the extending direction of the middle portion 12c, and the extending direction of the second gate 143 is perpendicular to the extending direction of the middle portion 12 c. Thereby further shortening the wiring space of the first gate electrode 142 and the second gate electrode 143, thereby improving the aperture ratio.

In addition, the data lines 161 are also disposed to overlap the middle portion 12c and the first portion 12a, respectively. Thus, the portion of the data line 161 overlapping the middle portion 12c shares the portion of the black matrix 22, and the portion of the data line 161 overlapping the first portion 12a shares the portion of the black matrix 22. That is, a portion of the black matrix 22 simultaneously blocks a portion of the data line 161 overlapping the first portion 12a and a portion of the data line 161 overlapping the middle portion 12c to improve the aperture ratio.

In the display panel 300 according to the third embodiment, the scan line 141 includes a first segment 14a and a second segment 14b that are disposed at intervals. The first gate 142 is disposed opposite to the second gate 143.

The first gate 142 is connected on the same side of the first segment 14a as the second segment 14b and is located between the first segment 14a and the second segment 14 b. The second gate 143 is connected to the same side of the first segment 14a as the second segment 14b, and is located between the first segment 14a and the second segment 14 b. Wherein the definition of the same side is the same as the definition of the same side.

The spacers 30 are disposed at intersections of the extending direction of the scan lines 141 and the extending direction of the data lines 161.

The spacers 30 are respectively disposed to overlap the intermediate portion 12c and the data line 161. Thus, the portion of the spacer 30 overlapping the intermediate portion 12c shares the portion of the black matrix 22, and the portion of the spacer 30 overlapping the data line 161 shares the portion of the black matrix 22. That is, the portion of the black matrix 22 simultaneously covers the portion of the spacer 30 overlapping the middle portion 12c and the portion of the spacer 30 overlapping the data line 161 to improve the aperture ratio.

The orthogonal projection of the spacer 30 on the plane of the first metal layer 14 is located between the first segment 14a and the second segment 14 b. Therefore, the base of the spacer 30 and the wiring positions of the first gate 142 and the second gate 143 share the same space, so as to save the area of the black matrix 22 and improve the aperture ratio.

Optionally, the orthographic projection of the spacer 30 on the plane of the first metal layer 14 covers the first gate 142 and the second gate 143, so as to save the shielding area of the black matrix 22 and improve the aperture ratio.

The embodiment of the present application also relates to a thin film transistor substrate, which is the thin film transistor substrate 10 of the display panel 300 of the third embodiment. The thin film transistor substrate can be applied to an OLED display panel, and can also be applied to a liquid crystal display panel or a Mini-LED display panel and the like.

The thin film transistor substrate and the display panel of the application compress the width of the active part in the vertical direction or the horizontal direction by changing the shape of the active part, and further improve the aperture opening ratio.

The foregoing detailed description is directed to a thin film transistor substrate and a display panel provided in the embodiments of the present application, and specific examples are applied in the present application to explain the principles and embodiments of the present application, and the description of the foregoing embodiments is only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.