阅读说明：本技术 减少掉电后读错误几率的方法、装置、存储介质和终端 (Method, device, storage medium and terminal for reducing probability of reading error after power failure ) 是由 冯鹏亮 陈纬荣 陈慧 王明 于 2021-05-21 设计创作，主要内容包括：本发明公开了一种减少掉电后读错误几率的方法、装置、存储介质和终端,在芯片执行擦除操作期间,若发生异常掉电时,芯片内部自动启动断电中断保护,结束芯片的擦除操作,并根据所述擦除指令信息对芯片内的存储单元执行过擦除修复；若出现快掉电,此时可能已经对部分需要执行过擦除修复的存储单元执行完过擦除修复,在重新上电时,虽然还是会有过擦除导致读数据出错的问题,但因为有部分存储单元已经执过擦除修复,所以因过擦除导致读数据出错的几率会有所下降；若出现慢掉电,这时可以对芯片内需要执行过擦除修复的全部存储单元都执行完过擦除修复,在重新上电时,即可避免因过擦除造成的读数据错误的问题。(The invention discloses a method, a device, a storage medium and a terminal for reducing the probability of reading errors after power failure.A power failure interrupt protection is automatically started in a chip during the execution of erasing operation of the chip if abnormal power failure occurs, the erasing operation of the chip is finished, and over-erasing repair is executed on a storage unit in the chip according to erasing instruction information; if fast power failure occurs, at this time, over-erase repair may have been performed on a part of the memory cells that need to be subjected to the over-erase repair, and when power is re-turned on, although there is still a problem of errors in read data due to over-erase, because some memory cells have already been subjected to the erase repair, the probability of errors in read data due to over-erase is reduced; if slow power down occurs, the over-erase repair can be executed on all the memory units in the chip which need to be subjected to the over-erase repair, and when power is re-turned on, the problem of data reading errors caused by over-erase can be avoided.)

1. A method for reducing the probability of a read error after power failure is characterized by specifically comprising the following steps:

receiving erasing instruction information;

executing erasing operation on a storage unit in the chip according to the erasing instruction information;

judging whether the chip has abnormal power failure or not,

if not, the current operation state of the chip is not changed;

if so, the power-off interrupt protection is started,

and finishing the erasing operation of the chip according to the power-off interrupt protection, and performing over-erasing repair on the storage unit in the chip according to the erasing instruction information.

2. The method for reducing the read error probability after power failure according to claim 1, wherein the step of judging whether the chip has abnormal power failure comprises the following specific steps: it is determined whether a voltage applied to a memory cell within the chip drops to a preset threshold.

3. The method for reducing the probability of a read error after power down of claim 1, wherein the abnormal power down comprises a fast power down and a slow power down.

4. The method for reducing the read error probability after power failure according to claim 3, wherein when the abnormal power failure is slow power failure, the following process is further included after the erasing operation of the chip is ended according to the power failure interrupt protection and the over-erase repair is performed on the memory unit in the chip according to the erasing instruction information:

s7: judging whether all the memory units needing to be subjected to the over-erase repair in the chip are subjected to the over-erase repair, if so, jumping to S8, otherwise, jumping to S9;

s8: reducing the voltage applied to the memory cells within the chip to 0 and exiting the over-erase repair procedure;

s9: and performing over-erase repair on the memory cells in the chip according to the erase instruction information and jumping to S7.

5. The method of claim 1, wherein the erasure instruction information includes an erasure instruction and an address of a storage unit to be erased in the chip.

6. A device for reducing the probability of a read error after power failure, comprising:

the receiving module is used for receiving erasing instruction information;

the erasing module is used for executing erasing operation on the storage unit in the chip according to the erasing instruction information;

the judging module judges whether the chip has abnormal power failure or not,

the state keeping module does not change the current operating state of the chip;

an interrupt starting module for starting the power-off interrupt protection,

and the over-erasing repair module is used for finishing the erasing operation of the chip according to the power-off interrupt protection and executing the over-erasing repair on the storage unit in the chip according to the erasing instruction information.

7. The apparatus for reducing the probability of a read error after power failure according to claim 6, wherein the determining module is implemented by a voltage detecting module.

8. The apparatus for reducing the probability of a read error after power down of claim 6, wherein the erase module and the over-erase repair module are implemented by an algorithm module inside a chip.

9. A storage medium having stored thereon a computer program which, when run on a computer, causes the computer to perform the method of any one of claims 1 to 5.

10. A terminal, characterized in that it comprises a processor and a memory, in which a computer program is stored, the processor being adapted to carry out the method of any one of claims 1 to 5 by calling the computer program stored in the memory.

Technical Field

The invention relates to the technical field of FLASH, in particular to a method, a device, a storage medium and a terminal for reducing the probability of reading errors after power failure.

Background

After the power failure of the existing NOR FLASH, the interior of the circuit judges whether the voltage reaches a low-voltage threshold value, if so, a power failure protection module is started, an interrupt is sent to an algorithm state machine, and the algorithm state machine responds to the interrupt, discharges a voltage pump and then exits the algorithm. The disadvantages of this procedure are:

in the case of the slow power down of NOR FLASH during the erasing of the sector a (sector a) in the array a (array a), if the internal algorithm flow is in the erasing step (as shown in fig. 1), and the step of repairing the "over-erased" cell is not suspended (i.e. branch 2), then there may be an error when reading the data of another sector B (sector B) in the same array a (array a) after the voltage is restored, and the read data is a random value (depending on the number and distribution of the "over-erased" cells in the sector a, since the threshold voltage of the "over-erased" cells is generally negative, when reading the data of the sector B, if the "over-erased" cell exists in the sector a, 0v cannot turn off the "over-erased" cell, and the "over-erased" cell may generate current, which may cause an error in the reading, as shown in fig. 2).

Therefore, the prior art still needs to be improved and developed.

Disclosure of Invention

The invention aims to provide a method, a device, a storage medium and a terminal for reducing the probability of a read error after power failure, and aims to solve one or more problems in the prior art.

The technical scheme of the invention is as follows: the technical scheme provides a method for reducing the probability of reading errors after power failure, which specifically comprises the following steps:

receiving erasing instruction information;

executing erasing operation on a storage unit in the chip according to the erasing instruction information;

judging whether the chip has abnormal power failure or not,

if not, the current operation state of the chip is not changed;

if so, the power-off interrupt protection is started,

and finishing the erasing operation of the chip according to the power-off interrupt protection, and performing over-erasing repair on the storage unit in the chip according to the erasing instruction information.

Further, whether the chip has abnormal power failure or not is judged, and the specific process is as follows: it is determined whether a voltage applied to a memory cell within the chip drops to a preset threshold.

Further, the abnormal power failure includes a fast power failure and a slow power failure.

Further, when the abnormal power failure is a slow power failure, the following processes are included after the erasing operation of the chip is ended according to the power-off interrupt protection and the over-erasing repair is performed on the memory unit in the chip according to the erasing instruction information:

s7: judging whether all the memory units needing to be subjected to the over-erase repair in the chip are subjected to the over-erase repair, if so, jumping to S8, otherwise, jumping to S9;

s8: reducing the voltage applied to the memory cells within the chip to 0 and exiting the over-erase repair procedure;

s9: and performing over-erase repair on the memory cells in the chip according to the erase instruction information and jumping to S7.

Further, the erasing instruction information comprises an erasing instruction and the address of a storage unit needing to be subjected to erasing operation in the chip.

This technical scheme still provides a device of error rate is read after reducing to fall electric, includes:

the receiving module is used for receiving erasing instruction information;

the erasing module is used for executing erasing operation on the storage unit in the chip according to the erasing instruction information;

the judging module judges whether the chip has abnormal power failure or not,

the state keeping module does not change the current operating state of the chip;

an interrupt starting module for starting the power-off interrupt protection,

and the over-erasing repair module is used for finishing the erasing operation of the chip according to the power-off interrupt protection and executing the over-erasing repair on the storage unit in the chip according to the erasing instruction information.

Further, the judging module is realized by adopting a voltage detecting module.

Further, the erasing module and the over-erasing repairing module are realized through an algorithm module inside the chip.

The present invention also provides a storage medium, in which a computer program is stored, and when the computer program runs on a computer, the computer is caused to execute any one of the methods described above.

The technical solution also provides a terminal, which includes a processor and a memory, wherein the memory stores a computer program, and the processor is used for executing any one of the methods by calling the computer program stored in the memory.

According to the method, during the erasing operation of the chip, if abnormal power failure occurs, the power-off interruption protection is automatically started in the chip, the erasing operation of the chip is finished, and the over-erasing repair is performed on the storage unit in the chip according to the erasing instruction information; if fast power failure occurs, at this time, over-erase repair may have been performed on part of the memory cells that need to be subjected to the over-erase repair, but over-erase repair cannot be performed on all the memory cells that need to be subjected to the over-erase repair in the chip, at this time, when power is re-turned on, although there is still a problem of data reading errors caused by over-erase, because some memory cells have already been subjected to the over-erase repair, the probability of data reading errors caused by over-erase is reduced; if slow power down occurs, the over-erase repair can be executed on all the memory units in the chip which need to be subjected to the over-erase repair, and when power is re-turned on, the problem of data reading errors caused by over-erase can be avoided.

Drawings

Fig. 1 is a schematic diagram of an erase algorithm in the prior art.

Fig. 2 is a block diagram in the prior art.

FIG. 3 is a flow chart of the steps of the method of the present invention for reducing the probability of a read error after a power failure.

Fig. 4 is a schematic diagram of the apparatus for reducing the probability of a read error after power failure in the present invention.

Fig. 5 is a schematic diagram of a terminal in the present invention.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

As shown in fig. 3, a method for reducing the probability of a read error after power failure is applicable to a NOR FLASH chip, and specifically includes the following steps:

s1: and receiving erasure instruction information.

The erasing instruction information comprises an erasing instruction and the address of a storage unit needing to be subjected to erasing operation in the chip.

S2: and executing an erasing operation on the memory unit in the chip according to the erasing instruction information.

S3: and judging whether the voltage applied to the memory cell in the chip is reduced to a preset threshold value, if so, jumping to S5, and otherwise, jumping to S4.

During the chip executing the erasing operation (at the moment, the internal algorithm process is in the erasing step, and the step of repairing the over-erasing unit is not available), the chip interior detects whether the erasing voltage applied to the storage unit in the chip is reduced to a preset threshold value in real time, if so, the abnormal power failure occurs by default, otherwise, the abnormal power failure does not occur.

S4: the current operating state of the chip is not changed.

And if the current operation state of the chip is not changed, continuing to execute the erasing operation on the memory unit in the chip according to the erasing instruction information and the normal flow.

S5: power-off interrupt protection is initiated.

When abnormal power failure occurs, the power-off interruption protection is automatically started in the chip, the erasing operation of the chip is finished, and the over-erasing repair is carried out on the storage unit in the chip according to the erasing instruction information.

S6: and finishing the erasing operation of the chip according to the power-off interrupt protection, and performing over-erasing repair on the storage unit in the chip according to the erasing instruction information.

The specific operation process of S6 is as follows: when an instruction sent by a user for erasing a certain sector in the chip is received, the internal algorithm module executes an erasing step, if abnormal power failure occurs, the power failure protection module sends power failure protection interruption to the internal algorithm module of the chip, the NOR Flash immediately responds to the interruption, the erasing is finished, and an over-erasing repair stage is entered.

Since the voltage applied to the memory cells within the chip when the over-erase repair is performed is lower than the voltage applied to the memory cells within the chip when the erase operation is performed, the over-erase repair can be performed although the erase operation cannot be continued when the abnormal power down occurs.

When abnormal power failure occurs, fast power failure may occur (the speed of power failure is fast, that is, the duration of a process that a voltage applied to a memory cell in a chip is reduced from a preset threshold to a voltage which needs to be applied to the memory cell when the chip performs over-erase repair is short, and the chip cannot be supported to perform the whole over-erase repair process), at this time, over-erase repair may be performed on a part of memory cells which need to perform the over-erase repair (according to the speed of power failure), but over-erase repair cannot be performed on all memory cells which need to perform the over-erase repair in the chip, at this time, when power is re-turned on, although the problem of reading data errors caused by over-erase still exists, because a part of the memory cells have performed the over-erase repair, the probability of reading data errors caused by over-erase is reduced; when abnormal power failure occurs, slow power failure may occur (the power failure speed is slow, that is, the duration of the process of reducing the voltage applied to the memory cells in the chip from the preset threshold to the voltage applied to the memory cells when the chip performs over-erase repair is long enough (about several ms), which may support the chip to perform the entire over-erase repair process).

In order to reduce power consumption when slow power down occurs, the following steps are also included after S6:

s7: judging whether all the memory units needing to be subjected to the over-erase repair in the chip are subjected to the over-erase repair, if so, jumping to S8, otherwise, jumping to S9;

s8: reducing the voltage applied to the memory cells within the chip to 0 and exiting the over-erase repair procedure;

s9: and performing over-erase repair on the memory cells in the chip according to the erase instruction information and jumping to S7.

Detecting whether the erasing voltage applied to the storage unit in the chip is reduced to a preset threshold value in real time during the erasing operation of the chip, for example, the erasing voltage applied to the storage unit in the chip is required to be 1.8v, when detecting whether the voltage applied to the storage unit in the chip is reduced to 1.5v, namely, an abnormal power failure condition occurs by default, automatically starting power-off interruption protection in the chip, finishing the erasing operation of the chip, and performing over-erasing repair on the storage unit in the chip according to the erasing instruction information; when the chip performs over-erase repair, the voltage applied to the memory unit is 1.2v, if the duration of the process from 1.5v to 1.2v is short (less than a few ms), fast power failure occurs, and at this time, the over-erase repair may be performed on part of the memory units which need to perform the over-erase repair, but the over-erase repair cannot be performed on all the memory units which need to perform the over-erase repair in the chip; if the process from 1.5v to 1.2v lasts for a relatively slow time (which can last for several ms), slow power failure occurs, at this time, over-erase repair can be performed on all memory cells in the chip that need to be subjected to the over-erase repair, and after the over-erase repair is performed on all the memory cells in the chip that need to be subjected to the over-erase repair, the voltage pump is controlled to discharge to 0v, and the algorithm is exited.

Compared with the scheme that after the chip is powered on again, the over-erase repair is executed before data reading (although the scheme can also solve the problem of data reading errors caused by over-erase after power failure), the technical scheme has the advantages of shorter operation time and higher efficiency, and because the system does not know which memory cells in the chip execute the over-erase operation after the chip is powered on again and cannot quickly find the over-erase units in the chip (all the memory cells in the chip need to be judged to see whether the memory cells are the over-erase units) under the condition that after the chip is powered on again and the over-erase repair is executed before the data reading, the time consumption is longer because the power of the front-erase operation is cut off; in the technical scheme, the over-erase repair is executed while the interrupt erase is responded, and although the erase operation is interrupted, the internal part of the chip knows which memory units execute the erase operation, so that the over-erase units can be quickly found (all the memory units in the chip are not needed to be judged, and only the memory units executing the erase operation need to be judged), so that the time consumption is shorter, and the efficiency is higher.

As shown in fig. 4, an apparatus for reducing the probability of a read error after power failure includes:

the receiving module 101 receives erasure instruction information;

the erasing module 102 is used for executing erasing operation on the memory unit in the chip according to the erasing instruction information;

the judging module 103 judges whether the chip has abnormal power failure,

the state holding module 104 does not change the current operating state of the chip;

an interrupt initiation module 105, initiates power-off interrupt protection,

and the over-erasing repair module 106 is used for finishing the erasing operation of the chip according to the power-off interrupt protection and executing over-erasing repair on the storage unit in the chip according to the erasing instruction information.

In some embodiments, the determining module 103 is implemented by a voltage detecting module.

In some embodiments, the erase module 102 and the over-erase repair module 106 are implemented by an algorithm module inside the chip.

When an instruction sent by a user for erasing a certain sector in a chip is received, an internal algorithm module executes an erasing step, if abnormal power failure occurs at the moment, a power failure protection module sends power failure protection interruption to the internal algorithm module of the chip, NOR Flash immediately responds to the interruption, the erasing is finished, and an over-erasing repair stage is entered; if the power failure is slow power failure, discharging the voltage pump to 0V (even if the voltage applied to the storage unit in the chip is reduced to 0) after the over-erase repair is finished, and exiting the over-erase repair algorithm flow; when the NOR FLASH power supply is restored again, the correctness of data reading of the selected unit cannot be influenced because the over-erasing unit is repaired.

Referring to fig. 5, an embodiment of the present invention further provides a terminal. As shown, the terminal 300 includes a processor 301 and a memory 302. The processor 301 is electrically connected to the memory 302. The processor 301 is a control center of the terminal 300, connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or calling a computer program stored in the memory 302 and calling data stored in the memory 302, thereby performing overall monitoring of the terminal 300.

In this embodiment, the processor 301 in the terminal 300 loads instructions corresponding to one or more processes of the computer program into the memory 302 according to the following steps, and the processor 301 runs the computer program stored in the memory 302, so as to implement various functions: receiving erasing instruction information; executing erasing operation on a storage unit in the chip according to the erasing instruction information; judging whether the chip has abnormal power failure or not, and if not, not changing the current operation state of the chip; if so, starting power-off interrupt protection, finishing the erasing operation of the chip according to the power-off interrupt protection, and performing over-erasing repair on the storage unit in the chip according to the erasing instruction information.

Memory 302 may be used to store computer programs and data. The memory 302 stores computer programs containing instructions executable in the processor. The computer program may constitute various functional modules. The processor 301 executes various functional applications and data processing by calling a computer program stored in the memory 302.

An embodiment of the present application provides a storage medium, and when being executed by a processor, the computer program performs a method in any optional implementation manner of the foregoing embodiment to implement the following functions: receiving erasing instruction information; executing erasing operation on a storage unit in the chip according to the erasing instruction information; judging whether the chip has abnormal power failure or not, and if not, not changing the current operation state of the chip; if so, starting power-off interrupt protection, finishing the erasing operation of the chip according to the power-off interrupt protection, and performing over-erasing repair on the storage unit in the chip according to the erasing instruction information. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.