阅读说明：本技术 存储器件及其编程方法 (Memory device and programming method thereof ) 是由 刘红涛 黄莹 魏文喆 蒋颂敏 黄德佳 陈文强 于 2020-04-29 设计创作，主要内容包括：公开了一种用于存储器件的编程方法。所述编程方法包括在针对第一字线的精细编程操作之前,使处于浅能级的多个第一电荷载流子移动到衬底层中的沟道,其中,处于浅能级的多个第一电荷载流子对应于要被编程的存储单元。(A programming method for a memory device is disclosed. The programming method includes moving a plurality of first charge carriers at a shallow energy level to a channel in a substrate layer prior to a fine programming operation for a first word line, wherein the plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed.)

1. A programming method for a memory device, the programming method comprising:

prior to a fine programming operation for a first word line, moving a plurality of first charge carriers at a shallow energy level to a channel in a substrate layer, wherein the plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed.

2. The programming method of claim 1, wherein:

moving the plurality of first charge carriers at the shallow energy level to the channel in the substrate layer immediately after a coarse programming operation for the first word line; or

Moving the plurality of first charge carriers at the shallow energy level to the channel in the substrate layer immediately after a coarse programming operation for a second word line immediately adjacent to the first word line.

3. The programming method of claim 1, wherein the plurality of first charge carriers at the shallow energy level are moved from a tunneling layer to the channel in the substrate layer.

4. The programming method of claim 1, wherein the plurality of first charge carriers at the shallow energy level are moved to the channel in the substrate layer as a result of an electric field applied to the memory cell.

5. The programming method of claim 4, wherein a plurality of second charge carriers at deep energy levels are inhibited from migrating to the channel in the substrate layer and are trapped in a storage layer when the electric field is appropriately controlled.

6. The programming method of claim 1, wherein:

at least one selected word line is grounded,

the plurality of bit lines are grounded and,

the common source line is connected to ground,

the well of the substrate layer is grounded,

a plurality of the selection units are turned off,

applying a first non-zero voltage to at least one unselected word line, an

Applying a second non-zero voltage to the plurality of dummy lines to move the plurality of first charge carriers at the shallow energy level to the channel in the substrate layer.

7. The programming method of claim 6, wherein the first non-zero voltage is greater than 0 volts but lower than a voltage of a programming pulse, and the second non-zero voltage is greater than 0 volts but lower than the first non-zero voltage.

8. The programming method of claim 1, wherein:

the plurality of bit lines are floating and,

the common source line is floating and,

the plurality of ground select lines are floating,

the plurality of string selection lines are floating,

at least one of the unselected word lines is floating,

the plurality of dummy lines are floating and,

at least one selected word line is grounded, and

applying a third non-zero voltage to a well of the substrate layer, thereby moving the plurality of first charge carriers at the shallow energy level to the channel in the substrate layer.

9. The programming method of claim 8, wherein the third non-zero voltage is greater than 0 volts but lower than the voltage of the programming pulse.

10. The programming method of claim 1, wherein at least one selected word line is grounded and a channel potential of the memory cell to be programmed is higher than 0 volts, thereby causing the plurality of first charge carriers at the shallow energy level to move to the channel in the substrate layer.

11. A memory device, comprising:

a plurality of memory cells;

a voltage generation circuit configured to generate a plurality of voltages applied to at least the plurality of memory cells according to a plurality of control signals; and

a control circuit configured to generate the plurality of control signals for the voltage generation circuit according to a programming method, wherein the programming method includes:

prior to a fine programming operation for a first word line, moving charge carriers at a shallow energy level to a channel in a substrate layer, wherein the plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed.

12. The storage device of claim 11, wherein:

moving the plurality of first charge carriers at the shallow energy level to the channel in the substrate layer immediately after a coarse programming operation for the first word line; or

Moving the plurality of first charge carriers at the shallow energy level to the channel in the substrate layer immediately after a coarse programming operation for a second word line immediately adjacent to the first word line.

13. The memory device of claim 11, wherein the plurality of first charge carriers at the shallow energy level are moved from a tunneling layer to the channel in the substrate layer.

14. The memory device of claim 11, wherein the plurality of first charge carriers at the shallow energy level are moved to the channel in the substrate layer as a result of an electric field applied to the memory cell.

15. The memory device of claim 14, wherein a plurality of second charge carriers at deep energy levels are inhibited from migrating to the channel in the substrate layer and are trapped in the storage layer when the electric field is appropriately controlled.

16. The storage device of claim 11, wherein:

at least one selected word line is grounded,

the plurality of bit lines are grounded and,

the common source line is connected to ground,

the well of the substrate layer is grounded,

a plurality of the selection units are turned off,

applying a first non-zero voltage to at least one unselected word line, an

Applying a second non-zero voltage to the plurality of dummy lines to move the plurality of first charge carriers at the shallow energy level to the channel in the substrate layer.

17. The memory device of claim 16, wherein the first non-zero voltage is greater than 0 volts but lower than a voltage of a programming pulse, and the second non-zero voltage is greater than 0 volts but lower than the first non-zero voltage.

18. The storage device of claim 11, wherein:

the plurality of bit lines are floating and,

the common source line is floating and,

the plurality of ground select lines are floating,

the plurality of string selection lines are floating,

at least one of the unselected word lines is floating,

the plurality of dummy lines are floating and,

at least one selected word line is grounded, and

applying a third non-zero voltage to a well of the substrate layer, thereby moving the plurality of first charge carriers at the shallow energy level to the channel in the substrate layer.

19. The memory device of claim 18, wherein the third non-zero voltage is greater than 0 volts but less than the voltage of the programming pulse.

20. The memory device of claim 11, wherein at least one selected word line is grounded and a channel potential of the memory cell to be programmed is higher than 0 volts, thereby causing the plurality of first charge carriers at the shallow energy level to move to the channel in the substrate layer.

Technical Field

The present invention relates to a memory device and a programming method thereof, and more particularly, to a memory device having higher reliability and programming quality and a programming method thereof.

Background

In recent years, the field of semiconductor memories has received increasing attention. Semiconductor memories may be volatile or non-volatile. Nonvolatile semiconductor memory devices can hold data even when power is not supplied, and are therefore widely used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

A multi-step programming operation may be undertaken to make the threshold voltage distribution of the data values to be stored less wide. In a multi-step programming operation, a coarse programming operation may be performed before a fine programming operation. The coarse programming operation may form a (rough) threshold voltage distribution. The fine programming operation can finely narrow the (rough) threshold voltage distribution formed by the coarse programming operation. However, undesired redistribution or recombination of charge carriers (e.g., movement of charge carriers at shallow energy levels to the channel) may distort the (completed) threshold voltage distribution, resulting in a threshold voltage shift effect.

Accordingly, it is desirable to provide a memory device and a programming method thereof that prevent a threshold voltage shift effect after a fine programming operation, thereby improving reliability and programming quality.

Disclosure of Invention

It is therefore an object of the present invention to provide a memory device and associated programming method to improve reliability and programming quality.

The invention discloses a programming method for a memory device. The programming method includes moving a plurality of first charge carriers at a shallow energy level to a channel in a substrate layer prior to a fine programming operation for a first word line, wherein the plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed.

The invention also discloses a memory device. The memory device includes a plurality of memory cells, a voltage generation circuit, and a control circuit. The voltage generation circuit is configured to generate a plurality of voltages applied to at least the plurality of memory cells according to a plurality of control signals. The control circuit is configured to generate a plurality of control signals for the voltage generation circuit according to a programming method. The programming method includes moving charge carriers at a shallow energy level to a channel in a substrate layer prior to a fine programming operation for a first word line, wherein a plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed.

These and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments, which are illustrated in the various drawing figures and drawings.

Drawings

FIG. 1 is a schematic diagram illustrating a cross-sectional view of a string in accordance with an embodiment of the present invention.

Fig. 2 is a schematic diagram showing an equivalent circuit of the string shown in fig. 1.

FIG. 3 is a flow chart of a programming method for programming memory cells of the string shown in FIG. 1, according to an embodiment of the present invention.

Fig. 4 and 5 are schematic diagrams each showing four threshold voltage distributions of states according to an embodiment of the present invention.

Fig. 6 is a schematic diagram showing a cross-sectional view of the string shown in fig. 1 and a channel potential profile (for presenting a potential with respect to position) in a channel of the substrate layer.

FIG. 7 shows a schematic diagram of a NAND architecture memory, according to an embodiment of the invention.

Fig. 8 and 9 are signal diagrams for a programming method of the memory shown in fig. 7.

Fig. 10 is a schematic diagram showing a comparison between threshold voltage distributions just after programming, threshold voltage distributions after a period of time of programming using a conventional programming method, and threshold voltage distributions after a period of time of programming using a new programming method with a charge redistribution step according to an embodiment of the present invention.

FIG. 11 is a functional block diagram of a memory device according to an embodiment of the present invention.

Detailed Description

The present invention aims to avoid the undesirable redistribution or recombination of charge carriers (electrons and/or holes) at shallow energy levels that may occur after a fine programming operation to improve reliability and programming quality. For example, redistribution or recombination of charge carriers at shallow energy levels may be intentionally triggered prior to a fine programming operation.

Fig. 1 is a schematic diagram showing a cross-sectional view of a string ST1 according to an embodiment of the present invention. Fig. 2 is a schematic diagram showing an equivalent circuit of the string ST1 shown in fig. 1. The string ST1 may be a NAND string for a flash memory of a NAND structure. The string ST1 shown in fig. 1 and 2 includes a selection cell SST1, GST1, a plurality of dummy cells DC1a, DC1b, and a plurality of memory cells MC1a, MC1b, MC1 c. The series-connected selection cells SST1, GST1, dummy cells DC1a, DC1b, and memory cells MC1a to MC1c include gates Gt, Gb, control gates CGda, CGdb, CGa, CGb, CGc, a memory layer FG, a barrier layer BKL, a tunneling layer TNL, and a substrate layer SBL, respectively. The selection unit SST1 is configured to connect the string ST1 to the bit line BL1, and the selection unit SST1 may be controlled by applying an appropriate voltage to the string selection line SSL 1. The selection cell GST1 is configured to connect the string ST1 to the common source line CSL, and the selection cell GST1 may be controlled by applying an appropriate voltage to the ground selection line GSL 1. Each of the control gates CGda, CGdb of the dummy cells DC1a, DC1b is connected to one of a plurality of dummy lines WLda, WLdb, respectively. Each of the control gates CGa-CGc of the memory cells MC1a, MC1b, MC1c is connected to one of a plurality of word lines WLa, WLb, WLc, respectively.

Basically, the charge carriers in string ST1 after programming may redistribute and leak over time. For example, as shown in fig. 1, just after programming, some charge carriers at shallow energy levels (also referred to as first charge carriers) that may be trapped in the tunneling layer TNL may migrate to the channel created between the source and drain terminals in the substrate layer SBL, and the charge carriers (in the tunneling layer TNL) may be quickly lost. Redistribution or recombination of charge (i.e., rapid charge carrier loss) can lead to threshold voltage shift effects that will shift or widen the (completed) threshold voltage distribution of each state, or shrink the read margin between two adjacent states. The narrower the read margin between two adjacent states, the more difficult it is to clearly distinguish the two adjacent states from each other. A memory cell (e.g., memory cell MC1b) that has been verified to have been properly programmed (or erased) may experience a threshold voltage shift effect that will radically change the programmed (or erased) state of the memory cell.

Charge redistribution may distort and distort the (completed) threshold voltage distribution, resulting in threshold voltage shift effects; however, the threshold voltage shift effect on the (completed) threshold voltage distribution can be reduced or eliminated by manipulating the timing of the charge redistribution. For example, FIG. 3 is a flowchart of a programming method 30 for programming a memory cell (e.g., memory cell MC1b) of string ST1 shown in FIG. 1, according to an embodiment of the invention. The programming method 30 may be compiled into program code. The method 30 may be performed by a control circuit (e.g., the control circuit 120 shown in fig. 11) and may include the steps of:

step S300: and starting.

Step S302: prior to a fine programming operation for the first word line, a plurality of first charge carriers at a shallow energy level are moved to a channel in the substrate layer SBL, wherein the plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed.

Step S304: and (6) ending.

In short, prior to the fine programming operation, charge carriers at a shallow energy level corresponding to a memory cell to be programmed (e.g., memory cell MC1b) are caused to migrate to the channel in substrate layer SBL, thereby avoiding undesirable redistribution or recombination of charge carriers after the fine programming operation. The present invention provides a satisfactory threshold voltage distribution by means of a charge redistribution step performed in step S302 prior to the fine programming operation. Thus, reliability and programming quality can be improved.

Specifically, the memory cell (e.g., memory cell MC1b) may be programmed in a multi-step programming operation. In a multi-step programming operation, a coarse programming operation may be performed before a fine programming operation. In step S302, a charge redistribution step may be performed prior to the fine programming operation for the word line corresponding to the memory cell to be programmed (e.g., word line WLb), thereby moving the charge carriers at the shallow energy level back to the channel in the substrate layer SBL. In this way, there are few charge carriers at the shallow energy level after the fine programming operation. Therefore, after the fine programming operation, the threshold voltage shift effect caused by the redistribution of the charge carriers at the shallow energy level rarely occurs.

In some embodiments, the charge redistribution step may be performed immediately after the coarse programming operation for a word line (e.g., word line WLb) and before the fine programming operation for that word line (i.e., word line WLb). In other words, charge carriers at a shallow energy level can be moved to a channel in the substrate layer SBL immediately after the coarse programming operation for the word line. For example, FIG. 4 shows a schematic diagram of four threshold voltage distributions for a state to be programmed, according to an embodiment of the present invention. Each of the four threshold voltage distributions has one distribution curve corresponding to the same state but representing different steps from each other. In FIG. 4, a distribution curve VD402 of the state of the memory cell is formed after the coarse programming operation for the word line (e.g., word line WLb). After the charge redistribution step (e.g., step S302), a distribution curve VD404 of the state of the memory cell is formed. After another coarse programming operation for the next word line (e.g., word line WLc), a distribution curve VD406 for that state of the memory cell is formed. After the fine programming operation on the previous word line (i.e., word line WLb), a distribution curve VD408 of the state of the memory cell is formed.

As shown in fig. 4, the width of the profile VD404 is wider than the width of the profile VD402, while the width of the profile VD408 is narrower than the width of the profile VD404 (and the width of the profile VD 402). As the profile VD404 of this state expands towards another profile of another state due to charge redistribution, the distinction between two successive states becomes increasingly difficult. For data reading, the widened distribution curve VD404 may be unacceptable, especially when the read margin between two adjacent states is small. On the other hand, the charge carriers at the shallow energy level are moved to the channel in the substrate layer SBL before the fine programming operation, and thus the distribution curve VD408 formed after the fine programming operation is not distorted by the charge redistribution. To improve reliability, it is desirable to narrow the various distribution curves in the threshold voltage distribution, because a narrower distribution curve brings a wider read margin (i.e., the distance between two adjacent states). Since the width of the distribution curve VD408 is and remains narrow, the distribution curve VD408 for that state can remain farther away from another distribution curve for another state, which improves read margin and ensures read accuracy for the state from the memory cell.

It is to be noted that various changes and modifications can be easily made by those skilled in the art. In some embodiments, the charge redistribution step may be performed immediately prior to the fine programming operation for a word line (e.g., word line WLb) and after the coarse programming operation for the next word line (i.e., word line WLc). In other words, the charge carriers at the shallow energy level can be moved to the channel in the substrate layer SBL immediately after the coarse programming operation for the next word line. For example, FIG. 5 shows a schematic diagram of four threshold voltage distributions in accordance with an embodiment of the present invention. Each of the four threshold voltage distributions has one distribution curve corresponding to the same state but representing different steps from each other. In FIG. 5, after a coarse programming operation for a word line (e.g., word line WLb), a distribution curve VD502 for that state of the memory cell is formed. After another coarse programming operation for the next word line (e.g., word line WLc), a distribution curve VD504 of that state of the memory cell is formed. After the charge redistribution step (e.g., step S302), a distribution curve VD506 of the state of the memory cell is formed. After the fine programming operation on the previous word line (i.e., word line WLb), a distribution curve VD508 of the state of the memory cell is formed.

As shown in fig. 5, the width of the profile VD506 is wider than the width of the profile VD502, while the width of the profile VD508 is narrower than the width of the profile VD506 (and the width of the profile VD 502). As the profile VD506 of this state expands towards another profile of another state due to charge redistribution, the distinction between two successive states becomes increasingly difficult. For data reading, the widened distribution curve VD506 may be unacceptable, especially when the read margin between two adjacent states is small. On the other hand, the charge carriers at the shallow energy level are moved to the channel in the substrate layer SBL before the fine programming operation, and thus the distribution curve VD508 formed after the fine programming operation is not distorted by the charge redistribution. To improve reliability, it is desirable to narrow the various distribution curves in the threshold voltage distribution, because a narrower distribution curve brings a wider read margin (i.e., the distance between two adjacent states). Since the width of the distribution curve VD508 is and remains narrow, the distribution curve VD508 for that state remains far from another distribution curve for another state, which improves the read margin and ensures read accuracy for the state from the memory cell.

The electric field can accelerate charge redistribution. Thus, the charge redistribution step in step S302 may be performed by applying an electric field in some embodiments. For example, fig. 6 is a schematic diagram showing a cross-sectional view of the string ST1 shown in fig. 1 and a channel potential distribution (for presenting a potential with respect to a position) in the channel of the substrate layer SBL. As shown in fig. 6, an electric field E1 is applied to the string ST 1. As a result of the applied electric field E1, charge carriers at shallow energy levels (e.g., charge carriers in the tunneling layer TNL) may move. The direction of the electric field E1 is considered to be the direction of the force it exerts on the positive charge carriers. Accordingly, the electric field E1 forces negative charge carriers to flow (e.g., from the tunneling layer TNL) toward the channel created between the source and drain terminals in the substrate layer SBL. On the other hand, if the magnitude of the electric field E1 is appropriately controlled, the charge carriers at the deep energy level (also referred to as second charge carriers) that may be trapped in the storage layer FG may not be affected and exhibit any change, so that data stored in the memory cell (e.g., the memory cell MC1b) is not lost.

Electric field E1 may be created by applying a voltage to string ST1 to accelerate charge redistribution. For example, please refer to fig. 6 to 8. FIG. 7 shows a schematic diagram of a NAND architecture memory 70, according to an embodiment of the invention. Fig. 8 shows a signal diagram of a programming method (e.g., programming method 30) for memory 70 shown in fig. 7.

As shown in fig. 7, the memory 70 includes a plurality of strings, such as a string ST1 and strings ST2 to ST 4. Like the string ST1 shown in fig. 1, each of the strings ST2 to ST4 shown in fig. 7 may include, but is not limited to, two selection cells, two dummy cells, and three memory cells, which are respectively connected in series and respectively extend vertically above the substrate layer SBL. The select cells disposed on top of the strings ST2 to ST4 are configured to connect the strings ST2 to ST4 to the bit lines BL1, BL2 (described), and the select cells disposed on top of the strings ST2 to ST4 may be controlled by applying appropriate voltages to the string select lines SSL1, SSL2 (described), respectively. The selection cells disposed at the bottom of the strings ST2 to ST4 are configured to connect the strings ST2 to ST4 to the common source line CSL, and the selection cells disposed at the bottom of the strings ST2 to ST4 may be controlled by applying appropriate voltages to the ground selection lines GSL1, GSL2 (described above), respectively. The control gates of the dummy cells in strings ST 2-ST 4 are connected to dummy lines WLda, WLdb, respectively. The control gates of the memory cells in strings ST 2-ST 4 are connected to word lines WLa, WLb, WLc, respectively. Typically, the bit lines BL1, BL2 extend in a direction perpendicular to the word lines WLa, WLb, WLc on top of the strings ST1 to ST 4.

Those skilled in the art will recognize that 2-dimensional planar storage structures, 3-dimensional stacked structures, NAND flash storage structures, and/or NOR flash storage structures may be implemented in the memory 70. Further, fig. 1, 2, 6, and 7 show three memory cells in the string ST1 for the purpose of illustration. In other embodiments, a string may include more storage units. The number of memory cells in a string does not limit the scope of the invention. In addition, the memory cells (e.g., the memory cells MC1a to MC1c) in the strings ST1 to ST4 may be floating gate transistors or charge trap transistors. Each memory cell may store 1-bit data or two or more bits of data, and thus may have a Single Level Cell (SLC) type, a multi-level cell (MLC) type, a three-level cell (TLC) type, a four-level cell (QLC) type, or a higher level type. Each memory cell may retain one of Q possible states, where Q is a positive integer equal to or greater than 2, typically Q-2 for SLC, 4 for MLC, 8 for TLC, and 16 for QLC.

A multi-step programming operation can be used to program a memory cell into a target programmed state (also referred to as a programmed state). The multi-step programming operation involves a sequence that begins at an initial programming level and proceeds to a target programming level until the threshold voltage of a selected memory cell (e.g., memory cell MC1b) reaches a corresponding verify voltage level for the target program state. During either the coarse programming operation or the fine programming operation, a program pulse (e.g., 20 volts) may be applied to the selected word line (e.g., word line WLb), thereby setting the selected memory cell (e.g., memory cell MC1b) corresponding to the selected word line to a respective target program state. The unselected word line(s) (e.g., word lines WLa, WLc) are subjected to a voltage of, for example, 10 volts. Also, a turn-on voltage (e.g., 1.5 volts or 3 volts) may be applied to a string selection line (e.g., string selection line SSL1) to turn on a corresponding selection cell (e.g., selection cell SST1), and a turn-off voltage (e.g., 0 volts) may be applied to a ground selection line (e.g., ground selection line GSL1) to turn off the corresponding selection cell (e.g., selection cell GST 1). In programming a selected memory cell, a ground voltage (e.g., 0 volts) may be applied to the selected bit line (e.g., bit line BL1) corresponding to the selected memory cell, while a supply voltage (e.g., 1.5 volts or 3 volts) may be applied to the unselected bit line(s) (e.g., bit line BL2) corresponding to the unselected cell(s). As a result, charge carriers may be injected into the storage layer FG (or sometimes into the tunneling layer TNL). When charge carriers are accumulated in the storage layer FG, the threshold voltage of the selected memory cell is raised so that the selected memory cell is in a programmed state.

As shown in fig. 7 and 8, during the charge redistribution step performed in step S302, the applied voltage is varied to create the channel potential distribution shown in fig. 6, thereby generating an electric field E1. As shown in fig. 8, an off voltage may be applied to the ground selection lines GSL1, GSL2 and the string selection lines SSL1, SSL2, thereby turning off the selection cells GST1, GST2, SST1, and SST2 to perform a charge redistribution step. A ground voltage may be applied to the bit lines BL1, BL2 and the common source line CSL such that the bit lines BL1, BL2 and the common source line CSL are grounded. The well (not shown) of the substrate layer SBL is subjected to a voltage of, for example, 0 volt and is thus also grounded. The voltage applied to the selected word line (e.g., word line WLb) corresponding to the selected memory cell (i.e., memory cell MC1b) is approximately 0 volts because the selected word line is grounded. The voltage applied to the unselected word line(s) (e.g., word lines WLa, WLc) corresponding to the unselected memory cell(s) (e.g., memory cells MC1a, MC1c) may reach (or increase to) a first non-zero voltage V1. The first non-zero voltage V1 may be in the range of 5 volts to 10 volts. The first non-zero voltage V1 may be greater than 0 volts, but lower than the voltage of the programming pulse. The voltage applied to the dummy lines WLda, WLdb of the dummy cells (e.g., dummy cells DC1a, DC1b) corresponding to the strings ST 1-ST 4 may reach (or increase to) a second non-zero voltage V2. The second non-zero voltage V2 may be in the range of 0 volts to 5 volts. The second non-zero voltage V2 may be greater than 0 volts, but lower than the first non-zero voltage V1.

During the charge redistribution step, the channels in the substrate layer SBL are floating, since the select cells GST1, GST2, SST1, SST2 of all strings (e.g., strings ST1 to ST4) are turned off. The voltages applied to the dummy lines WLda, WLdb and the unselected word lines WLa, WLc are non-zero, which will increase the channel potential of the dummy cells DC1a, DC1b and the unselected memory cells MC1a, MC1 c. As shown in fig. 6, the channel potential of the memory cell MC1a at the position Pga or the channel potential of the memory cell MC1c at the position Pgc is higher than the channel potential at the position Pt or Pb. In some embodiments, the channel potential at the position Pga or Pgc is higher than the channel potential at the position Pgda or Pgdb, and the channel potential at the position Pgda or Pgdb is higher than the channel potential at the position Pt or Pb. In some embodiments, the channel potential at location Pgda or Pgdb is lower than the voltage applied to dummy line WLda or WLdb, and the channel potential at location Pga or Pgc is lower than the voltage applied to unselected word lines WLa or WLc.

Although the voltage applied to the selected word line WLb corresponding to the selected memory cell MC1b is equal to 0 volts, the channel potential of memory cell MC1b at location Pgb may be higher than 0 volts. This is because the equivalent channels of the dummy cells DC1a, DC1b and the unselected memory cells MC1a, MC1c are connected to the equivalent channel of the selected memory cell MC1b — more specifically, the channel in the substrate layer SBL is continuous. Accordingly, the channel potentials of dummy cells DC1a, DC1b and unselected memory cells MC1a, MC1c may cause the channel potential of selected memory cell MC1b at location Pgb to be non-zero. In some embodiments, the channel potential at position Pgb is lower than the channel potential at positions Pga, Pgc, Pgda, or Pgdb, but higher than 0 volts, as a result of the channel potential at position Pgb being pulled up by the adjacent channel potential at position Pga or Pgc. In this way, an electric field E1 (and potentially lateral electric fields E2 and E3) is induced that points from the channel in the substrate layer SBL to the tunneling layer TNL, accelerating the movement of charge carriers at shallow energy levels to the channel.

It is noted that the first non-zero voltage V1 for the unselected word lines WLa, WLc and the second non-zero voltage V2 for the dummy lines WLda, WLdb may be determined and optimized from experimental data or simulation results so that charge carriers at deep energy levels may not migrate to channels in the substrate layer SBL as charge carriers at shallow energy levels. That is, when the electric field E1 is appropriately controlled, the charge carriers at the deep level are inhibited from migrating to the channel in the substrate layer SBL. Charge carriers at deep energy levels may remain and still be trapped in the storage layer FG. Therefore, the data stored in memory cell MC1b will not be lost or erased. To further understand, the shallow energy level is close to (the band edge of) the conduction band, e.g., the energy difference relative to the conduction band edge is less than kBT (boltzmann constant times temperature). Deep energy levels in semiconductors generally describe energy levels that are further away from the conduction or valence band and have a much larger energy difference than kBT. The deep level may be near the center of the bandgap.

As set forth above, prior to the fine programming operation, a charge redistribution step is performed to rapidly move charge carriers at a shallow level to a channel in the substrate layer SBL in the case where the voltage applied to the selected word line WLb corresponding to the selected memory cell MC1b is close to 0 volts and the channel potential of the selected memory cell MC1b is higher than 0 volts. Since the distribution curves assigned to each state (e.g., distribution curve VD408 or VD508) in the (completed) threshold voltage distribution must be made narrower and more closely packed as the number of states stored on each memory cell increases, programming of the selected memory cells must be performed with improved accuracy and the extent of any post-shifts in the (completed) threshold voltage distribution that can be tolerated is reduced. According to the present invention, there are few charge carriers at a shallow energy level after the fine programming operation; therefore, the threshold voltage shift effect caused by the redistribution of charge carriers at shallow energy levels rarely occurs after the fine programming operation. Reliability and programming quality can thus be improved by means of a charge redistribution step performed prior to the fine programming operation.

Alternatively, electric field E1 may be created by applying a voltage to string ST1 as an erase operation to accelerate charge redistribution. For example, please refer to fig. 7 and 9. Fig. 9 is a signal diagram of a programming method (e.g., programming method 30) for memory 70 shown in fig. 7.

As shown in fig. 7 and 9, during the charge redistribution step performed in step S302, a ground voltage may be applied on the selected word line (e.g., word line WLb) corresponding to the selected memory cell (i.e., memory cell MC1b) so that the selected word line is grounded, as shown in fig. 8. Unlike the signal diagram shown in fig. 8, the voltage applied to the well of the substrate layer SBL may reach (or increase to) a third non-zero voltage V3 during the charge redistribution step. The third non-zero voltage V3 may be in the range of 5 volts to 10 volts. The third non-zero voltage V3 may be greater than 0 volts, but lower than the voltage of the programming pulse. Further, ground select lines GSL1, GSL2, string select lines SSL1, SSL2, bit lines BL1, BL2, common source line CSL, dummy lines WLda, WLdb corresponding to dummy cells of strings ST1 through ST4 (i.e., dummy cells DC1a, DC1b), and unselected word line(s) (e.g., word lines WLa, WLc) corresponding to unselected memory cell(s) (i.e., memory cells MC1a, MC1c) are floating during the charge redistribution step. Since all of the ground select lines GSL1, GSL2, string select lines SSL1, SSL2, bit lines BL1, BL2, common source line CSL, dummy lines WLda, WLdb, and unselected word lines WLa, WLc are placed in a floating state, the corresponding elements of strings ST 1-ST 4 are also raised to a non-zero voltage, e.g., due to capacitive coupling with the well.

By raising the well to a third non-zero voltage V3 (similar to an erase voltage of 20V or less) and grounding the selected word line WLb corresponding to the selected memory cell MC1b, a tunneling layer TNL is induced from the electric field E1 towards the channel in the substrate layer SBL to accelerate the movement of charge carriers at shallow energy levels to the channel. In other words, charge carriers at shallow energy levels are "erased".

It is noted that the third non-zero voltage V3 of the well of substrate layer SBL may be determined and optimized from experimental data or simulation results such that charge carriers at deep energy levels may not migrate to a channel in substrate layer SBL as charge carriers at shallow energy levels. That is, when the electric field E1 is appropriately controlled, the charge carriers at the deep level are inhibited from migrating to the channel in the substrate layer SBL. Charge carriers at deep energy levels may remain and still be trapped in the storage layer FG. Therefore, the data stored in memory cell MC1b will not be lost or erased.

As set forth above, prior to the fine programming operation, a charge redistribution step is performed to cause charge carriers at shallow energy levels to rapidly move to channels in the substrate layer SBL if the voltage applied to the selected word line WLb corresponding to the selected memory cell MC1b is close to 0 volts and the voltage applied to the well is higher than 0 volts. Since the distribution curves assigned to each state (e.g., distribution curve VD408 or VD508) in the (completed) threshold voltage distribution must be made narrower and more closely packed as the number of states stored on each memory cell increases, programming of the selected memory cells must be performed with improved accuracy and the extent of any post-shifts in the (completed) threshold voltage distribution that can be tolerated is reduced. According to the present invention, there are few charge carriers at a shallow energy level after the fine programming operation; therefore, the threshold voltage shift effect caused by the redistribution of charge carriers at shallow energy levels rarely occurs after the fine programming operation. Reliability and programming quality can thus be improved by means of a charge redistribution step performed prior to the fine programming operation.

Fig. 10 is a schematic diagram showing a comparison between threshold voltage distributions just after programming, threshold voltage distributions after a period of time of programming using a conventional programming method, and threshold voltage distributions after a period of time of programming using a new programming method with a charge redistribution step according to an embodiment of the present invention. A threshold voltage distribution comprising the distribution curve VD1002 for that state of the programmed memory cell is formed just after programming. The threshold voltage distribution including the distribution curve VD1004 for that state is formed after a period of time has been programmed into the memory cell by the new programming method of the present invention which performs a charge redistribution step prior to the fine programming operation. The threshold voltage distribution including the distribution curve VD1006 for that state is formed after a period of time for the memory cell has been programmed by a conventional programming method without a charge redistribution step.

As shown in fig. 10, the width of the distribution curve VD1004 or the width of the distribution curve VD1006 is wider than the width of the distribution curve VD1002 because an undesired redistribution or recombination of charge carriers at shallow energy levels may cause threshold voltage shift effects and thus distort the (completed) threshold voltage distribution (i.e., the distribution curve VD 1002). Over time, the threshold voltage shift effect may even become severe. However, the width of the profile VD1004 is narrower than the width of the profile VD 1006. As the distribution curve VD1006 for that state expands due to charge redistribution towards another distribution curve for another state in the threshold voltage distribution of conventional programming methods, it becomes more difficult to distinguish between two successive states. For data reading, the widened distribution curve VD1006 may be unacceptable, especially when the read margin between two adjacent states is small. On the other hand, before the fine programming operation, the charge carriers at the shallow energy level are moved to the channels in the substrate layer SBL, and thus the charge redistribution formed even after a certain period of programming the memory cell does not cause a strong distortion to the distribution curve VD1004 in the threshold voltage distribution of the new programming method of the present invention. Since the width of the distribution curve VVD1004 is and remains narrow, the distribution curve VD1004 of the state can remain far from another distribution curve of another state, which improves the read margin and ensures the read accuracy of the state from the memory cell.

FIG. 11 is a functional block diagram of a memory device 11 according to an embodiment of the present invention. The memory device 11 includes the memory 70 shown in fig. 7, the aforementioned control circuit 120, and the voltage generation circuit 130. The control circuit 120 is configured to generate a plurality of control signals for the voltage generation circuit 130 to perform a programming operation or a charge redistribution step. The control circuit 120 may be a controller, an embedded microprocessor, or a microcontroller, etc. The voltage generation circuit 130 is coupled to the control circuit 120 and the memory 70, and the voltage generation circuit 130 is configured to generate a plurality of voltages applied to the bit lines BL1, BL2, the string selection lines SSL1, SSL2, the ground selection lines GSL1, GSL2, the word lines WLa, WLb, WLc, the dummy lines WLda, WLdb, the common source line CSL, and the wells of the substrate layer SBL (i.e., voltages applied to at least the memory cells MC1a, MC1b, MC1c) according to a control signal generated by the control circuit 120.

In summary, charge carriers at shallow energy levels corresponding to the memory cell to be programmed are made to migrate to the channel in the substrate layer prior to the fine programming operation, thereby avoiding undesirable redistribution or recombination of charge carriers after the fine programming operation. The present invention provides satisfactory threshold voltage distribution by means of a charge redistribution step performed prior to the fine programming operation. Thus, reliability and programming quality can be improved.

Those skilled in the art will readily recognize many modifications and variations that may be made to the devices and methods while following the teachings of the present invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.