Array substrate and preparation method thereof
阅读说明:本技术 阵列基板及其制备方法 (Array substrate and preparation method thereof ) 是由 *** 于 2020-06-08 设计创作,主要内容包括:本发明提供一种阵列基板及其制备方法,包括:衬底、至少一个第一薄膜晶体管以及至少一个第二薄膜晶体管。本发明通过第一刻蚀阻挡块限定了第一薄膜晶体管以及第二薄膜晶体管。并且通过将第二刻蚀阻挡块设置在有源层与第一源极之间,而第一漏级靠近所述有源层,进而缩短了第一薄膜晶体管的有效沟道,使得晶体管的迁移率和面板的像素数量可以大幅度提升。(The invention provides an array substrate and a preparation method thereof, wherein the preparation method comprises the following steps: the device comprises a substrate, at least one first thin film transistor and at least one second thin film transistor. The present invention defines a first thin film transistor and a second thin film transistor by a first etch stopper. And the second etching stop block is arranged between the active layer and the first source electrode, and the first drain electrode is close to the active layer, so that the effective channel of the first thin film transistor is shortened, and the mobility of the transistor and the pixel number of the panel can be greatly improved.)
1. An array substrate, comprising:
a substrate; and
the transistor comprises at least one first thin film transistor and at least one second thin film transistor which are arranged on the substrate in parallel, wherein the first thin film transistor is an oxide thin film transistor, and the second thin film transistor is an LTPS thin film transistor;
wherein the first thin film transistor includes:
the first grid is arranged on the substrate;
a gate insulating layer disposed on the first gate and the substrate;
an active layer disposed on the gate insulating layer;
the first drain electrode is arranged on the grid electrode insulating layer, and the first drain electrode and the active layer are prepared in the same layer;
the first etching barrier layer is arranged on the grid electrode insulating layer, and the first etching barrier block is positioned between the second thin film transistor and the first drain electrode; and
the first source electrode is arranged on the active layer.
2. The array substrate of claim 1,
the first thin film transistor further includes:
and the second etching barrier block is arranged between the active layer and the first drain electrode.
3. The array substrate of claim 2,
and preparing the second etching barrier block and the first etching barrier block in the same layer.
4. The array substrate of claim 1,
the active layer and the first drain electrode are made of indium gallium zinc oxide.
5. The array substrate of claim 1,
the second thin film transistor includes:
the second grid electrode is arranged on the substrate and is coated by the grid electrode insulating layer, and the second grid electrode and the first grid electrode are prepared on the same layer;
a polysilicon layer disposed on the gate insulating layer;
the second source level is arranged on the first etching barrier block and the polycrystalline silicon layer;
and the second drain electrode is arranged on the polycrystalline silicon layer.
6. The array substrate of claim 5,
and preparing the second source stage, the second drain stage and the first source stage in the same layer.
7. The array substrate of claim 5,
the gate insulating layer is provided with a slot, the slot extends downwards to the surface of the second gate, and the active layer is connected with the second gate through the through hole.
8. The array substrate of claim 1,
the passivation layer is arranged on the first thin film transistor and the second thin film transistor;
and the first electrode is arranged on the passivation layer and is connected with the second thin film transistor.
9. A preparation method of an array substrate is characterized by comprising the following steps:
providing a substrate;
forming a first grid and a second grid on the substrate layer;
forming a gate insulating layer on the first gate, the second gate and the substrate;
forming an active layer, a first drain and a polysilicon layer on the gate insulating layer;
forming a first etching stop block on the grid electrode insulating layer, wherein the first etching stop block is arranged between the polycrystalline silicon layer and the first drain electrode, and forming a second etching stop block on the active layer; and
and forming a first source electrode on the active layer, forming a second source electrode on the first etching barrier block and the polycrystalline silicon layer, and forming a second drain electrode on the polycrystalline silicon layer.
10. The method of manufacturing an array substrate of claim 9,
in the step of forming the active layer, the first drain and the polysilicon layer on the gate insulating layer, the method specifically includes:
forming a semiconductor layer on the gate insulating layer;
after forming a first monocrystalline silicon layer on the semiconductor layer, the semiconductor layer forms the active layer and the first drain, a second monocrystalline silicon layer is formed on the gate insulating layer, and an inducing layer is formed on the second monocrystalline silicon layer;
applying a high temperature annealing process to the active layer and the second single crystal silicon layer, the second single crystal silicon layer forming the polysilicon layer;
the inducing layer and the first single crystal silicon layer are removed.
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a preparation method thereof.
Background
Generally, the mobility of a polycrystalline silicon active layer of a thin film transistor is high, so that the leakage current (Ioff) of a low-temperature polycrystalline silicon (LTPS) thin film transistor is high, the power consumption of an LTPS substrate under low-frequency driving is high, a static black picture is difficult to well maintain, and the picture quality is poor; in addition, in order to better develop gray scales, a channel of a Driving Thin Film Transistor (DTFT) needs to be made long in the LTPS substrate, so that it is difficult to realize high resolution of the LTPS substrate (resolution means the number of pixels disposed Per Inch (PPI)).
In addition, the poly active layer has a large Hysteresis (english: hystersis), so the LTPS substrate is prone to the problem of image sticking.
The mobility of the active layer of the oxide material is low, so that the leakage current of the oxide thin film transistor is low, the power consumption of the oxide substrate under low-frequency driving is low, a static black picture can be well kept, and the picture quality is improved; in addition, in the oxide substrate, the gray scale can be better expanded without making the channel of the DTFT very long, and high PPI is realized.
In addition, the hysteresis of the oxide active layer is small, and the problem of image retention of the oxide substrate is not easy to occur; the uniformity of the oxide thin film transistor is better than that of the LTPS thin film transistor.
Therefore, it is necessary to provide an array substrate, which can use a metal oxide thin film transistor as a switching thin film transistor and an LTPS as a driving thin film transistor, and simultaneously solve the problems of resolution and low mobility of the LTPS substrate.
Disclosure of Invention
The invention aims to provide an array substrate and a preparation method thereof, and the array substrate prepared by mixing an oxide thin film transistor and a low-temperature polycrystalline silicon thin film transistor can improve the mobility of the transistor and the number of pixels of a panel.
In order to achieve the above object, an array substrate is provided, which includes: a substrate; the first thin film transistor is an oxide thin film transistor, and the second thin film transistor is an LTPS thin film transistor; wherein the first thin film transistor includes: the first grid is arranged on the substrate; a gate insulating layer disposed on the first gate and the substrate; an active layer disposed on the gate insulating layer; the first drain electrode is arranged on the grid electrode insulating layer, and the first drain electrode and the active layer are prepared in the same layer; the first etching barrier block is arranged on the grid electrode insulating layer and is positioned between the second thin film transistor and the first drain electrode; and a first source electrode disposed on the active layer.
Further, the first thin film transistor further includes: and the second etching barrier block is arranged between the active layer and the first drain electrode.
Further, the second etching barrier and the first etching barrier are prepared in the same layer.
Furthermore, the active layer and the first drain are made of indium gallium zinc oxide.
Further, the second thin film transistor includes: the second grid electrode is arranged on the substrate and is coated by the grid electrode insulating layer, and the second grid electrode and the first grid electrode are prepared on the same layer; a polysilicon layer disposed on the gate insulating layer; the second source level is arranged on the first etching barrier block and the polycrystalline silicon layer; and the second drain electrode is arranged on the polycrystalline silicon layer.
Further, the second source, the second drain and the first source are prepared in the same layer.
Furthermore, the gate insulating layer is provided with a slot, the slot extends downwards to the surface of the second gate, and the active layer is connected with the second gate through the through hole.
Further, a passivation layer is arranged on the first thin film transistor and the second thin film transistor; and the first electrode is arranged on the passivation layer and is connected with the second thin film transistor.
Another object of the present invention is to provide a method for manufacturing an array substrate, including: providing a substrate; forming a first grid and a second grid on the substrate layer; forming a gate insulating layer on the first gate, the second gate and the substrate; forming an active layer, a first drain and a polysilicon layer on the gate insulating layer; forming a first etching stop block on the grid electrode insulating layer, wherein the first etching stop block is arranged between the polycrystalline silicon layer and the first drain electrode, and forming a second etching stop block on the active layer; and forming a first source electrode on the active layer, forming a second source electrode on the first etching barrier block and the polysilicon layer, and forming a second drain electrode on the polysilicon layer.
Further, in the step of forming the active layer, the first drain and the polysilicon layer on the gate insulating layer, the method specifically includes: forming a semiconductor layer on the gate insulating layer; after forming a first monocrystalline silicon layer on the semiconductor layer, the semiconductor layer forms the active layer and the first drain, a second monocrystalline silicon layer is formed on the gate insulating layer, and an inducing layer is formed on the second monocrystalline silicon layer; applying a high temperature annealing process to the active layer and the second single crystal silicon layer, the second single crystal silicon layer forming the polysilicon layer; the inducing layer and the first single crystal silicon layer are removed.
The invention has the beneficial effects that: the invention provides an array substrate and a preparation method thereof. And the second etching stop block is arranged between the active layer and the first source electrode, and the first drain electrode is close to the active layer, so that the effective channel of the first thin film transistor is shortened, and the mobility of the transistor and the pixel number of the panel can be greatly improved.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
Fig. 1 is a schematic structural diagram of an array substrate provided by the present invention.
FIG. 2 is a partial schematic structural view of steps S1-S2 of the array substrate preparation method provided by the present invention.
Fig. 3 is a plan view of a first metal layer pattern provided by the present invention.
Fig. 4 is a partial structural schematic diagram of step S3 of the array substrate preparation method provided by the present invention.
Fig. 5 is a plan view of the gate insulation layer trenching provided by the present invention.
Fig. 6 is a partial structural schematic diagram of step S4 of the array substrate preparation method provided by the present invention.
Fig. 7 is a plan view of an active layer pattern provided by the present invention.
Fig. 8 is a partial structural schematic view of step S4 of the array substrate preparation method provided by the present invention.
Fig. 9 is a partial structural schematic view of step S4 of the array substrate preparation method provided by the present invention.
Fig. 10 is a plan view of a polysilicon layer pattern provided in the present invention.
Fig. 11 is a partial structural schematic view of step S5 of the array substrate manufacturing method provided by the present invention.
Fig. 12 is a plan view of a polysilicon layer pattern provided by the present invention.
Fig. 13 is a partial structural schematic view of step S6 of the array substrate preparation method provided by the present invention.
Fig. 14 is a plan view of a second metal layer pattern provided by the present invention.
Fig. 15 is a plan view of a passivation layer opening provided by the present invention.
Fig. 16 is a plan view of a first electrode pattern provided by the present invention.
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Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the present invention, it should be noted that unless otherwise explicitly stated or limited, the terms "integrated," "connected," and "connected" may be directly connected or indirectly connected through an intermediate, or may be a connection between two elements or an interaction relationship between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
As shown in fig. 1, the present invention provides an
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The invention provides an
The invention also provides a preparation method of the array substrate, which is used for preparing the array substrate and comprises the following steps.
S1, as shown in fig. 2, providing a
S2, referring to fig. 3, a
Specifically, 2000-5500 angstroms of metal materials are respectively deposited by using a PVD (physical vapor deposition) process, and then the
The
S3, as shown in fig. 4 and 5, a
Specifically, a silicon nitride material or a silicon oxide material is deposited by a plasma enhanced chemical vapor deposition process and patterned by a yellow light process and an etching process to obtain the
The thickness of the
S4, forming an
The steps of forming the
S401, as shown in fig. 6, a
Specifically, an IGZO oxide material is deposited by a PVD (physical vapor deposition) process, the thickness of the IGZO oxide material is 300-700 angstroms, and the
S402, referring to fig. 8, after forming the first
Since the first single
Specifically, an a-Si layer is deposited by a plasma enhanced chemical vapor deposition process, the thickness of the a-Si layer is 400-1000 angstroms, an inducing layer of 50-200 angstroms of Ni-Si alloy is deposited by PVD, and finally patterning is performed by a yellow light process and an etching process to obtain the first single
S403, using a high temperature annealing process on the
Specifically, the
S404, removing the inducing
S5, as shown in fig. 11 and 12, forming a
Specifically, silicon oxide or silicon nitride materials with the thickness of 100-2000 angstroms are deposited by a plasma enhanced chemical vapor deposition process, and then the first
Fig. 12 is a diagram of the patterns of the
S6, as shown in fig. 13 and 14, a
Specifically, 2000-5500 angstroms of metal materials are respectively deposited and formed through a PVD (physical vapor deposition) process, and then a
Fig. 14 shows the pattern of the second metal layer (M2), and the upper and lower horizontal lines are data lines. The vertical broken line shows the cross-sectional structure of fig. 1.
Finally, the opening of the passivation layer as shown in fig. 15 and the coating of the
The invention provides a preparation method of an array substrate, which comprises the steps of preparing a
The present invention has been described in detail, and the principle and the implementation of the present invention are explained by applying specific examples, and the description of the above examples is only used to help understanding the technical scheme and the core idea of the present invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
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