阅读说明：本技术 半导体器件及其形成方法 (Semiconductor device and method of forming the same ) 是由 杨柏峰 杨世海 贾汉中 王圣祯 林佑明 于 2021-03-24 设计创作，主要内容包括：选通铁电存储器单元包括：设置在衬底上方的介电材料层；金属底部电极；与底部电极的顶面接触的铁电介电层；覆盖在铁电介电层上并通过铁电介电层电容耦合到金属底部电极的柱状半导体沟道；栅极介电层,包括覆盖在铁电介电层上的水平栅极介电部分和横向围绕柱状半导体沟道的管状栅极介电部分；覆盖在水平栅极介电部分上并横向围绕管状栅极介电部分的栅电极带；以及与柱状半导体沟道的顶面接触的金属顶部电极。本申请的实施例还涉及半导体器件及其形成方法。(The gated ferroelectric memory cell includes: a layer of dielectric material disposed over the substrate; a metal bottom electrode; a ferroelectric dielectric layer in contact with the top surface of the bottom electrode; a columnar semiconductor channel overlying the ferroelectric dielectric layer and capacitively coupled to the metal bottom electrode through the ferroelectric dielectric layer; a gate dielectric layer including a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the columnar semiconductor channel; a gate electrode strip overlying the horizontal gate dielectric portion and laterally surrounding the tubular gate dielectric portion; and a metal top electrode in contact with a top surface of the columnar semiconductor channel. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.)

1. A semiconductor device, comprising:

at least one gated ferroelectric memory cell comprising:

a dielectric material layer disposed over the substrate;

a metal bottom electrode; and

a ferroelectric dielectric layer in contact with a top surface of the metal bottom electrode;

a columnar semiconductor channel overlying the ferroelectric dielectric layer and capacitively coupled to the metal bottom electrode through the ferroelectric dielectric layer;

a gate dielectric layer comprising a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the columnar semiconductor channel;

a gate strip including a horizontal gate electrode portion overlying the horizontal gate dielectric portion and a tubular gate electrode portion laterally surrounding the tubular gate dielectric portion; and

and the metal top electrode is in contact with the top surface of the columnar semiconductor channel.

2. The semiconductor device of claim 1, wherein:

the columnar semiconductor channel comprises a bottom surface in contact with a top surface of the ferroelectric dielectric layer; and

the gated ferroelectric memory cell includes a metal-ferroelectric-semiconductor (MFS) capacitor.

3. The semiconductor device of claim 1, wherein:

an intermediate metal electrode contacting a bottom surface of the columnar semiconductor channel and a top surface of the ferroelectric dielectric layer; and

the gated ferroelectric memory cell includes a metal-ferroelectric-metal (MFM) capacitor.

4. The semiconductor device according to claim 3, wherein a periphery of a top surface of the intermediate metal electrode coincides with a periphery of the bottom surface of the columnar semiconductor channel.

5. The semiconductor device of claim 1, wherein the horizontal gate dielectric portion and the tubular gate dielectric portion are connected portions of a continuously extending layer of dielectric material and have the same thickness and the same material composition.

6. The semiconductor device of claim 1, wherein said horizontal gate electrode strip portion and said tubular gate electrode strip portion are connected portions of gate electrode strip material that extend continuously and have the same material composition.

7. The semiconductor device of claim 6, wherein the tubular gate electrode strip portion comprises an annular top surface vertically spaced from the top electrode by a uniform vertical spacing.

8. The semiconductor device of claim 1, wherein an annular top surface of the tubular gate dielectric portion is located within the same horizontal plane as the top surface of the columnar semiconductor channel.

9. A semiconductor device, comprising:

at least one two-dimensional array of gated ferroelectric memory cells, wherein each of the at least one two-dimensional array of gated ferroelectric memory cells comprises:

a first metal line embedded in the first dielectric material layer and extending laterally along a first horizontal direction; and

a ferroelectric dielectric layer extending continuously over the first metal line;

a two-dimensional array of columnar semiconductor channels overlying the ferroelectric dielectric layer, wherein each row of columnar semiconductor channels is disposed along the first horizontal direction and capacitively coupled to a respective one of the first metal lines;

a gate dielectric layer comprising a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the columnar semiconductor channel;

gate electrode strips laterally surrounding respective columns of columnar semiconductor channels disposed along the second horizontal direction and laterally spaced from each other along the first horizontal direction; and

and second metal lines embedded in the second dielectric material layer, extending laterally along the first horizontal direction, and contacting top surfaces of the columnar semiconductor channels of the corresponding rows.

10. A method of forming a semiconductor device, comprising:

forming a first metal line extending in a first horizontal direction in an upper portion of the dielectric material layer;

depositing a ferroelectric dielectric layer over a top surface of the first metal line;

forming a two-dimensional array of columnar semiconductor channels over the ferroelectric dielectric layer, wherein each row of columnar semiconductor channels is formed over and capacitively coupled to a respective one of the first metal lines;

depositing a gate dielectric layer over the two-dimensional array of columnar semiconductor channels;

forming gate strips over the gate dielectric layer, wherein each gate strip laterally surrounds a respective column of columnar semiconductor channels; and

second metal lines are formed over the two-dimensional array of columnar semiconductor channels, wherein each second metal line is formed directly on a top surface of a corresponding row of columnar semiconductor channels.

Technical Field

Embodiments of the present application relate to semiconductor devices and methods of forming the same.

Background

Ferroelectric material is a material that can maintain an electrical polarization in the absence of an applied electric field. The electric polarization in the ferroelectric material has a hysteresis effect, enabling the encoding of the data bits as a direction of polarization within the ferroelectric material. In ferroelectric tunnel junction devices, a change in polarization direction causes a change in tunnel resistance, which can be used to measure the direction of electrical polarization and extract the value of the data bit stored in the ferroelectric tunnel junction.

Disclosure of Invention

Some embodiments of the present application provide a semiconductor device, including: at least one gated ferroelectric memory cell comprising: a dielectric material layer disposed over the substrate; a metal bottom electrode; and a ferroelectric dielectric layer in contact with a top surface of the metal bottom electrode; a columnar semiconductor channel overlying the ferroelectric dielectric layer and capacitively coupled to the metal bottom electrode through the ferroelectric dielectric layer; a gate dielectric layer comprising a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the columnar semiconductor channel; a gate strip including a horizontal gate electrode portion overlying the horizontal gate dielectric portion and a tubular gate electrode portion laterally surrounding the tubular gate dielectric portion; and a metal top electrode in contact with a top surface of the columnar semiconductor channel.

Other embodiments of the present application provide a semiconductor device, including: at least one two-dimensional array of gated ferroelectric memory cells, wherein each of the at least one two-dimensional array of gated ferroelectric memory cells comprises: a first metal line embedded in the first dielectric material layer and extending laterally along a first horizontal direction; and a ferroelectric dielectric layer extending continuously over the first metal line; a two-dimensional array of columnar semiconductor channels overlying the ferroelectric dielectric layer, wherein each row of columnar semiconductor channels is disposed along the first horizontal direction and capacitively coupled to a respective one of the first metal lines; a gate dielectric layer comprising a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the columnar semiconductor channel; gate electrode strips laterally surrounding respective columns of columnar semiconductor channels disposed along the second horizontal direction and laterally spaced from each other along the first horizontal direction; and a second metal line embedded in the second dielectric material layer, extending laterally along the first horizontal direction, and contacting top surfaces of the columnar semiconductor channels of the corresponding row.

Still further embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a first metal line extending in a first horizontal direction in an upper portion of the dielectric material layer; depositing a ferroelectric dielectric layer over a top surface of the first metal line; forming a two-dimensional array of columnar semiconductor channels over the ferroelectric dielectric layer, wherein each row of columnar semiconductor channels is formed over and capacitively coupled to a respective one of the first metal lines; depositing a gate dielectric layer over the two-dimensional array of columnar semiconductor channels; forming gate strips over the gate dielectric layer, wherein each gate strip laterally surrounds a respective column of columnar semiconductor channels; and forming second metal lines over the two-dimensional array of columnar semiconductor channels, wherein each second metal line is formed directly on a top surface of a corresponding row of columnar semiconductor channels.

Drawings

Embodiments of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A is a vertical cross-sectional view of an exemplary structure after forming complementary metal-oxide-semiconductor (CMOS) transistors, metal interconnect structures embedded in a layer of dielectric material, and a layer of dielectric material connecting via-levels (c-via-level) in accordance with an embodiment of the present disclosure.

Fig. 1B is a vertical cross-sectional view of a first example structure during formation of a fin backside gate field effect transistor array in accordance with an embodiment of the present disclosure.

Fig. 1C is a vertical cross-sectional view of the first exemplary structure after forming an upper level metal interconnect structure according to an embodiment of the present disclosure.

Fig. 2A is a horizontal cross-sectional view of an exemplary structure after etching and patterning a first metal line trench in a first dielectric material layer, according to an embodiment of the present disclosure.

Fig. 2B is a vertical cross-sectional view of an exemplary structure along plane B-B' of fig. 2A.

Fig. 2C is a vertical cross-sectional view of an exemplary structure along plane a-a' of fig. 2A.

Fig. 3A is a horizontal cross-sectional view of an example structure after depositing and planarizing a conductive metal material in a first metal line trench to form a first metal line, according to an embodiment of the present disclosure.

Fig. 3B is a vertical cross-sectional view of an exemplary structure along plane B-B' of fig. 3A.

Fig. 3C is a vertical cross-sectional view of an exemplary structure along plane a-a' of fig. 3A.

Figure 4A is a vertical cross-sectional view of an example structure along a first horizontal direction hd1 (i.e., plane B-B') after depositing a plurality of layers including a ferroelectric dielectric layer and a semiconductor channel material layer on a first metal line and a substrate according to an embodiment of this disclosure.

Figure 4B is a vertical cross-sectional view of an example structure along a second horizontal direction hd2 (i.e., plane a-a') after depositing a plurality of layers including a ferroelectric dielectric layer and a semiconductor channel material layer over a first metal line and a substrate according to an embodiment of this disclosure.

Fig. 5A is a vertical cross-sectional view of an exemplary structure along a first horizontal direction hd1 (i.e., plane B-B') after etching and patterning a pillar-shaped semiconductor channel of a gated ferroelectric memory cell according to an embodiment of the present disclosure.

Fig. 5B is a vertical cross-sectional view of an exemplary structure along the second horizontal direction hd2 (i.e., plane a-a') after etching and patterning a pillar-shaped semiconductor channel of a gated ferroelectric memory cell according to an embodiment of the present disclosure.

Fig. 6A is a vertical cross-sectional view of an exemplary structure along a first horizontal direction hd1 (i.e., plane B-B') after depositing a gate dielectric layer over a formed pillar-shaped semiconductor channel of a gated ferroelectric memory cell in accordance with an embodiment of the present disclosure.

Fig. 6B is a vertical cross-sectional view of an exemplary structure along a second horizontal direction hd2 (i.e., plane a-a') after depositing a gate dielectric layer over the formed pillar-shaped semiconductor channel of a gated ferroelectric memory cell in accordance with an embodiment of the present disclosure.

Fig. 7A is a vertical cross-sectional view of an exemplary structure along a first horizontal direction hd1 (i.e., plane B-B') after depositing a layer of conductive metallic material over the formed columnar semiconductor channel and gate dielectric layer of a gated ferroelectric memory cell in accordance with an embodiment of the present disclosure.

Fig. 7B is a vertical cross-sectional view of an exemplary structure along a second horizontal direction hd2 (i.e., plane a-a') after depositing a layer of conductive metallic material over the formed columnar semiconductor channel and gate dielectric layer of a gated ferroelectric memory cell in accordance with an embodiment of the present disclosure.

Fig. 8A is a vertical cross-sectional view of an example structure along a first horizontal direction hd1 (i.e., plane B-B') after patterning a layer of conductive metal material to form word lines and gate electrodes for gated ferroelectric memory cells in accordance with an embodiment of the present disclosure.

Fig. 8B is a vertical cross-sectional view of an example structure along a second horizontal direction hd2 (i.e., plane a-a') after patterning a layer of conductive metal material to form word lines and gate electrodes for gated ferroelectric memory cells, according to an embodiment of the present disclosure.

Fig. 9A is a vertical cross-sectional view of an example structure along a first horizontal direction hd1 (i.e., plane B-B') after depositing a first layer of dielectric material over a field controlled vertical current switch, according to an embodiment of the present disclosure.

Fig. 9B is a vertical cross-sectional view of an example structure along a second horizontal direction hd2 (i.e., plane a-a') after depositing a first layer of dielectric material over a field controlled vertical current switch, according to an embodiment of the present disclosure.

Fig. 10A is a vertical cross-sectional view of an exemplary structure along a first horizontal direction hd1 (i.e., plane B-B') after planarizing the conductive metallic material layer, the gate dielectric layer, and the columnar semiconductor channel of the gated ferroelectric memory cell in accordance with an embodiment of the present disclosure.

Fig. 10B is a vertical cross-sectional view of an exemplary structure along the second horizontal direction hd2 (i.e., plane a-a') after planarizing the conductive metallic material layer, the gate dielectric layer, and the columnar semiconductor channel of the gated ferroelectric memory cell in accordance with an embodiment of the present disclosure.

Fig. 11A is a vertical cross-sectional view of an exemplary structure along a first horizontal direction hd1 (i.e., plane B-B') after a selective etch process for vertically recessing the top annular portion of the gate electrode strip of a field controlled vertical current switch, in accordance with an embodiment of the present disclosure.

Fig. 11B is an exemplary structural square vertical cross-sectional view along the second horizontal direction hd2 (i.e., plane a-a') after a selective etch process for vertically recessing the top annular portion of the gate electrode strip for a field controlled vertical current switch, in accordance with an embodiment of the present disclosure.

Fig. 12A is a vertical cross-sectional view of an example structure along a first horizontal direction hd1 (i.e., plane B-B') after depositing a conductive metal material to form a bit line for a field controlled vertical current switch, according to an embodiment of the present disclosure.

Fig. 12B is a vertical cross-sectional view of an example structure along a second horizontal direction hd2 (i.e., plane a-a') after depositing a conductive metal material to form a bit line for a field controlled vertical current switch, according to an embodiment of the present disclosure.

Figure 13A is a vertical cross-sectional view of a second alternative embodiment structure along a first horizontal direction hd1 (i.e., plane B-B') after deposition of multiple layers including a ferroelectric dielectric layer, a metallic top electrode layer, and a semiconductor channel material layer over a first metal line and substrate in accordance with an embodiment of the present disclosure.

Figure 13B is a vertical cross-sectional view of a second alternative embodiment structure along a second horizontal direction hd2 (i.e., plane a-a') after depositing a plurality of layers including a ferroelectric dielectric layer, a metallic top electrode layer, and a semiconductor channel material layer over a first metal line and a substrate in accordance with an embodiment of the present disclosure.

Fig. 14A is a vertical cross-sectional view of a second alternative embodiment structure along a first horizontal direction hd1 (i.e., plane B-B') after etching and patterning a pillar-shaped semiconductor channel of a gated ferroelectric memory cell in accordance with an embodiment of the present disclosure.

Fig. 14B is a vertical cross-sectional view of a second alternative embodiment structure along a second horizontal direction hd2 (i.e., plane a-a') after etching and patterning a pillar-shaped semiconductor channel of a gated ferroelectric memory cell in accordance with an embodiment of the present disclosure.

Fig. 15A is a vertical cross-sectional view of a second alternative embodiment structure along a first horizontal direction hd1 (i.e., plane B-B') after depositing a conductive metal material to form the bit line of the field controlled vertical current switch, according to an embodiment of the present disclosure.

Fig. 15B is a vertical cross-sectional view of a second alternative embodiment structure along a second horizontal direction hd2 (i.e., plane a-a') after depositing a conductive metal material to form the bit line of the field controlled vertical current switch, according to an embodiment of the present disclosure.

Fig. 16A is a partial perspective view of an exemplary semiconductor memory device according to various embodiments of the present disclosure.

Fig. 16B is a schematic top view of the exemplary semiconductor memory device of fig. 16A.

Fig. 16C is a cross-sectional partial perspective view of the exemplary semiconductor memory device of fig. 16A taken through a memory structure of the semiconductor memory device.

Fig. 16D is an enlarged sectional view of a portion P of fig. 16C.

Fig. 17A is a vertical-portion sectional perspective view of a semiconductor memory device according to a second embodiment of the present disclosure.

Fig. 17B is an enlarged sectional view of a portion P of fig. 17A.

Fig. 18 is a partial cross-sectional perspective view of a semiconductor memory device according to another embodiment of the present disclosure.

Fig. 19 is a flow chart including steps of forming a semiconductor memory device according to various embodiments of the present disclosure.

Detailed Description

The following provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used therein interpreted accordingly. Unless explicitly stated otherwise, it is assumed that each element having the same reference numeral has the same material composition and has a thickness within the same thickness range.

The present invention relates to semiconductor devices, and more particularly to vertical field-controlled current selector switches operable in conjunction with memory cell devices as memory cell selection devices. Various embodiments of the present disclosure may relate to a gated ferroelectric memory device and a method of forming the same.

The memory device includes a grid of individually functioning memory cells formed on a substrate. The memory device may include volatile memory cells or non-volatile (NV) memory cells. Emerging memory technologies seek to store more data at a lower cost than the costly silicon chips used by popular consumer electronics. In the near future, such emerging memory devices may be used to replace existing memory technologies, such as flash memory. While existing resistive random access memories are generally adequate for their intended purposes, they are not entirely satisfactory in all respects as devices continue to shrink. For example, emerging non-volatile memory technologies may include resistive random access memory (RRAM or ReRAM), Magnetoresistive Random Access Memory (MRAM), ferroelectric random access memory (FeRAM), and Phase Change Memory (PCM).

RRAM is a NV RAM that operates by changing the resistance across a dielectric solid-state material (commonly referred to as a memristor). MRAM is a NV RAM that stores data in magnetic domains. Unlike conventional RAM chip technology, data in MRAM is not stored in the form of electrical charge or current, but rather by magnetic storage elements. These elements are made up of two ferromagnetic plates, each of which can hold a magnetization, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a specific polarity; the magnetization of the other plate can be changed to match the magnetization of the external magnetic field to store the memory. If the insulating layer is thin enough (typically only a few nanometers), electrons can tunnel from one ferromagnetic into the other. This configuration is called a Magnetic Tunnel Junction (MTJ) and is the simplest structure of an MRAM bit.

Ferroelectric RAM (FeRAM, F-RAM or FRAM) is a random access memory similar in structure to dynamic RAM (dram), but using a ferroelectric dielectric layer instead of a layer of dielectric material to achieve non-volatility. In older generations of PCMs, current generated by a heating element, typically made of titanium nitride (TiN), is used to rapidly heat and cool the glass, either into an amorphous state or to maintain it within a crystallization temperature range for a period of time, thereby switching it into the crystalline state.

In some memory devices, CMOS transistors may be used as selection transistors. However, size limitations of CMOS transistor technology may be a limiting factor in increasing the size of memory devices and memory cell density. Various embodiments described herein increase size and memory cell density by forming gated ferroelectric memory devices in back end of line (BEOL).

Fig. 1A is a vertical cross-sectional view of an example structure after formation of Complementary Metal Oxide Semiconductor (CMOS) transistors, metal interconnect structures embedded in a layer of dielectric material, and a layer of dielectric material connecting via levels, and before formation of an array of memory structures, in accordance with various embodiments of the present disclosure. Referring to fig. 1A, an exemplary structure according to an embodiment of the present disclosure is shown. The exemplary structure includes a Complementary Metal Oxide Semiconductor (CMOS) transistor and a metal interconnect structure formed in a layer of dielectric material. Specifically, the first exemplary structure includes a substrate 8 including a layer of semiconductor material 10. The substrate 8 may comprise a bulk semiconductor substrate, such as a silicon substrate in which a layer of semiconductor material extends continuously from the top surface of the substrate 8 to the bottom surface of the substrate 8, or a semiconductor-on-insulator layer comprising the layer of semiconductor material 10 as a top semiconductor layer overlying a buried insulating layer, such as a silicon oxide layer. Shallow trench isolation structures 12 comprising a dielectric material such as silicon oxide may be formed in an upper portion of the substrate 8. Suitable doped semiconductor wells, such as p-type wells and n-type wells, may be formed in each region that may be laterally enclosed by a portion of the shallow trench isolation structure 12. The field effect transistor may be formed on the top surface of the substrate 8. For example, each field effect transistor may include active source/drain regions 14, a semiconductor channel 15, and a gate structure 20, the semiconductor channel 15 including a surface portion of the substrate 8 extending between the active source/drain regions 14. Each gate structure 20 may include a gate dielectric 22, a gate electrode strip 24, a gate capping dielectric 28, and a dielectric gate spacer 26. An active source/drain metal semiconductor alloy region 18 may be formed on each active source/drain region 14. Although planar field effect transistors are shown in the figures, embodiments are expressly contemplated herein in which the field effect transistors may additionally or alternatively include fin field effect transistors (finfets), full ring gate field effect transistors (GAAFET) transistors, or any other type of Field Effect Transistors (FETs).

The exemplary structure may include a memory array region 50 in which an array of memory elements may be subsequently formed and a peripheral region 52 in which a logic device supporting the operation of the array of memory elements may be formed. In one embodiment, the devices (e.g., field effect transistors) in the memory array region 50 may include bottom electrode access transistors that provide access to the bottom electrodes of the memory cells to be subsequently formed. In this processing step, a top electrode access transistor may be formed in peripheral region 52 that provides access to the top electrode of a memory cell to be subsequently formed. The devices (e.g., field effect transistors) in the peripheral region 52 may provide functions that may be required to operate a subsequently formed array of memory cells. Specifically, the devices in the peripheral region may be configured to control a program operation, an erase operation, and a sensing (read) operation of the memory cell array. For example, devices in the peripheral region may include sensing circuitry and/or top electrode biasing circuitry. The devices formed on the top surface of the substrate 8 may include Complementary Metal Oxide Semiconductor (CMOS) transistors and optional additional semiconductor devices such as resistors, diodes, capacitors, etc., and are collectively referred to as CMOS circuitry 75.

Various interconnect level structures may then be formed, which are formed prior to forming the fin backside gate field effect transistor array, and are referred to herein as lower interconnect level structures (L0, L1, L2). In the case where a two-dimensional array of TFTs is to be subsequently formed on two levels of interconnect-level metal lines, the lower interconnect-level structures (L0, L1, L2) may include an interconnect-level structure L0, a first interconnect-level structure L1, and a second interconnect-level structure L2. For example, the dielectric material layers may include a contact level dielectric material layer 31A, a first metal line level dielectric material layer 31B, and a second line and via level dielectric material layer 32. Respective metal interconnect structures embedded in the layer of dielectric material may then be formed over the substrate 8 and devices (e.g., field effect transistors). The metal interconnect structures may include a device contact via structure 41V (interconnect level structure L0) formed in the contact level dielectric material layer 31A and contacting various components of the CMOS circuit 75, a first metal line structure 41L (interconnect level structure L1) formed in the first metal line level dielectric material layer 31B, a first metal via structure 42V formed in a lower portion of the second line and via level dielectric material layer 32, a second metal line structure 42L (interconnect level structure L2) formed in an upper portion of the second line and via level dielectric material layer 32.

Each dielectric material layer (31A, 31B, and 32) may include a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each metal interconnect structure (41V, 41L, 42V and 42L) may include at least one conductive material, which may be a combination of a metal liner layer (e.g., a metal nitride or a metal carbide) and a metal fill material. Each metallic liner layer may include TiN, TaN, WN, TiC, Tac, and WC, and each metallic filler material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and/or combinations thereof. Other suitable materials within the intended scope of the invention may also be used. In one embodiment, the first and second metal via structures 42V and 42L may be formed as integrated line and via structures through a dual damascene process, and the second and third metal via structures 43V and 43L may be formed as integrated line and via structures.

The dielectric material layers (31A, 31B, and 32) may be at a lower level relative to a subsequently formed memory cell array. Accordingly, the layers of dielectric material (31A, 31B, and 32) are referred to herein as lower-level layers of dielectric material, i.e., layers of dielectric material that are at a lower level relative to a subsequently formed array of memory cells. Here, the metal interconnection structures (41V, 41L, 42V, and 42L) refer to lower-level metal interconnection structures. The subset of metal interconnect structures (41V, 41L, 42V, and 42L) includes lower level metal lines (such as third metal line structure 42L) embedded in the lower level dielectric material layer and having a top surface within a horizontal plane that includes a topmost surface of the lower level dielectric material layer. Typically, the total number of metal line levels within the lower level dielectric material layers (31A, 31B and 32) may be in the range of 1 to 3.

The exemplary structure may include various device regions, which may include a memory array region 50, in which at least one array of non-volatile memory cells may be subsequently formed in the memory array region 50. For example, the array of at least one non-volatile memory cell may include a resistive random access memory (RRAM or ReRAM), a magnetic/Magnetoresistive Random Access Memory (MRAM), a ferroelectric random access memory (FeRAM), and a Phase Change Memory (PCM) device. The exemplary structure may also include a peripheral logic region 52, in which peripheral logic region 52 electrical connections between each non-volatile memory cell array and peripheral circuitry including field effect transistors may be subsequently formed. The areas of memory array area 50 and logic area 52 may be employed to form various elements of peripheral circuitry.

Referring to fig. 1B, an array 95 of non-volatile memory cells and TFT select devices may be formed in the memory array region 50 above the second interconnect level structure L2. Details of the structure and processing steps of the array 95 of non-volatile gated ferroelectric memory cells will be described in detail below. The third interconnect-level dielectric material layer 33 may be formed during the formation of the array 95 of non-volatile gated ferroelectric memory cells. The collection of all structures formed at the level of the array 95 of non-volatile memory cell and gated ferroelectric memory cell devices is referred to herein as a third interconnect level structure L3.

Referring to fig. 1C, a third interconnect-level metal interconnect structure (43V, 43L) may be formed in the third interconnect-level dielectric material layer 33. The third interconnect level metal interconnect structure (43V, 43L) may include a second metal via structure 43V and a third metal line 43L. Additional interconnect levels, referred to herein as upper level interconnect levels (L4, L5, L6, L7) may then be formed. For example, the upper level interconnect level structures (L4, L5, L6, L7) may include a fourth interconnect level structure L4, a fifth interconnect level structure L5, a sixth interconnect level structure L6, and a seventh interconnect level structure L7. The fourth interconnect level structure L4 may include a fourth interconnect level dielectric material layer 34 having a fourth interconnect level metal interconnect structure (44V, 44L) formed therein, which may include a third metal via structure 44V and a fourth metal line 44L. The fifth interconnect level structure L5 may include a fifth interconnect level dielectric material layer 35 having a fifth interconnect level metal interconnect structure (45V, 45L) formed therein, which may include a fourth metal via structure 45V and a fifth metal line 45L. The sixth interconnect level structure L6 may include a sixth interconnect level dielectric material layer 36 having a sixth interconnect level metal interconnect structure (46V, 46L) formed therein, which may include a fifth metal via structure 46V and a sixth metal line 46L. The seventh interconnect-level structure L7 may include a seventh interconnect-level dielectric material layer 37 with a sixth metal via structure 47V (which is a seventh interconnect-level metal interconnect structure) and a metal bond pad 47B formed in the seventh interconnect-level dielectric material layer 37. Metal bond pad 47B may be configured for solder bonding (C4 ball bonding or wire bonding may be employed), or may be configured for metal-to-metal bonding (e.g., copper-to-copper bonding).

Each interconnect-level dielectric material layer may be referred to as an interconnect-level dielectric (ILD) layer 30 (i.e., 31A, 31B, 32, 33, 34, 35, 36, and 37). Each interconnect-level metal interconnect structure may be referred to as a metal interconnect structure 40. Each successive combination of a metal via structure and a overlying metal line within the same interconnect level structure (L2-L7) may be formed sequentially as two different structures by employing two single damascene processes, or may be formed simultaneously as a single structure employing a dual damascene process. Each of the metal interconnect structures 40 (i.e., 41V, 41L, 42V, 42L, 43V, 43L, 44V, 44L, 45V, 45L, 46V, 46L, 47V, 47B) may include a respective metal liner (e.g., a TiN, TaN, or WN layer having a thickness in a range of 2 nanometers to 20 nanometers) and a respective metal fill material (e.g., W, Cu, Co, Mo, Ru, other elemental metals or alloys). Other suitable materials for use as the metal liner and the metal filler material are also within the intended scope of the invention. Various etch stop dielectric material layers and dielectric capping layers may be interposed between vertically adjacent pairs of ILD layers 30, or may be incorporated into one or more of ILD layers 30.

While the present disclosure is described with an embodiment in which the array of non-volatile memory cells and TFT select devices 95 may be formed as components of the third interconnect level structure L3, embodiments are expressly contemplated herein in which the array of non-volatile memory cells and TFT select devices 95 may be formed as components of any other interconnect level structure (e.g., L1-L7). Furthermore, while the present disclosure is described using an embodiment in which a set of eight interconnect levels are formed, embodiments in which a different number of interconnect levels are used are expressly contemplated herein. Furthermore, in embodiments expressly contemplated herein, two or more arrays 95 of non-volatile memory cells and TFT select devices may be disposed within multiple interconnect levels in memory array region 50. While the present disclosure is described with an embodiment in which the array of non-volatile memory cells and TFT select devices 95 may be formed in a single interconnect level structure, embodiments in which the array of non-volatile memory cells and TFT select devices 95 may be formed over two vertically adjacent interconnect levels structures are expressly contemplated herein.

Fig. 2A is a horizontal cross-sectional view of an exemplary structure after etching and patterning a first metal line trench in a first dielectric material layer, according to an embodiment of the present disclosure. Fig. 2B is a vertical cross-sectional view of an exemplary structure along plane B-B' of fig. 2A. Fig. 2C is a vertical cross-sectional view of an exemplary structure along plane a-a' of fig. 2A. Referring to fig. 2A-2C, a first layer of dielectric material 120 may be deposited on the substrate 110. The substrate 110 may be any suitable substrate, such as a semiconductor device substrate. In other embodiments, the substrate 110 may be the third interconnect-level dielectric material layer 33 as shown in fig. 1C. The first dielectric material layer 120 may include a dielectric material, such as silicon dioxide (SiO)₂)、Undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. The first layer of dielectric material 120 may be deposited or grown over the ILD layer 30 by any of a variety of suitable deposition processes. A photoresist layer (not shown) may be applied on the first dielectric material layer 120 and may be patterned to form trenches 121 in the regions of the first dielectric material layer 120, and then first metal lines may be formed in the trenches 121. For example, the photoresist pattern may be formed by depositing a photoresist material and then patterning the deposited photoresist material using a photolithography technique. The patterned photoresist may mask portions of the first layer of dielectric material 120 to protect these portions during a subsequent etching process. An etching process may be performed to form first metal line trenches 121 in the first dielectric material layer 120. For example, first dielectric material layer 120 may be etched using any suitable etching process (e.g., wet or dry etching processes). In one embodiment, each first metal line trench 121 may be located within an upper portion of the first dielectric material layer 120. The first metal line trenches 121 may extend laterally along the first horizontal direction hd1, and may be laterally spaced along the second horizontal direction hd2 perpendicular to the first horizontal direction hd 1. The photoresist may then be removed, for example, by ashing or a chemical process.

Fig. 3A is a horizontal cross-sectional view of an example structure after depositing and planarizing a conductive metal material in a first metal line trench to form a first metal line, according to an embodiment of the present disclosure. Fig. 3B is a vertical cross-sectional view of an exemplary structure along plane B-B' of fig. 3A. Fig. 3C is a vertical cross-sectional view of an exemplary structure along plane a-a' of fig. 3A. Referring to fig. 3A to 3C, a first metal line 122 may be formed in the first metal line trench 121. A conductive material may be deposited over the first dielectric material layer 120 so as to fill the first metal line trenches 121. The first metal line 122 may be formed of a conductive metal material, such as copper, aluminum, zirconium, titanium nitride, tungsten, tantalum nitride, ruthenium, palladium, platinum, cobalt, nickel, iridium, alloys thereof, and the like. Other suitable conductive materials for the first metal line 122 are also within the intended scope of the present invention. The first metal line 122 (also referred to as a plate line or source line 122) may be formed by depositing a layer of conductive material using any suitable deposition process. Here, the "suitable deposition process" may include a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, a high density plasma CVD (hdpcvd) process, a metal organic CVD (mocvd) process, a plasma enhanced CVD (pecvd) process, a sputtering process, a laser ablation process, and the like.

A planarization process, such as a Chemical Mechanical Polishing (CMP) process or the like, may then be performed to remove excess conductive metallic material from the surface of the first dielectric material layer 120 and to make the top surface of the first metal line 122 coplanar with the top surface of the first dielectric material layer 120. In one embodiment, each first metal line 122 may be located within an upper portion of the first dielectric material layer 120. The first metal lines 222 may extend laterally along the first horizontal direction hd1, and may be laterally spaced along a second horizontal direction hd2 perpendicular to the first horizontal direction hd 1.

Fig. 4A is a vertical cross-sectional view of an exemplary structure along a first horizontal direction hd1 (i.e., plane B-B') after deposition of a plurality of layers including a ferroelectric dielectric layer 130 and a semiconductor channel material layer 140L over a first metal line 122 and a substrate 110 in accordance with an embodiment of the present disclosure. Fig. 4B is a vertical cross-sectional view of an exemplary structure along the second horizontal direction hd2 (i.e., plane a-a') after depositing a plurality of layers including the ferroelectric dielectric layer 130 and the semiconductor channel material layer 140L over the first metal line 122 and the substrate 110 according to an embodiment of the present disclosure. Referring to fig. 4A and 4B, a blanket layer of Ferroelectric (FE) material 130 may be deposited over the first dielectric material layer 120 and the first metal line 122. Ferroelectric dielectric layer (FE)130 can be formed of any suitable ferroelectric material, such as HfO₂、ZrO₂、HfZrO₂、AlScN、PbZrO₃、Pb[Zr_xTi_1-x]O₃、(0≤x≤)(PZT)、BaTiO₃、PbTiO₃、PbNb₂O₆、LiNbO₃、LiTaO₃Polyvinylidene fluoride (PVDF), potassium dihydrogen phosphate (KDP), PbMg_{1/ 3}Nb_2/3O₃(PMN)、PbSc_1/2Ta_1/2O₃PbSc_1/2Ta_1/2O₃(PST)、SrBi₂Ta₂O₉(SBT)、Bi_1/2Na_1/2TiO₃Bi_1/2Na_{1/ 2}TiO₃Combinations thereof, and the like. In particular, a ferroelectric dielectric layer 130 may be deposited on the first dielectric material layer 120 so as to cover the first metal line 122.

A layer of semiconductor material 140L may be deposited on the ferroelectric dielectric layer 130. The semiconductor material layer 140L may include polysilicon, amorphous silicon, or a semiconductor oxide such as ingazno (igzo), Indium Tin Oxide (ITO), InWO, InZnO, InSnO, GaOx, Inox, or the like. Other suitable semiconductor materials are also within the scope of the present invention. In some embodiments, the columnar semiconductor channel 140 may be preferably formed of IGZO. IGZO may be "intrinsic" or dopants may be added as necessary. The conductive range of the semiconductor material layer 140L may be at least from 1 × 10^-5S/m to 1S/m, and may be from 1X 10^-10S/m to 1X 120S/m, although greater or lesser conductivities may be within the contemplated scope of the invention. Semiconductor material layer 140L may allow for the subsequent formation of gated ferroelectric memory cells to control and select the memory cells formed by the underlying ferroelectric dielectric layer 130. The layer of semiconductor material 140L may be deposited using any suitable deposition process. Here, the "suitable deposition process" may include a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, a high density plasma CVD (hdpcvd) process, a metal organic CVD (mocvd) process, a plasma enhanced CVD (pecvd) process, a sputtering process, a laser ablation process, and the like.

Fig. 5A is a vertical cross-sectional view of an exemplary structure along a first horizontal direction hd1 (i.e., plane B-B') after etching and patterning a pillar-shaped semiconductor channel of a gated ferroelectric memory cell according to an embodiment of the present disclosure. Fig. 5B is a vertical cross-sectional view of an exemplary structure along the second horizontal direction hd2 (i.e., plane a-a') after etching and patterning a pillar-shaped semiconductor channel of a gated ferroelectric memory cell according to an embodiment of the present disclosure. Referring to fig. 5A and 5B, the semiconductor material layer 140L may be patterned to form a pillar-shaped semiconductor channel 140. For example, a two-dimensional array of etch mask material, such as a photoresist material (not shown), may be applied over the layer of semiconductor material 140L. The photolithography process can transfer a pattern to the photoresist material. Using the two-dimensional array of etch mask material portions as an etch mask, the remaining portions of the semiconductor channel material layer 140 can be patterned to include a two-dimensional array of columnar semiconductor channels by anisotropically etching unmasked portions of the semiconductor channel material layer 140 selective to the ferroelectric dielectric layer 130. Generally, a two-dimensional array of columnar semiconductor channels 140 may be formed over ferroelectric dielectric layer 130. Each row of pillar-shaped semiconductor channels 140 is formed over a respective one of the first metal lines 122 and is capacitively coupled to the respective one of the first metal lines 122.

The resulting columnar semiconductor channel 140 may be in the form of a cylinder, a column, or a nanowire. However, the columnar semiconductor channel 140 is not limited to any particular shape. The columnar semiconductor channel 140 may be vertically aligned with respect to the first dielectric material layer 120. In other words, the long axis of each columnar semiconductor channel 140 may extend perpendicular to the plane of the first dielectric material layer 120 and/or the underlying semiconductor substrate. After the formation of the pillar-shaped semiconductor channel 140, the photoresist material (not shown) may be removed, for example, by ashing or a chemical process.

After the columnar semiconductor channel structures 140 can be formed, a two-dimensional array of memory cells 100 can be provided. Each memory cell 100 may include a bottom portion of the pillar-shaped semiconductor channel 140, a portion of the ferroelectric dielectric layer 130 having a planar overlap with the pillar-shaped semiconductor channel 140, and a portion of the first metal line 122 having a planar overlap with the pillar-shaped semiconductor channel 140. Thus, the memory cell 100 may be a Metal Ferroelectric Semiconductor (MFS) capacitor. Memory cell 100 may also include a metal-ferroelectric-metal capacitor, as described below. Still further, other memory cell structures 100 are within the intended scope of the invention. For example, memory cell 100 may be formed as a PCM, ReRAM, MRAM, or other suitable memory cell structure.

FIG. 6A is a deposition of a gate dielectric layer according to an embodiment of the disclosureA vertical cross-sectional view of an exemplary structure along a first horizontal direction hd1 (i.e., plane B-B') after gating over the formed pillar-shaped semiconductor channel of the ferroelectric memory cell. Fig. 6B is a vertical cross-sectional view of an exemplary structure along a second horizontal direction hd2 (i.e., plane a-a') after a gate dielectric layer is deposited over the formed pillar-shaped semiconductor channel of a gated ferroelectric memory cell in accordance with an embodiment of the present disclosure. Referring to fig. 6A and 6B, a gate dielectric layer may be conformally deposited over ferroelectric dielectric layer 130 and the two-dimensional array of columnar semiconductor channels 140. A gate dielectric layer 150 may be deposited on the ferroelectric dielectric layer 130 so as to cover the columnar semiconductor channel 140. The gate dielectric layer 150 may be formed of any suitable dielectric material, such as silicon oxide or a high-k dielectric material. Here, the "high-k dielectric material" has a dielectric constant greater than 3.9, and may include, but is not limited to, silicon nitride, hafnium oxide (HfO)₂) Hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (Hf)_0.5Zr_0.5O₂) (HZO), tantalum oxide (Ta)₂O₅) Alumina (Al)₂O₃) Mercury-aluminum oxide dioxide (HfO)₂-Al₂O₃) Zirconium oxide (ZrO)₂). Other suitable dielectric materials are also within the scope of the present invention.

The gate dielectric layer 150 may be formed by any suitable deposition method. Here, the "suitable deposition process" may include a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, a high density plasma CVD (hdpcvd) process, a metal organic CVD (mocvd) process, a plasma enhanced CVD (pecvd) process, a sputtering process, a laser ablation process, and the like.

In various embodiments, the gate dielectric layer 150 may have a thickness t in the range of 0.5-5.0 nanometers_hkE.g., 1-4 nanometers, although greater or lesser thicknesses may be used. In various embodiments, the columnar semiconductor channel 140 may have a thickness t in the range of 1-20 nanometers_cE.g., 3-15 nanometers, although greater or lesser thicknesses may be used.

Portions of the gate dielectric layer 150 may extend vertically from the first dielectric material layer 120 (e.g., perpendicular to the plane of the first dielectric material layer 120) and form Surrounding Gate Insulators (SGI)150A that respectively surround the columnar semiconductor channels 140 (refer to fig. 16D and 17B).

Fig. 7A is a vertical cross-sectional view of an exemplary structure along a first horizontal direction hd1 (i.e., plane B-B') after depositing a layer of conductive metallic material as a gate electrode and word line over the formed columnar semiconductor channel and gate dielectric layer of a gated ferroelectric memory cell in accordance with an embodiment of the present disclosure. Fig. 7B is a vertical cross-sectional view of an exemplary structure along a second horizontal direction hd2 (i.e., plane a-a') after depositing a layer of conductive metallic material as a gate electrode and word line over the formed columnar semiconductor channel and gate dielectric layer of a gated ferroelectric memory cell in accordance with an embodiment of the present disclosure. Referring to fig. 7A and 7B, a layer of gate electrode material 160L may be deposited on the gate dielectric layer 150 by a conformal or non-conformal deposition process. The gate electrode material layer 160L may be formed of a conductive metal material such as copper, aluminum, zirconium, titanium nitride, tungsten, tantalum nitride, ruthenium, palladium, platinum, cobalt, nickel, iridium, alloys thereof, or the like. Other suitable conductive materials for the gate electrode material layer 160L are also within the intended scope of the present invention. The gate electrode material 160L may be deposited using any suitable deposition process using any suitable conductive material, such as a gate metal. Here, the "suitable deposition process" may include a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, a high density plasma CVD (hdpcvd) process, a metal organic CVD (mocvd) process, a plasma enhanced CVD (pecvd) process, a sputtering process, a laser ablation process, and the like.

Fig. 8A is a vertical cross-sectional view of an example structure along a first horizontal direction hd1 (i.e., plane B-B') after patterning a layer of conductive metal material to form word lines and gate electrodes for gated ferroelectric memory cells in accordance with an embodiment of the present disclosure. Fig. 8B is a vertical cross-sectional view of an example structure along a second horizontal direction hd2 (i.e., plane a-a') after patterning a layer of conductive metal material to form word lines and gate electrodes for gated ferroelectric memory cells, according to an embodiment of the present disclosure.

Referring to fig. 8A and 8B, the gate electrode material layer 160L may be patterned to form the gate electrode 160 and the gate electrode stripe. For example, a two-dimensional array of etch mask material, such as photoresist material 177, may be applied over the layer of semiconductor material 160L covering the respective columns of pillar-shaped semiconductor channels 140. The photolithography process can transfer the pattern over the photoresist material 177. Using the two-dimensional array of photoresist material 177 as an etch mask, remaining portions of the gate electrode material layer 140 can be patterned to include gate electrodes 160 and gate electrode strips 160 that can serve as word lines by anisotropically etching unmasked portions of the gate electrode material layer 160, which gate electrodes 160 can surround the respective columnar semiconductor channels 140 and gate dielectric layer 150. The gate strip 160 may be formed as a Gate All Around (GAA) gate to laterally surround the pillar shaped semiconductor channel 140 to provide better gate control. The photoresist layer material 177 can then be removed, for example, by ashing.

Fig. 9A is a vertical cross-sectional view of an example structure along a first horizontal direction hd1 (i.e., plane B-B') after depositing a first layer of dielectric material over a field controlled vertical current switch, according to an embodiment of the present disclosure. Fig. 9B is a vertical cross-sectional view of an example structure along a second horizontal direction hd2 (i.e., plane a-a') after depositing a first layer of dielectric material over a field controlled vertical current switch, according to an embodiment of the present disclosure. Referring to fig. 9A and 9B, a dielectric matrix layer 170 may be deposited to embed the pillar-shaped semiconductor channels 140, the gate dielectric layer 150, and the gate electrode stripes 160.

Dielectric matrix layer 170 may be formed of silicon oxide or any suitable high-k dielectric material. The dielectric matrix layer 170 may be formed of the same or different material as the first dielectric material layer 120. The dielectric matrix layer 170 may be formed using any suitable deposition process.

Fig. 10A is a vertical cross-sectional view of an exemplary structure along a first horizontal direction hd1 (i.e., plane B-B') after planarizing the conductive metallic material layer, the gate dielectric layer, and the columnar semiconductor channel of the gated ferroelectric memory cell in accordance with an embodiment of the present disclosure. Fig. 10B is a vertical cross-sectional view of an exemplary structure along the second horizontal direction hd2 (i.e., plane a-a') after planarizing the conductive metallic material layer, the gate dielectric layer, and the columnar semiconductor channel of the gated ferroelectric memory cell in accordance with an embodiment of the present disclosure. Referring to fig. 10A and 10B, a planarization process such as CMP may be performed to planarize the top surfaces of the pillar-shaped semiconductor channel 140, the gate dielectric layer 150, and the gate electrode stripe 160 such that the top surfaces of the pillar-shaped semiconductor channel 140, the gate dielectric layer 150, and the gate electrode stripe 160 are coplanar. Specifically, portions of the dielectric matrix layer 170, the gate electrode stripes 160, and the gate dielectric layer 150 may be removed from above a horizontal plane including the top surface of the columnar semiconductor channel 140. After the planarization operation, each of the columnar semiconductor channels 140 within the two-dimensional array of columnar semiconductor channels 140 may have a respective top surface that lies within a horizontal plane that includes the planarized top surface of the dielectric matrix layer 170. Further, each gate electrode strip 160 may have an annular top surface 161, the annular top surface 161 being located within a horizontal plane that includes the planarized top surface of the dielectric matrix layer 170.

Fig. 11A is a vertical cross-sectional view of an exemplary structure along a first horizontal direction hd1 (i.e., plane B-B') after a selective etch process for vertically recessing the top annular portion of the gate electrode strip of a field controlled vertical current switch, in accordance with an embodiment of the present disclosure. Fig. 11B is an exemplary structural square vertical cross-sectional view along the second horizontal direction hd1 (i.e., plane a-a') after a selective etch process for vertically recessing the top annular portion of the gate electrode strip for a field controlled vertical current switch, in accordance with an embodiment of the present disclosure. Referring to fig. 11A and 11B, a selective etching process may be performed to vertically recess each annular top surface of the gate electrode strip 160 with respect to the planarized top surface of the dielectric matrix layer 170 and the top surface of the two-dimensional array of columnar semiconductor channels 140. The etching process etches the gate electrode material selective to both the gate electrode strip 160 material and the dielectric matrix layer 170. The etching process may include an isotropic etching process, such as a wet etching process, or an anisotropic etching process, such as a reactive ion etching process. The groove depth of the gate electrode stripes 160 may cause the gate electrodes 160 to surround the columnar semiconductor channels 140 to a height of 60-90% of the height of each columnar semiconductor channel 140. In other words, the groove depth of the etching process may be in the range of 10% to 40% of the height of each of the pillar-shaped semiconductor channels 140. The annular cavity 171 may be formed as a result of an etching process that vertically recesses the gate electrode 160.

Fig. 12A is a vertical cross-sectional view of an example structure along a first horizontal direction hd1 (i.e., plane B-B') after depositing a conductive metal material to form a bit line for a field controlled vertical current switch, according to an embodiment of the present disclosure. Fig. 12B is a vertical cross-sectional view of an example structure along a second horizontal direction hd1 (i.e., plane a-a') after depositing a conductive metal material to form a bit line for a field controlled vertical current switch, according to an embodiment of the present disclosure. Referring to fig. 12A and 12B, after depositing the second layer of dielectric material 180, the annular cavity 171 may be filled with the dielectric material of the second layer of dielectric material 180. For example, a conformal deposition process (such as chemical vapor deposition) may be employed to deposit the second dielectric material layer 180. With such an embodiment, the second layer of dielectric material 180 may include a two-dimensional array of tubular dielectric material portions 172, the tubular dielectric material portions 172 filling the cylindrical cavities 171 and contacting the annular top surfaces of the respective tubular portions of the gate strip 160T.

A photoresist material (not shown) may be applied over the second layer of dielectric material 180. The photoresist material may be patterned by photolithography techniques to mask the second dielectric material layer 180 to form line trenches (not shown) extending laterally along the first horizontal direction hd1 in the second dielectric material layer 180 after the etching process. The wireway may be filled with at least one metallic filler material. Each metallic fill material portion can be any suitable conductive electrode material, such as copper, aluminum, zirconium, titanium nitride, tungsten, tantalum nitride, ruthenium, palladium, platinum, cobalt, nickel, iridium, alloys thereof, and the like. Other suitable second metal wire materials are also within the intended scope of the present invention. The second metal line 182 may be formed by depositing a layer of conductive material using any suitable deposition process. Here, the "suitable deposition process" may include a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, a high density plasma CVD (hdpcvd) process, a metal organic CVD (mocvd) process, a plasma enhanced CVD (pecvd) process, a sputtering process, a laser ablation process, and the like. In some embodiments, an optional metal liner material may be deposited prior to the metal fill portion. Each metallic liner layer may comprise TiN, TaN, WN, TiC, TaC, and WC. Other suitable materials within the intended scope of the invention may also be used. A planarization process (e.g., a chemical mechanical polishing process) may be used to remove excess portions of the at least one metallic material from above a level including the top surface of the second layer of dielectric material 180. Each remaining portion of the at least one metal material filling a respective line slot in the second layer of dielectric material 180 includes a second metal line 182 that can serve as an active bit line. Each of the second metal lines 182 may be directly formed on a corresponding one of the rows of top surfaces of the pillar-shaped semiconductor channels 140. Accordingly, the second metal lines 182 may be formed over the two-dimensional array of pillar-shaped semiconductor channels 140, wherein each of the second metal lines 182 is formed directly on a top surface of a respective row of pillar-shaped semiconductor channels 140. As described above, in other embodiments, a metal pad (not shown) may be used to improve the electrical coupling between the second metal line 182 and the pillar-shaped semiconductor channel 140.

In this way, a gated ferroelectric memory cell 200 may be provided above each memory cell 100. The gated ferroelectric memory cell 200 may include a columnar semiconductor channel 140 and a portion of a gate electrode band 160 laterally surrounding the columnar semiconductor channel 140. A two-dimensional array of gated ferroelectric memory cells 200 is provided. Each gated ferroelectric memory cell 200 includes a series connection of a memory element 100, a field controlled vertical current switch 600, and a metal top electrode as part of a second metal line 182. Accordingly, each gated ferroelectric memory cell 200 includes a metal bottom electrode, which may be a portion of the first metal line 122, a portion of the ferroelectric dielectric layer 130, the pillar-shaped semiconductor channel 140, a portion of the gate dielectric layer 150, a portion of the gate electrode strap 160, and a metal top electrode that is a portion of the second metal line 182.

FIG. 13A is a deposition of a layer of material including a ferroelectric dielectric layer, a metallic top electrode layer, and a semiconductor channel material over a first metal line and a substrate according to an embodiment of the disclosureVertical cross-sectional view of a second alternative embodiment structure following the plurality of layers, along a first horizontal direction hd1 (i.e., plane B-B'). Figure 13B is a vertical cross-sectional view of a second alternative embodiment structure along a first horizontal direction hd1 (i.e., plane B-B') after deposition of multiple layers including a ferroelectric dielectric layer, a metallic top electrode layer, and a semiconductor channel material layer over the first metal line and the substrate in accordance with an embodiment of the present disclosure. Referring to fig. 13A and 13B, an intermediate structure as shown in fig. 3A-3C may be provided. As described above, a blanket layer of Ferroelectric (FE) material 130 may be deposited over the first dielectric material layer 120 and the first metal lines 122. Ferroelectric dielectric layer (FE)130 can be formed of any suitable ferroelectric material, such as HfO₂、ZrO₂、HfZrO₂、AlScN、PbZrO₃、Pb[Zr_xTi_1-x]O₃、(0≤x≤)(PZT)、BaTiO₃、PbTiO₃、PbNb₂O₆、LiNbO₃、LiTaO₃Polyvinylidene fluoride (PVDF), potassium dihydrogen phosphate (KDP), PbMg_1/3Nb_2/3O₃(PMN)、PbSc_1/2Ta_1/2O₃PbSc_1/2Ta_1/2O₃(PST)、SrBi₂Ta₂O₉(SBT)、Bi_1/2Na_1/2TiO₃Bi_1/2Na_1/2TiO₃Combinations thereof, and the like. In particular, a ferroelectric dielectric layer 130 may be deposited on the first dielectric material layer 120 so as to cover the first metal line 122.

A layer of semiconductor material 140L may be deposited on the ferroelectric dielectric layer 130. The semiconductor material layer 140L may include polysilicon, amorphous silicon, or a semiconductor oxide such as ingazno (igzo), Indium Tin Oxide (ITO), InWO, InZnO, InSnO, GaOx, Inox, or the like. Other suitable semiconductor materials are also within the scope of the present invention. In some embodiments, the columnar semiconductor channel 140 may be preferably formed of IGZO. IGZO may be "intrinsic" or dopants may be added as necessary. The conductive range of the semiconductor material layer 140L may be at least from 1 × 10^-5S/m to 1S/m, and may be from 1X 10^-10S/m to 1X 120S/m, although greater or lesser conductivities are contemplated by the inventionWithin the range. Semiconductor material layer 140L may allow for the subsequent formation of gated ferroelectric memory cells to control and select the memory cells formed by the underlying ferroelectric dielectric layer 130. The layer of semiconductor material 140L may be deposited using any suitable deposition process. In addition, an intermediate metal electrode 142L may be deposited between the semiconductor material layer 140L and the ferroelectric dielectric layer 130. The intermediate metal electrode 142L may be formed of a material such as copper, aluminum, zirconium, titanium nitride, tungsten, tantalum nitride, ruthenium, palladium, platinum, cobalt, nickel, iridium, an alloy thereof, or the like. Other suitable conductive materials for the intermediate metal electrode 142L are within the intended scope of the invention. In such an alternative embodiment, the two-dimensional array of etch mask material portions is used as an etch mask to subsequently pattern the intermediate metal electrodes 142L into a two-dimensional array of intermediate metal electrodes. Intermediate metal electrode 142L may be patterned to form a top metal plate 142 over ferroelectric dielectric layer 130 in a metal-ferroelectric-metal capacitor memory cell.

Fig. 14A is a vertical cross-sectional view of a second alternative embodiment structure along a first horizontal direction hd1 (i.e., plane B-B') after etching and patterning a pillar-shaped semiconductor channel of a gated ferroelectric memory cell in accordance with an embodiment of the present disclosure. Fig. 14B is a vertical cross-sectional view of a second alternative embodiment structure along a second horizontal direction hd2 (i.e., plane a-a') after etching and patterning a pillar-shaped semiconductor channel of a gated ferroelectric memory cell in accordance with an embodiment of the present disclosure. Referring to fig. 14A and 14B, and similar to the steps described above with respect to fig. 5A and 5B, the semiconductor material layer 140L may be patterned to form the columnar semiconductor channel 140. Using the two-dimensional array of etch mask material portions as an etch mask, the remaining portions of the semiconductor channel material layer 140 can be patterned to include a two-dimensional array of columnar semiconductor channels by anisotropically etching unmasked portions of the semiconductor channel material layer 140 selective to the ferroelectric dielectric layer 130. Generally, a two-dimensional array of columnar semiconductor channels 140 may be formed over ferroelectric dielectric layer 130. Each row of pillar-shaped semiconductor channels 140 is formed over a respective one of the first metal lines 122 and is capacitively coupled to the respective one of the first metal lines 122. In addition, as shown in fig. 14A and 14B, the etching process of patterning the pillar-shaped semiconductor channel 140 may also etch and pattern the intermediate metal electrode 142L to form a top metal plate 142 between the pillar-shaped semiconductor channel 140 and the ferroelectric dielectric layer 130, as shown in fig. 4B. Thus, the top metal plate 142, the ferroelectric dielectric layer 130, and the first metal line 122 may be used to form a metal-ferroelectric-metal junction memory cell device. Such memory cell devices may have improved memory endurance and retention time. After the formation of the pillar-shaped semiconductor channel 140, the photoresist material (not shown) may be removed, for example, by ashing or a chemical process.

Fig. 15A is a vertical cross-sectional view of a second alternative embodiment structure along a first horizontal direction hd1 (i.e., plane B-B') after depositing a conductive metal material to form the bit line of the field controlled vertical current switch, according to an embodiment of the present disclosure. Fig. 15B is a vertical cross-sectional view of a second alternative embodiment structure along a second horizontal direction hd1 (i.e., plane a-a') after depositing a conductive metal material to form the bit line of the field controlled vertical current switch, according to an embodiment of the present disclosure. Referring to fig. 15A and 15B, the process steps described above with reference to fig. 6A-12B may be performed. Thus, an optional gated ferroelectric memory cell 601 may be provided above each memory cell 101. A two-dimensional array of memory cells 101 may be provided. Each memory cell 101 may include a bottom portion of the columnar semiconductor channel 140, a portion of the ferroelectric dielectric layer 130 having planar overlap with the columnar semiconductor channel 140, and an intermediate metal layer forming a top electrode 142.

The gated ferroelectric memory cell 601 may include a columnar semiconductor channel 140 and a portion of the gate electrode strip 160 laterally surrounding the columnar semiconductor channel 140. A two-dimensional array of gated ferroelectric memory cells 201 is provided. Each gated ferroelectric memory cell 201 comprises a series connection of a memory element 101, a gated ferroelectric memory cell 601 and a metal top electrode as part of a second metal line 182. Accordingly, each gated ferroelectric memory cell 201 includes a metal bottom electrode, which may be a portion of first metal line 122, a portion of ferroelectric dielectric layer 130, top electrode 142, columnar semiconductor channel 140, a portion of gate dielectric layer 150, a portion of gate electrode strap 160, and a metal top electrode that is a portion of second metal line 182.

Fig. 16A is a partial perspective view of a semiconductor memory device according to various embodiments of the present disclosure. Fig. 16B is a schematic top view of the semiconductor memory device of fig. 16A. Fig. 16C is a cross-sectional partial perspective view of the semiconductor memory device of fig. 16A taken through a memory structure of the semiconductor memory device. Fig. 16D is an enlarged sectional view of a portion P of fig. 16C. Fig. 17A is a vertical partial sectional perspective view of a semiconductor memory device according to another embodiment of the present disclosure. Fig. 17B is an enlarged sectional view of a portion P of fig. 17A.

For example, fig. 16A may illustrate a perspective view of a complete two-dimensional array 300 of gated ferroelectric memory cells 200 as shown in fig. 12A and 12B. The two-dimensional array 300 of gated ferroelectric memory cells 200 includes a two-dimensional array of field-controlled vertical current switches 600. Each gated ferroelectric memory cell 200 may include a field controlled vertical current switch 600 (refer to fig. 12A, 12B, 15A, 15B, 16D, and 17B) formed over and coupled to the memory element (100, 101). The field controlled vertical current switch 600 includes a gate electrode strip 160 and a gate dielectric layer 150 surrounding a pillar-shaped semiconductor channel 140. The distal end 140S of the pillar-shaped semiconductor channel 140 may be electrically coupled to the second metal line 182. The proximal end 140D of the pillar shaped semiconductor channel 140 may be electrically coupled in series to the memory elements 100, 101.

The memory elements 100, 101 may comprise metal-ferroelectric-metal (MFM) capacitors or metal-ferroelectric-semiconductor (MFS) capacitor memory elements 100. For example, referring to fig. 12A, 12B, and 16D, in one embodiment, memory element 100 may include a metal-ferroelectric-semiconductor (MFS) capacitor ferroelectric tunnel junction operating as a capacitor or ferroelectric tunnel junction memory cell. As shown in fig. 12A, 12B, and 16D, a ferroelectric dielectric layer 130 may be disposed between the conductive metal first metal line 122 and the pillar-shaped semiconductor channel 140. In such embodiments, the bottom of the pillar-shaped semiconductor channel 140 may serve as the top electrode of a capacitor or FTJ memory device. The top of the first metal line 122 may serve as a bottom electrode of a capacitor or an FTJ memory device. The first metal line 122 may be coupled to a first metal line via 128, and the first metal line via 128 may extend vertically through the interconnect dielectric layer.

In another embodiment, as shown in fig. 15A, 15B, 17A and 17B, a complete two-dimensional array 301 of gated ferroelectric memory cells 201 may be provided. The two-dimensional array 301 of gated ferroelectric memory cells 201 is similar to the two-dimensional array 300 of gated ferroelectric memory cells 200 shown in fig. 16A. However, in the two-dimensional array 301 of gated ferroelectric memory cells 201, an intermediate metal electrode 142 may be formed between the ferroelectric dielectric layer 130 and the columnar semiconductor channel 140. In such an embodiment, a metal-ferroelectric-metal (MFM) capacitor may be formed using the top of the first metal line 122 as the bottom metal plate, the ferroelectric dielectric layer 130 as the inter-node dielectric, and the intermediate metal electrode 142 as the top metal plate. The intermediate metal electrode 142 may be electrically coupled in series with the pillar-shaped semiconductor channel 140.

Referring to fig. 1A-12B and 16A-16D, a semiconductor device 300 may be provided, the semiconductor device 300 including at least one gated ferroelectric memory cell 200, 201, wherein each gated ferroelectric memory cell 200, 201 includes a layer of dielectric material 120 disposed over a substrate 110, according to various embodiments of the invention. Memory cells 200, 201 also include a metal bottom electrode 122 and a ferroelectric dielectric layer 130 contacting the top surface of metal bottom electrode 122. The gated ferroelectric memory cell 200, 201 further includes a pillar shaped semiconductor channel 140 overlying the ferroelectric dielectric layer 130 and capacitively coupled to the metal bottom electrode 122 through the ferroelectric dielectric layer 130. As shown in fig. 12A, 12B, 15A and 15B, the gated ferroelectric memory cell 200, 201 further includes a gate dielectric layer 150, the gate dielectric layer 150 including a horizontal gate dielectric portion 150H overlying the ferroelectric dielectric layer 130 and a tubular gate dielectric 150T portion laterally surrounding the columnar semiconductor channel 140. Gated ferroelectric memory cell 200 further includes a gate electrode stripe 160 overlying horizontal gate dielectric portion 150H and laterally surrounding tubular gate dielectric portion 150T. As shown in fig. 12A, 12B, 15A and 15B, the gated ferroelectric memory cell 200, 201 further comprises a gate strip 160, the gate strip 160 comprising a horizontal gate strip portion 160H overlying the horizontal gate dielectric portion 150H and a tubular gate strip portion 160T laterally surrounding the tubular gate dielectric portion 150T. The horizontal portion of the gate strip 160H may be coupled to a gate electrode via 168, and the gate electrode via 168 may extend vertically through the interconnect dielectric layer. The gated ferroelectric memory cell 200, 201 further comprises a metal top electrode 182 in contact with the top surface of the pillar shaped semiconductor channel 140. The metal top electrode 182 may be coupled to a metal top electrode via 188, and the metal top electrode via 188 may extend vertically through the interconnect dielectric layer.

In various embodiments, the pillar-shaped semiconductor channel 140 of the memory cell 200 may include a bottom surface in contact with the top surface of the ferroelectric dielectric layer 130; and the gated ferroelectric memory cell 200 includes a metal-ferroelectric-semiconductor (MFS) capacitor 100.

In one embodiment of the semiconductor device 301, the intermediate metal electrode 142 contacts the bottom surface of the columnar semiconductor channel 140 and the top surface of the ferroelectric dielectric layer 130; and gated ferroelectric memory cell 201 includes metal-ferroelectric-metal (MFM) capacitor 101.

In one embodiment of the semiconductor device 301, the periphery of the top surface of the intermediate metal electrode 142 coincides with the periphery of the bottom surface of the columnar semiconductor channel 140.

In one embodiment of the semiconductor device 300, the horizontal gate dielectric portion 150H and the tubular gate dielectric portion 150T may be connected portions of the continuously extending layer of dielectric material 150 and have the same thickness and the same material composition.

In one embodiment of the semiconductor device 300, the gate electrode strip 160 includes a horizontal gate electrode strip portion 160H and a tubular gate electrode strip portion 160T, which may be continuously extending gate electrode strip material and connecting portions of the same material composition.

In one embodiment of the semiconductor device 300, the annular top surface of the tubular gate dielectric portion 150T is located within the same horizontal plane as the top surface of the columnar semiconductor channel 140.

In one embodiment of the semiconductor device 300, the tubular gate electrode stripe portion 160T includes a ring-shaped top surface 161, the ring-shaped top surface 161 being vertically spaced apart from the top electrode 182 by a uniform vertical spacing.

In one embodiment of the semiconductor device 300, the semiconductor device 300 may include at least one row of gated ferroelectric memory cells 200, wherein each gated ferroelectric memory cell 200 within each row of gated ferroelectric memory cells may be disposed along a first horizontal direction. Furthermore, the metal bottom electrode 122 of each row of gated ferroelectric memory cells 200 comprises a portion of the respective first metal line 122 extending laterally along the first horizontal direction; and the metal top electrode of each row of gated ferroelectric memory cells comprises a portion of a respective second metal line 182 extending laterally in a second horizontal direction.

In one embodiment, the semiconductor device 300 may include a two-dimensional array of gated ferroelectric memory cells, wherein the two-dimensional array of gated ferroelectric memory cells 200 includes a plurality of columns of gated ferroelectric memory cells 200 and a plurality of rows of gated ferroelectric memory cells 200. Each row of gated ferroelectric memory cells 200 may include a respective group of gated ferroelectric memory cells arranged along a first horizontal direction with a first period. Each column of gated ferroelectric memory cells 200 may include a respective group of gated ferroelectric memory cells disposed at a second period along a second horizontal direction. Furthermore, each column gated ferroelectric memory cell 200 may comprise a gate strip 160, wherein the gate strip 160 may comprise a respective portion of the continuously extending gate strip material 160 laterally surrounding each columnar semiconductor channel 140 within a column gated ferroelectric memory cell 200.

In this manner, various embodiments may provide FeRAM devices (200, 300) with field controlled vertical current switches 600 of selectable memory elements 100 that may be fabricated in BEOL. The memory element 100 may include an MFM or MFS capacitor. By forming both the memory element 100 and the field controlled vertical current switch 600 of the memory element 100 in the selectable BEOL, memory density can be increased by utilizing the smaller area required to form the field controlled vertical current switch 600 of the selectable memory element 100. Furthermore, the field controlled vertical current switch 600 may be directly coupled to the memory element 100. Therefore, the gated ferroelectric memory cell 200 including the field controlled vertical current switch 600 in direct contact with the memory element 100 has a more compact configuration than other configurations. For example, other configurations may include transistors disposed below the word lines or on the memory cell side. Accordingly, gating ferroelectric memory cell 200 may allow for higher memory cell densities than conventional memory structures.

In addition, the GAA gate electrode strip 160 laterally surrounding the columnar semiconductor channel 140 provides better gate control. Application of a voltage to the GAA gate electrode strap 160 can selectively control the current flow to the memory element 100. The gate strips 160 may provide a gate voltage to the field controlled vertical current switch 600 to control the current flowing through the pillar shaped semiconductor channel 140 and the memory element 100.

Each memory element 100 may include a ferroelectric dielectric layer 130 that provides a tunnel barrier. Thus, memory element 100 may be referred to as a FE memory cell. In various embodiments, a portion of the columnar semiconductor channel 140 (e.g., the drain side of the channel) directly contacts the ferroelectric dielectric layer 130 and may operate as a top electrode, a portion of the first metal line 122 may operate as a bottom electrode, and a portion of the ferroelectric dielectric layer 130 may operate as an FE tunnel barrier.

In various embodiments, the memory element 100 may operate as a Ferroelectric Tunnel Junction (FTJ). In particular, the FE tunnel barrier may be a ferroelectric thin film that is sufficiently thin to allow electrons to tunnel therethrough. For example, FE tunnel barrier 130 may be about 1 nanometer (nm) to about 50 nanometers thick, such as from about 5 nanometers to about 25 nanometers, or about 10 nanometers thick.

According to another embodiment of the present invention, a semiconductor device 300 is provided comprising a two-dimensional array of at least one gated ferroelectric memory cell 200, wherein each of the at least one two-dimensional array of gated ferroelectric memory cells 200 comprises: a first metal line 122 embedded in the first dielectric material layer 120 and extending laterally in a first horizontal direction; a ferroelectric dielectric layer 130 extending continuously over the first metal line 122; a two-dimensional array of columnar semiconductor channels 140 overlying the ferroelectric dielectric layer 130, wherein each row of columnar semiconductor channels 140 is disposed in a first horizontal direction and is capacitively coupled to a respective one of the first metal lines 122; a gate dielectric layer 150 comprising a horizontal gate dielectric portion overlying the ferroelectric dielectric layer 130 and a tubular gate dielectric portion laterally surrounding the columnar semiconductor channel 140; gate electrode strips 160 laterally surrounding the respective columns of the columnar semiconductor channels 140, the columnar semiconductor channels 140 being disposed in the second horizontal direction and laterally spaced from each other in the first horizontal direction; and second metal lines 182 embedded in the second dielectric material layer 180, the second metal lines 182 extending laterally in the first horizontal direction and contacting top surfaces of the respective rows of pillar-shaped semiconductor channels 140.

In one embodiment, the pillar-shaped semiconductor channel 140 of the semiconductor device 300 is in contact with the top surface of the ferroelectric dielectric layer 130. In another embodiment, each of the two-dimensional array of at least one gated ferroelectric memory cell 201 includes a two-dimensional array of inter-metal electrodes 142 in contact with the ferroelectric dielectric layer 130 and in contact with a respective columnar semiconductor channel 140 within the two-dimensional array of columnar semiconductor channels 140.

Fig. 18 is a partial cross-sectional perspective view of a semiconductor memory device 400 according to various embodiments of the present disclosure. Referring to fig. 18, the memory device 400 includes a first two-dimensional array 300A of gated ferroelectric memory cells and a second two-dimensional array 300B of gated ferroelectric memory cells that are vertically stacked. Each of the first and second two-dimensional arrays (300A, 300B) of gated ferroelectric memory cells may be the same as any of the two-dimensional arrays 300 of gated ferroelectric memory cells described above. Thus, in an embodiment of the semiconductor device 300, the two-dimensional array of at least one gated ferroelectric memory cell comprises a plurality of two-dimensional arrays 300A, 300B of gated ferroelectric memory cells located above the common substrate and vertically stacked along a vertical direction perpendicular to the top surface of the common substrate 110.

The semiconductor memory device 400 may include a plurality of two-dimensional arrays of gated ferroelectric memory cells such as those shown in fig. 1A-17B. Accordingly, the semiconductor memory device 400 may provide a higher memory density than a memory device including only a single memory device layer. Although two-dimensional arrays 300 of gated ferroelectric memory cells (200 or 201) are shown in fig. 18, the memory device 400 may include additional two-dimensional arrays 300 of gated ferroelectric memory cells (200 or 201), e.g., 3 to 20 interconnected memory layers. The compact configuration of each individual memory layer further increases memory density.

Fig. 19 is a flow chart including steps for forming a semiconductor memory device 300, 301, 400 according to various embodiments of the present disclosure. Referring to fig. 2A-2C and 19, in operation 501, a first metal line 122 extending in a first horizontal direction may be formed within an upper portion of the dielectric material layer 120. Referring to fig. 3A-3C and 19, in operation 502, a ferroelectric dielectric layer 130 may be deposited over the top surface of the first metal line 122. Referring to fig. 4A-5B and 19, in operation 503, a two-dimensional array of pillar-shaped semiconductor channels 140 may be formed over the ferroelectric dielectric layer 130, wherein each row of pillar-shaped semiconductor channels 140 is formed over and capacitively coupled to a respective one of the first metal lines 122. Referring to fig. 6A, 6B, and 19, in operation 504, a gate dielectric layer 150 may be deposited over the two-dimensional array of columnar semiconductor channels 140. Referring to fig. 7A-11A and 19, in operation 505, gate strips 160 may be formed over the gate dielectric layer 150, wherein each gate strip 160 laterally surrounds a respective column of the columnar semiconductor channels 140. Referring to fig. 12A, 12B, and 19, in operation 506, second metal lines 182 may be formed on the two-dimensional array of pillar-shaped semiconductor channels 140, wherein each second metal line 182 may be formed directly on a top surface of a corresponding row of pillar-shaped semiconductor channels 140.

According to various embodiments, memory structures and devices are provided that have a higher memory cell density than existing memory configurations.

Some embodiments of the present application provide a semiconductor device, including: at least one gated ferroelectric memory cell comprising: a dielectric material layer disposed over the substrate; a metal bottom electrode; and a ferroelectric dielectric layer in contact with a top surface of the metal bottom electrode; a columnar semiconductor channel overlying the ferroelectric dielectric layer and capacitively coupled to the metal bottom electrode through the ferroelectric dielectric layer; a gate dielectric layer comprising a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the columnar semiconductor channel; a gate strip including a horizontal gate electrode portion overlying the horizontal gate dielectric portion and a tubular gate electrode portion laterally surrounding the tubular gate dielectric portion; and a metal top electrode in contact with a top surface of the columnar semiconductor channel.

In some embodiments, the columnar semiconductor channel includes a bottom surface in contact with a top surface of the ferroelectric dielectric layer; and the gated ferroelectric memory cell comprises a metal-ferroelectric-semiconductor (MFS) capacitor. In some embodiments, an intermediate metal electrode contacts a bottom surface of the columnar semiconductor channel and a top surface of the ferroelectric dielectric layer; and the gated ferroelectric memory cell comprises a metal-ferroelectric-metal (MFM) capacitor. In some embodiments, a periphery of a top surface of the intermediate metal electrode coincides with a periphery of the bottom surface of the columnar semiconductor channel. In some embodiments, the horizontal gate dielectric portion and the tubular gate dielectric portion are connected portions of a continuously extending layer of dielectric material and have the same thickness and the same material composition. In some embodiments, the horizontal gate electrode strip portion and the tubular gate electrode strip portion are connected portions of gate electrode strip material that extend continuously and have the same material composition. In some embodiments, the tubular gate electrode strip portion includes an annular top surface vertically spaced from the top electrode by a uniform vertical spacing. In some embodiments, an annular top surface of the tubular gate dielectric portion is located within the same horizontal plane as the top surface of the columnar semiconductor channel. In some embodiments, the semiconductor device further comprises: at least one row of gated ferroelectric memory cells including the at least one gated ferroelectric memory cell, wherein: the gated ferroelectric memory cells in each row of gated ferroelectric memory cells are arranged in a first horizontal direction; the metal bottom electrode of each row of gated ferroelectric memory cells comprises a portion of a respective first metal line extending laterally along the first horizontal direction; and the metal top electrode of each row of gated ferroelectric memory cells comprises a portion of a respective second metal line extending laterally along the second horizontal direction. In some embodiments, the semiconductor device further comprises: a two-dimensional array of gated ferroelectric memory cells, comprising: the at least one row of gated ferroelectric memory cells arranged in a first horizontal direction with a first period; at least one column of gated ferroelectric memory cells arranged with a second periodicity along a second horizontal direction, wherein the at least one column of gated ferroelectric memory cells comprises a corresponding group of gated ferroelectric memory cells, wherein the at least one column of gated ferroelectric memory cells comprises a gate strip, wherein the gate strip comprises a corresponding portion of continuously extending gate strip material laterally surrounding each columnar semiconductor channel within the at least one column of gated ferroelectric memory cells.

Other embodiments of the present application provide a semiconductor device, including: at least one two-dimensional array of gated ferroelectric memory cells, wherein each of the at least one two-dimensional array of gated ferroelectric memory cells comprises: a first metal line embedded in the first dielectric material layer and extending laterally along a first horizontal direction; and a ferroelectric dielectric layer extending continuously over the first metal line; a two-dimensional array of columnar semiconductor channels overlying the ferroelectric dielectric layer, wherein each row of columnar semiconductor channels is disposed along the first horizontal direction and capacitively coupled to a respective one of the first metal lines; a gate dielectric layer comprising a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the columnar semiconductor channel; gate electrode strips laterally surrounding respective columns of columnar semiconductor channels disposed along the second horizontal direction and laterally spaced from each other along the first horizontal direction; and a second metal line embedded in the second dielectric material layer, extending laterally along the first horizontal direction, and contacting top surfaces of the columnar semiconductor channels of the corresponding row.

In some embodiments, each of the two-dimensional array of columnar semiconductor channels is in contact with a top surface of the ferroelectric dielectric layer. In some embodiments, each of the at least one two-dimensional array of gated ferroelectric memory cells includes a two-dimensional array of intermediate metal electrodes in contact with the ferroelectric dielectric layer and in contact with a respective one of the two-dimensional array of columnar semiconductor channels. In some embodiments, the at least one two-dimensional array of gated ferroelectric memory cells comprises a plurality of two-dimensional arrays of gated ferroelectric memory cells located above a common substrate and vertically stacked along a vertical direction perpendicular to a top surface of the common substrate.

Still further embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a first metal line extending in a first horizontal direction in an upper portion of the dielectric material layer; depositing a ferroelectric dielectric layer over a top surface of the first metal line; forming a two-dimensional array of columnar semiconductor channels over the ferroelectric dielectric layer, wherein each row of columnar semiconductor channels is formed over and capacitively coupled to a respective one of the first metal lines; depositing a gate dielectric layer over the two-dimensional array of columnar semiconductor channels; forming gate strips over the gate dielectric layer, wherein each gate strip laterally surrounds a respective column of columnar semiconductor channels; and forming second metal lines over the two-dimensional array of columnar semiconductor channels, wherein each second metal line is formed directly on a top surface of a corresponding row of columnar semiconductor channels. In some embodiments, the method further comprises: depositing a dielectric matrix layer over the gate electrode strip; and planarizing the dielectric matrix layer, the gate strip, and the gate dielectric layer, wherein: each of the columnar semiconductor channels within the two-dimensional array of columnar semiconductor channels has a respective top surface lying within a horizontal plane, the respective top surface comprising a planarized top surface of the dielectric matrix layer; and each gate strip has an annular top surface column located within the horizontal plane, the annular top surface column comprising the planarized top surface of the dielectric matrix layer.

In some embodiments, the method further comprises: vertically recessing each annular top surface of the gate electrode strip relative to the planarized top surface of the dielectric matrix layer and top surfaces of the two-dimensional array of columnar semiconductor channels; and depositing a ring of dielectric fill material within each cavity formed by vertically recessing the annular top surface of the gate electrode strip. In some embodiments, forming the two-dimensional array of pillar-shaped semiconductor channels comprises: depositing a layer of semiconductor channel material over the ferroelectric dielectric layer; forming a two-dimensional array of etch mask material portions over the layer of semiconductor channel material; and anisotropically etching unmasked portions of the semiconductor channel material layer selective to the ferroelectric dielectric layer using the two-dimensional array of etch mask material portions as an etch mask, wherein remaining portions of the semiconductor channel material layer comprise the two-dimensional array of pillar-shaped semiconductor channels. In some embodiments, the method further comprises: depositing an intermediate metal electrode material layer over the ferroelectric dielectric layer, wherein the semiconductor channel material layer is deposited on the intermediate metal electrode material layer; and using the two-dimensional array of etch mask material portions as an etch mask to pattern the intermediate metal electrode material layer into a two-dimensional array of intermediate metal electrodes. In some embodiments, the method further comprises: depositing a layer of gate electrode material over the gate dielectric layer; applying and patterning a photoresist layer over the layer of gate electrode material to provide a plurality of patterned photoresist strips overlying respective columns of columnar semiconductor channels; and etching unmasked portions of the layer of gate electrode material, wherein remaining portions of the layer of gate electrode material comprise the gate electrode strips.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.