阅读说明：本技术 一种非易失性存储器的制备方法 (Preparation method of nonvolatile memory ) 是由 张傲峰 李建财 于 2020-04-10 设计创作，主要内容包括：本发明公开了一种非易失性存储器的制备方法,属于集成电路技术领域。本发明的制备方法至少包括以下步骤：提供一衬底；在所述衬底中形成至少两个隔离结构,每个所述隔离结构的顶面高于所述衬底表面；采用等向性蚀刻在所述隔离结构侧壁与相邻所述衬底侧壁之间形成一凹部；在所述衬底表面及所述衬底侧壁上形成隧穿氧化层；在所述隧穿氧化层上形成栅极层,所述栅极层覆盖所述隧穿氧化层和所述凹部。本发明形成的栅极与衬底之间形成多个电流隧穿通道控制面,有效的提高了栅极对于电流隧穿通道的控制能力,减少漏电,提高了非易失性存储器的饱和电流。(The invention discloses a preparation method of a nonvolatile memory, and belongs to the technical field of integrated circuits. The preparation method at least comprises the following steps: providing a substrate; forming at least two isolation structures in the substrate, wherein the top surface of each isolation structure is higher than the surface of the substrate; forming a concave part between the side wall of the isolation structure and the adjacent side wall of the substrate by adopting isotropic etching; forming a tunneling oxide layer on the surface and the side wall of the substrate; and forming a gate layer on the tunneling oxide layer, wherein the gate layer covers the tunneling oxide layer and the recess. A plurality of current tunneling channel control surfaces are formed between the grid electrode and the substrate, so that the control capability of the grid electrode on the current tunneling channels is effectively improved, the electric leakage is reduced, and the saturation current of the nonvolatile memory is improved.)

1. A method for preparing a nonvolatile memory is characterized by at least comprising the following steps:

providing a substrate;

forming at least two isolation structures in the substrate, wherein the top surface of each isolation structure is higher than the surface of the substrate;

forming a concave part between the side wall of the isolation structure and the adjacent side wall of the substrate by adopting isotropic etching;

forming a tunneling oxide layer on the surface and the side wall of the substrate;

and forming a gate layer on the tunneling oxide layer, wherein the gate layer covers the tunneling oxide layer and the recess.

2. The method of claim 1, wherein the gate layer comprises a floating gate layer, a dielectric layer and a control gate layer stacked one on another.

3. The method of claim 1, wherein a radius of curvature of a curved surface where the recess and the sidewall of the substrate adjoin is different from a radius of curvature of a curved surface where the recess and the sidewall of the isolation structure adjoin.

4. The method of claim 1, wherein the step of forming the gate layer comprises:

forming a floating gate layer on the tunneling oxide layer, wherein the floating gate layer covers the tunneling oxide layer, the concave part and the isolation structure;

and flattening the floating gate layer to expose the surface of the isolation structure.

5. The method of claim 4, wherein the step of forming the gate layer further comprises:

forming a dielectric layer on the floating gate layer and the surface of the isolation structure;

and patterning the dielectric layer to form a second groove, wherein the second groove exposes the surface of the isolation structure.

6. The method of claim 5, wherein the step of forming the gate layer further comprises:

forming a control gate layer on the dielectric layer, wherein the control gate layer fills the second groove;

and patterning the control gate layer to expose the surface of the isolation structure.

7. The method of claim 1, wherein the isotropic etching is wet etching.

8. The method as claimed in claim 1, wherein the step of forming the isolation structure comprises:

forming a pad oxide layer and a barrier layer on the substrate;

and etching the barrier layer, the pad oxide layer and the substrate to form a first groove.

9. The method as claimed in claim 8, wherein the step of forming the isolation structure further comprises:

depositing an insulating material within the first trench;

an upper surface of the insulating material is made flush with an upper surface of the barrier layer.

10. The method of claim 9, wherein the step of forming the isolation structure further comprises:

and removing the barrier layer after the planarization treatment is carried out on the surface of the insulating material deposited in the first groove.

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a preparation method of a nonvolatile memory.

Background

Non-Volatile Memory (NVM) is all forms of solid-state Memory that does not require periodic refreshing of data stored in the Memory. Non-volatile memory includes all forms of read-only memory (ROM), such as programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable read-only memory (EEPROM), and Flash memory (Flash), as well as battery-powered Random Access Memory (RAM). As device feature sizes continue to shrink and integration continues to increase, conventional non-volatile memories based on charge storage face physical and technological limits. As the process size of the nonvolatile memory is continuously reduced, the short channel effect sce (short channel effect) is greatly affected, which results in the decrease of the control capability of the gate to the current channel and the increase of the leakage current.

Disclosure of Invention

The invention aims to provide a preparation method of a nonvolatile memory, which solves the problem that the control capability of a grid electrode in the conventional nonvolatile memory to a current tunneling channel is weak.

In order to solve the technical problems, the invention is realized by the following technical scheme:

the invention also provides a preparation method of the nonvolatile memory, which at least comprises the following steps:

providing a substrate;

forming at least two isolation structures in the substrate, wherein the top surface of each isolation structure is higher than the surface of the substrate;

forming a concave part between the side wall of the isolation structure and the adjacent side wall of the substrate by adopting isotropic etching;

forming a tunneling oxide layer on the surface and the side wall of the substrate;

and forming a gate layer on the tunneling oxide layer, wherein the gate layer covers the tunneling oxide layer and the recess.

In one embodiment of the invention, the gate layer includes a floating gate layer, a dielectric layer and a control gate layer which are stacked.

In one embodiment of the present invention, a radius of curvature of a curved surface where the recess and the substrate side wall adjoin is different from a radius of curvature of a curved surface where the recess and the isolation structure side wall adjoin.

In one embodiment of the present invention, the step of forming the gate layer includes:

forming a floating gate layer on the tunneling oxide layer, wherein the floating gate layer covers the tunneling oxide layer, the concave part and the isolation structure;

planarizing the floating gate layer to expose the surface of the isolation structure;

in one embodiment of the present invention, the step of forming the gate layer further includes:

forming a dielectric layer on the floating gate layer and the surface of the isolation structure;

and patterning the dielectric layer to form a second groove, wherein the second groove exposes the surface of the isolation structure.

In one embodiment of the present invention, the step of forming the gate layer further includes:

forming a control gate layer on the dielectric layer, wherein the control gate layer fills the second groove;

and patterning the control gate layer to expose the surface of the isolation structure.

In one embodiment of the invention, the isotropic etching is wet etching.

In one embodiment of the present invention, the forming process of the isolation structure includes:

forming a pad oxide layer and a barrier layer on the substrate;

and etching the barrier layer, the pad oxide layer and the substrate to form a first groove.

In one embodiment of the invention, an insulating material is deposited within the first trench;

an upper surface of the insulating material is made flush with an upper surface of the barrier layer.

In an embodiment of the present invention, the forming process of the isolation structure further includes:

and removing the barrier layer after the planarization treatment is carried out on the surface of the insulating material deposited in the first groove.

The invention forms the grid structure with a plurality of current tunneling channel control surfaces in the nonvolatile memory structure, thereby effectively increasing the control capability of the grid on the current tunneling channels and reducing the electric leakage. In addition, the grid structure with a plurality of current tunneling channel control surfaces can increase the width of an effective current tunneling channel, so that the saturation current of the nonvolatile memory is improved, and the charge acquisition capacity is improved in practical application. Due to the increase of the width of the effective current tunneling channel, the device can be miniaturized to a certain extent in the horizontal direction while the original performance is kept, so that the device achieves a higher integration level.

Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a flow chart of a method for fabricating a non-volatile memory structure according to an embodiment of the present invention;

fig. 2-6 are schematic structural diagrams corresponding to step S2 in fig. 1;

fig. 6 and 7 are schematic structural diagrams corresponding to step S3 in fig. 1;

FIG. 8 is a schematic view of a portion of the structure of FIG. 7;

FIG. 9 is a schematic structural diagram corresponding to step S4 in FIG. 1;

FIG. 10 is a schematic structural diagram corresponding to step S5 in FIG. 1;

fig. 11-17 are schematic structural diagrams corresponding to a method for manufacturing a non-volatile memory structure according to another embodiment of the invention.

Fig. 18 is a schematic structural view in another direction of fig. 17.

Reference numerals

100 a substrate; 200 source electrodes; 300 drain electrode; a 400 grid electrode; 500 an isolation structure; 600 recess; 401 pad oxide layer; 402 a barrier layer; 403 carbon layers; 404 a antireflection layer; 405 a first patterned photoresist layer; 406 a first oxide layer; 407P well; 408N well; 409 a second patterned photoresist layer; 410 tunneling through the oxide layer; 411 a floating gate layer; 412 a first silicon oxide layer; 413 a silicon nitride layer; 414 a second silicon dioxide layer; 415 a third patterned photoresist layer; 416 a second trench; 417 a control gate layer; 419 a dielectric layer; 501 first trenches.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1 and 18, the nonvolatile memory of the present invention may include a plurality of memory cells, and in one embodiment, the nonvolatile memory structure may include a plurality of memory cells, each memory cell including a substrate 100, a source 200, a drain 300, and a gate 400, wherein the substrate 100 may include, but is not limited to, a single crystal or polycrystalline semiconductor material, and the substrate 100 may further include an intrinsic single crystal silicon substrate 100 or a doped silicon substrate 100. The substrate 100 includes a substrate 100 of a first doping type, where the first doping type may be a P-type or an N-type, and in this embodiment, only the first doping type is a P-type, that is, in this embodiment, the substrate 100 only exemplifies a P-type substrate 100, such as a P-type silicon substrate 100. In some embodiments, the substrate 100 may also be a single crystal silicon substrate 100, a Ge substrate 100, a SiGe substrate 100, a Silicon On Insulator (SOI), or any combination thereof, and an appropriate semiconductor material may be selected as the substrate 100 according to the actual requirements of the device, which is not limited herein. In some embodiments, the substrate 100 may also be composed of a compound semiconductor material, such as a III-V semiconductor material or a II-VI semiconductor material. On the substrate 100, a gate 400 structure is formed on the substrate 100 by chemical vapor deposition, physical vapor deposition, photolithography, and the like, and then a source 200/a drain 300 are respectively formed on both sides of the gate 400 structure by ion implantation, so as to obtain the memory cell, and a plurality of memory cells are connected to obtain the nonvolatile memory of the present invention.

Referring to fig. 1 and 18, in one embodiment of the present invention, the following process steps, but not limited to, are considered to have been completed on the substrate 100: a region corresponding to the memory cell on the substrate 100 is provided with well implants such as a P-well 407 implant and an N-well 408 implant. In addition, only one complete gate 400 structure and two adjacent partial gate 400 structures are shown in the drawings, but it should be understood by those skilled in the art that, in order to clearly express the core idea of the present application, only the devices and structures of the memory partial memory cell region are shown in the drawings in a schematic form, which does not represent that the memory process related to the present invention only includes these parts, and well-known memory structures and process steps can also be included therein.

Referring to fig. 17, the gate 400 in this embodiment may be a stacked gate structure, and specifically includes a tunnel oxide layer 410, a floating gate layer 411, a dielectric layer 419, and a control gate layer 417 stacked in sequence on the surface of the substrate 100, where the control gate layer 417 and the floating gate layer 411 may be made of polysilicon, and can perform data writing and erasing through a tunneling effect.

Referring to fig. 17, in the structure of the non-volatile memory of this embodiment, the floating gate layer 411 is electrically isolated, so that electrons reaching the gate 400 are captured even after the voltage is removed, which is the principle of the non-volatility of the non-volatile memory. The threshold voltage of the nonvolatile memory structure in this embodiment depends on the amount of charge stored in the floating gate layer 411, and the more the charge, the higher the threshold voltage. When the voltage applied to the control gate layer 417 is higher than the threshold voltage, the nonvolatile memory structure starts to be turned on. Thus, by measuring its threshold voltage and comparing it to a fixed voltage level to identify the information stored in the non-volatile memory structure, referred to as a read operation of the non-volatile memory structure, electrons can be placed in the floating gate layer 411 using fowler-nordheim tunneling, for which a strong electric field is applied between the negatively charged source 200 and the positively charged control gate layer 417, which causes electrons from the source 200 to tunnel through the tunnel oxide layer 410 and to the floating gate layer 411, the voltage required for tunneling depending on the thickness of the tunnel oxide layer. By applying a strong negative voltage on the control gate layer 417 and a strong positive voltage on the source 200 and drain 300 terminals, electrons can be removed from the floating gate layer 411 using fowler-nordheim tunneling, which will cause the trapped electrons to return to the tunnel through the tunnel oxide layer 410. In a non-volatile memory structure, placing electrons in the floating gate layer 411 is considered a program/write operation, and removing electrons is considered an erase operation.

Referring to fig. 17, in another embodiment of the present invention, the nonvolatile memory includes a plurality of memory cells, each memory cell including: the semiconductor device includes a substrate 100, at least two isolation structures 500, a recess 600, a tunnel oxide layer 410, a floating gate layer 411, a first silicon oxide layer 412, a silicon nitride layer 413, and a second silicon oxide layer 414.

Referring to fig. 1 to 18, the memory cell substrate 100 material may include, but is not limited to, single crystal or polycrystalline semiconductor material, and the substrate 100 may also include an intrinsic single crystal silicon substrate 100 or a doped silicon substrate 100. The substrate 100 includes a substrate 100 of a first doping type, which may be a P-type substrate or an N-type substrate, and in this embodiment, only the first doping type is a P-type substrate, that is, in this embodiment, the substrate 100 only exemplifies a P-type substrate 100, for example, a P-type silicon substrate 100. In some embodiments, the substrate 100 may also be a single crystal silicon substrate 100, a Ge substrate 100, a SiGe substrate 100, a Silicon On Insulator (SOI), or any combination thereof, and an appropriate semiconductor material may be selected as the substrate 100 according to the actual requirements of the device, which is not limited herein. In some embodiments, the substrate 100 may also be composed of a compound semiconductor material, such as a III-V semiconductor material or a II-VI semiconductor material.

Referring to fig. 17, at least two isolation structures 500, one end of each isolation structure 500 is located in the substrate 100, and the top surface of the isolation structure 500 is higher than the surface of the substrate 100. In some embodiments, the nonvolatile memory may further include a plurality of isolation structures 500, the plurality of isolation structures 500 divides the nonvolatile memory into a plurality of memory cells, and the plurality of memory cells may be distributed in parallel at intervals, or may be randomly arranged according to the semiconductor structure. In this embodiment, the adjacent isolation structures 500 and the region of the substrate 100 therebetween form a high voltage device memory cell region or a low voltage device memory cell region.

Referring to fig. 17, in the present embodiment, the isolation structure 500 is, for example, a shallow trench isolation structure 500, the isolation structure 500 is an inverted trapezoid, and one end of the isolation structure 500 is located in the substrate 100, so that an inclined sidewall is formed at a joint of the substrate 100 and the isolation structure 500, the isolation structure 500 is made of, for example, silicon oxide, silicon nitride or silicon oxynitride, and a width of the isolation structure 500 can be set according to design requirements of the semiconductor structure.

Referring to fig. 17, a concave portion 600 is disposed between two sidewalls of the isolation structure 500 and the adjacent sidewall of the substrate 100, the cross section of the concave portion 600 is an arc curve, specifically, the curvature radius of the curved surface adjacent to the sidewalls of the concave portion 600 and the substrate 100 may be the same as or different from the curvature radius of the curved surface adjacent to the sidewalls of the concave portion 600 and the isolation structure 500, in this embodiment, the curvature radius of the curved surface adjacent to the sidewalls of the concave portion 600 and the substrate 100 is different from the curvature radius of the curved surface adjacent to the sidewalls of the concave portion 600 and the isolation structure 500.

Referring to fig. 17, a tunnel oxide layer 410 is disposed on the substrate 100, the tunnel oxide layer 410 covers the surface of the substrate 100 and the sidewall of the substrate 100, the tunnel oxide layer 410 may be made of silicon oxide, for example, in this embodiment, the tunnel oxide layer 410 made of silicon oxide may be formed by furnace oxidation, rapid thermal annealing oxidation, in-situ steam oxidation or other thermal oxidation methods.

Referring to fig. 17, a floating gate layer 411 is disposed on the tunnel oxide layer 410, the floating gate layer 411 covers the tunnel oxide layer 410 and the recess 600, an upper surface of the floating gate layer 411 is flush with an upper surface of the isolation structure 500, the floating gate layer 411 may be made of doped polysilicon, or the polysilicon may be deposited in an undoped form and then implanted to form doped polysilicon. In other embodiments, other suitable conductive materials may be used in place of doped polysilicon.

Referring to fig. 17, due to the existence of the recess 600, a plurality of current tunneling channel control surfaces are formed between the floating gate layer 411 and the tunnel oxide layer 410, which in this embodiment includes three current tunneling channel control surfaces, for example, the three current tunneling channel control surfaces include the upper surface of the substrate 100 and the curved surfaces of the two sides of the substrate 100 adjacent to the adjacent recess 600. As the number of control surfaces of the current tunneling channel increases, the effective width of the current tunneling channel increases, so that the control force of the gate 400 on the current tunneling channel is stronger, which is beneficial to reducing the leakage. The recess 600 between the sidewall of the isolation structure 500 and the sidewalls of the substrates 100 on both sides effectively increases the effective width of the current tunneling channel, so that the control capability of the gate 400 on the current tunneling channel is further enhanced, the saturation current of the nonvolatile memory can be improved, and the charge acquisition capability is increased in practical application. Due to the increase of the width of the effective current tunneling channel, the device can be miniaturized to a certain extent in the horizontal direction while the original performance is kept, so that the device achieves a higher integration level.

Referring to fig. 17, each individual floating gate layer 411 is electrically isolated from the substrate 100 by a tunnel oxide layer 410, such electrical isolation allows the floating gate layer 411 to function as a charge storage cell, the tunnel oxide layer 410 allows charge to enter the floating gate under certain conditions, the charge level in the floating gate may correspond to a logic level, and thus data may be stored in the storage cell. The recess 600 between the sidewall of the isolation structure 500 and the sidewall of the substrate 100 effectively increases the width of the current tunneling channel, so that the control capability of the gate 400 on the current tunneling channel is further enhanced, and the other three sides of the gate structure can increase the width of the effective current tunneling channel, thereby improving the saturation current of the nonvolatile memory and increasing the charge acquisition capability in practical application. Due to the increase of the width of the effective current tunneling channel, the device can be miniaturized to a certain extent in the horizontal direction while the original performance is kept, so that the device achieves a higher integration level.

Referring to fig. 17, in another embodiment of the present invention, the structure of the non-volatile memory further includes a control gate layer 417, the control gate layer 417 is located on a side of the floating gate layer 411 facing away from the substrate 100 and is isolated from the floating gate layer 411 by a dielectric layer 419, the control gate layer 417 can be a conductive gate formed of doped polysilicon, by applying a strong negative voltage on the control gate layer 417 and a strong positive voltage on the source 200 and drain 300 terminals, electrons can be removed from the floating gate layer 411 using fowler-nordheim tunneling effect, which will cause electrons trapped in the floating gate layer 411 to tunnel back through the tunnel oxide layer 410, and this process of removing electrons is considered as an operation of erasing the non-volatile memory.

Referring to fig. 17, in another embodiment of the present invention, the dielectric layer 419 is located between the floating gate layer 411 and the control gate layer 417, the dielectric layer 419 separates the control gate layer 417 from the floating gate layer 411 and cannot be directly electrically connected to the floating gate layer 411, and the dielectric layer 419 may include a silicon oxide layer and a silicon nitride layer sequentially stacked on the surface of the floating gate layer 411, where the silicon oxide layer may be, for example, silicon oxynitride or silicon dioxide, specifically, the silicon oxide layer covers the surface of the floating gate layer 411, and the silicon nitride layer is stacked on the surface of the silicon oxide layer. In some embodiments, the dielectric layer 419 may further include a first silicon oxide layer 412, a silicon nitride layer 413, and a second silicon oxide layer 414 sequentially stacked on the surface of the floating gate layer 411. In this embodiment, the silicon oxide layer and the silicon nitride layer may be formed by a chemical vapor deposition process. In this embodiment, the thickness of each layer of the dielectric layer may be set by using the existing process, and specifically, may include a first silicon oxide layer 412, a silicon nitride layer 413, and a second silicon oxide layer 414, which have a conventional thickness and are sequentially located on the surface of the floating gate layer 411.

Referring to fig. 1, the present invention provides a method for manufacturing a nonvolatile memory, which at least includes the following steps:

s1, providing a substrate 100;

s2, forming at least two isolation structures 500 on the substrate 100, wherein the top surface of each isolation structure 500 is higher than the surface of the substrate;

s3, forming a concave part between the side wall of the isolation structure and the side wall of the adjacent substrate by adopting isotropic etching;

s4, forming tunneling oxide layers on the surface and the side wall of the substrate;

and S5, forming a grid layer on the tunneling oxide layer, wherein the grid layer covers the tunneling oxide layer and the concave part.

The method for manufacturing the non-volatile memory according to the present invention is described in detail below with reference to fig. 1 to 18.

Referring to fig. 1 and fig. 2, in the present embodiment, for example, to prepare a memory cell, specifically, in step S1, a substrate 100 is first provided, the material of the substrate 100 may include, but is not limited to, a single crystal or polycrystalline semiconductor material, and the substrate 100 may further include an intrinsic single crystal silicon substrate 100 or a doped silicon substrate 100. The substrate 100 includes a substrate 100 of a first doping type, where the first doping type may be a P-type or an N-type, and in this embodiment, only the first doping type is a P-type, that is, in this embodiment, the substrate 100 only exemplifies a P-type substrate 100, such as a P-type silicon substrate 100. In some embodiments, the substrate 100 may also be a single crystal silicon substrate 100, a Ge substrate 100, a SiGe substrate 100, a Silicon On Insulator (SOI), or any combination thereof, and an appropriate semiconductor material may be selected as the substrate 100 according to the actual requirements of the device, which is not limited herein. In some embodiments, the substrate 100 may also be composed of a compound semiconductor material, such as a III-V semiconductor material or a II-VI semiconductor material.

Referring to fig. 1 and 2, in step S2, a pad oxide layer 401 is formed on the substrate 100, the pad oxide layer 401 may be made of, for example, silicon oxide or silicon oxynitride, and the pad oxide layer 401 may be formed by, for example, furnace oxidation, rapid thermal annealing oxidation, in-situ steam oxidation or other thermal oxidation methods, and a nitridation process may be performed on the silicon oxide to form silicon oxynitride, wherein the nitridation process may be high temperature furnace nitridation, rapid thermal annealing nitridation, plasma nitridation or other nitridation processes.

Referring to fig. 1 and 2, in step S2, a barrier layer 402 is formed on a side of the pad oxide layer 401 away from the substrate 100, the pad oxide layer 401 is used to reduce stress between the substrate 100 and the barrier layer 402, and the barrier layer 402 is used to protect an active region in a subsequent etching process.

Referring to fig. 1 and 2, in other embodiments, the carbon layer 403 and/or the anti-reflection layer 404 may be formed on the barrier layer 402 by physical vapor deposition or chemical vapor deposition.

Referring to fig. 1, 3 to 6, in step S2, at least two isolation structures 500 are formed on the substrate 100, the two isolation structures 500 are used to separate the adjacent gate structures 400 formed later, and the isolation structures 500 may be, for example, shallow trench isolation structures 500. In some embodiments, a plurality of isolation structures 500 may also be formed in the substrate 100, the plurality of isolation structures 500 divides the substrate 100 into a plurality of regions, and the plurality of regions may be distributed in parallel at intervals, or may be arbitrarily arranged according to the semiconductor structure. In this embodiment, the region of the substrate 100 between adjacent isolation structures 500 constitutes a high voltage device region or a low voltage device region.

Referring to fig. 1, fig. 3 and fig. 4, in step S2, in the present embodiment, the isolation structure 500 includes: a first patterned photoresist layer 405 is formed on the antireflective layer 404, and the first patterned photoresist layer 405 exposes a portion of the antireflective layer 404, defining the location of the isolation structure 500 by the first patterned photoresist layer 405. In this embodiment, for example, the subtractive layer 404, the carbon layer 403, the barrier layer 402, and the pad oxide layer 401 may be etched by using a reactive ion etching or plasma etching process, in which the subtractive layer, the carbon layer 403, the barrier layer 402, and the pad oxide layer 401 are sequentially etched by using a reactive ion etching or plasma etching process to expose the surface material of the substrate 100, and then the substrate 100 is continuously etched by using a fluorine-containing etching gas, so as to form the first trench 501 extending into the substrate 100.

Referring to fig. 1, fig. 3 and fig. 4, in step S2, in some embodiments, a photoresist layer may be formed on the antireflective layer 404 by, for example, a spin coating method, an exposure and development process is performed to form an opening on the photoresist layer, a first patterned photoresist layer 405 is obtained, and the antireflective layer 404, the carbon layer 403, the barrier layer 402 and the pad oxide layer 401 under the opening pattern are removed by using the first patterned photoresist layer 405 as a mask until the substrate 100 is exposed. The substrate 100 is etched by a dry etching method to form a first trench 501, the antireflective layer 404 and the carbon layer 403 are also removed simultaneously during the formation of the first trench 501, and finally the photoresist layer 405 may be removed by an ashing method. The first trench 501 penetrates through the pad oxide layer 401 and the barrier layer 402 and extends into the substrate 100, and in some embodiments, an antireflection layer 404 may be further disposed directly on the barrier layer 402, so that the first trench 501 forms an inverted trapezoid shape during etching through an antireflection effect of the antireflection layer 404 on an etching beam. The first trench 501 region will form an isolation structure 500 in the subsequent manufacturing process, one end of the isolation structure 500 extends into the substrate 100, and the substrate 100 covered by the barrier layer 402 and the pad oxide layer 401 is used as an active region for forming a semiconductor device.

Referring to fig. 1, 3 to 5, in step S2, the specific steps of obtaining the isolation structure 500 include: first, a first oxide layer 406 is formed on the bottom surface and the sidewall of the substrate 100 by furnace oxidation, rapid thermal annealing oxidation, in-situ steam oxidation or other thermal oxidation methods, then an insulating material is deposited on the first trench 501 and the barrier layer 402 by using a high-density plasma chemical vapor deposition method to fill the first trench 501, and then the upper surface of the insulating material in the first trench 501 is flush with the upper surface of the barrier layer 402 by, for example, chemical mechanical polishing, so as to form the isolation structures 500, wherein the top surface of each of the isolation structures 500 is higher than the substrate surface. In the present embodiment, the material of the first oxide layer 406 may be, for example, silicon oxide, an insulating material such as silicon oxide, silicon nitride or silicon oxynitride, and the width of the isolation structure 500 may be set according to the design requirements of the semiconductor structure.

Referring to fig. 5, in step S2, the barrier layer 402 is removed by dry etching or wet etching to expose the pad oxide layer 401, in this embodiment, the barrier layer 402 is removed by wet etching, for example, using phosphoric acid or hydrofluoric acid as a reagent for wet etching.

Referring to fig. 5, in step S2, after removing the barrier layer 402, an ion implantation is performed on the substrate 100 region between the adjacent isolation structures 500, for example, forming a P-well 407 or an N-well 408 in the corresponding substrate 100 region, and the ion implantation source is preferably a phosphorus source, a boron source, or a fluorine source.

Referring to fig. 6 to 8, in step S3, the specific step of forming a recess 600 between the sidewall of the isolation structure 500 and the sidewall of the substrate 100 includes: after the isolation structure 500 is obtained, the pad oxide layer 401 is first removed by selective etching on the surface of the pad oxide layer 401, and the pad oxide layer 401 is removed by dry etching or wet etching in the etching process to expose the surface of the substrate 100. After the selective etching, isotropic etching, such as wet etching, is performed on the surface of the isolation structure 500 downward along the sidewall of the isolation structure 500, since the isotropic etching performs etching simultaneously in the vertical direction and the horizontal direction, the material used for the isolation structure 500 and the material used for the substrate 100 in the present embodiment have an etching effect simultaneously, so that a concave portion 600 having an arc-shaped curved profile is formed between the sidewall of the isolation structure 500 and the sidewall of the adjacent substrate 100, wherein the sidewall of the substrate 100 in the concave portion 600 is also in an arc-shaped cross-sectional shape due to being etched, and the composition of the etching reagent can be adjusted, so that the curvature radius of the curved surface adjacent to the sidewall of the concave portion 600 and the sidewall of the substrate 100 can be the same as or different from the curvature radius of the curved surface adjacent to the sidewall of the concave portion 600 and the sidewall of the substrate 100 can be different from the curvature radius of the curved surface adjacent to the sidewall of the concave portion 600 and the sidewall of the isolation structure 500, for example, the curvature radius of the curved surface adjacent to the concave portion 600 and the sidewall of the isolation structure 500 is different from the curvature of the concave portion 600 and the sidewall of the curved surface of the substrate 100 . In this embodiment, the etching reagent used in the wet etching may be, for example, a hydrofluoric acid solution, a mixed solution of nitric acid and hydrofluoric acid, a hot phosphoric acid solution, a potassium hydroxide solution, or the like, and in this embodiment, for example, hot phosphoric acid is used as the etching reagent.

Referring to fig. 9, in step S4, a tunnel oxide layer 410 is formed on the exposed surface of the substrate 100 and the sidewalls of the substrate 100 in the recess 600 at two sides thereof, where the tunnel oxide layer 410 is made of silicon oxide, and in the present embodiment, the tunnel oxide layer 410 made of silicon oxide is formed by, for example, furnace oxidation, rapid thermal annealing oxidation, in-situ steam oxidation or other thermal oxidation methods.

Referring to fig. 10, in step S5, a floating gate layer 411 is formed on a side of the tunnel oxide layer 410 away from the substrate 100, wherein the floating gate layer 411 may be made of doped polysilicon, or polysilicon may be deposited in an undoped form, and then implanted to form doped polysilicon. In other embodiments, other suitable conductive materials may be used in place of doped polysilicon.

Referring to fig. 11, in step S5, the specific step of forming the floating gate layer 411 on the tunnel oxide layer 410 includes: and depositing polysilicon on the surface of the tunneling oxide layer 410, the surface of the recess 600 and the surface of the isolation structure 500, and planarizing the deposited polysilicon until the surface of the isolation structure 500 is exposed, thereby obtaining the floating gate layer 411. The deposition and planarization processes described above are preferably performed using techniques conventional in the art, such as chemical mechanical planarization to planarize the polysilicon. In this embodiment, the floating gate layer 411 is used to store charges to set the threshold voltage characteristics of the memory cell, wherein the thermally induced grain size growth of the poly structure is reduced and the threshold voltage characteristics of the gate 400 structure are maintained by interacting with the poly structure through an impurity layer, such as impurities implanted into the poly structure of the poly floating gate.

Referring to fig. 11, the floating gate layer 411 contacts the tunnel oxide layer 410 to form a plurality of current tunneling channel control surfaces, which in this embodiment includes three current tunneling channel control surfaces, for example, the three current tunneling channel control surfaces include the upper surface of the substrate 100 and the surfaces formed by the curved sidewalls at the two sides of the substrate 100. The gate can control the current from the tunnel oxide layer 410 to the floating gate, and the control surface of the current tunnel increases, so the stronger the control force of the gate on the current tunnel. The concave part 600 formed between the side wall of the isolation structure 500 and the side walls of the substrates 100 at two sides effectively increases the number of control surfaces of the current tunneling channel, so that the control capability of the grid electrode on the current tunneling channel is further enhanced, and in addition, the width of the effective current tunneling channel can be increased by the three-sided grid structure, so that the saturation current of the nonvolatile memory is improved, and in practical application, the acquisition capability of charges is increased. Due to the increase of the width of the effective current tunneling channel, the device can be miniaturized to a certain extent in the horizontal direction while the original performance is kept, so that the device achieves a higher integration level.

Referring to fig. 12, in another embodiment, a dielectric layer 419 may be further formed on a side of the floating gate layer 411 away from the tunnel oxide layer 410, the dielectric layer 419 covers the floating gate layer 411 and the exposed surface of the isolation structure 500, and the dielectric layer 419 may include a silicon oxide layer and a silicon nitride layer sequentially formed on the surface of the floating gate layer 411, where the silicon oxide layer may be, for example, silicon oxynitride or silicon dioxide, specifically, the silicon oxide layer covers the exposed surfaces of the floating gate layer 411 and the isolation structure 500, and the silicon nitride layer is stacked on the surface of the silicon oxide layer. In some embodiments, the dielectric layer 419 may further include a first silicon oxide layer 412, a silicon nitride layer 413, and a second silicon oxide layer 414 sequentially formed on the surface of the floating gate layer 411. Specifically, in this embodiment, a first silicon oxide layer 412 is first formed on the exposed surface of the floating gate layer 411 and the isolation structure 500 by a chemical vapor deposition method, a silicon nitride layer 413 is then formed on the first silicon oxide layer 412 by, for example, a chemical vapor deposition method, and finally a second silicon oxide layer 414 is formed by a chemical vapor deposition method. In this embodiment, the thickness of each layer of the dielectric layer may be set by using the existing process, and specifically, may include a first silicon oxide layer 412, a silicon nitride layer 413, and a second silicon oxide layer 414, which are formed on the surface of the floating gate layer 411 in sequence and have a conventional thickness.

Referring to fig. 13 and 14, in some embodiments, a second patterned photoresist layer 409 is formed on a side of the dielectric layer 419 away from the floating gate layer 411, the second patterned photoresist layer 409 exposes a surface of the dielectric layer 419 corresponding to the first trench 501, and the second trench 416 is defined by the second patterned photoresist layer 409. In this embodiment, the dielectric layer 419 not covered by the second patterned photoresist layer 409 may be etched by, for example, a reactive ion etching or plasma etching process, and the etching is stopped until the upper surface of the isolation structure 500 is exposed, so as to form the second trench 416 penetrating through the dielectric layer 419 in the dielectric layer 419. The width of the second trench 416 may be equal to the width of the upper surface of the isolation structure 500, and in other embodiments, the width of the second trench 416 may be greater than the width of the upper surface of the isolation structure 500. After forming the second trench 416, the second patterned photoresist layer 409 is removed, which may be the same as the first patterned photoresist layer 405, and will not be described herein again.

Referring to fig. 15, in another embodiment, a control gate layer 417 is formed on a side of the dielectric layer 419 away from the floating gate layer 411, and the control gate layer 417 covers the dielectric layer 419 and fills the second trench 416. Dielectric layer 419 separates control gate layer 417 from floating gate layer 411 from direct electrical connection. Each individual floating gate layer 411 is electrically isolated from the substrate 100 by a tunnel oxide layer 410, which allows the floating gate layer 411 to act as a charge storage cell, the tunnel oxide layer 410 allowing charge to enter the floating gate under certain conditions, the charge level in the floating gate may correspond to a logic level, and thus data may be stored in the cell. The increased number of control surfaces of the current tunneling channel provides greater control of the tunneling charges from the floating gate layer 411 to the substrate 100. The recess 600 formed between the sidewall of the isolation structure 500 and the sidewall of the substrate 100 effectively increases the width of the current tunneling channel, so that the control capability of the gate on the tunneling charges is further enhanced.

Referring to fig. 16 to 18, a third patterned photoresist layer 415 is formed on a side of the control gate layer 417 away from the dielectric layer 419, where the third patterned photoresist layer 415 exposes a surface of the control gate layer 417 corresponding to the second trench 416, in this embodiment, a reactive ion etching or plasma etching process may be used to perform etching, that is, etching is performed downwards along a portion of the surface of the control gate layer 417 except the portion shielded by the third patterned photoresist layer 415 through the reactive ion etching or plasma etching process, and after the etching process penetrates through the control gate layer 417, the material of the control gate layer 417 filled in the second trench 416 is etched together until the upper surface of the isolation structure 500 is exposed, so as to obtain the nonvolatile memory structure of the present invention.

The above disclosure of selected embodiments of the invention is intended to be illustrative only. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.