阅读说明：本技术 用于高性能磁性随机存取存储器装置的自由层氧化与间隔物辅助磁性穿隧结蚀刻 (Free layer oxidation and spacer assisted magnetic tunneling junction etch for high performance magnetic random access memory devices ) 是由 杨毅 沈冬娜 王郁仁 于 2018-10-18 设计创作，主要内容包括：公开一种磁性穿隧结,其避免电性短路且改良资料保存。最顶盖层具有第一侧壁,其与多个氧化外部及自由层铁磁性中心部之间的结共平面,上述自由层具有自由层宽度。介电间隔物形成在第一侧壁及该些自由层氧化外部上。固定层具有实质上大于自由层宽度的一宽度,且在其上的第二侧壁是通过使用介电间隔物及盖层作为蚀刻掩模的自对准蚀刻而形成。侧壁层可形成在第二侧壁及介电间隔物上,但是不会降低MTJ性质,因为侧壁层不接触负责装置性能的自由层中心部及固定层中心部。固定层宽度＞自由层宽度,确保资料保存的更大容量,尤其当自由层宽度＜60纳米。(A magnetic tunneling junction is disclosed that avoids electrical shorting and improves data retention. The topmost layer has a first sidewall coplanar with junctions between the plurality of oxidized outer portions and the ferromagnetic center portion of the free layer, the free layer having a free layer width. Dielectric spacers are formed on the first sidewalls and the free layer oxide exteriors. The fixed layer has a width substantially greater than the width of the free layer and second sidewalls thereon are formed by self-aligned etching using the dielectric spacers and the capping layer as an etch mask. A sidewall layer may be formed on the second sidewall and the dielectric spacer, but without degrading MTJ properties because the sidewall layer does not contact the center portions of the free layer and the fixed layer responsible for device performance. The fixed layer width is larger than the free layer width, so that larger capacity of data storage is ensured, especially when the free layer width is smaller than 60 nanometers.)

1. A magnetic tunneling junction structure comprising:

(a) a first stack of layers, including an optional seed layer, a pinned layer, and a tunnel barrier layer, sequentially formed on a substrate and having a first width determined by a first sidewall, wherein the first sidewall is substantially vertically aligned with a top surface of the substrate;

(b) a second stack of layers, comprising:

(1) a free layer formed on the tunnel barrier layer, wherein the free layer has a ferromagnetic center portion and a plurality of oxidized outer portions each forming a junction with the free layer center portion; and

(2) a cap layer over the free layer center, wherein the free layer center and the cap layer have a free layer width, the free layer width being less than the first width, and the cap layer having a second sidewall coplanar with the junction; and

(c) a dielectric spacer adjacent the second sidewall and contacting a top surface of the free layer oxide outer portions, and wherein the dielectric spacer has an outer surface forming a third sidewall with an outer surface of the free layer oxide outer portions, and the dielectric spacer has a width that increases with increasing distance from a top surface of the cap layer.

2. The mtj of claim 1 wherein the first width is at least 20 angstroms greater than the free layer width such that a bottom surface of the outer oxidized portions of the free layers has a width of at least 10 angstroms on each side of a center portion of the free layer.

3. The mtj of claim 2 wherein the free layer width is less than 60 nm.

4. The mtj of claim 1 wherein the substrate is a bottom electrode in a memory device.

5. The mtj of claim 1 wherein the dielectric spacer comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, magnesium oxide, aluminum oxide, tantalum oxide, metal oxynitride, metal carbide, or metal nitride.

6. The mtj of claim 1 wherein the third sidewall connects the first sidewall near a top surface of the tunnel barrier.

7. The mtj of claim 1 wherein the second stack of layers further comprises a high-k promoting layer having the width of the free layer and contacting a top surface of the center portion of the free layer and a bottom surface of the cap layer and bounded by the second sidewall.

8. The mtj of claim 1 wherein the free layers are oxidized to have a stoichiometric oxidation state.

9. A method of fabricating a magnetic tunneling junction cell, comprising:

(a) providing a magnetic tunnel junction film stack comprising an optional seed layer, a pinned layer, a tunnel barrier layer, a free layer, and a top cap layer, sequentially formed on a substrate;

(b) patterning the cap layer to form a first sidewall and a first width thereon;

(c) oxidizing the outer portions of the free layers not covered by the cap layer to form a junction between the oxidized outer portions of the free layers and a central portion of the free layers, wherein the junction is coplanar with the first sidewall such that the central portion of the free layers has the first width;

(d) forming a dielectric spacer on the free layer oxide exteriors and on the first sidewall; and

(e) performing a self-aligned etch with the dielectric spacer and the capping layer as an etch mask to produce a second sidewall on the tunnel barrier layer, the pinned layer and the optional seed layer such that the pinned layer has a second width substantially greater than the first width, and to produce a third sidewall on the outer surface of the oxidized outer portions of the free layers and on the outer surface of the dielectric layer such that the third sidewall is connected to the second sidewall near a top surface of the tunnel barrier layer.

10. The method of claim 9, further comprising forming a high-k dielectric constant promoting layer on said free layer in step (a) and contacting a bottom surface of said uppermost capping layer, said first sidewall being formed on said capping layer and said high-k dielectric constant promoting layer after step (b).

11. The method of claim 9, wherein patterning the cap layer comprises:

(a) forming a bottom anti-reflective coating or a dielectric anti-reflective coating on the cap layer;

(b) forming a photoresist layer on the BARC layer or the DARC layer and patterning the photoresist layer to generate a photoresist island having the first width; and

(c) performing an ion beam etching or a reactive ion etching to transfer the first width in the photoresist island.

12. The method of claim 9, wherein a native oxidation, a thermal oxidation, or an oxygen-based plasma is performed to form the free layer oxide outer portions.

13. The method of claim 12, wherein the natural oxidation comprises an oxidant that is pure oxygen or ozone or a combination of pure oxygen and ozone, in combination with one or more of nitrogen, ammonia, water, or hydrogen peroxide.

14. The method of claim 13, wherein the natural oxidation occurs at an oxidant flow rate of 100 to 10000 standard cubic centimeters per minute.

15. The method of claim 12, wherein the thermal oxidation comprises an oxidant that is pure oxygen or ozone or a combination of pure oxygen and ozone, in combination with one or more of nitrogen, ammonia, water, or hydrogen peroxide.

16. The method of claim 15, wherein the thermal oxidation comprises an oxidant flow rate of 100 to 10000 standard cubic centimeters per minute and is heated to a temperature of 100 ℃ to 400 ℃.

17. The method of claim 12, wherein the oxygen-based plasma comprises an oxidant that is pure oxygen or ozone or a combination of pure oxygen and ozone, in combination with one or more of nitrogen, ammonia, water, or hydrogen peroxide.

18. The method of claim 17, wherein the oxygen-based plasma is generated under reactive ion etching conditions comprising an oxidant flow rate of 10 to 500 standard cubic centimeters per minute, an rf power of 50 to 500 watts, a bias power of <50 watts, and a chamber pressure of 5 to 50 mtorr.

19. The method of claim 11, wherein forming said dielectric spacers is accomplished in a process comprising:

(a) depositing a dielectric layer on the free layer oxide outer portions, the first sidewalls and a top surface of the BARC layer or the DARC layer; and

(b) performing a vertical ion beam etch or a reactive ion etch to remove the dielectric layer on the BARC layer or the DARC layer and to remove the dielectric layer from a portion of the top surface on the free layer oxide exteriors.

20. The method of claim 9, wherein a sidewall layer comprises redeposited material and/or damage to the optional seed layer, the pinned layer and the tunnel barrier layer formed on the second and third sidewalls as a result of the self-aligned etching, and wherein the sidewall layer does not contact a central portion of the pinned layer having a width substantially equal to the first width.

21. The method of claim 9 further comprising depositing an encapsulation layer that electrically insulates the mtj cell from adjacent mtj cells and planarizing the encapsulation layer to have a top surface that is coplanar with a top surface of the cap layer.

22. The method of claim 9, wherein the second width is at least 20 angstroms greater than the first width.

23. The method of claim 9, wherein the first width is less than about 60 nm.

24. The method of claim 11, wherein oxidizing the outer portions of the free layers removes the photoresist layer, including the photoresist islands.

25. The method of claim 9, wherein performing the self-aligned etch removes the BARC layer or the DARC layer.

Technical Field

The present disclosure relates to a method of forming a free layer to oxidize the top spacer outside and adjacent to the cap layer to eliminate electrical shorts and chemical and physical damage to the MTJ sidewalls, which is typically caused by Reactive Ion Etch (RIE) and Ion Beam Etch (IBE) processes conventionally used to form multiple MTJ cells, thereby enabling a pinned layer in each MTJ with improved magnetoresistance ratio and greater pinning strength to the free layer.

Background

The MTJ element is also referred to as an MTJ cell and is a key component of magnetic recording devices and memory devices, such as magnetic random access memory (mram) and Spin Torque Transfer (STT) -mram. An important step in fabricating a set of MTJ cells is the etch transfer of the overlying hard mask pattern to the stack of MTJ layers to form a set of MTJ cells with Critical Dimension (CD) substantially smaller than 100 nm in the most advanced devices in view of overhead. Etch transfer processes typically involve multiple etching steps involving one or both of reactive ion etching and ion beam etching.

MTJ film stacks include two ferromagnetic layers, called a Free Layer (FL) and a Pinned Layer (PL), and a tunnel barrier layer (tunnel barrier layer) between the Free layer and the pinned layer, including one or more dielectric layers. Conductive layers (electrodes) are above and below the pinned layer/tunnel barrier layer/free layer stack for electrical connection to bit and source lines, respectively, above and below the MTJ. The fixed layer has a fixed magnetization, the perpendicular to the plane direction (perpendicular magnetic anisotropy perpendicular to the plane or PMA) is preferred, while the free layer is free to rotate to a direction parallel (P) or anti-parallel (AP) to the fixed layer magnetization direction, establishing a memory state of "0" or "1" for the MTJ. The magnetoresistance ratio (DRR) is expressed as dR/R, where dR is the difference in resistance between the parallel and anti-parallel magnetic states when current is passed through the MTJ, and R is the minimum resistance value. The bottommost MTJ layer is typically a non-magnetic seed layer that promotes uniform growth of the upper layers and enhances the perpendicular magnetic anisotropy of the overlying fixed or free layer. A capping layer (also referred to as a top electrode) such as Ta is commonly formed with the topmost MTJ layer and serves as a protective layer during subsequent physical and chemical etching.

Precise patterning techniques, including lithography and reactive ion etching, typically involve defining millions of MTJ cells in a MRAM bank. The etch process for transferring the photoresist mask pattern to the underlying MTJ film stack is challenging because the various materials (magnetic alloy, non-magnetic metal, and dielectric film) in the MTJ film stack have different etch rates when subjected to ion beam etching or reactive ion etching. In addition, portions of the MTJ layers adjacent to the sidewalls are susceptible to damage due to chemical reactions during reactive ion etching, due to exposure to moisture, oxygen, and other oxidizing agents such as methanol, thereby reducing magnetoresistance and coercivity (Hc). This impairment is dependent on cell size, indicating that the problem is exacerbated as cell size decreases.

To avoid chemical damage to the MTJ sidewalls, purely physical etching techniques such as argon-based reactive ion etching or ion beam etching have been applied. However, because of their non-volatile nature, metals such as Ta from the top and bottom electrodes or ferromagnetic materials from the pinned or free layers can easily redeposit on the MTJ sidewalls and cause electrical shorts that render the device useless. Physical damage to the sidewalls may also occur due to the energetic ions in the physical etch. Additional steps such as horizontal reactive ion etching or ion beam etching trimming have been performed to remove physical damage to the sidewalls or redeposited material, but these additional steps increase the cost and cycle time of the process. The feasibility of surface modification is also limited by the density of MTJ cells.

Another problem with conventional MTJ etch processes is that the volumes (width x thickness) of the free layer and the pinned layer are equal or substantially equal. Therefore, when the cell size is reduced to 60 nm or less, the magnetization of the pinned layer becomes too weak to stabilize the internal magnetic state in the free layer. Furthermore, if the pinning layer size and Energy Barrier (EB) continues to decrease, data retention is affected. It should be noted that the energy barrier in the magnetic layer is related to the thermal stability (Δ), as shown in equation (1) below.

A＝kV/k_BT equation (1)

Where k is a constant, V is the volume of the magnetic layer (pinned layer), k_BIs the Botzmann constant, and T is the temperature.

To overcome the aforementioned problems associated with conventional MTJ patterning techniques, a new process flow is required so that MTJ cells having critical dimensions substantially less than 60 nanometers are formed while maintaining magnetic values such as magnetoresistance ratio, integrity of MTJ sidewalls, and pinning strength to the fixed layer of the free layer. In addition, new process programs must have high throughput and low cost to compete with other memory devices.

Disclosure of Invention

A first object of the present disclosure is to provide an MTJ cell with a structure that prevents electrical shorting and avoids chemical damage to the sidewalls of the pinned and free layers, thereby enhancing magnetic properties including magnetoresistance and coercivity.

It is a second object of the present disclosure to provide an MTJ cell that satisfies the first object and has a free layer with improved data retention and enhanced pinning strength to the fixed layer of the free layer, especially at critical dimensions <60 nm of the MTJ cell.

It is another object of the present disclosure to provide a method of patterning an MTJ stack such that reactive ion etching or ion beam etching does not damage portions of the free layer and the fixed layer that are responsible for device performance of the resulting MTJ cell.

According to a preferred embodiment, the first two objects are achieved by a MTJ film stack having at least a fixed layer, a free layer, a tunnel barrier layer between the free layer and the fixed layer, and a topmost layer, also referred to as a top electrode. In some embodiments, a seed layer is used as the bottommost MTJ layer. The MTJ stack is configured as a cell having a thickness perpendicular to the planar direction, and has a width of a plurality of layers including a Free Layer Width (FLW) in the in-plane direction. In a preferred embodiment, the optional seed layer, pinned layer, and tunnel barrier layer are sequentially formed on the bottom electrode and have a first width (w1) and a first sidewall substantially vertically aligned with the top surface of the bottom electrode. The free layer contacts a top surface of the tunnel barrier layer, and a cap layer and sidewalls vertically aligned to the top surface of the free layer are formed on the free layer. The key feature is that the free layer has an oxidized outer portion and a magnetic center portion that defines the width of the free layer. The free layer center portion abuts the outer portion at a junction substantially coplanar with the cap layer sidewalls. Thus, each of the free layer center portion and the cap layer has a second width that is equal to the free layer width, where the free layer width < the first width. Furthermore, dielectric spacers are formed on the top surface of the cap layer sidewalls outside the free layer and adjacent to the cap layer sidewalls.

In some embodiments, a sidewall layer, comprising redeposited material or damaged material from ion beam etching or reactive ion etching, abuts the outer surface of the dielectric spacer and the outer surface and first sidewall outside of the free layer. However, the free layer hub and the pinned layer hub, which are responsible for device performance, do not contact the sidewall layer, so that the magnetoresistance ratio and coercivity are enhanced compared to conventional MTJ device designs. Furthermore, because the first width > the free layer width, the fixed layer has stronger pinning strength to the free layer than in the prior art, which is substantially the same as the free layer width.

The present disclosure also includes a method of fabricating the aforementioned MTJ cell, preferably with an optional seed layer, pinned layer, tunnel barrier layer, free layer, and cap layer formed sequentially on a Bottom Electrode (BE). Then, a bottom-antireflective coating (BARC) or a dielectric-antireflective coating (DARC) is deposited on the capping layer. A photoresist layer is formed on the BARC layer or the DARC layer and patterned by photolithography exposure. After treatment with the photoresist developer, the resulting photoresist pattern, comprising a plurality of photoresist islands, serves as an etch mask for a subsequent etch process involving one or both of reactive ion etching or ion beam etching, which transfers the pattern to the BARC layer or the dielectric ARC layer and the cap layer. The first sidewall is formed on the BARC layer or the DARC layer and the cap layer, and stops on the top surface of the free layer.

Then, plasma is performed to oxidize the outer portions of the plurality of free layers not protected by the upper cap layer, wherein the plasma is derived from oxygen, ozone or a combination of oxygen and ozone, and N is used₂、NH₃、H₂O or other oxidizing agents. Thus, the free layer exterior is converted into free layer oxide portions that intersect the free layer center at junctions, and the photoresist mask is removed. The junction is effectively an extension of the first sidewall and is substantially coplanar with the sidewall. Dielectric spacers are then deposited on the partially formed MTJ cell and removed in a subsequent step by vertical etching except for a portion of the free layer adjacent to the capping layer. Thus, the spacer abuts the first sidewall and has a width that increases as the distance from the top surface of the bottom anti-reflective coating or the dielectric anti-reflective coating increases. The partially formed MTJ cell is then etched by one or both of reactive ion etching or ion beam etching to remove portions of the free layer oxide, the tunnel barrier layer, and the pinned layer that are not protected by the spacers or cap layers, thereby forming second sidewalls on the tunnel barrier layer, the pinned layer, and the seed layer, stopping on the bottom electrode. In addition, the BARC or DIW is removedThe reflective coating exposes a top surface of the cap layer. The second sidewall is substantially perpendicular to the top surface of the bottom electrode and defines a fixed layer width that is greater than the free layer width. The outer surface of the free layer oxide and the outer surface of the spacer adjacent to the cap layer form a third sidewall that connects to the second sidewall near the top surface of the tunnel barrier layer.

Sidewall layers, including redeposited MTJ material, are typically formed on the second and third sidewalls. However, the center of the free layer, which contains the junction with the oxidized portion of the free layer, and the center of the pinned layer, which determine device performance, are not damaged or affected by the sidewall layer. Thereafter, an encapsulation layer including one or more dielectric layers is deposited to fill the space between adjacent MTJ cells. A Chemical Mechanical Polishing (CMP) or other planarization step is performed to form a top surface on the encapsulation layer that is coplanar with the top surface of the cap layer.

Drawings

Fig. 1 is a cross-sectional view illustrating the formation of an MTJ cell according to a first embodiment of the disclosure, in which the free layer has multiple oxidized outer portions and a width of the ferromagnetic center portion that is less than the widths of the fixed layer and the tunnel barrier layer.

FIG. 2 is a cross-sectional view of a stack of MTJ films, with a photoresist pattern formed thereon, and representing a first step in the fabrication of an MTJ cell according to an embodiment of the present disclosure.

FIG. 3 is a cross-sectional view of the MTJ stack of FIG. 2 after performing an etching step to transfer a photoresist pattern to the cap layer and the BARC or DARC hard mask, according to an embodiment of the present disclosure.

FIG. 4 is a cross-sectional view of the MTJ stack of FIG. 3 after being processed using an oxygen plasma to oxidize the free layer exterior unprotected by the cap layer, according to an embodiment of the present disclosure.

FIG. 5 is a cross-sectional view of the MTJ stack of FIG. 4 after depositing dielectric spacers on the free layer oxides and the hard mask, according to an embodiment of the present disclosure.

FIG. 6 is a cross-sectional view of the MTJ stack of FIG. 5 after another etching step to remove the spacers except along the sidewalls of the hard mask and cap layer, according to an embodiment of the present disclosure.

FIG. 7 is a cross-sectional view of the MTJ stack of FIG. 6 after a self-aligned etch to form sidewalls on all of the MTJ layers below the spacers and sidewall layers on the completed MTJ cell, according to an embodiment of the present disclosure.

FIG. 8 is a cross-sectional view of the MTJ element of FIG. 7 after deposition of packaging layers and planarization for electrical isolation, according to an embodiment of the present disclosure.

FIG. 9 shows an overhead view of a plurality of MTJ cells having a circular shape in a set of rows and columns according to an embodiment of the present disclosure.

Fig. 10 shows a cross-sectional view of forming an MTJ cell according to a second embodiment of the disclosure, where the free layer has multiple oxidized outer portions and a width of the ferromagnetic center portion that is less than the widths of the fixed layer and the tunnel barrier layer.

FIGS. 11-14 illustrate cross-sectional views of intermediate steps during fabrication of the MTJ cell of FIG. 10.

Detailed Description

The disclosure is a MTJ cell in which the free layer has multiple oxidized exteriors that form a junction with a central portion having a free layer width, where the free layer width is less than the width of the tunnel barrier layer and the pinned layer, and dielectric spacers are formed on the free layer oxidized exteriors and adjacent to the sidewalls of the cap layer so that the sidewalls are coplanar with the junction and avoid electrical shorts. The present disclosure also includes processes for fabricating the aforementioned MTJ cell in which ion beam etching or reactive ion etching does not physically or chemically damage the free layer core or the pinned layer interior responsible for device performance. Although only one MTJ cell is depicted in the figure, those skilled in the art understand that multiple MTJ cells are formed in a typical memory device pattern. The processes defined herein may include one or more steps. The plane of the MTJ layers is in the x-axis and y-axis directions, and the thickness of each layer is in the z-axis direction.

In related U.S. patent application No. 15/595,484, we disclose a method of etching a stack of magnetic tunneling interface films that includes both an inert gas and an oxidizing agent to minimize chemical damage to the MTJ sidewalls and redeposited material on the MTJ sidewalls that can cause electrical shorts. In practice, it is difficult to completely prevent chemical damage to the sidewalls or redeposited material thereon. Therefore, additional steps of sidewall trimming with horizontal reactive ion etching or ion beam etching are typically performed, which have higher manufacturing costs and cycle times. Furthermore, in conventional MTJ cell designs, the free layer and the fixed layer have substantially equal volumes (widths). As MTJ cell sizes continue to decrease below 60 nanometers, the fixed layer magnetization becomes too weak to stabilize the free layer magnetic state. Also, the Energy Barrier (EB) of the anchoring layer decreases and adversely affects data preservation.

In related U.S. patent application No. 15/465,644, a process for patterning a magnetic tunneling interface such that the pinned layer width is substantially greater than the free layer width is disclosed. However, after the MTJ sidewalls are formed, ion beam etch trimming of the free layer is required to remove the damaged material. More preferably, the MTJ sidewalls are formed followed by a process of patterning the MTJ without ion beam etch trimming, resulting in improved throughput and minimized manufacturing costs.

Referring to fig. 1, a first embodiment of the present disclosure depicts an MTJ cell design that overcomes the problems associated with prior art fabrication methods when the cell size is reduced to less than 60 nanometers in conventional MTJ cells and advanced devices. The MTJ cell is formed on a substrate, which in one embodiment includes a Bottom Electrode (BE) 10 in the memory device. The bottom electrode may be a multi-layer structure and is typically embedded in a dielectric layer (not shown). In addition, other device layers (not shown) are typically under the bottom electrode, such as a bit line (or source line) that is electrically connected to the bottom electrode.

The MTJ cell, including the film stacks 11-15, is formed on a substrate, which may BE a Bottom Electrode (BE) 10 and a top surface 10 t. In an exemplary embodiment, the seed layer 11, the fixed layer 12, the tunnel barrier layer 13, the free layer 14, and the capping layer 15 are sequentially formed on the bottom electrode. The key feature is that the layers 11-13 have sidewalls 24 that are substantially perpendicular to the top surface 10t and define a fixed layer width d that is greater than the free layer width in the free layer center portion 14. Note that the cap layer 15 has sidewalls 20 that are also substantially vertically aligned to the top surface 10t and that are coplanar with the junctions 14s between the free layer center and the multiple oxidized outer portions 14 x. In a preferred embodiment, the difference (fixed layer width-free layer width) is at least 20 angstroms, and in some MTJ cells is substantially greater than 20 angstroms, meaning that the substantial width e of the outer portion 14x is at least 10 angstroms on each side of the center portion of the free layer. In addition, the free layers have a stoichiometric oxidation state outside in which all metal atoms are substantially completely oxidized. Having a pinned layer width substantially greater than the free layer width has the advantage of maintaining sufficient magnetization of the pinned layer to stabilize the free layer magnetic moment, especially at free layer width reductions of less than 60 nanometers. In addition, the pinned layer barrier does not drop as much as the smaller free layer compared to prior art MTJ cells where the free layer width is close to the pinned layer width, thus providing improved data retention.

An additional feature of the MTJ cell of the first embodiment is that dielectric spacers 21s are formed on the free layer oxide outer portions 14x and sidewalls 20. The dielectric spacers act as a buffer to prevent conductive material in sidewall layer 22 from causing electrical shorts in the MTJ cell. Note that in the following sections, the deposition of the sidewall layer during the step of ion beam etching or reactive ion etching to form the sidewalls 24 will be explained. The aforementioned etching step also produces sidewalls 23 on the outer surfaces of the dielectric spacers 21s and the outer surfaces of the free layer oxidized outer portions 14 x. Note that the sidewalls 23 extend from an angle 15c of the cap layer top surface 15t at an angle alpha, where alpha is greater than 0 deg. but may be less than 30 deg., depending on the desired base width e, and connect the sidewalls 24 near the top surface of the tunnel barrier layer 13.

It should be understood that the sidewall layer 22 has a width b, which may be in the range of 5-10 angstroms, depending on the nature of the ion beam etching or reactive ion etching used to create the sidewall 24, and includes magnetic metals or alloys, such as from the pinned layer 12, and metals or alloys from the seed layer 11 and the bottom electrode 10. Similar sidewall layers in conventional MTJs can easily cause electrical shorts and degrade magnetic performance if a channel is formed near the tunnel barrier layer 13. However, the presence of the spacers 21s and the plurality of free layer oxidized outer portions 14x prevents electrical connection to the MTJ cells on the tunnel barrier layer, which substantially eliminates the possibility of shorting in the present disclosure. The sidewall layer may also include the outer periphery of the pinned layer and the outer peripheral region of the seed layer, which are chemically damaged or partially oxidized during ion beam etching or reactive ion etching to form the sidewalls 24. In the present disclosure, the pinned layer center portion has a width that is close to the width of the free layer (within dashed line 11 c) that is primarily responsible for device performance, and does not include or abut the sidewall layer. Thus, magnetic performance is enhanced over prior art schemes having a single sidewall along all MTJ layers, with the sidewall layer formed on the single sidewall.

The sidewall layer 22 has an outer side 22s that, in some embodiments, is formed substantially parallel to the sidewalls 24 below the top surface of the tunnel barrier layer 13 and parallel to the sidewalls 23 above the tunnel barrier layer top surface. As described in later sections, an encapsulation layer is typically deposited to insulate adjacent MTJ cells. The encapsulation layer may include one or more dielectric layers, wherein at least one of the dielectric layers is adjacent to the outer side 22 s. Because the sidewall layer does not have a detrimental effect on MTJ performance, it is not necessary to remove the layer by performing an ion beam etch or reactive ion etch trimming step prior to packaging, thereby improving throughput over conventional processing methods.

The present disclosure also includes a process for fabricating an MTJ cell, as shown in FIG. 1. In fig. 2-7, key aspects of the flow chart describing steps are depicted with respect to steps.

Referring to FIG. 2, a deposited MTJ stack 1 is deposited on a substrate 10, and in an exemplary embodiment has a bottom spin valve configuration, in which an optional seed layer 11, a fixed layer 12, a tunnel barrier layer 13, a free layer 14, and a cap layer 15 are formed in sequence on the substrate. Preferably, each of the pinned and free layers has a perpendicular magnetic anisotropy with a magnetization aligned in the positive or negative z-axis direction. In other embodiments, at least one additional layer may be included in the aforementioned MTJ stack, such as a high-k promoting layer, which is a metal oxide layer between the free layer and the cap layer, enhancing the perpendicular magnetic anisotropy in the free layer. A seed layer, which may comprise one or more NiCr, Ta, Ru, Ti, TaN, Cu, Mg or other materials, is typically used to promote a smooth and uniform grain structure in the upper layer.

The pinned layer 12 may have a synthetic anti-parallel (SyAP) configuration, represented by AP2/Ru/AP1, in which the antiferromagnetic coupling layer is formed of Ru, Rh, Ir, for example, sandwiched between an AP2 magnetic layer and an AP1 magnetic layer (not shown). The AP2 layer, also referred to as the outer pinned layer, is formed on the seed layer, while AP1 is the inner pinned layer and typically contacts the tunnel barrier layer. An AP1 layer and an AP2 layer, which may comprise CoFe, CoFeB, Co, or combinations thereof. In other embodiments, the reference layer can be a lamination stack with intrinsic perpendicular magnetic anisotropy, e.g. (Co/Ni)_n、(CoFe/Ni)_n、(Co/NiFe)_n、(Co/Pt)_n、(Co/Pd)_nOr the like, where n is the number of layers. Furthermore, a transition layer such as CoFeB or Co may be inserted between the top-most layer and the tunnel barrier layer in the stack of build-up layers.

The tunnel barrier layer 13 is preferably a metal oxide layer comprising MgO, TiO_x、AlTiO、MgZnO、Al₂O₃、ZnO、ZrO_x、HfO_xAnd MgTaO. More preferably, magnesium oxide is selected as the tunnel barrier layer because it provides the highest magnetoresistance ratio, for example, particularly when sandwiched between two layers of cofeb.

The free layer 14 may be a multilayer stack of Co, Fe, CoFe or alloys, with one or both of B or Ni or including the aforementioned compositions. In other embodiments, the free layer may have a non-moment diluting layer such as Ta or Mg interposed between two ferromagnetically coupled CoFe or CoFeB layers, and in alternative embodiments, the free layer has a synthetic antiparallel configuration such as free layer 1/Ru/free layer 2, where free layer 1 and free layer 2 are either antiferromagnetically coupled two magnetic layers, or an intrinsic perpendicular magnetic anisotropy stack as described above with respect to the pinned layer composition.

The capping layer 15 also serves as a hard mask during subsequent etching steps for fabricating the plurality of MTJ cells, and typically includes one or more of Ta, Ru, TaN, Ti, TiN, and W. It should be understood that other cap layer materials may be selected to include MnPt or conductive oxides such as RuO_xTo be opposed during the etching stepHigh etch selectivity is provided at the bottom of the MTJ layer, which defines the width of the fixed layer in the completed MTJ cell and stops on the substrate 10. all layers in the MTJ stack can be deposited in a DC sputtering chamber of a sputtering system, such as the Anelva C-7100 sputter deposition system, which includes an ultra high vacuum DC magnetron sputtering chamber in combination with multiple targets and at least one oxidation chamber^-8To 5 × 10^-9Base pressure between torr.

When all of the layers 11-15 are formed, the MTJ stack 1 may be annealed by heating to a temperature between about 360 ℃ and 400 ℃ for a period of time up to several hours to grow a cubic-centered structure in the pinned, free, and tunnel barrier layers, thereby enhancing perpendicular magnetic anisotropy in the pinned and free layers. The matching lattice structure in the foregoing layers is also believed to improve the magnetoresistance ratio in the formation of the MTJ cell in subsequent patterning processes.

According to the present disclosure, as a first step of the MTJ patterning process, a bottom anti-reflective coating or dielectric anti-reflective coating 16 and a photoresist layer are sequentially coated on the cap layer 15. The bottom anti-reflective coating or dielectric anti-reflective coating has a top surface 16t with a refractive index that minimizes light reflection during subsequent patterned exposures, thereby allowing more uniform photoresist islands 40 with less critical dimension variation to be formed on the patterned photoresist layer. Then, a photolithography process including a conventional pattern exposure and development process is performed to form a pattern including a plurality of islands having sidewalls 40s in the photoresist layer. As indicated later in the aerial view of fig. 9, the islands are in an array having a plurality of rows and columns. However, only one island is shown in fig. 2 to simplify the drawing. Each island has a critical dimension w, which in some embodiments corresponds to the critical dimension required in state-of-the-art memory devices, between 10 nm and 60 nm. Note that some devices are circular such that w is formed in both the x-axis and y-axis directions. However, the bird's-eye shape of the island 40 may be elliptical or polygonal such that the y-axis direction is different from the x-axis direction.

Referring to FIG. 3, an initial etching step 29 is performed, and may be an ion beam etch, wherein ions may be from one or more of Ar, Kr, Xe, or Ne, or may include a reactive ion etch with carbon fluoride or carbon chloride gas to transfer the shape of the islands 40 to the BARC or DARC 16 and the cap layer 15. Further, ion beam etching or reactive ion etching may contain oxygen. Accordingly, the sidewall 20 is formed and is an extension of the sidewall 40s to the top surface 14t of the free layer 14. Note that in embodiments where the sidewalls 20 are substantially perpendicular to the top surface of the free layer, the critical dimension w is effectively replicated in the layers 15, 16.

In some embodiments, the passivation step includes applying an oxygen plasma or flowing oxygen into the process chamber immediately after the initial reactive ion etch or ion beam etch is completed, without breaking vacuum, to produce a smoother sidewall 20.

It should be understood that the embodiments described herein, ion beam etching, generally includes rotating a workpiece (wafer) having a stack of MTJ films and a substrate formed thereon. In addition, the incident angle and the penetration angle of the inert gas ions directed toward the substrate 10 may vary from 0 ° to 90 °. Reactive ion etching, on the other hand, involves a stationary wafer, and the resulting plasma is confined to a 90 ° direction (perpendicular to the wafer surface).

Referring to FIG. 4, a key feature of the process according to the present disclosure includes a step 30 in which a plasma, including pure oxygen, ozone, or a mixture thereof, is formulated with N₂、NH₃、H₂O or H₂O₂Or other oxidizing agent, under reactive ion etching conditions, and serves to oxidize the free layer outer portions 14x not covered by the cap layer 15. Thus, the free layer width is defined by the width of the free layer center portion 14 that maintains ferromagnetic properties. A junction 14s is formed between the free layer portions 14, 14x and is aligned underneath the sidewall 20 and coplanar with the sidewall 20. A low bias power of less than 50 watts is preferred to prevent ions or plasma from penetrating into the underlying fixed layer and oxidizing portions thereof. Preferably, the reactive ion etching conditions include an oxidant flow rate of 10 to 500 standard cubic centimeters per minute (sccm), a radio frequency power of 50 to 500 watts, a bias work of less than 50 wattsRate and a chamber pressure of 5 to 50 millitorr.

Alternatively, step 30 may include native oxidation, thermal oxidation, or other well-known oxidation methods to produce the free layer oxidized outer portions 14 x. For example, natural oxidation may include an oxidant flow rate of 100 to 10000 standard cubic centimeters per minute. In addition, thermal oxidation, preferably including an oxidant of pure oxygen or ozone or a combination thereof, with N₂、NH₃、H₂O or H₂O₂Is preferred. In some embodiments, the thermal oxidation is produced at an oxidant flow rate of 100 to 10000 standard cubic centimeters per minute and is heated to a temperature of 100 ℃ to 400 ℃.

As described earlier, the oxidized outer portions of the free layers act as an insulating buffer to prevent electrical shorting and chemical damage to the central portion 14 of the free layer responsible for device performance, including magnetoresistance and coercivity. Step 30 also removes the photoresist pattern including islands 40.

Referring to fig. 5, a dielectric layer 21, which may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, magnesium oxide, aluminum oxide, tantalum oxide, or other metal oxides, metal oxynitrides, metal nitrides, or metal carbides, and has a thickness of at least 50 angstroms, is deposited on the top surfaces 14t, 16t, and the sidewalls 20 by Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or Plasma Enhanced CVD (PECVD) methods. Preferably, chemical vapor deposition is used to maximize coverage of the dielectric layer on the sidewalls 20. The dielectric layer is generally not conformal, meaning that the thickness on the top surface 16t is generally greater than the thickness on the sidewalls 20.

Thereafter, as shown in fig. 6, a vertical etch 31 (ion beam etch or reactive ion etch) is performed to remove the dielectric layer 21 on the top surface 16t and a substantial portion of the dielectric layer 21 from the top surface 14 t. Preferably, the etching step 31 produces dielectric spacers, referred to herein as spacers 21s, on portions of the top surface 14t of the free layer oxide outer portions 14x and on the sidewalls 20. The spacers contact the corner 16c of the overlying bottom anti-reflective coating or dielectric anti-reflective coating at the top surface 16t and have increasingly larger widths until reaching a width c of at least 10 angstroms at the top surface 14 t. The ion beam etching or reactive ion etching step 31 may be based on ions or plasma generated from carbon fluoride, chlorine gas or argon gas. The spacer 21s and layers 15, 16 act as etch masks for subsequent etch steps to the residual layers 11-13 and 14x in the MTJ stack.

Referring to fig. 7, an etching step 32 is performed and includes ion beam etching, reactive ion etching, or a combination thereof. In a preferred embodiment, the etching step 32 is based on ions or plasma generated from an inert gas, which is one of Ar, Kr, Ne, or Xe and methanol, ethanol, O₂、H₂O₂、H₂O、N₂O, or CO. Accordingly, sidewalls 24 are formed on the tunnel barrier layer 13, the pinned layer 12 and the seed layer 11, and stop on the top surface 10t of the substrate. Portions of the BARC or DARC 16 and the free layer oxide outer portions 14x not covered by the spacers 21s are also removed. Note that sidewalls 24 on layers 11-13 connect sidewalls 23 on the outer portions 14x of the free layers and sidewalls 23 on spacers 21s near the top surface of the tunnel barrier layer. Step 32 determines a fixed layer width d, which in a preferred embodiment is substantially greater than the free layer width. The tunnel barrier layer and optional seed layer also have a width d. In other embodiments, an inert gas or oxidant based ion beam etch or a reactive ion etch may be performed in step 32. Depending on the reactive ion etch or ion beam etch conditions, the base width e of the outer portions of the free layers may be less than the maximum spacer width c of the previous etch 32, but preferably at least 10 angstroms on each side of the center portion 14 of the free layer.

In embodiments where the etching step 32 comprises reactive ion etching conditions, the plasma is preferably induced and sustained at a rf power between 600 and 3000 watts and at a temperature near room temperature. In addition, the RF power applied to the top electrode may be different from the RF power applied to the bottom electrode in a reactive ion etch process chamber. The sidewalls 24 may be substantially perpendicular to the top surface 10t as mentioned in the exemplary embodiment, with particular ion beam etching or reactive ion etching conditions. Further, as a result of the etching step 32, a sidewall layer 22 having a width b of about 5 to 10 angstroms is typically formed on sidewalls 23 and 24. The sidewall layers, including redeposited material from layers 11-13, the free layer outer portion 14x, and from the substrate 10. When the etching step 32 includes an oxidizing agent, the sidewall layer may also include oxidation-induced damage to portions of the layers 11-13. It will be appreciated that depending on the pattern density (spacing between MTJ cells), the bottom layer 11 between MTJ cells with larger spacing tends to be removed before the bottom layer 11 between MTJ cells with closer spacing. Thus, the etching step 32 may remove a portion of the substrate exposed between the MTJ elements with the larger spacing, while the area of the top surface 10t between the MTJ elements with the smaller spacing is eventually exposed.

Note that the etching step 32 is a self-aligned etching process, which means that no photolithography process is required to create the sidewalls 24. Thus, using the MTJ patterning procedure defined herein avoids the problem of overlay, which is particularly difficult for patterning a fixed layer below a patterned free layer. Because the MTJ patterning process is more controlled by removing the performance variables associated with the sidewall layer 22 contact or active portions of the layer including the free layer and pinned layer in prior art devices, we find the MTJ switching current to be more uniform as well.

Referring to fig. 8, an encapsulation layer 25, comprising a dielectric material, is deposited over sidewall layer 22 and over top surface 15t in the MTJ cell of fig. 7, and over other MTJ cells (not shown) in the memory array. Preferably, the encapsulation layer has a thickness of 5-250 nanometers and is one or more of: silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, metal nitrides, metal oxides, metal oxynitrides, metal carbides including but not limited to SiOYN_z、AlOYN_z、TiOYN_z、SiCYN_zMgO, TaOY and AlOY, wherein y + z>0. Preferably, the encapsulation layer is deposited by physical vapor deposition, chemical vapor deposition, Ion Beam Deposition (IBD), or Atomic Layer Deposition (ALD) without vacuum in the process chamber in which the etching step 32 was previously performed.

Thereafter, a Chemical Mechanical Polishing (CMP) process or other planarization method is performed to form a top surface 25t on the encapsulation layer that is coplanar with the top surface 15t on the cap layer 15. In some embodiments, after the etching step 32, a chemical mechanical polish removes any dielectric anti-reflective coating or bottom anti-reflective coating 16 residues.

Referring to FIG. 9, a flowchart illustrating an overhead view of island shapes of a plurality of MTJ cells formed after CMP or an alternative planarization process is shown in the flowchart of the present disclosure. The MTJ cell has a width w and a length v at a top surface 15 t. As explained previously, the MTJ cell is depicted in a circle, where w ═ v, but may have an elliptical or polygonal shape in other embodiments, such that w is not equal to v. Typically, millions of MTJ cells are arranged in an array of rows and columns, but only four are shown to simplify the drawing.

Thereafter, a top conductive layer, including a plurality of parallel conductive lines (not shown), is formed over the MTJ cell and the encapsulation layer 25 by conventional methods, as will be understood by those skilled in the art. Thus, a write current for switching the magnetic state in the free layer, or a read current for detecting the actual magnetic state in the device, can pass from the top conductive line through the MTJ cell to the bottom electrode 10, or vice versa.

Referring to fig. 10, which shows a second embodiment of the present disclosure, the MTJ of fig. 1 is modified to obtain an MTJ cell with an interposed high-k promoting layer 17, the high-k promoting layer 17 contacting the top surface of the free layer core 14 and the bottom surface of the cap layer 15. The sidewalls 20 now extend from the cap layer top surface 15t to the free layer top surface 14t and define the outer surface of the high dielectric constant promoting layer, which has a width substantially equal to the width of the free layer. Further, dielectric spacers 21s adjoin sidewalls 20 from the cap layer top surface to the free layer top surface.

Referring to fig. 11, a first fabrication step of the MTJ cell in fig. 10 is the formation of the MTJ stack 2, wherein an optional seed layer 11, a pinned layer 12, a tunnel barrier layer 13, a free layer 14, a high-k promoting layer 17, and a cap layer 15 are sequentially deposited on the substrate 10. It is preferred that the high permittivity promoter layer be a metal oxide such as magnesium oxide or other metal oxides as mentioned above with respect to the tunnel barrier layer composition. The high dielectric constant layer is advantageously used to improve thermal stability at the point where the second free layer/metal oxide junction is provided (except for the free layer/tunnel barrier layer junction), thereby increasing the perpendicular magnetic anisotropy within the free layer. After depositing the BARC and DARC 16 layers on the cap layer, similar to the first embodiment, a photoresist pattern including islands 40 and sidewalls 40s is formed on the cap layer top surface 16 t.

Thereafter, the etching step 29 and plasma oxidation 30 described above are performed to produce the intermediate of the MTJ cell structure depicted in FIG. 12. Note that the sidewalls 20 extend from the top surface of the bottom anti-reflective coating or dielectric anti-reflective coating 16 to the top surface 14t of the free layer oxide outer portions 14 x. In other words, each layer 15-17 has a width w, substantially equal to the width FLW of the free layer central portion 14, with a junction 14s with the free layer oxidized outer portion.

Then, as shown in FIG. 13, a dielectric layer is deposited and then a vertical etch is performed to provide dielectric spacers 21s adjacent the sidewalls 20 at the high-k promoting layer 17, the cap layer 15 and the BARC or DARC 16. The dielectric spacers have a width that increases with distance from the top corner 16c until the top surface 14t reaches the width c at the free layer oxide outer portions 14 x.

Referring to fig. 14, showing the encapsulated MTJ cell, after etching the middle of the MTJ cell of fig. 13 to form the sidewalls 24, depositing an encapsulation layer 25 and performing the planarization steps described above in fig. 7-8 of the first embodiment. Therefore, the MTJ cell according to the second embodiment maintains all the characteristics and advantages of the first embodiment. Moreover, the high dielectric constant promoting layer 17 is expected to provide the additional advantage of higher thermal stability against unintended switching of the free layer magnetic properties (not shown) from the (+) z-axis direction to the (-) z-direction, or vice versa, due to stray magnetic fields or high temperature conditions.

In all of the embodiments disclosed herein, the fixed layer width is substantially greater than the free layer width. Thus, data retention in the MTJ cell is believed to be improved over prior art MTJ cells having a free layer width substantially equal to the fixed layer width because the fixed layer provides greater stability to the free layer magnetic properties, particularly for values less than 60 nanometers in free layer width.

While the disclosure has been shown and described with reference to preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit of the disclosure or the scope of the appended claims.