阅读说明：本技术 阵列基板及其制造方法 (Array substrate and manufacturing method thereof ) 是由 胡小波 于 2020-05-11 设计创作，主要内容包括：本申请实施例提供了一种阵列基板及其制造方法,其中,该阵列基板包括衬底层和依次层叠设置于所述衬底层上的栅极层、绝缘层、半导体层、源漏极层、钝化层和像素电极层；其中,所述阵列基板还包括阻挡层,所述阻挡层覆盖于所述栅极层上和/或所述源漏极层上。本方案可以解决由于受到的挤压应力过大而导致栅极层和/或源漏极层的表面出现小丘的问题。(The embodiment of the application provides an array substrate and a manufacturing method thereof, wherein the array substrate comprises a substrate layer, and a gate electrode layer, an insulating layer, a semiconductor layer, a source drain electrode layer, a passivation layer and a pixel electrode layer which are sequentially stacked on the substrate layer; the array substrate further comprises a blocking layer, and the blocking layer covers the grid layer and/or the source drain layer. The scheme can solve the problem that hillocks appear on the surface of the gate layer and/or the source drain layer due to overlarge compression stress.)

1. The array substrate is characterized by comprising a substrate layer, and a gate electrode layer, an insulating layer, a semiconductor layer, a source drain electrode layer, a passivation layer and a pixel electrode layer which are sequentially stacked on the substrate layer; the array substrate further comprises a blocking layer, and the blocking layer covers the grid layer and/or the source drain layer.

2. The array substrate of claim 1, wherein the material of the barrier layer comprises tantalum pentoxide, niobium pentoxide, or titanium dioxide.

3. The array substrate of claim 2, wherein the barrier layer has a thickness of 50 a to 500 a.

4. The array substrate of claim 3, wherein the gate layer and/or the source drain layer comprises a first metal sublayer and a second metal sublayer, wherein the first metal sublayer comprises aluminum, and the second metal sublayer comprises molybdenum or titanium.

5. The array substrate of claim 4, wherein the second metal sub-layer covers the first metal sub-layer or is stacked on the first metal sub-layer.

6. The array substrate according to claim 5, wherein when the second metal sublayer is stacked on the first metal sublayer, a thickness of the barrier layer on a side surface of the gate layer and/or the source drain layer is greater than a thickness of the barrier layer on an upper surface of the gate layer and/or the source drain layer.

7. The array substrate of claim 1, wherein the material of the barrier layer comprises molybdenum or titanium.

8. A method for manufacturing an array substrate includes:

providing a substrate layer;

sequentially forming a grid layer, an insulating layer, a semiconductor layer, a source drain layer, a passivation layer and a pixel electrode layer on the substrate layer;

the manufacturing method of the array substrate further comprises the step of forming a barrier layer covering the gate layer and/or the source drain layer on the gate layer and/or the source drain layer.

9. The method of claim 8, wherein the material of the barrier layer comprises tantalum pentoxide, niobium pentoxide, or titanium dioxide.

10. The method of manufacturing the array substrate of claim 9, wherein the thickness of the barrier layer is 50 a to 500 a.

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to an array substrate and a method for manufacturing the same.

Background

With the trend of large-scale TFT-LCD (Thin Film Transistor-Liquid Crystal Display), in order to satisfy the electrical performance, the gate layer and the source/drain layer of the array substrate need to be deposited thicker and thicker.

In order to reduce the production cost, the material of the gate layer and the source drain layer is generally metallic aluminum. However, since the thermal expansion coefficient of the aluminum metal is relatively large, when heated, hillocks (hillocks) are easily formed on the surfaces of the gate layer and the source/drain layer due to excessive compressive stress, so that the surfaces of the gate layer and the source/drain layer become uneven, and the hillocks pierce through the insulating layer in a serious condition, thereby causing short circuit and reducing the performance and yield of the array substrate.

Disclosure of Invention

The embodiment of the application provides an array substrate and a manufacturing method thereof, which can solve the problem that hillocks appear on the surface of a gate layer and/or a source drain layer due to overlarge compression stress.

In a first aspect, an embodiment of the present application provides an array substrate, including a substrate layer, and a gate electrode layer, an insulating layer, a semiconductor layer, a source drain electrode layer, a passivation layer, and a pixel electrode layer, which are sequentially stacked on the substrate layer; the array substrate further comprises a blocking layer, and the blocking layer covers the grid layer and/or the source drain layer.

In the array substrate provided by the embodiment of the present application, the material of the barrier layer includes tantalum pentoxide, niobium pentoxide, or titanium dioxide.

In the array substrate provided by the embodiment of the application, the thickness of the barrier layer is 50-500 angstroms.

In the array substrate provided by the embodiment of the application, the gate layer and/or the source drain layer include a first metal sublayer and a second metal sublayer, the first metal sublayer includes aluminum, and the second metal sublayer includes molybdenum or titanium.

In the array substrate provided by the embodiment of the application, the second metal sublayer covers the first metal sublayer or is stacked on the first metal sublayer.

In the array substrate provided by the embodiment of the application, when the second metal sublayer is stacked on the first metal sublayer, the thickness of the barrier layer on the side surface of the gate layer and/or the source drain layer is larger than the thickness of the barrier layer on the upper surface of the gate layer and/or the source drain layer.

In the array substrate provided by the embodiment of the application, the material of the barrier layer includes molybdenum or titanium.

In a second aspect, an embodiment of the present application provides a method for manufacturing an array substrate, including:

providing a substrate layer;

sequentially forming a grid layer, an insulating layer, a semiconductor layer, a source drain layer, a passivation layer and a pixel electrode layer on the substrate layer;

the manufacturing method of the array substrate further comprises the step of forming a barrier layer covering the gate layer and/or the source drain layer on the gate layer and/or the source drain layer.

In the method for manufacturing the array substrate, the material of the barrier layer includes tantalum pentoxide, niobium pentoxide, or titanium dioxide.

In the manufacturing method of the array substrate provided by the embodiment of the application, the thickness of the barrier layer is 50-500 angstroms.

The array substrate provided by the embodiment of the application comprises a substrate layer, and a gate electrode layer, an insulating layer, a semiconductor layer, a source drain electrode layer, a passivation layer and a pixel electrode layer which are sequentially stacked on the substrate layer; the array substrate further comprises a blocking layer, and the blocking layer covers the grid layer and/or the source drain layer. The scheme can solve the problem that hillocks appear on the surface of the gate layer and/or the source drain layer due to overlarge compression stress.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an array substrate provided in an embodiment of the present application.

Fig. 2 is another schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

Fig. 3 is a schematic structural diagram of a gate layer and/or a source drain layer in the array substrate shown in fig. 2.

Fig. 4 is another schematic structural diagram of a gate layer and/or a source drain layer in the array substrate shown in fig. 2.

Fig. 5 is a schematic flowchart of a manufacturing method of an array substrate according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Embodiments of the present invention provide an array substrate and a method for manufacturing the same, which will be described in detail below.

Referring to fig. 1 or fig. 2, fig. 1 and fig. 2 are schematic structural diagrams of an array substrate according to an embodiment of the present disclosure. The array substrate 100 may include a substrate layer 10, and a gate electrode layer 20, an insulating layer 30, a semiconductor layer 40, a source drain electrode layer 50, a passivation layer 60, and a pixel electrode layer 70 sequentially stacked on the substrate layer 10. The array substrate 100 may further include a barrier layer 800, and the barrier layer 800 covers the gate layer 30 and/or the source/drain layer 50.

The material of the substrate layer 10 may include glass, quartz, sapphire, etc., and it should be noted that the material of the substrate layer 10 includes, but is not limited to, the above materials, and it may also include other materials, such as flexible materials, etc., which are not listed here. The material of the insulating layer 30 may include silicon nitride, silicon oxide, silicon oxynitride, or the like. The material of the semiconductor layer 40 may include one or more of indium gallium zinc oxide, indium zinc tin oxide, and indium gallium zinc tin oxide. The passivation layer 60 may be a silicon oxide film, a silicon nitride film, or a composite film formed by alternately stacking a silicon oxide film and a silicon nitride film.

As shown in fig. 1, in some embodiments, hillocks generated by the surface of the gate layer 20 and/or the source and drain layer 50 when thermally expanded are prevented from piercing the insulating layer 30 and/or the passivation layer 60. A barrier layer 80 may be disposed on the gate layer 20 and/or the source drain layer 50 to cover the gate layer 20 and/or the source drain layer 50. At this time, the material of the gate layer 20 and/or the source drain layer 50 may be aluminum metal. The material of the barrier layer 80 may be metallic molybdenum or metallic titanium.

As shown in fig. 2-4, in some embodiments, the gate layer 20 and/or the source drain layer 50 may include a first metal sublayer 21 and a second metal sublayer 22. The second metal sub-layer 22 may cover the first metal sub-layer 21 or be stacked on the first metal sub-layer 21. The material of the first metal sub-layer 21 may be metal aluminum. The material of the second metal sub-layer 22 may be metal molybdenum or metal titanium.

In this case, the material of the barrier layer 80 may include metal oxides with high compactness and high stability, such as tantalum pentoxide, niobium pentoxide, or titanium dioxide. The thickness of the barrier layer 80 may be 50 a to 500 a. When the thickness of the barrier layer 80 is 50 a to 500 a, the barrier layer 80 has high stability, high density, and high permeability.

It is understood that when the second metal sublayer 22 is overlaid on the first metal sublayer 21, the second metal sublayer 22 can prevent the first metal sublayer 21 from directly contacting the insulating layer 30 and/or the source/drain layer 50, so as to prevent the hillock from piercing the insulating layer 30 and/or the passivation layer 60 when the surface of the first metal sublayer 21 expands under heat to generate the hillock. In this case, the barrier layer 80 may further improve its protective effect.

It is understood that when the second metal sub-layer 22 is stacked on the first metal sub-layer 21, the second metal sub-layer 22 can prevent the upper surface of the first metal sub-layer 21 from directly contacting the insulating layer 30 and/or the passivation layer 60, so as to prevent the hillock from penetrating the insulating layer 30 and/or the passivation layer 60 when the upper surface of the first metal sub-layer 21 expands under heat to generate the hillock. At this time, the side surface of the first metal sublayer 21 is in contact with the barrier layer 80. Therefore, the barrier layer 80 can be used not only to prevent the side surface of the metal layer 21 from contacting the insulating layer 30 and/or the passivation layer 60, but also to further improve the protection thereof.

It is understood that, when the second metal sub-layer 22 is stacked on the first metal sub-layer 21, the side surface of the first metal sub-layer 21 is directly in contact with the barrier layer 80. Therefore, hillocks generated at the side surface of the first metal sublayer 21 penetrate the insulating layer 30 and/or the passivation layer 60 more easily than the upper surface of the first metal sublayer 21. Therefore, in order to improve the protective effect of the barrier layer 80 on the side surface of the first metal sublayer 21, the thickness of the barrier layer 80 on the side surface of the gate layer 20 and/or the source drain layer 50 may be set to be greater than the thickness of the barrier layer 80 on the upper surface of the gate layer 20 and/or the source drain layer 50.

In summary, the barrier layer 80 is disposed on the gate layer 30 and/or the source/drain layer 50 of the array substrate 100 provided in the embodiment of the present disclosure, which can block the metal aluminum, so that the metal aluminum can inhibit the generation of hillocks when expanding due to heating, and thus the hillocks generated when the metal aluminum expands due to heating can be prevented from piercing the insulating layer 40 and/or the passivation layer 60. Therefore, the array substrate 100 with the gate layer 30 and/or the source and drain layers 50 with larger thickness can be produced by the scheme. It can be understood that the present solution can puncture the insulating layer 40 and/or the passivation layer 60 with hillocks generated when the aluminum metal expands due to heat, thereby improving the electrical stability and yield of the array substrate 100.

Referring to fig. 5, fig. 5 is a schematic flow chart illustrating a manufacturing method of an array substrate according to an embodiment of the present disclosure. The specific manufacturing process of the array substrate 100 may be as follows:

101. a substrate layer 10 is provided.

102. A gate electrode layer 20, an insulating layer 30, a semiconductor layer 40, a source drain electrode layer 50, a passivation layer 60 and a pixel electrode layer 70 are sequentially formed on the substrate layer 10.

103. The manufacturing method of the array substrate 100 further includes forming a barrier layer 80 covering the gate layer 20 and/or the source drain layer 50 on the gate layer 20 and/or the source drain layer 50.

In some embodiments, the material of the barrier layer 80 may include metal oxides with high densification and high stability, such as tantalum pentoxide, niobium pentoxide, or titanium dioxide. The thickness of the barrier layer 80 may be 50 a to 500 a. When the thickness of the barrier layer 80 is 50 a to 500 a, the barrier layer 80 has high stability, high density, and high permeability.

From the above, the manufacturing method of the array substrate provided by the embodiment of the present application provides a substrate layer 10. A gate electrode layer 20, an insulating layer 30, a semiconductor layer 40, a source drain electrode layer 50, a passivation layer 60 and a pixel electrode layer 70 are sequentially formed on the substrate layer 10. The manufacturing method of the array substrate 100 further includes forming a barrier layer 80 covering the gate layer 20 and/or the source drain layer 50 on the gate layer 20 and/or the source drain layer 50. The scheme can inhibit the generation of metal aluminum hillocks, thereby improving the electrical stability and the yield of the array substrate 100.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The array substrate and the manufacturing method thereof provided by the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are explained herein by applying specific examples, and the description of the embodiments above is only used to help understanding the technical solutions and the core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.