阅读说明：本技术 用于校验的子组选择 (Subgroup selection for verification ) 是由 连佑中 X·杨 Z·周 D·杜塔 H-Y·曾 于 2019-03-22 设计创作，主要内容包括：本发明公开了一种用于识别和选择在编程或擦除操作期间使用的存储器单元子组以便在更短的时间内执行该编程或擦除操作同时避免过编程错误和欠编程错误的设备、系统和方法。本文所公开的存储器装置可包括状态变化/编程电路、计数电路、确定电路、识别电路和/或子组选择电路,其中这些电路中的每个电路被配置为执行与识别和选择在编程操作期间使用的存储器单元的子组的总体过程相关的操作。(An apparatus, system, and method are disclosed for identifying and selecting a subset of memory cells for use during a program or erase operation in order to perform the program or erase operation in a shorter time while avoiding over-program errors and under-program errors. Memory devices disclosed herein may include state change/programming circuitry, counting circuitry, determination circuitry, identification circuitry, and/or subset selection circuitry, wherein each of these circuits is configured to perform operations related to the overall process of identifying and selecting a subset of memory cells for use during a programming operation.)

1. An apparatus, comprising:

a plurality of memory cells;

a state change circuit configured to change a data state of each of the memory cells configured to be programmed;

a determination circuit configured to determine relative rates of state change for at least two subsets of memory cells; and

an identification circuit configured to identify a subset of memory cells that satisfy a state change characteristic based on the relative rate of state change.

2. The apparatus of claim 1, wherein the identified subset of memory cells that satisfy the state change characteristic comprises at least one of:

a fastest subset of memory cells; and

a slowest subset of memory cells.

3. The apparatus of claim 2, wherein:

the data state of each of the memory cells includes at least:

a lower data state; and

a higher data state higher than the lower data state; and is

The identification circuit is further configured to identify at least one of:

a subset of memory cells that is fastest when the state change circuit changes the data state of at least some of the memory cells from the lower data state to the higher data state; and

a slowest subset of memory cells when the state change circuit changes the data state of at least some of the memory cells from the lower data state to the higher data state.

4. The device of claim 1, further comprising a counting circuit configured to count a total number of memory cells that satisfy a programming threshold and determine whether the total number of memory cells satisfies a digital threshold, and

wherein the identification circuit is further configured to identify the subset of memory cells that satisfy the state-change characteristic in response to the total number of the memory cells that satisfy the programming threshold being greater than the digital threshold.

5. The apparatus of claim 4, wherein the numerical threshold comprises at least one of:

a predetermined number; and

a percentage of the memory cells.

6. The apparatus of claim 1, wherein the identification circuit is configured to identify the subset of memory cells during each programming procedure.

7. The apparatus of claim 1, wherein the identification circuit is configured to identify the subset of memory cells according to a predetermined schedule.

8. The apparatus of claim 1, wherein the identified subset of memory cells comprises a group of layers.

9. A non-volatile memory storage system, comprising:

an array of memory cells organized into a plurality of subgroups;

a programming circuit configured to apply one or more programming pulses to the array of memory cells to program the memory cells to a target data state;

a counting circuit configured to count a first number of cells of a first subset that satisfy a threshold and to count a second number of cells of a second subset that satisfy the threshold; and

an identification circuit configured to identify the first subset as a fastest subset of memory cells and the second subset as a slowest subset of memory cells in response to the first number of cells being greater than the second number of cells.

10. The non-volatile memory storage system of claim 9, wherein the identification circuit is further configured to identify at least one intermediate programming speed subset of memory cells.

11. The non-volatile memory storage system of claim 9, wherein

The target data state of the memory cell comprises at least one of:

a lower data state; and

a higher data state higher than the lower data state; and is

The identification circuit is further configured to identify at least one of:

the fastest subset of memory cells when the programming circuitry programs the memory cells from the lower data state to the higher data state; and

the slowest subset of memory cells when the programming circuitry programs the memory cells from the lower data state to the higher data state.

12. The non-volatile memory storage system of claim 9, wherein the identification circuit is configured to identify the fastest subset of memory cells and the slowest subset of memory cells during each programming procedure.

13. The non-volatile memory storage system of claim 9, wherein the identification circuit is configured to identify the fastest subset of memory cells and the slowest subset of memory cells according to a predetermined schedule.

14. The non-volatile memory storage system of claim 9, wherein the fastest subset of memory cells and the slowest subset of memory cells comprise tiers.

15. A memory device, the memory device configured to:

applying one or more programming pulses to a subset of memory cells in a programming operation;

counting a total number of the memory cells that satisfy a programming threshold;

determining whether the total number is greater than a numerical threshold;

in response to determining that the total number is greater than the numerical threshold, determining a number of memory cells within each subset that satisfy the programming threshold;

identifying at least one of a fastest programming subset and a slowest programming subset based on the determined number of memory cells within each subset; and

the identified subset is used for subsequent verify steps of the programming operation.

16. The memory device of claim 15, wherein:

in the programming operation, applying the one or more programming pulses to a subset of memory cells changes data states of at least some of the memory cells, the data states including at least:

a lower data state; and

a higher data state higher than the lower data state; and

identifying the at least one of the fastest programming subset and the slowest programming subset further comprises at least one of:

identifying the fastest programming subset when the programming operation changes the data state of at least some of the memory cells from the lower data state to the higher data state; and

identifying the slowest programming subset when the programming operation changes the data state of at least some of the memory cells from the lower data state to the higher data state.

17. The memory device of claim 15, further comprising identifying intermediate programming speed subgroups based on the determined number of memory cells within each subgroup.

18. The memory device of claim 15, wherein identifying the at least one of the fastest programming subset and the slowest programming subset is performed during each programming operation.

19. The memory device of claim 15, wherein identifying the at least one of the fastest programming subset and the slowest programming subset is performed according to a predetermined schedule.

20. The memory device of claim 15, wherein the program threshold comprises a program verify level.

Technical Field

In various embodiments, the present disclosure relates to non-volatile and/or volatile memory device communication, and more particularly to subgroup selection for program verify operations of non-volatile and/or volatile memory devices.

Background

In a memory device, the count may be employed to determine the state of the memory cell, such as during a programming process. Counting all memory cells can be quite time consuming. Therefore, it would be beneficial to count only a portion of the memory cells during a particular operation.

Drawings

More particular description is now included with reference to specific embodiments that are illustrated in the accompanying drawings. Understanding that these drawings depict only certain embodiments of the disclosure and are not therefore to be considered to be limiting of its scope, the disclosure will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:

FIG. 1 illustrates an embodiment of an array of memory cells including bit lines and word lines;

FIG. 2 illustrates a schematic diagram of a three-dimensional (3D) memory in a NAND configuration;

FIG. 3 is a schematic block diagram illustrating an embodiment of a 3D vertical memory structure;

FIG. 4 is a schematic diagram showing a top view of a 3D memory block;

FIG. 5 is a plan view illustrating an array of sense amplifier banks for a memory device;

FIG. 6 illustrates various distributions of a group of memory cells during a program operation for a program threshold;

FIG. 7 illustrates distributions of three subgroups of memory cells and an overall combined distribution of the three subgroups of memory cells relative to the programmed thresholds shown in FIG. 6;

FIG. 8A illustrates a distribution of the fastest subset of the memory cells of FIG. 7; FIG. 8B illustrates a distribution of an intermediate subset of the memory cells of FIG. 7; and FIG. 8C illustrates a distribution of the slowest subset of the memory cells of FIG. 7;

FIG. 9A illustrates various distributions of a set of memory cells, including a conventional single subgroup scan in which over-programming occurs and a set of distributions using a full subgroup scan;

FIG. 9B illustrates a set of distributions in which under-programming occurs during a single subgroup scan;

FIG. 10 is a flow chart illustrating an embodiment of a method for identifying relative programming speeds of a subset of memory cells;

FIG. 11 is a schematic block diagram illustrating an embodiment of a system for memory cell subset identification and selection;

FIG. 12 is a schematic block diagram illustrating an apparatus for memory cell subset identification and selection;

FIG. 13 is a block diagram illustrating an embodiment of a subgroup selection circuit; and is

Fig. 14 illustrates an example of threshold voltage distributions that exist in multi-level flash memory cells over time, according to one or more implementations.

Detailed Description

Aspects of the present disclosure may be embodied as an apparatus, system, method, or computer program product. Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a "circuit," module, "" device, "or" system. Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more non-transitory computer-readable storage media storing computer-readable program code and/or computer-executable program code.

For example, a module may be implemented as a hardware circuit comprising custom V L SI circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components.

Modules may also be implemented, at least in part, in software for execution by various types of processors. An identified module of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions which may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an identified module need not be physically located together, but may comprise disparate instructions stored in different locations which, when joined logically together, comprise the module and achieve the stated purpose for the module.

Indeed, a module of executable code may comprise a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, across several memory devices, and so forth. When the modules or portions of modules are implemented in software, these software portions may be stored on one or more computer-readable and/or computer-executable storage media. Any combination of one or more computer-readable storage media may be utilized. For example, a computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing, but does not include a propagated signal. In the context of this document, a computer-readable storage medium and/or computer-executable storage medium may be any tangible and/or non-transitory medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, processor, or device.

Computer program code for carrying out operations for aspects of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Python, Java, Smalltalk, C + +, C #, Objective C, etc., a conventional procedural programming language such as the "C" programming language, a scripting programming language, and/or other similar programming languages. The program code may execute partially or completely on one or more users' computers and/or on remote computers or servers over a data network or the like.

As used herein, a component may include one or more silicon integrated circuit devices (e.g., chips, dies, die planes, packages) or other discrete electrical devices, which are in electrical communication with one or more other components via wires or the like of a Printed Circuit Board (PCB). in some embodiments, each of the modules described herein may alternatively be embodied as or implemented as a component.

As used herein, a circuit includes a set of one or more electrical and/or electronic components that provide one or more paths for electrical current, in some embodiments the circuit may include a return path for electrical current such that the circuit is closed loop, however, in another embodiment, a set of components that do not include a return path for electrical current may be referred to as a circuit (e.g., open loop). In various embodiments, a circuit may include a portion of an integrated circuit, a set of integrated circuits, a set of non-integrated electronic components and/or electronic components with or without integrated circuit devices, etc., whether or not the integrated circuit is grounded (as a return path for electrical current).

By way of introduction, the following brief definitions are provided for various terms used in this patent application. Additional definitions will be provided in the context of discussing the figures herein. As used herein, "exemplary" may indicate examples, implementations, and/or aspects, and should not be construed as limiting or indicating a preference or preferred implementation. Further, it should be understood that certain ordinal terms (e.g., "first" or "second") may be provided for identification and ease of reference, and may not necessarily imply physical characteristics or ordering. Thus, as used herein, sequential terms (e.g., "first," "second," "third") used to modify an element such as a structure, component, operation, etc., do not necessarily indicate a priority or order of that element relative to another element, but rather distinguish that element from another element having the same name (but using the sequential terms). In addition, as used herein, the indefinite articles "a" and "an" may indicate "one or more" rather than "one". As used herein, a structure or operation that "comprises" or "includes" an element may include one or more other elements not expressly recited. Furthermore, the terms "include," "have," and variations thereof mean "including, but not limited to," unless expressly specified otherwise. The terms "a", "an" and "the" also refer to "one or more", unless expressly specified otherwise. Further, an operation performed "based on" a condition or event may also be performed based on one or more other conditions or events not expressly recited. As used in this application, the terms "embodiment," "one embodiment," "another embodiment," or similar language do not relate to a single variation of the disclosed subject matter; rather, this language refers to variations of the disclosed subject matter that may be applied and used with many different implementations of the disclosed subject matter. The enumerated listing of items does not imply that any or all of the items are mutually exclusive and/or mutually inclusive, unless expressly specified otherwise.

Aspects of the present disclosure are described below with reference to schematic flow charts and/or schematic block diagrams of methods, apparatus, systems, and computer program products according to embodiments of the disclosure. It will be understood that each block of the schematic flow chart diagrams and/or schematic block diagrams, and combinations of blocks in the schematic flow chart diagrams and/or schematic block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor or other programmable data processing apparatus, create means for implementing the functions and/or acts specified in the schematic flow chart diagram and/or schematic block diagram block or blocks.

It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. Other steps and methods may be conceived that are equivalent in function, logic, or effect to one or more blocks, or portions thereof, of the illustrated figures. Although various arrow types and line types may be employed in the flow chart diagrams and/or block diagram block diagrams, they are understood not to limit the scope of the corresponding embodiments. For instance, an arrow may indicate a waiting or monitoring period of unspecified duration between enumerated steps of the depicted embodiment.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description. The description of the elements in each figure may refer to elements of previous figures. Like numbers may refer to like elements in the drawings, including alternative embodiments of like elements.

Rather than counting all of the memory cells during the verify phase, one or more of a plurality of subgroups of memory cells (e.g., layers, groups of layers, partitions, input/output (IO) groups, etc.) may be used. Unfortunately, data errors, such as under-programming or over-programming, may occur, for example, if the subset utilized is not a suitable representation of the desired programming characteristics or criteria. As used herein, "memory cell" includes a hardware component that can store a single state. The memory cells may include volatile or nonvolatile memory cells. The state stored in the memory cell may represent one of various types of values, such as a single bit value or a multi-bit value.

As used herein, examples of non-volatile memory include flash memory (e.g., NAND-type and NOR-type flash memory), Electrically Erasable Programmable Read Only Memory (EEPROM), ferroelectric memory (e.g., FeRAM), magnetoresistive memory (e.g., MRAM), spin transfer torque magnetic random access memory (STT-RAM or STT-MRAM), resistive random access memory (e.g., ReRAM or RRAM), and phase change memory (e.g., PRAM or PCM). non-volatile memory includes one or more memory cells ". a" memory cell "is an electronic device or component capable of storing electronic information, hi one embodiment, non-volatile memory utilizes a floating gate transistor or charge trapping transistor as a memory cell.an embodiment of a memory cell that adjusts the floating gate transistor or charge trapping transistor to act as a threshold voltage trapping transistor or charge trapping transistor, such as a threshold voltage trapping cell (S) that may provide more than one or more than three levels of bits per bit of voltage (e.g., a threshold voltage trapping cell) such as a threshold voltage (C) or a threshold voltage trapping cell (S2, e.g., a threshold voltage trapping cell) may be provided per level of a read bit of a memory cell (e.g., a memory cell) such as a multi-level read voltage (S633, a multi-level read cell, a read-bit memory cell, 363, a multi-level read-bit memory cell, or a multi-read-bit memory cell (e.g., a multi-bit memory cell) and a multi-read memory cell (e.g., a read-read memory cell).

The memory array 126 may include a number of memory blocks. A "memory block" is a group of memory cells. For example, a memory block (e.g., an array of memory cells) includes memory cells arranged in word lines and bit lines. A "subblock" of memory is a subset of a block of memory. For example, a sub-block is a subset of memory cells corresponding to a subset of word lines of a memory block. In one implementation, the sub-block includes fifty word lines in the memory block, where the memory block includes more than fifty word lines. The sub-blocks may represent physical sub-blocks, logical sub-blocks, or both. The memory block includes two or more sub-blocks. In one implementation, the memory is structured as a two-dimensional (2D) NAND. In another embodiment, the memory is structured as a three-dimensional (3D) NAND. In one embodiment, one or more of the components described herein (e.g., memory die, memory, block, sub-block, memory cell, circuit, controller, and/or non-volatile storage system) are implemented with one or more elements (e.g., transistors, resistors, capacitors, inductors, and/or conductors) in an integrated circuit.

As shown in FIG. 1, an illustrative memory block (or block) 100 includes a plurality of NAND strings NS 0-NS 11 each connected at one end to a drain Select Gate (SGD) and the control gate of which is connected via a common SGD line, and corresponding bit lines (e.g., B L0-B L11 shared between blocks). Each NAND string is connected at its other end to a source Select Gate (SGS) which in turn is connected to a common source line 154. for example, NS0 includes a source side select gate transistor 152 and a drain side select gate transistor 140. example storage elements 142, 144, 146, 148 and 149 are in NS 0-NS 4, respectively, and are connected to a word line W L3. for example, W L3 may be the selected word line selected for programming and example storage elements may be the selected storage elements selected for programming. other storage elements connected to W L3 may also be the selected storage elements.sixty four word lines L0-W L63 extend between the source select gate and the drain select gate.

Other types of non-volatile memory may be used in addition to NAND flash memory. For example, another type of memory cell that can be used in flash EEPROM systems utilizes a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner. In one implementation, a triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (ONO) is sandwiched between a conductive control gate and a surface of a semiconductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region. This stored charge then changes the voltage level of a portion of the channel of the cell in a manner that is detectable. The cell is erased by injecting hot holes into the nitride. Similar cells may be provided in a split gate configuration, where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor. Another type of memory uses metal (conductive) charge storage elements in a NAND architecture.

In another approach, NROM cells are used. For example, two bits are stored in each NROM cell, with an ONO dielectric layer extending across the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit localized in the dielectric layer adjacent to the source. Multi-state data storage is obtained by separately reading binary states of the spatially separated charge storage regions within the dielectric. Other types of non-volatile memory are also known. In alternative embodiments, resistance levels may be stored and sensed instead of threshold voltage levels.

Fig. 2 illustrates an embodiment of a 3D memory 226 in a NAND flash configuration. The 3D memory 226 includes a plurality of physical layers integrally formed over a substrate 234, such as a silicon substrate. Storage elements (e.g., memory cells), such as representative memory cell 246, are arranged in an array in a physical layer.

The representative memory cell 246 includes a charge trapping structure 244 located between the word line/control gate W L4 and the conductive channel 242 Charge may be injected into or drained from the charge trapping structure 244 via a bias of the conductive channel 242 with respect to the word line W L4 for example, the charge trapping structure 244 may comprise silicon nitride and may be separated from the word line W L4 and the conductive channel 242 by a gate dielectric such as silicon oxide.

The 3D memory 226 includes a plurality of erase blocks, including a first block (block 0)276, a second block (block 1)278, and a third block (block 2) 280. each block 276, 278, 280 includes a "vertical slice" of a physical layer that includes a stack of word lines, shown as a first word line W L, a second word line W L1, a third word line W L, a fourth word line W L, and a fifth word line W L. a plurality of conductive channels (having a substantially vertical orientation, as shown in FIG. 2) extend through the stack of word lines. each conductive channel is coupled to storage elements in each word line W L0-W L, forming a NAND string of storage elements.

Read/write circuit 268 is coupled to the conductive channel via a plurality of conductive lines, shown as first, second, and third bit lines B L, B L, and B L at a first end of the conductive channel (e.g., the end furthest from substrate 234) and first, second, and third source lines S L, S L, and S L at a second end of the conductive channel (e.g., the end closer to or within substrate 234).

In a particular embodiment, each of the bit lines B L0-B L2 and each of the source lines S L0-S L2 may be coupled to the same end (e.g., a first end or a second end) of different conductive channels-for example, a particular bit line B L0-B L2 may be coupled to a first end of the conductive channel 282 and a particular source line may be coupled to a first end of the conductive channel 242A second end of the conductive channel 282 may be coupled (e.g., electrically coupled) to a second end of the conductive channel 242A conductive channel 282 and a conductive channel 242 may thus be coupled in series and may be coupled to a particular bit line B L0-B L2 and a particular source line S L0-S L2, each of which is coupled to a particular NAND string.

Although each of the conductive channels, such as conductive channels 242, 282, is illustrated as a single conductive channel, each conductive channel may include a plurality of conductive channels in a stacked configuration. The plurality of conductive channels in the stack configuration may be coupled by one or more connectors. Additionally, an etch stop layer (not shown in fig. 2) having a conductive connector coupled to a physically proximate portion of the conductive channel may be included in the plurality of conductive channels, such as between the first set of physical layers 232 and the second set of physical layers 233. Additionally or alternatively, one or more sub-block gate transistors (not shown in fig. 2) may be coupled between the first set of physical layers 232 and the second set of physical layers 233.

In one embodiment, the first set of physical layers 232 is an example of a first sub-block and the second set of physical layers 233 is an example of a second sub-block.

For example, data may be stored to storage elements coupled to word lines W L0-W L4, and read/write circuitry 268 may read bit values from the storage elements (e.g., memory cells) using one or more sense blocks 236. As another example, read/write circuitry 268 may apply a select signal to control lines coupled to word lines W L0-W L4, bit lines B L0-B L2, and source lines S L0-S L2 to cause a programming voltage (e.g., a voltage pulse or series of voltage pulses) to be applied across selected storage element (S) 44 of a selected word line (e.g., fourth word line W L4).

The read/write circuits 268 include one or more sense blocks 236. the sense blocks 236 are used to read or sense one or more values stored in the memory cells in one approach, one sense block 236 is provided for a group of NAND strings, each of which is coupled to a particular bit line B L0-B L2. for example, the sense block 236 is associated with B L0. another sense block 236 is associated with B L1, and yet another sense block 236 is associated with B L2. each sense block 236 may include a memory controller (not shown in FIG. 2.) each sense block 236 also includes a sense module for each NAND string.

During a read operation, the controller may receive a request from a host device, such as a computer, smart phone, or laptop computer. The controller may cause the read/write circuit 268 to read a bit from a particular storage element of the 3D memory 226 by applying appropriate signals to the control lines to cause the storage element of the selected word line to be sensed. Thus, a 3D memory 226 having a plurality of conductive channels in a stacked configuration may be configured to read data from and write data to one or more storage elements.

One or more sub-blocks of memory cells 246 in the array of memory cells 246 may be coupled by a channel (e.g., a physical communication channel). in one embodiment, the channel includes bit lines B L0-B L2 and/or source lines S L0-S L2.

FIG. 3 illustrates one embodiment of a 3D vertical memory structure or string 329. In one embodiment, the vertical column 332 is circular and includes four layers; however, in other embodiments, more or less than four layers may be included, and other shapes may be used (e.g., "U" shaped rather than "I" shaped, etc.). In one embodiment, the vertical column 332 includes an inner core layer 370 made of a dielectric such as SiO 2. Other materials may also be used. Surrounding the inner core or core layer 370 is a polysilicon channel 371. Materials other than polysilicon may also be used. Note that channel 371 is connected to a bit line. Surrounding the channel 371 is a tunnel dielectric 372. In one embodiment, the tunnel dielectric 372 has an ONO structure. Surrounding the tunnel dielectric 372 is a shared charge trapping layer 373, such as, for example, silicon nitride. Other materials and structures may also be used. The techniques described herein are not limited to any particular material or structure.

Fig. 3 depicts dielectric layers D LL, D LL, D LL 051, D LL and D LL 253, and word lines W LL 343, W LL 444, W LL, W LL and W LL each of the word line layers includes a word line region 376 surrounded by an alumina layer 377, the alumina layer 377 being surrounded by a blocking oxide (SiO2) layer 378 the physical interaction of the word line layers with the vertical columns 332 forming the memory cells, thus, in one embodiment, the memory cells include a channel 371, a tunneling dielectric 372, a charge trapping layer 373 (e.g., shared with other memory cells), a blocking oxide layer 378, an alumina layer 377, and a word line region 376. in some embodiments, the blocking oxide layer 378 and the alumina layer 377 may be replaced by a single layer of material having insulating properties or by more than two layers of different materials having insulating properties-furthermore, the materials used (SiO2) or alumina layer 378 are not limited to the word line layer 378. for example, word line layer 8947 and a portion of the vertical column of the word line layer constitute a memory cell portion of mcw 1. mcw 964. the memory cells constituting a memory cell portion of mcw 38 and a memory cell structure 3644, while the memory cells in the memory cell portion of mcw 3638 and a memory cell portion of the memory cell structure 3635.

In response to an appropriate voltage on the word line region 376, these electrons are attracted from the channel 371 into the charge trapping layer 373 by the tunnel dielectric 372.

In some embodiments, the memory cells in the same location or positions in different memory structures 329 (e.g., different memory strings 329) on different bit lines may be on the same word line each word line may store one page of data, such as when each cell (S L C) stores 1 bit of data, two pages of data, such as when each cell (M L C) stores 2 bits of data, three pages of data, such as when each cell (T L C) stores 3 bits of data, four pages of data, such as when each cell (Q L C) stores 4 bits of data, or other number of pages of data.

In the depicted implementation, the vertical 3D memory structure 329 includes an "I" shaped memory structure 329. In other embodiments, the vertical 3D memory structure 329 may comprise a "U" shaped structure or may have another vertical and/or stacked architecture. In some implementations, four sets of strings 329 (e.g., four sets of 48 word lines, or another predefined number of word lines) can form an erase block, while in other implementations, fewer or more than four sets of strings 329 can form an erase block. As can be appreciated, any suitable number of memory cells may be part of a single string 329. In one embodiment, a single string 329 includes 48 storage units.

Fig. 4 is a diagram illustrating a top view of a 3D memory block 400 according to an embodiment. As shown, the 3D memory block 400 may include a series of memory holes or cells (represented in fig. 4 by circles labeled "0 o" through "7 o" and "0 e" through "7 e"). Each of these memory holes may be organized into strings (labeled "string 0" through "string 3" in fig. 4) and/or further organized into IO groups (labeled "O," "I1," "I2," and "I3" in fig. 4). Each IO group is located between two different types of etched features formed in 3D memory block 400, namely a shallow etched feature 410 and a deep etched feature 420. The set of IOs adjacent to deep-etched feature 420 is labeled as external IO set (O); the set of IOs adjacent to the shallow etch feature 410 is labeled as the internal 3IO set (I3); the IO group adjacent to the external IO group is marked as an internal 1IO group (I1); and the IO group adjacent to the internal 3IO group (I3) is labeled as internal 2IO group (I2). It should be noted that the programs and methods disclosed herein may be implemented in connection with various types of memory, such as NAND or NOR memory, 2D memory, 3D memory, or memory employing charge-based or resistance-based storage technologies. In one example, the illustrated memory block 400 may contain 16K memory cells, which may be further divided into smaller groups of memory cells, each group including 1K memory cells.

Some manufacturing processes for 3D memory may include film deposition processes that tend to be superior to etching processes performed during manufacturing. For these types of manufacturing processes, the external memory holes in the external IOIO group (O) are typically programmed more slowly than the internal memory holes (I3). However, other manufacturing processes for 3D memory may include etching processes that tend to be superior to film deposition processes during manufacturing. For these types of manufacturing processes, the internal memory hole (I3) will typically be programmed more slowly than the external memory hole (O). However, it should be noted that the physical location of the IO group of memory cells within a 3D memory structure does not always determine its relative programming speed due to such variations introduced during the manufacturing process or due to wear caused by the use of the device. Furthermore, cycling degradation can also cause the relative programming speeds of different memory cells or groups of memory cells to change over time.

Continuing with FIG. 4, each memory hole (0o-7o and 0e-7e) may be connected to a bit line 430 (labeled as bit lines 0-7 in FIG. 4). The bit line 430 extends over the memory hole and connects to the selected memory hole via a connection point (shown in fig. 4 as a small solid ellipse) that indicates where the bit line 430 connects to the memory hole. For ease of illustration, only eight bit lines 430 (0-7) are shown in FIG. 4. However, it should be understood that other bit lines (not shown) also extend over other memory holes in FIG. 4.

FIG. 5 illustrates an array of sense amplifier banks 500 for the 3D memory structure 400 of FIG. 4, according to one example. The bit lines 430 shown in FIG. 4 extend to an array of sense amplifier banks 500, as can be seen in FIG. 5. In this manner, certain memory holes of the 3D memory structure 400 may be electrically coupled to one of the bit lines 430, and then each bit line may be electrically coupled to the bit line interface 510. In one embodiment, the bit line interface 510 may additionally use scrambling, as shown by the angled/non-vertical lines shown in FIG. 5 between the bit lines 430 and the bit line interface 510. Each bit line 430 may then be electrically coupled to a set of sense amplifiers (labeled layer #0 through layer #15 in fig. 5). As shown in fig. 5, each sense amplifier bank extends horizontally across the page. Thus, each "layer" includes a set of memory holes in electrical communication with a particular set of sense amplifiers via bit lines 430. A layer may also be referred to as a "subset of memory cells" or simply a "subset". A "subset" of memory cells can be any subset of memory cells formed from a larger set of memory cells. In this application, a subset of memory cells may be referred to as a layer, group of layers, IO group, partition, and the like. Thus, although "subset of memory cells" is one term that may be used to refer to a subset of memory cells, any of these terms (i.e., "subset," "subset of memory cells," "layer," "group of layers," "IO group," "partition," etc.) may be used interchangeably throughout this disclosure.

Fig. 6-8C illustrate steps of a method for identifying programming characteristics of one or more subsets of memory cells. Fig. 6 illustrates various memory cell distributions 600 a-600 c for a group of memory cells, such as a group of voltages or resistance states stored in the group of memory cells, during an example programming operation toward a particular programming threshold 603 (which may include a program or erase verify level or a verify level, and represents a level at which verification may occur, such as a voltage level). As used herein, "program threshold" or "threshold" refers to the state or condition of a memory cell that is reachable during programming or erasing of the memory cell. For example, a "program threshold" or "threshold" may include a threshold voltage level or a threshold resistance level, such as a program verify level. In various implementations, a "program threshold" or "threshold" can be associated with or not associated with a verify level for a particular state. The example programming operation shown in fig. 6 includes a first distribution of memory cells 600a, a second distribution of memory cells 600b (after the first programming cycle 601 a), and a third distribution of memory cells 600c (after the second programming cycle 601 b). A "program loop" includes a period of time that encompasses a program pulse and extends until another program pulse is issued or until the end of a particular program. Thus, a programming cycle encompasses a programming pulse followed by one or more verify pulses. "verify," "verify process," "verify program," or "program verify operation" includes, for example, a procedure to determine whether a particular characteristic has been met in a memory cell, such as determining that a particular program threshold 603 has been stored in the memory cell. For example, during the programming process, a programming pulse can be applied to a particular NAND memory cell. A set of one or more verify pulses may then be applied, for example, to determine whether the NAND cell has reached the target programming threshold 603. If not, a program pulse of a higher voltage level may be applied during the next program cycle, and within the same program cycle, another verify process may be performed. This procedure is repeated until all or a portion of the cell page is programmed to the desired programming threshold.

Fig. 7 illustrates various memory cell distributions 700 a-700 d, including three memory cell distributions 700 b-700 d corresponding to three different subgroups of memory cells (labeled "layer 1", "layer 2", and "layer 3" in fig. 7), and an overall memory cell distribution 700a relative to a programming threshold 603. The overall memory cell distribution 700a shown in fig. 7 is a combination of the memory cell distributions 700 b-700 d for the three subgroups of memory cells labeled layer 1, layer 2, and layer 3 in fig. 7. As shown in FIG. 7, the memory cells for tier 1, tier 2, and tier 3 each have different programming speeds, as indicated by the relative offsets of the memory cell distributions 700b through 700d of each tier along the horizontal axis shown in FIG. 7.

Fig. 8A-8C show various memory cell distributions 700 b-700 d for the fastest, slowest, and middle layers of memory cells from fig. 7 relative to a programming threshold 603. Thus, certain subsets (or layers) of memory cells respond to a programming pulse faster or slower than other subsets of memory cells. Likewise, some subsets (or layers) of memory cells may respond to an erase pulse faster or slower than other subsets of memory cells. In other words, the concepts described herein are applicable to "programming" a memory cell or group of memory cells, as well as "erasing" a memory cell or group of memory cells. While the physical location of a particular subset of memory cells on a memory substrate (as explained in connection with fig. 4) may indicate their programming speed, variations in manufacturing process and cycle degradation may also affect the programming speed of a particular subset of memory cells. Therefore, it is desirable to detect which subset of memory cells is the fastest subset (represented by distribution 700b of layer 1 in the example provided in fig. 8A-8C). As shown in fig. 8A-8C, 60 bits in layer 1 are above the threshold programming level 603. Alternatively, it may be desirable to detect which subset of memory cells is the slowest subset (represented by distribution 700d of layer 3 in the example provided in fig. 8A-8C). As shown in fig. 8A-8C, only 20 bits in layer 2 are above the threshold programming level 603. It should also be noted that detecting which subgroups of memory cells have intermediate programming speeds (represented by the distribution 700C of layer 2 in the example provided in fig. 8A-8C) may also be used for a particular application or program. As shown in fig. 8A-8C, no bits in layer 3 are above the threshold programming level 603. In one implementation, the subset of memory cells of the intermediate programming speed includes memory cells having a programming speed between the programming speed of the fastest subset and the programming speed of the slowest subset. In other embodiments, a subset of intermediate programming speeds may have a number of subsets equal or approximately equal (e.g., +/-1) to the speed above or below the intermediate programming speed, taking into account whether there are odd or even numbers of subsets and whether there is any linkage in the programming speeds. For example, in the case of a tie (where multiple subgroups have the same measured speed), one of the same speed subgroups may be selected for use as the representative subgroup.

6-8C illustrate one embodiment of general steps for identifying the relative rates of state change for two or more subgroups of memory cells. Specifically, in fig. 6, in one implementation, once a certain number of memory cells meet (e.g., meet or exceed) a programming threshold 603 (e.g., a number of memory cells meet or exceed a particular programming threshold, such as the programming threshold of the lowest state). The number of cells above the programming threshold 603 is counted to determine the relative programming speed of each subset/layer. As shown in fig. 8A-8C and as noted above, for layer 1, 60 bits are above the program threshold; for layer 2, 20 bits are above the program threshold; also, for layer 3, the 0 bit is above the program threshold. Thus, in this example, tier 1 is the fastest programming tier, tier 3 is the slowest programming tier, and tier 2 is the intermediate or medium speed programming tier.

In the examples shown in fig. 7-8C, the speed at which a memory cell responds to a programming pulse is the rate of change of state of the memory cells in each layer. The rate of change of state (e.g., programming speed) of each layer is compared to the other layers to determine the relative rate of change of state. In this example, tier 1 is identified as the fastest subset of memory cells. Layer 2 is identified as the subset of memory cells for the intermediate programming speed. And, layer 3 is identified as the slowest subset of memory cells.

According to this procedure, the fastest, slowest, or intermediate subset of memory cells may be identified for current or future memory operations, such as programming operations. In this way, adaptive scanning or counting may be performed with subsets of memory cells that meet a particular programming criterion, programming characteristic, or state change characteristic that specifies whether a fast, slow, or intermediate subset of memory cells is required for a particular storage operation.

As used herein, "state change characteristic" includes any property associated with a memory cell when the memory cell transitions from one state to another. For example, the state-change property may include, but is not limited to, velocity, momentum, polarization, resistance, temperature, crystalline composition, amorphous composition, and the like.

Thus, for example, one state change characteristic may relate to the speed at which a memory cell or group of memory cells changes from a first state to a second state in response to a common or similar program or erase pulse during programming or erasing. In one embodiment, the state change characteristics may simply include characteristics that reflect how fast or slow a particular memory cell or group of memory cells responds to a set of one or more programming pulses (i.e., how fast the storage state changes in response to a programming pulse).

FIG. 9A shows a first set of memory cell distributions 910 generated using a conventional single subgroup scan (where it is not determined which subgroup is the fastest) and a second set of memory cell distributions 920 generated using a full subgroup scan (where all memory cells are counted, i.e., scanned). A full subset scan produces an acceptable set of distributions 920, but scanning all subsets is too time consuming and results in a slower program or erase process. In contrast, a conventional single subgroup scan produces a poorer set of distributions 910. Arrow 930 in fig. 9A identifies the region of the first set of distributions 910 where over-programming as shown may result when the subset is assumed to be the fastest subset but not the fastest subset. (note how some of the upper tails in the set of memory cell distributions 910, indicated by arrow 930, appear to spread out and move to the next highest state toward the right in FIG. 9.) in contrast, the second set of memory cell distributions 920 do not exhibit these programming errors. Likewise, for an under-programmed error (shown in FIG. 9B), the lower tail of the memory cell distribution group will appear to spread out and move to the left in FIG. 9B, forming an adjacent and lower distribution, as indicated by arrow 940. Under-programming errors may occur when, for example, the subset is assumed to be the slowest subset but not the slowest subset. Some of the causes of over/under programming errors will be discussed in more detail below along with a presentation of implementations to mitigate these over/under programming errors. It should also be noted that under-program errors and over-program errors do not necessarily occur in the highest or lowest data states, but may occur in conjunction with other intermediate data states.

During the verification process, it is time consuming to count the entire number of memory cells per layer. Thus, a subset of memory cells may be selected for counting (sometimes referred to as scanning). Scanning is used to verify the programmed state (or current state) of a memory cell, for example, during a programming procedure. A scan is performed to determine whether the memory cell has reached a target data state or threshold. When the target programming threshold is reached, programming of those cells may be stopped; if the target programming threshold has not been reached, programming will continue until the target is reached. Thus, in one embodiment, one or more initial programming pulses may be used during a programming procedure, followed by a scan to determine which subset of memory cells to select for a scan operation. Alternatively, a subset of memory cells can be selected based on information obtained from a previous programming procedure, such as during a manufacturing or calibration procedure.

In some 3D NAND flash technologies, the program verify operation may use a "1-level bit scan" approach (which may also be referred to as a single subset scan), or the like, meaning that the controller scans only a subset of the memory cells on a page of data to determine whether the target programming level (or threshold) has been reached, rather than scanning all of the cells on the page. It should be noted that whether a single or full subgroup scan is employed, in many cases not all cells will reach the target programming threshold because some of the cells are defective or simply respond too slowly to the applied programming pulse. In one embodiment, the memory cells of a page are organized into subsets of memory cells (e.g., layers, IO groups, partitions, etc., as previously described). For example, if a page includes 16KB of memory units, the page may be divided into 16 layers, where each layer includes 1KB of memory units for the page. The "1-horizon scan" verification operation may select one of the 16 layers to perform a representative program-verify operation that is used to verify all other layers based on the assumption that the selected layer exhibits the desired relative programming speed of the program-verify operation. Thus, it is desirable that the performance of the selected layer be such that it represents well all other layers that together make up the entire page.

As previously discussed with reference to fig. 4 and 5, in an embodiment of a 3D memory architecture, memory cells may be organized into four IO groups (e.g., internal 1IO, internal 2IO, internal 3IO, external IO, etc.). The outer IO groups may be those memory cells physically located along the outer edges of the memory cell array (adjacent to the deep etch) and the inner IO groups may be those memory cells physically located closer to the center of the memory cell array (adjacent to the shallow etch). In one embodiment of the "1-horizon scanning" method, either the external IO group or the internal IO group may be selected as a default IO group representing the other IO group during the program verify operation. In such embodiments, the default IO group may always be used to perform certain program verify operations, such that other unselected IO groups need not undergo the same program verify operations, since the results of the program verify operations that may rely on the default IO group are assumed and considered to be a good representation of all other IO groups. For example, it may be assumed that the representative default IO group is the fastest (or slowest) memory cell programming subgroup of the plurality of subgroups.

In another embodiment, selecting the fastest IO bank for certain programming operations may ensure that the memory cells are not over programmed in order to avoid over programming errors as previously discussed. However, if the slower IO bank is selected in error to represent all IO banks for certain programming operations, the memory array may exhibit over-programming errors (e.g., memory cell distributions with extended and/or incorrect upper tails) after the programming operation is complete.

FIG. 10 is a flow chart illustrating an embodiment of a method 1000 for identifying the relative programming speed of a subset of memory cells. The identified subset of memory cells may then be used for programming operations, such as for verification steps in an adaptive smart inlay scan. The method 1000 may be used with the memory devices and systems disclosed herein and any other suitable memory devices and systems as may be contemplated.

In step 1010, one or more programming pulses may be applied to a subset of memory cells in a programming operation. As previously described, a programming operation may target at least some of the memory cells within a subset of memory cells a desired program threshold by applying one or more programming cycles (e.g., a programming pulse followed by one or more verify pulses).

In step 1020, the total number of memory cells that satisfy the programming threshold (e.g., a particular threshold voltage level, etc.) may be counted before, during, or after each verify pulse to determine (in step 1030) whether the total number of memory cells that satisfy the programming threshold is greater than a digital threshold (e.g., a predetermined number, a percentage of the total number of memory cells, etc.). In this manner, subsequent steps of method 1000 may be delayed/avoided until a sufficient sample size of memory cells satisfying the digital threshold is obtained.

In step 1040, if it is determined that the total number of memory cells satisfying the programming threshold is greater than the digital threshold (as determined in step 1030), the number of memory cells within each subset that satisfy the programming threshold may be determined/counted. For example, as previously discussed with reference to fig. 8A-8C, it is determined that the first subset (layer 1) has 60 bits above the programming threshold, the second subset (layer 2) has 20 bits above the programming threshold, and the third subset (layer 3) has 0 bits above the programming threshold.

Once the number of memory cells within each subset that meet the programming threshold has been determined/counted, method 1000 may proceed to step 1050, where at least one relative programming speed for the subset of memory cells may be identified based on the determined number of memory cells within each subset that are above the particular programming threshold. In one implementation, at least one of the fastest programming subset and the slowest programming subset is identified based on the determined number of memory cells within each subset. In addition, a subset of intermediate programming speeds can be identified.

Once at least a subset of memory cells has been identified, method 1000 can proceed to step 1060, where in step 1060 the identified subset of memory cells can be used for a verify step in a programming operation, as previously described, and method 1000 can end.

As previously described, scanning using all of the subgroups to determine whether the set target data state of the memory cells has been reached is time consuming and unduly slows down programming or erasing. Thus, a subgroup may be selected for scanning based on determining that the selected subgroup represents a desired attribute (e.g., the subgroup is the fastest, slowest, or intermediate subgroup). In conventional approaches, a particular IO group or layer is generally considered the slowest or fastest (e.g., an external IO group or an internal 3IO group). However, this assumption is not always accurate and produces overlapping distributions, as shown in fig. 9A to 9B. As previously discussed with reference to fig. 9A, over-programming may result if, for example, the subset is selected as the fastest subset but it is not the fastest subset. Alternatively, if the subset is selected as the slowest subset but it is not, then under-programming may result. Thus, as described above, subsets of memory holes or memory cells (e.g., layers, groups of layers, IO groups, partitions, etc.) may be identified based on a determination of the programming speed for each subset. Thereafter, a programming operation (such as verification) can be implemented by utilizing the identified subset as representative of all other subsets. Thus, the term "program verify subset selection" may refer to any system, method, or apparatus disclosed herein for identifying a subset (e.g., layer, group of layers, IO group, partition, etc.) of memory cells having a particular characteristic (e.g., slowest or fastest subset) to be used during a programming operation (e.g., scan during verify, etc.).

FIG. 11 is a schematic block diagram illustrating embodiments of a system 1100 and apparatus 1110 for memory cell subset identification and selection; the computing device 1110 includes one or more identification circuits or subset selection circuits 1150 for the memory medium 1122 of the non-volatile and/or volatile memory device 1120. As used herein, "subset selection circuitry" refers to circuitry for identifying a programming speed of a subset of memory cells (e.g., an IO group or group of groups of memory cells) relative to at least one other subset of memory cells and selecting the identified subset of memory cells for at least one programming operation. For example, in one implementation, the subset selection circuitry 1150 may perform the method outlined in FIG. 10. The subset selection circuit 1150 may be part of the non-volatile and/or volatile memory elements 1123 (e.g., disposed on the same integrated circuit device as the non-volatile memory medium 1122). In some implementations, the memory device 1120 can operate at least partially on and/or communicate with a non-volatile and/or volatile memory system 1102 of the computing device 1110, and the computing device 1110 can include a processor 1111, volatile memory 1112, and a communication interface 1113. Processor 1111 may include one or more central processing units, one or more general purpose processors, one or more special purpose processors, one or more virtual processors (e.g., computing device 1110 may be a virtual machine operating within a host), one or more processor cores, and the like. The communication interfaces 1113 can include one or more network interfaces configured to communicatively couple the computing device 1110 and/or the memory controller 1126 to a communication network 1115, such as an Internet Protocol (IP) network, a Storage Area Network (SAN), a wireless network, a wired network, or the like.

In one implementation, subgroup selection circuitry 1150 can be disposed at or toward an edge and/or perimeter of memory element 1123, adjacent to and/or near memory medium array 1122 (e.g., as depicted in fig. 11). In another embodiment, subgroup selection circuitry 1150 may be disposed on a different level, layer, and/or plane of the integrated circuit device than memory media array 1122 (e.g., as CMOS or other circuitry beneath, parallel to, and offset from the array, etc.).

In one embodiment, the slowest subset for each string (e.g., four subsets per string, as shown in FIG. 4) may be selected for the program verify operation to ensure that each page is sufficiently programmed. In other embodiments, the fastest subset of each string may be selected for certain programming operations in order to avoid over-programming problems, as previously described. The external IO group is typically the slowest subgroup, and in some embodiments may be a default setting, depending on the manufacturing process used. However, due to process variations, word line dependencies, string dependencies, degeneration, etc., sometimes an internal IO group or another IO group may be the slowest subgroup, as previously described. If an external IO bank is used but the internal 3IO bank is slower, it may result in a lower tail problem for the highest data state (or other state), where some memory cells may not be sufficiently programmed, resulting in data errors (as shown by arrow 940 of FIG. 9B).

In some implementations, the subset selection circuit 1150 can determine whether a plurality of memory cells of a plurality of subsets (e.g., an external IO set, an internal 1IO set, an internal 2IO set, and an internal 3IO set as shown in fig. 4) exceed an a-state program verify level (and/or another predefined verify level) during an a-verify programming operation (as shown in fig. 14). As used herein, a verify or verify level can refer to any level associated with a particular state reachable during programming or erasing of a memory cell. Subgroup selection circuit 1150 may accomplish this by scanning (or counting) the number of bits that exceed the a-state program verify level, where each bit corresponds to a memory cell. A predetermined threshold number of bits (e.g., 100 bits) may also be selected. In one embodiment, a predetermined threshold is exceeded before the next operation is performed by subgroup selection circuit 1150. For example, if it is determined that the number of memory cells (e.g., bits) that exceed the A-verify level (the programming threshold for the lowest state in the memory cells) satisfies the digital threshold, then the subset selection circuit 1150 may count the number of bits for each individual subset that is above the programming threshold to determine which subset is the fastest subset and/or which subset is the slowest subset based on which subset has the largest number of bits that exceed the A-verify level and which subset has the smallest number of bits that exceed the A-verify level. Thereafter, all other IO groups may be represented in a programming operation using the identified fastest and/or slowest subgroup, as previously described. For example, the identified slowest subset may be used to perform all other subset program verify operations representing an entire page program operation. In this way, the time it takes to perform a program verify operation for the entire page program will be greatly reduced while mitigating errors due to under-programming.

The default settings (e.g., one or more default subgroups that have been identified and/or selected) may be different for each chip, die plane, wordline, page, string, etc., and the slowest subgroup, fastest subgroup, intermediate subgroup, etc. may be determined separately for each chip, die plane, wordline, page, string, etc. The subgroup selection circuitry 1150 may also store the selection of the slowest subgroup, the fastest subgroup, the intermediate subgroup, etc. as parameters for future reference (e.g., such that these parameters need only be determined once), or the subgroup selection circuitry 1150 may re-determine the selection of each programming operation periodically, according to a predetermined schedule, etc.

In one embodiment, subset selection circuitry 1150 may automatically detect the correct (e.g., slowest) subset for the program verify operation and dynamically use the correct subset for each word line for the program verify operation. In one embodiment, dynamically selecting the slowest subset for a program verify operation may prevent or mitigate (e.g., at a highest state or other up state, etc.) the risk of lower tail skew, thereby reducing failed bit counts or other error indicators. In one embodiment, the subset selection circuit 1150 may also select the best (e.g., slowest) IO group for program verification of different chips, dies, die planes, word lines, etc., so that process variations resulting in different IO group programming speeds may be improved.

In one embodiment, subgroup selection circuitry 1150 may define a certain number of bits (e.g., 100 bits) as a digital threshold and may use the a-verify level (e.g., the level of the a-state, which may be, for example, 0.5V, as shown in fig. 14) as a checkpoint. For example, the A-verify level may be selected because it has the lowest programming threshold when programming from a lower state to a higher state within the memory cell, and thus precedes all other verify levels. However, the subgroup selection circuit 1150 may use any verify level as a checkpoint and any number of bits as a digital threshold. During programming, the subset selection circuit 1150 may also detect the subset that first exceeded the verify level (e.g., ≧ 100 bits) at the checkpoint (e.g., A-verify level). Thus, the other subgroups may be slower subgroups. The subset selection circuitry 1150 may also select subsets for a program verify scan or an overall programming process, etc. Thus, in general, the subset selection circuit 1150 may enable adaptive and intelligent programming operations (such as adaptive smart tier scanning) that may dynamically select slower, faster, intermediate, etc. IO groups for a particular programming operation (e.g., dynamically select a slower IO group for an entire page programming).

In various implementations, memory device 1120 may be disposed in one or more different locations relative to computing device 1110. In one embodiment, the memory device 1120 includes one or more non-volatile and/or volatile memory elements 1123, such as a semiconductor chip or package or other integrated circuit device disposed on one or more printed circuit boards, a memory enclosure, and/or other mechanical and/or electrical support structures. For example, memory device 1120 may include one or more in-line memory module (DIMM) cards, one or more expansion cards and/or daughter cards, memory cards, Universal Serial Bus (USB) drives, Solid State Drives (SSDs), or other hard drive devices, and/or may have another memory and/or storage form factor. The memory device 1120 may be integrated with and/or mounted on a motherboard of the computing device 1110, mounted in a port and/or slot of the computing device 1110, mounted on a different computing device 1110, and/or on a dedicated storage device on the network 1115, communicate with the computing device 1110 over an external bus (e.g., an external hard drive), etc.

In one embodiment, the memory device 1120 may be disposed on a memory bus of the processor 1111 (e.g., on the same memory bus AS the volatile memory 1112, on a different memory bus than the volatile memory 1112, in place of the volatile memory 1112, etc.) in another embodiment, the memory device 1120 may be disposed on a peripheral bus of the computing device 1110, such AS a peripheral component interconnect Express (PCI Express or PCIe) bus, a Serial Advanced Technology Attachment (SATA) bus, a Parallel Advanced Technology Attachment (PATA) bus, a Small Computer System Interface (SCSI) bus, a FireWire bus, a fibre channel connection, a Universal Serial Bus (USB), a PCIe advanced switch (PCIe-AS) bus, etc. in another embodiment, the memory device 1120 may be disposed on a data network 1115, such AS AN Ethernet, AN Infiniband network, SCSI over network 1115, a Storage Area Network (SAN), a local area network (L), a Wide Area Network (WAN) such AS the Internet, another wired 1115, and/or wireless network, etc.

The computing device 1110 can also include a non-transitory computer-readable storage medium 1114. The computer-readable storage medium 1114 may include executable instructions configured to cause the computing device 1110 (e.g., the processor 1111) to perform steps of one or more methods disclosed herein. In one embodiment, the subgroup selection circuitry 1150 may comprise hardware of the non-volatile and/or volatile memory element 1123, computer executable program code of a device driver, firmware of the memory controller 1126 and/or a memory medium controller for the memory element 1123, another electronic component, and the like. In one embodiment, the subgroup selection circuitry 1150 may be integrated on the memory element 1123 (e.g., on-die subgroup selection circuitry 1150 and/or other integrated hardware).

According to various implementations, the memory controller 1126 may manage one or more memory devices 1120 and/or memory elements 1123, one or more of which memory devices 1120 and/or memory elements 1123 may include on-die subset selection circuitry 1150. The one or more memory devices 1120 may include recording, memory and/or storage devices, such as one or more solid state storage devices and/or one or more semiconductor storage devices, arranged and/or divided into a plurality of addressable media storage locations. As used herein, a media storage location refers to any physical unit of memory (e.g., any number of physical storage media on memory device 1120). The memory cells and/or regions may include, but are not limited to: a page, a memory partition, a block, a sector, a set or collection (e.g., a logical page, a logical block), etc., of physical memory locations.

In certain embodiments, the device driver and/or memory controller 1126 may present the storage client 1116 with a logical address space 1134. as used herein, a logical address space 1134 refers to a logical representation of a memory resource the logical address space 1134 may include a plurality (e.g., a range) of logical addresses.

A device driver for the memory device 1120 may maintain metadata 1135, such as a logical-to-physical address mapping structure, to map logical addresses of the logical address space 1134 to media storage locations on the one or more memory devices 1120. The device driver may be configured to provide storage services to one or more storage clients 1116. Storage clients 1116 may include local storage clients 1116 operating on computing device 1110 and/or remote storage clients 1116 accessible via network 1115 and/or network interface 1113. Storage clients 1116 may include, but are not limited to: an operating system, a file system, a database application, a server application, a kernel-level process, a user-level process, an application, and the like.

The device drivers may be communicatively coupled to one or more memory devices 1120. The one or more memory devices 1120 can include different types of memory devices, including but not limited to: solid state storage devices, semiconductor storage devices, SAN storage resources, volatile memory devices, non-volatile memory devices, and the like. The one or more memory devices 1120 may include one or more respective memory media controllers 1126 and memory media 1122. The device driver may provide access to one or more memory devices 1120 via a conventional block I/O interface 1131. Additionally, the device driver may provide access to enhanced functionality through the SCM interface 1132. Metadata 1135 may be used to manage and/or track data operations performed through any of block I/O interface 1131, SCM interface 1132, cache interface 1133, or other related interfaces.

Cache interface 1133 may expose cache-specific features that are accessible via a device driver for memory device 1120. Further, in some embodiments, SCM interface 1132 presented to storage client 1116 provides access to data conversion implemented by one or more memory devices 1120 and/or one or more memory media controllers 1126.

The device driver may present the logical address space 1134 to the storage client 1116 through one or more interfaces. As described above, logical address space 1134 may include a plurality of logical addresses, each corresponding to a respective media location on one or more memory devices 1120. The device driver may maintain metadata 1135, the metadata 1135 including any to any mapping between logical addresses and media locations, and the like.

The device driver may also include and/or communicate with a memory device interface 1139, the memory device interface 1139 configured to transmit data, commands, and/or queries to one or more memory devices 1120 via a bus 1125, the bus 1125 may include, but is not limited to, a memory bus of the processor 1111, a peripheral component interconnect Express (PCI Express or PCIe) bus, a serial Advanced Technology Attachment (ATA) bus, a parallel ATA bus, a Small Computer System Interface (SCSI), FireWire, fibre channel, Universal Serial Bus (USB), a PCIe advanced switch (PCIe-AS) bus, a network 1115, Infiniband, SCSIRDMA, etc. the memory device interface 1139 may communicate with the one or more memory devices 1120 using one or more input output control (IO-CT L) commands, one or more IO-CT L command extensions, remote direct memory access, etc.

The communication interfaces 1113 may include one or more network interfaces configured to communicatively couple the computing device 1110 and/or the memory controller 1126 to a network 1115 and/or to one or more network-accessible remote storage clients 1116. Storage clients 1116 may include local storage clients 1116 operating on computing device 1110 and/or remote storage clients 1116 accessible via network 1115 and/or network interface 1113. Memory controller 1126 is part of and/or in communication with one or more memory devices 1120 and/or 120. Although fig. 11 depicts a single memory device 1120, the present disclosure is not limited in this regard and may be adapted to incorporate any number of memory devices 1120, a combination of one or more volatile memory devices 1120 and one or more non-volatile memory devices 1120, and the like.

Memory device 1120 may include one or more elements 1123 of memory medium 1122. In one embodiment, elements 1123 of memory medium 1122 include volatile memory medium 1122 such as Random Access Memory (RAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate (DDR) SDRAM, Static RAM (SRAM), thyristor RAM (T-RAM), zero capacitance RAM (Z-RAM), and the like. In certain embodiments, elements 1123 of memory medium 1122 include a non-volatile memory medium 1122 such as ReRAM, memristor memory, programmable metallization cell memory, phase change memory (PCM, PCME, PRAM, PCRAM, ovonic unified memory, chalcogenide RAM, or C-RAM), NAND flash memory (e.g., 2D NAND flash memory, 3D NAND flash memory), NOR flash memory, nano-random access memory (nano-RAM or NRAM), nano-crystal line based memory, silicon oxide based sub-10 nanometer process memory, graphene memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, Programmable Metallization Cell (PMC) memory, conductive bridge RAM (cbram), magnetoresistive (RAM mram), magnetic storage medium (e.g., hard disk, magnetic tape), Optical storage media, and the like. Thus, the memory device 1120 may depend on, for example, a stored voltage level or a stored resistance level. In certain embodiments, one or more elements 1123 of memory medium 1122 comprise storage-class memory (SCM).

While conventional technologies such as NAND flash memory may be block and/or page addressable, in one embodiment, storage level memory is byte addressable. In further embodiments, the storage level memory may be faster and/or have a longer life (e.g., endurance) than the NAND flash memory; may have lower cost, use less power, and/or have higher storage density than DRAM; or to provide one or more other benefits or improvements over other techniques. For example, the storage level memory may include one or more non-volatile memory elements 1123 of ReRAM, memristor memory, programmable metallization cell memory, phase change memory, nano-RAM, nano-crystal line based memory, silicon oxide based sub-10 nanometer process memory, graphene memory, SONOS memory, PMC memory, CBRAM, MRAM, and/or variations thereof.

While the non-volatile memory medium 1122 is referred to herein as a "memory medium," in various embodiments, the non-volatile memory medium 1122 may more generally include one or more non-volatile recording media capable of recording data, which may be referred to as non-volatile memory media, non-volatile storage media, or the like. Further, in various implementations, the non-volatile memory device 1120 can include a non-volatile recording device, a non-volatile memory device, a non-volatile storage device, and so forth. Similarly, in various embodiments, the non-volatile memory elements 1123 may include non-volatile recording elements, non-volatile memory elements, non-volatile storage elements, and the like.

The non-volatile memory medium 1122 may include one or more non-volatile memory elements 1123, and the one or more non-volatile memory elements 1123 may include, but are not limited to: chip, package, plane, die, etc. The non-volatile memory controller 1126 may be configured to manage data operations on the non-volatile memory medium 1122 and may include one or more processors, programmable processors (e.g., FPGAs), ASICs, microcontrollers, etc. In some embodiments, the non-volatile memory controller 1126 is configured to store data on non-volatile memory media 1122 and/or read data from non-volatile memory media 1122, to transfer data back to one or more non-volatile memory devices 1120, and/or the like.

The non-volatile memory controller 1126 may be communicatively coupled to the non-volatile memory medium 1122 via the bus 1127. The bus 1127 may include an I/O bus for transferring data to and from the non-volatile memory elements 1123. The bus 1127 may also include a control bus for communicating addressing and other command and control information to the non-volatile memory elements 1123. In some embodiments, a bus 1127 may communicatively couple one or more non-volatile memory elements 1123 to the non-volatile memory controller 1126 in parallel. This parallel access may allow the non-volatile memory elements 1123 to be managed as a group, forming logical memory elements 1129. The logical memory elements may be divided into respective logical memory units (e.g., logical pages) and/or logical memory partitions (e.g., logical blocks). The logical memory cells may be formed by logically combining the physical memory cells of each of the non-volatile memory elements.

The non-volatile memory controller 1126 may include and/or communicate with a device driver executing on the computing device 1110. The device driver may provide storage services to the storage client 1116 via one or more interfaces 1131, 1132, and/or 1133. In some embodiments, the device driver provides a block-to-device I/O interface 1131 through which the storage client 1116 performs block-level I/O operations. Alternatively or in addition, the device driver may provide a storage-level memory (SCM) interface 1132, which SCM interface 1132 may provide other storage services to the storage client 1116. In some embodiments, SCM interface 1132 may include an extension to block device interface 1131 (e.g., storage client 1116 may access SCM interface 1132 through an extension or addition to block device interface 1131). Alternatively or in addition, the SCM interface 1132 may be provided as a separate API, service, and/or library. The device driver may be further configured to provide a cache interface 1133 for caching data using the non-volatile memory system 1102. The device driver may also include a non-volatile memory device interface 1139, the interface 1139 configured to transmit data, commands, and/or queries to the non-volatile memory controller 1126 via bus 1125, as described above.

FIG. 12 is a schematic block diagram illustrating an embodiment of a non-volatile storage 1210 for memory cell subset identification and selection. Non-volatile memory device 1210 may include one or more memory dies or chips 1212 having one or more subset selection circuits 1250. These subset selection circuits 1250 can perform the same functions and variations discussed in connection with the subset selection circuit 1150 of fig. 11. A "memory die" comprises a block of semiconductor material having memory circuitry fabricated thereon, and as used herein, further comprises memory circuitry disposed thereon. Non-volatile storage 1210 may be substantially similar to computing device 1110 described with reference to fig. 11. While the subset selection circuitry 1250 of fig. 12 is depicted towards the periphery of the memory die or chip 1212 (e.g., at the same physical level as the memory array 1200 in an integrated circuit device), in other embodiments, one or more subset selection circuitry 1250 can be disposed on a different physical level of the memory die and/or chip 1212 than the memory array 1200 (e.g., parallel to and offset from the level of the memory array 1200 in an integrated circuit device). In one embodiment, the subgroup selection circuit 1250 may be part of the on-die controller 1220. In another embodiment, the subset select circuit 1250 can be part of the read/write circuits 1230A-1230B, row decoder circuits 1240A-1240B, column decoder circuits 1242A-1242B, and so on.

In some embodiments, the memory die 1212 includes an array of memory cells 1200 (e.g., two-dimensional or three-dimensional), an on-die controller 1220, and read/write circuits 1230A/1230B. In one implementation, access to the memory array 1200 by the various peripheral circuits is implemented in a symmetric fashion, on opposite sides of the memory array 1200, so that the densities of access lines and circuitry on each side are reduced by half. In yet another embodiment, the read/write circuits 1230A/1230B include multiple sense blocks 1251 that allow a page of memory cells to be read or programmed in parallel.

In various implementations, the memory array 1200 is addressable by word lines via row decoder circuits 1240A/1240B and the memory array 1200 is addressable by bit lines via column decoder circuits 1242A/1242B. In some implementations, the controller 1244 is included in the same memory device 1210 (e.g., a removable storage card or package) as the one or more memory die 1212. Commands and data are transferred between the host and controller 1244 via lines 1232 and between the controller and the one or more memory dies 1212 via lines 1234. One implementation may include multiple chips 1212.

In one embodiment, the on-die controller 1220 cooperates with the read/write circuits 1230A/1230B to perform memory operations on the memory array 1200. In some embodiments, the on-die controller 1220 includes a state machine 1222, an on-chip address decoder 1224, and a power control circuit 1226. In one implementation, the on-chip address decoder 1224 and/or the power control circuit 1226 may be part of the controller 1244 and/or controlled by the controller 1244.

In one embodiment, the state machine 1222 provides chip-level control of memory operations. On-chip address decoder 1224 provides an address interface to translate between addresses used by a host or a memory controller to hardware addresses used by decoder circuits 1240A, 1240B, 1242A, 1242B. Power control circuit 1226 controls the power and voltages supplied to the word lines and bit lines during memory operations. In one embodiment, the power control circuit 1226 includes one or more charge pumps that can generate voltages greater than the supply voltage.

In one embodiment, one or any combination of the on-die controller 1220, the state machine 1222, the power control circuitry 1226, the on-chip address decoder 1224, the decoder circuitry 1242A, the decoder circuitry 1242B, the decoder circuitry 1240A, the decoder circuitry 1240B, the read/write circuits 1230A, the read/write circuits 1230B, and/or the controller 1244 may be referred to as one or more managing circuits.

Figure 13 is a block diagram illustrating one embodiment of a subset select circuit 1350. As indicated in connection with the subset selection circuits of FIGS. 11 and 12, the subset selection circuit 1350 may be located at various locations on a memory die or chip and may perform various functions in connection with the identification of subsets having particular programming characteristics or state change characteristics. The subset selection circuit 1350 shown in fig. 13 includes a state change/programming circuit 1330, a counting circuit 1331, a determination circuit 1332, and an identification circuit 1333.

As used herein, "state change circuit" or "programming circuit" refers to any circuit for performing or delivering one or more programming cycles. For example, the programming circuitry may perform step 1010 of FIG. 10. As used herein, "counting circuitry" refers to circuitry that counts the total number of memory cells that satisfy a programming threshold during a program verify operation within each subset and/or the total number of memory cells that satisfy a programming threshold in all subsets. By way of example, the counting circuit may perform steps 1020 or 1040 of fig. 10.

As used herein, "determining circuitry" refers to any circuitry that infers, calculates, considers, or determines the relative rate of change of state of two or more subsets of memory cells. For example, each memory cell has a data state that includes at least a first data state (e.g., a higher or lower data state) and a second data state (e.g., a higher or lower data state). The determination circuit may determine which subset of memory cells from a set of subsets of memory cells transitions from the first state to the second state or from the second state to the first state more quickly.

In certain implementations, the variable characteristic of the memory cell is used to represent or store a data value (e.g., a binary 1 or a binary 0). A memory cell may be used to store a multi-bit data value if its variable characteristic may have more than two different values/settings. Each distinct value of a characteristic of a memory cell is referred to herein as a data state. For example, in one implementation, a threshold voltage level or a threshold resistance level in a memory cell may comprise a data state.

In certain embodiments, the relationship between data states and characteristics is linear. Thus, if the first data state includes a threshold voltage level that is higher than the threshold voltage level represented by the second data state, the first data state may be higher than the second data state. A state change occurs when the data state of a memory cell changes from one data state to another (or to an intermediate data state). In some embodiments, one data state is considered lower than another data state because its corresponding threshold voltage level is lower than the other data state. Moving from a lower data state to a higher data state may involve, for example, transitioning from a lower threshold voltage level to a higher threshold voltage level stored in the memory cell. Moving from a lower data state to a higher data state may also involve, for example, transitioning from a lower threshold resistance level to a higher threshold resistance level. The state change may also involve transitioning from a higher data state to a lower data state, for example, during an erase procedure.

In an embodiment of the solution, one goal is to determine the rate of change of state of a group of memory cells. The rate of change of state is a measure of how (e.g., the magnitude of the change) the state of a memory cell changes within a given number of program pulses or erase pulses. Thus, the relative rate of change of state of a subset of memory cells indicates how fast or slow the subset of memory cells changes from one data state to another data state relative to at least one other subset of memory cells undergoing a similar set of programming or erase pulses. For example, the determination circuitry may perform steps 1020, 1030, 1040 shown in FIG. 10. As used herein, "identification circuitry" refers to circuitry for identifying a programming speed of a subset of memory cells relative to at least one other subset of memory cells. For example, the step identified in step 1050 of FIG. 10 may be performed using identification circuitry.

In one embodiment, the state change/programming circuit 1330 is configured to change the data state of each of the memory cells in the memory array by delivering (or supplying) a programming cycle to at least some of the memory cells. In other words, the state change/programming circuit 1330 is configured to apply one or more programming pulses to the array of memory cells to program the memory cells to the target data state. The target data state can be any desired data state of a memory cell or a subset of memory cells. Each programming cycle covers a single programming pulse and extends until a subsequent programming pulse is sent. For example, the state change/programming circuit 1330 sends a series of programming pulses to a selected word line coupled to the memory cells of the memory array. The programming pulse may increase in magnitude (e.g., increase in voltage in a linear or non-linear manner) over multiple programming cycles to gradually (or incrementally) increase the threshold voltage of the memory cell (e.g., a threshold voltage in a flash configuration or a resistance state in a resistive memory configuration) to a state corresponding to the stored data. The term "progressively" or "incrementally" means occurring gradually over time (e.g., over multiple programming cycles).

In one embodiment, the counting circuit 1331 is configured to count the total number of memory cells within a group of memory cells that satisfy a programming threshold in order to determine whether the total number of memory cells satisfies a digital threshold. This counting process may occur during or after a program verify operation. The program threshold may be, for example, an A-state program verify level or any other verify level. The number threshold may be any predetermined number (such as a predetermined positive integer) or any number derived (such as a percentage of memory cells within a given group or subgroup of memory cells).

In one implementation, the number of memory cells that meet (e.g., meet or exceed) the programming threshold is determined to be greater than (e.g., exceed) the digital threshold before the counting circuit 1331, determining circuit 1332, and/or identifying circuit 1333 perform their respective operations. In this way, certain subsequent operations performed by the counting circuit 1331, the determining circuit 1332, and/or the identifying circuit 1333 may be delayed/avoided until a sufficient sample size of memory cells meeting the programming threshold is obtained. For example, if it is determined that the number of memory cells that exceed the programming threshold satisfies the digital threshold, the count circuit 1331 may continue to count the number of memory cells in each individual subset of memory cells that satisfy the programming threshold. As previously described, determination circuit 1332 and/or identification circuit 1333 may also continue to determine/identify the relative rate of change of state (e.g., programming speed) of at least a subset of the memory cells. In one embodiment, if it is determined that the number of memory cells that satisfy the programming threshold satisfies the digital threshold (e.g., the number of memory cells that satisfy the programming threshold is greater than or less than the digital threshold), the counting circuit 1331 may continue to count a first number of cells of the first subset that satisfy the programming threshold and to count a second number of cells of the second subset that satisfy the programming threshold.

In one embodiment, the determination circuit 1332 is configured to determine the relative rates of state change for at least two subsets of memory cells. For example, the relative rates of state change of the subsets of memory cells can be characterized numerically (e.g., by the number of memory cells in a first subset of memory cells that satisfy a programming threshold relative to the number of memory cells in a second subset of memory cells that satisfy the programming threshold), or via suitable tag/state change characteristics (e.g., fastest subset of memory cells, slowest subset of memory cells, intermediate subsets of memory cells, etc.).

In one embodiment, the identification circuit 1333 is configured to identify a subset of memory cells that meet the state change characteristics based on the relative rates of state change of at least two subsets of memory cells. For example, it may be desirable to identify and select a particular subset of memory cells (e.g., the fastest/slowest/middle subset of memory cells relative to programming speed) having particular state change characteristics in order to complete a programming operation (e.g., a program verify operation). In this embodiment, identification circuit 1333 may identify a subset of memory cells that meet the desired state change characteristics and/or select the identified subset of memory cells for use during a programming operation (e.g., a verify step of a programming operation using the identified subset).

In one embodiment, the identification circuit 1333 is configured to identify the first subset as the fastest subset of memory cells and the second subset as the slowest subset of memory cells in response to a first number of cells of the first subset satisfying a threshold (e.g., a program verify level) being greater than a second number of cells of the second subset satisfying the threshold.

In one implementation, the identification circuit 1333 is configured to identify at least one of: (1) the fastest subset of memory cells when the state change/programming circuit 1330 changes the data state of at least some of the memory cells from a lower data state to a higher data state; and (2) the slowest subset of memory cells when the state change/programming circuit 1330 changes the data state of at least some of the memory cells from a lower data state to a higher data state (or to an intermediate data state).

In one embodiment, the identification circuit 1333 is configured to identify at least one subset of memory cells (e.g., fastest/slowest/intermediate subset of memory cells) that meet the state change characteristics during each programming operation (e.g., during each program verify operation). This may be useful in certain situations, such as: (1) wherein a tradeoff between data accuracy and overall speed of the memory device is favorable for data accuracy; (2) once the memory device has entered its "end of use" or "end of expected life" time period (e.g., the memory device has completed many write cycles, such as having written a certain number of Terabytes to the memory device); and (3) if the memory device begins to detect a certain number or percentage of data errors.

However, it should also be understood that in other embodiments, the identification circuit 1333 may be configured to identify at least a subset of memory cells that meet the state change characteristic according to a predetermined schedule. For example, the predetermined schedule may include: (1) once at the time of manufacture or initial testing of the memory device; or (2) periodically (e.g., after a number of programming operations have been completed, after a period of time has elapsed, etc.).

Embodiments of the devices disclosed herein include a plurality of memory cells and a state change circuit configured to change a data state of each of the memory cells. The apparatus further comprises: a determination circuit configured to determine a relative rate of change of state of two subsets of memory cells; and an identification circuit configured to identify a subset of memory cells that satisfy the state change characteristic based on the relative rate of state change.

In one embodiment of the apparatus, the identified subset of memory cells that satisfy the state change characteristic may include at least one of a fastest subset of memory cells and a slowest subset of memory cells. In one embodiment of the device, the data states of each of the memory cells include at least a lower data state and a higher data state. The identification circuit is further configured to identify at least one of: the memory cell subset that is fastest when the state change circuit changes the data state of at least some of the memory cells from a lower data state to a higher data state, and the memory cell subset that is slowest when the state change circuit changes the data state of at least some of the memory cells from a lower data state to a higher data state.

In one embodiment of the apparatus, the apparatus further includes a counting circuit configured to count a total number of memory cells that satisfy the programming threshold and determine whether the total number satisfies a digital threshold. The identification circuit is further configured to identify a subset of the memory cells that satisfy the state-change characteristic in response to a total number of the memory cells that satisfy the programming threshold being greater than a digital threshold. In one embodiment of the device, the digital threshold comprises at least one of a predetermined number and percentage of memory cells.

In one embodiment of the device, the identification circuit is configured to identify the subset of memory cells according to a predetermined schedule. In one embodiment of the apparatus, the identified subset of memory cells includes a set of layers.

Embodiments of a non-volatile memory storage system include an array of memory cells organized into a plurality of subgroups, and programming circuitry configured to apply one or more programming pulses to the array of memory cells to program the memory cells to a target data state. The non-volatile memory storage system further comprises: a counting circuit configured to count a first number of cells of a first subset that satisfy a threshold and to count a second number of cells of a second subset that satisfy the threshold; and an identification circuit configured to identify the first subset as a fastest subset of memory cells and the second subset as a slowest subset of memory cells in response to the first number of cells being greater than the second number of cells.

In one embodiment of the non-volatile memory storage system, the identification circuit is further configured to identify at least one intermediate programming speed subset of memory cells.

In one embodiment of a non-volatile memory storage system, the target data state of a memory cell includes at least one of a lower data state and an upper data state. The identification circuit is further configured to identify at least one of: the fastest subset of memory cells when the programming circuitry is to program the memory cells from a lower data state to a higher data state, and the slowest subset of memory cells when the programming circuitry is to program the memory cells from a lower data state to a higher data state.

In one embodiment of the non-volatile memory storage system, the identification circuit is configured to identify a fastest subset of memory cells and a slowest subset of memory cells during each programming procedure. In an embodiment of the non-volatile memory storage system, the identification circuit is configured to identify the fastest subset of memory cells and the slowest subset of memory cells according to a predetermined schedule. In one implementation of a non-volatile memory storage system, the fastest subset of memory cells and the slowest subset of memory cells comprise a set of layers.

In one embodiment of the memory device, the memory device is configured to apply one or more programming pulses to a subset of the memory cells in a programming operation. The memory device is further configured to count a total number of memory cells that satisfy the programming threshold, determine whether the total number is greater than a digital threshold, and determine a number of memory cells within each sub-group that satisfy the programming threshold in response to determining that the total number is greater than the digital threshold. The memory device is further configured to identify at least one of a fastest programming subset and a slowest programming subset based on the determined number of memory cells within each subset, and to use the identified subset for a verification step of the programming operation.

In one implementation of a memory device, in a programming operation, applying one or more programming pulses to a subset of memory cells changes the data states of at least some of the memory cells, where the data states include at least a lower data state and a higher data state. Identifying at least one of the fastest programming subset and the slowest programming subset further comprises at least one of: the fastest programming subset is identified when the programming operation changes the data state of at least some of the memory cells from a lower data state to a higher data state, and the slowest programming subset is identified when the programming operation changes the data state of at least some of the memory cells from a lower data state to a higher data state.

In one embodiment of the memory device, the memory device further includes identifying intermediate programming speed subgroups based on the determined number of memory cells within each subgroup. In one embodiment of the memory device, the identifying of at least one of the fastest programming subset and the slowest programming subset is performed during each programming operation. In one embodiment of the memory device, the identifying of at least one of the fastest programming subset and the slowest programming subset is performed according to a predetermined schedule. In one implementation of the memory device, the identified subset includes a set of layers.

Fig. 14 illustrates an example of a voltage distribution 1400 that exists over time in a multi-level flash memory cell in accordance with one or more implementations. The voltage profile 1400 shown in fig. 14 is simplified for illustrative purposes.

After a programming operation, a group of memory cells associated with voltage distribution 1400 is connected to a word line, where eight data states are used. The Vth distribution 1410 is provided for erased (Er) state memory cells. Vth distributions 1420, 1422, 1424, 1426, 1428, 1430 and 1432 represent assigned data states A, B, C, D, E, F and G, respectively, which are reached when the threshold voltage (Vth) of a memory cell exceeds a verify voltage VvA, VvB, VvC, VvD, VvE, VvF or VvG, respectively. Read voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG are used to read data from a group of cells having the Vth distribution.

Three pages of data may be stored with eight data states or three bits per cell. Example codes for bits for A, B, C, D, E, F and the G state are 111, 110, 100, 000, 010, 011, 001, and 101, respectively. The data of the lower page can be determined by reading the memory cells using the read voltages of VrA and VRE. The data of the middle page can be determined by reading the memory cells using the read voltages of VrB, VrD, and VrF. The data of the upper page can be determined by reading the memory cells using the read voltages of VrC and VrG.

The read voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG are positioned between adjacent center voltages (e.g., positioned at or near a midpoint between the adjacent center voltages), and thus define threshold voltages between voltage ranges 1410, 1420, 1422, 1424, 1426, 1428, 1430, and 1432. during a read operation, one of the read voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG is applied to determine the cell voltage using a comparison process.

In one embodiment, a "program threshold" or "threshold" may include a lowest verify or verify level, such as an A verify level (e.g., VvA), regardless of the number of states that may be stored in each memory cell.

The present disclosure may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the disclosure is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.