阅读说明：本技术 改善闪存的读取重试的方法、控制器以及相关存储装置 (Method for improving read retry of flash memory, controller and related memory device ) 是由 杜建东 蔡璧如 杨宗杰 于 2019-02-12 设计创作，主要内容包括：本发明公开了一种管理闪存模块的多个存储单元的方法。所述方法包括：针对每一第一存储单元的数据写入时间建立对应于所述第一存储单元的编程时戳；根据所述第一存储单元的所述编程时戳,选择相对应的读取重试表来对所述第一存储单元进行读取操作；以及根据已写入数据的第一存储单元的编程时戳,执行第一刷新操作。通过周期性地对已写入数据的第一存储单元进行刷新,并且在每个使用历程中执行前一个使用历程中有写入的存储单元,本发明能够有效地减少所需的读取重试表的数量。此外,通过周期性地选择第二存储单元的部分进行错误检查,本发明能够更好地保证读读取重试表的数量在减少后仍能有效率地进行读取重试,进而改善读取重试的效率。(The invention discloses a method for managing a plurality of memory cells of a flash memory module. The method comprises the following steps: establishing a programming time stamp corresponding to each first storage unit for a data write time of the first storage unit; selecting a corresponding read retry table to perform a read operation on the first storage unit according to the programming timestamp of the first storage unit; and executing a first refresh operation according to the programming time stamp of the first memory cell in which the data is written. By periodically refreshing the first memory cell to which data has been written and executing the memory cell written in the previous usage history in each usage history, the present invention can effectively reduce the number of read retry tables required. In addition, by periodically selecting the part of the second storage unit for error check, the invention can better ensure that the read retry can be efficiently performed after the number of the read retry tables is reduced, thereby improving the efficiency of the read retry.)

1. A method of managing a plurality of memory cells in a flash memory module, comprising:

establishing a programming time stamp corresponding to each first storage unit according to the data writing time of the first storage unit;

selecting a corresponding read retry table to perform a read operation on the first memory cell according to the programming timestamp of the first memory cell; and

and executing a first refresh operation according to the programming time stamp of the first memory cell written with the data.

2. The method of claim 1, further comprising:

performing an error check on at least a portion of each of the second memory cells to which data has been written; and

and executing a second refresh operation according to the error check result.

3. The method of claim 2, wherein flushing the second refresh operation based on the result of the error check comprises:

when the error checking result indicates that the number of error bits included in at least one part of a second storage unit is larger than a critical value, reading out data stored in a first storage unit including the second storage unit, correcting the data and writing the corrected data into another first storage unit; and

a programming time stamp associated with the other first memory cell is established.

4. The method of claim 1, wherein the step of performing the first refresh operation comprises:

the first refresh operation is performed in a second usage history for a plurality of first memory cells to which data has been written in a first usage history, wherein the first usage history follows the second usage history, and the first refresh operation is to complete a refresh for all first memory cells in the second usage history.

5. The method of claim 4, wherein selecting the corresponding read retry table comprises:

selecting a first read retry table for reading of the first memory cell to which data is written in the first usage history; and

and selecting a second read retry table for reading the first memory cell written with data in the second use history.

6. The method of claim 1, wherein performing the portion of the first refresh operation comprises:

for each first memory cell:

reading out data stored in the first storage unit and writing the data into another first storage unit; and

a program time stamp of the other first memory cell is established.

7. A controller for managing a plurality of memory cells of a flash memory, comprising:

a storage unit for storing a program code; and

a processing unit, coupled to the storage unit, for reading the program code from the storage unit to execute the program code, thereby performing the following operations:

establishing a programming time stamp corresponding to each first storage unit according to the data writing time of the first storage unit;

selecting a corresponding read retry table to perform a read operation on the first memory cell according to the programming timestamp of the first memory cell; and

and executing a first refresh operation according to the programming time stamp of the first memory cell written with the data.

8. The controller as claimed in claim 7, wherein said processing unit executes said program code to perform an error check on at least a portion of each of the second storage units to which data has been written; and executing a second refresh operation according to the result of the error check.

9. The controller as claimed in claim 8, wherein the processing unit executes the program code to read data stored in a first storage unit including a second storage unit and correct the data for writing to another first storage unit when the result of the error check indicates that at least a portion of the second storage unit includes more error bits than a threshold; and establishing a programming time stamp of the other first memory cell.

10. The controller of claim 7, wherein the processing unit executes the program code to perform the first refresh operation in a second usage history for a plurality of first memory cells having writes in a first usage history, wherein the first usage history follows the second usage history, and the first refresh operation completes a refresh for all first memory cells in the second usage history.

11. The controller of claim 10, wherein the processing unit executes the program code to:

selecting a first read retry table for reading of the first memory cell to which data is written in the first usage history; and

and selecting a second read retry table for reading the first memory cell written with data in the second use history.

12. The controller of claim 7, wherein the processing unit executes the program code to, for each first storage unit: reading out data stored in the first storage unit and writing the data into another first storage unit; and establishing a programming time stamp of the other first memory cell.

13. A memory device, comprising:

a flash memory module, including a plurality of memory cells; and

a controller for accessing a flash memory module, comprising:

a storage unit for storing a program code; and

a processing unit, coupled to the storage unit, for reading the program code from the storage unit to execute the program code, thereby performing the following operations:

establishing a programming time stamp corresponding to each first storage unit according to the data writing time of the first storage unit;

selecting a corresponding read retry table to perform a read operation on the first memory cell according to the programming timestamp of the first memory cell; and

and executing a first refresh operation according to the programming time stamp of the first memory cell written with the data.

14. The memory device as claimed in claim 13, wherein the controller further performs an error check on at least a portion of each of the second memory cells to which data has been written; and executing a second refresh operation according to the result of the error check.

15. The memory device as claimed in claim 14, wherein the controller reads data stored in a first memory cell including a second memory cell when the error check result indicates that at least a portion of the second memory cell includes a greater number of error bits than a threshold value, and writes the corrected data to another first memory cell; and establishing a programming time stamp of the other first memory cell.

16. The memory device according to claim 13, wherein the controller performs the first refresh operation in a second usage history for a plurality of first memory cells to which data has been written in a first usage history, wherein the first usage history is subsequent to the second usage history, and the first refresh operation is to complete the refresh for all the first memory cells in the second usage history.

17. The memory device of claim 16, wherein the controller selects a first read retry table for a read of a first memory location to which data was written during the first usage history; and selecting a second read retry table for reading the first memory cell to which data is written in the second usage history.

18. The storage device of claim 13, wherein the controller, for each first storage unit: reading out data stored in the first storage unit and writing the data into another first storage unit; and establishing a programming time stamp of the other first memory cell, thereby completing the first refresh operation.

Technical Field

The present invention relates to flash memory, and more particularly, to a method and related controller for improving read retry of flash memory and related memory device.

Background

In recent years, the use of flash memory has become more popular, especially in various types of mobile devices. The reason is that the flash memory has the characteristics of high speed, high density, non-volatility, and the like compared with other conventional memory devices. However, although the flash memory has the advantages mentioned above, there are still some drawbacks that have to be looked upon, namely, the lifetime and Data Retention (Data Retention). Memory cells (e.g., blocks) in a flash memory are often used for a certain number of times, resulting in errors and failure to read correct data. Among them, the cause of the error is mainly related to the number of times of erasing (Program/Erase Cycles) and the data storage time. Generally, flash memories have a higher probability of error occurrence after more erase cycles or when the stored data is not updated for a long time. Therefore, the controller often needs to perform read retries on the flash memory to improve the chances of correctly reading data by adjusting the read voltage. However, during the read retry, various combinations of read voltages may be tried according to the above factors such as the number of times of erasing and the data storage time, so as to correctly read data. However, such a process increases the delay, decreasing the reading efficiency.

Disclosure of Invention

In view of the above-mentioned problems, the present invention discloses a management mechanism of a flash memory device to improve read retry. The method of the invention reduces the influence of data storage time on read retry by periodically refreshing the data stored in the memory cells in the flash memory. That is, the storage time of data in the memory cell varies within a small range, so that the adjustment width of the read voltage in the read retry can be effectively reduced. On the other hand, the invention also adds an error checking mechanism to carry out conditional refreshing aiming at the memory cells with high error rate, thus reducing the burden of read retry operation.

An embodiment of the invention discloses a method for managing a plurality of memory cells in a flash memory module. The method comprises the following steps: establishing a programming time stamp corresponding to each first storage unit according to the data writing time of the first storage unit; selecting a corresponding read retry table to perform a read operation on the first memory cell according to the programming timestamp of the first memory cell; and executing a first refresh operation according to the programming time stamp of the first memory cell in which the data is written.

An embodiment of the invention discloses a controller for managing a plurality of memory cells of a flash memory. The controller includes: a storage unit and a processing unit. The storage unit is used for storing a program code. The processing unit is coupled to the storage unit, and configured to read the program code from the storage unit to execute the program code, so as to perform the following operations: establishing a programming time stamp corresponding to each first storage unit according to the data writing time of the first storage unit; selecting a corresponding read retry table to perform a read operation on the first memory cell according to the programming timestamp of the first memory cell; and executing a first refresh operation according to the programming time stamp of the first memory cell in which the data is written.

An embodiment of the invention discloses a storage device. The storage device includes: a flash memory module and a controller. The flash memory module includes a plurality of memory cells. The controller is used for accessing the flash memory module and comprises: a storage unit and a processing unit. The storage unit is used for storing a program code. The processing unit is coupled to the storage unit, and configured to read the program code from the storage unit to execute the program code, so as to perform the following operations: establishing a programming time stamp corresponding to each first storage unit according to the data writing time of the first storage unit; selecting a corresponding read retry table to perform a read operation on the first memory cell according to the programming timestamp of the first memory cell; and executing a first refresh operation according to the programming time stamp of the first memory cell in which the data is written.

Drawings

FIG. 1 is a block diagram illustrating an architecture of a related memory device, a controller and a flash memory module according to an embodiment of the invention.

Fig. 2 explains how the invention chooses to read the retry table.

Fig. 3 explains how the present invention performs a first refresh operation for a first memory cell.

FIG. 4 is a flow chart illustrating the selection of the read retry table and the execution of the first refresh operation according to an embodiment of the present invention.

FIG. 5 is a flow chart showing a second refresh operation in the embodiment of the present invention.

FIG. 6 illustrates a selection of the second sub-memory cells for error checking in an embodiment of the present invention.

Fig. 7 explains association of the first refresh operation with the second refresh operation in the embodiment of the present invention.

Wherein the reference numerals are as follows:

100 storage device

120 controller

122 processing unit

124 memory cell

130 flash memory module

130_1 ~ 130_ N flash memory chip

UNT 1-UNTM first storage unit

SUNT1 SUNTQ second memory cell

SSUNT 1-SSUNTZ second sub-memory cell

410-430, 510-530 steps

200 host

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the invention to the reader. However, it will be apparent to one skilled in the art how to implement the invention without one or more of the specific details, or with other methods or components, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

Moreover, any examples or illustrations presented herein are not intended to be limited or defined by any of the words used therein. Rather, these examples or illustrations should be considered in descriptive sense only and with respect to one particular embodiment. It will be appreciated by those skilled in the art that any words used in these examples or illustrations will encompass other embodiments given elsewhere in this specification. Where words used to indicate such non-limiting examples include, but are not limited to: "for example," such as, "" for example, "" in one embodiment, "and" in an example.

The flowcharts and blocks in the flowcharts within this specification illustrate the architecture, functionality, and operation of what may be implemented by systems, methods and computer software products according to various embodiments of the present invention. In this regard, each block in the flowchart or functional block diagrams may represent a module, segment, or portion of program code, which comprises one or more executable instructions for implementing the specified logical function(s). In addition, each block of the functional block diagrams and/or flowchart illustrations, and combinations of blocks, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer program instructions. These computer program instructions may also be stored in a computer-readable medium that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable medium implement the function/act specified in the flowchart and/or block diagram block or blocks.

FIG. 1 is a schematic diagram of an embodiment of the present invention. As shown, the memory device 100 includes a controller 120 and a flash memory module 130, and is controlled by a host (host device)200 (the memory device 100 may even be a part of the host 200). The host 200 may include at least one central processing unit (not shown), and controls the operation of the host 200 by operating an operating system and an application program, and is linked with a peripheral device (not shown). The memory device 100 may be used to provide memory space for the host 200 to store the program codes and data necessary to operate the operating system and various application programs. Examples of the master device 50 may include: a multifunctional mobile phone (tablet), a wearable device (wearable), and a personal computer (personal computer) such as a desktop computer or a notebook computer. Examples of storage device 100 may include (but are not limited to): solid State Drives (SSDs) and various embedded storage devices (e.g., embedded storage devices conforming to the UFS or EMMC specifications).

The controller 120 may be used to access (access) the flash memory module 130. In one embodiment, the Flash memory module 130 may be a stereo NAND type Flash memory (3D NAND-type Flash) and may include at least one Flash memory chip (Flash memory), but this is not a limitation of the present invention. Each flash memory chip comprises a plurality of blocks (blocks), and the data erasing operation of the flash memory module 130 by the controller 120 is performed in units of blocks. In addition, one block can record a specific number of pages (pages), and the data writing operation of the controller 120 to the flash memory module 130 is performed in units of pages.

The controller 120 may include processing circuitry such as a microprocessor 122, and a storage unit 124 such as a Read Only Memory (ROM), wherein the ROM 124 is used for storing program codes and specific data, and the microprocessor 122 is used for executing the program codes to control access to the flash Memory module 130. In addition, the controller 120 may include other interface logic, control logic, buffers, etc. to facilitate various operations described below. However, for the sake of brevity of the description, it is omitted here. Those skilled in the art will understand how to implement various operations and related applications of the present invention using known circuits and circuit elements and configurations described herein, after reading the following description.

In this embodiment, the host 200 may indirectly access the memory device 100 by transmitting a host command (host command) and a corresponding logical address to the controller 120. The controller 120 receives a master command (read or write command) and a logical address, translates the master command into a memory operation command, and controls the flash memory module 130 to read, write, program, or erase (erase) a memory cell (memory) or a data page (page) or a block (block) at a specific physical address in the flash memory module 130 according to the memory operation command. The controller 120 executes the program code 1242C and/or references data in the memory unit 124 to perform a sequence of operations to implement certain operations described below.

For a read operation, if the controller 120 cannot read correct data in one read operation, the controller 120 reads one or more read retry tables stored in the storage unit 124, and controls the flash memory module 130 to read data at different read voltages according to the read voltages recorded in the read retry tables, so as to correctly read data required by the host 200.

In the present invention, the selection of the controller 120 to read the retry table is related to the data retention time. The controller 120 establishes a program time stamp corresponding to each first memory cell in the flash memory module 130 according to the time information corresponding to the write operation of the first memory cell. When the host 200 subsequently issues a read command, the controller 120 selects to read the retry table according to the information in the program timestamp and the system time. In one embodiment, the first storage unit may be a super block.

Please further refer to the example of fig. 2. In the example, it is assumed that the flash memory module 130 includes the first memory cells UNT 1-UNTM (not limiting the invention), and that there are data written in the first memory cell UNT1 in the history of use P1, data written in the first memory cell UNT2 in the history of use P2, and data written in the first memory cell UNT3 in the history of use P3. Then, if in the usage history P1, when the host 200 issues a read command requesting to read the data in the first memory cell UNT1, the controller 120 reads using the retry table read RTAB 1. If, in the usage history P2, when the host 200 issues a read command requesting reading of data in the first memory cell UNT1, the controller 120 reads using the read retry table RTAB2, and a read operation for data in the first memory cell UNT2 in the usage history P2 reads using the read retry table RTAB 1. If the host 200 issues a read command requesting to read data in the first memory cell UNT1, the first memory cell UNT2 and the first memory cell UNT3 in the usage history P3, the controller 120 reads the data using the read retry tables RTAB3, RTAB2 and RTAB1, respectively. The reading retry tables RTAB3, RTAB2 and RTAB1 are sequentially suitable for reading data with long data storage time and short data storage time.

In one embodiment, to reduce the number of read retry tables and thereby improve the efficiency of read retries, the controller 120 performs a first refresh operation globally and periodically with respect to the program time stamps corresponding to the first memory cells in the flash memory module 130. referring to the example of FIG. 3, the operation principle and effect of the first refresh operation of the present invention can be further understood, as shown in the figure, assuming that the flash memory 130 includes the first memory cells UNT 1-UNTM (which is not a limitation of the present invention), the controller 120 maintains a refresh list R L IST in the memory cells 124, records the program time stamps corresponding to each first memory cell, and performs the refresh operation by sorting according to the new and old memory cells.

The controller 120 refreshes the first memory cell UNT and UNT having data written therein in the previous usage history P in the current usage history P and completes the refresh operation before the end of the current usage history P, as in the present embodiment, the controller 120 refreshes the first memory cell UNT and UNT having data written therein in the previous usage history P according to the sequence of the refresh list R IST for the first memory cell UNT and UNT having data written therein in the previous usage history P and completes the refresh operation before the end of the usage history P, and in the usage history P, the controller 120 refreshes the first memory cell UNT and UNT having data written therein in the previous usage history P according to the sequence of the refresh list R IST for the first memory cell UNT and UNT having data written therein in the previous usage history P, and completes the refresh operation before the end of the usage history P, and in the refresh history P, the controller 120 controls the refresh operation for the first memory cell UNT and UNT having data written therein in the previous usage history P and the refresh history P, and the refresh operation for the first memory cell UNT and the refresh history P.

In this way, the data retention time of any first memory cell in the flash memory module 130 is only two usage histories at the maximum (assuming that the refresh is completed at the end of one usage history at the latest). Therefore, only two read retry tables RTAB1 and RTAB2 need to be stored in the memory unit 124 of the controller 120 to cover all read errors caused by too long a storage time. For example, if in the usage history P2, when the data in the first memory cell UNT1 is to be read, if the data in the first memory cell UNT1 has been moved to the first memory cell UNT3 by the refresh operation, then only the read retry table RTAB1 is needed for reading; also in the history P2, when the data in the first memory cell UNT4 is to be read, if the data in the first memory cell UNT4 is not refreshed at this time, the read retry table RTAB2 is required for reading.

The above first refresh operation and the selection of the read retry table can be summarized as the flow shown in fig. 4, which includes the following steps:

step 410: establishing a programming time stamp corresponding to each first storage unit according to the data writing time of the first storage unit;

step 420: selecting a corresponding read retry table to perform a read operation on the first memory cell according to the programming timestamp of the first memory cell; and

step 430: and executing a first refresh operation according to the programming time stamp of the first memory cell written with the data.

Since the steps 410-430 are simplified from the operations described in the previous embodiments, the description thereof will not be repeated.

In one embodiment, in order to increase the reliability of the data and to ensure the success rate of the read retry, a second refresh operation is performed in addition to the first refresh operation. The flow of the second refresh operation is shown in fig. 5, and includes the following steps:

step 510: performing an error check on at least a portion of each of the second memory cells to which data has been written; and

step 520: when the error checking result indicates that the number of error bits is larger than a critical value, reading data stored in a first storage unit comprising the second storage unit, correcting the data and writing the corrected data into another first storage unit; and

step 530: a program time stamp of the other first memory cell is established.

Please further combine the description of fig. 6 to further understand how the second refresh operation is performed according to the embodiment of the present invention. As shown, the flash memory 130 may include a plurality of second memory units sut 1, sut 2, … and SNTQ having the same size. Each of the SUNT 1-SUNTQ cells may include the same number of second sub-cells SSUNT 1-SSUNTZ.

In step 510, the controller 120 performs an error check on at least a portion of each of the second memory cells SUNT 1-SUNTQ. In one embodiment, the controller 120 unit may select the second sub-storage unit SSUNT1 from the second storage unit SUNT1, select the second sub-storage units SSUNT2, … from the second storage unit SUNT2, and select the second sub-storage unit SSUNTQ from the second storage unit SNTQ for error checking. This is chosen to avoid non-uniform sampling. For example, if sub-storage unit SSUNT1 or SSUNTQ is selected for checking in each second storage unit, then it is possible that the same numbered sub-storage units have similar physical characteristics because they are physically close, and that other storage units that have different physical characteristics and are prone to errors are ignored. In one embodiment, the second sub-storage units SUNT 1-SUNTP may be super pages (super pages), and the second sub-storage units SSUNT 1-SSNTQ may be pages.

In the present invention, the second refresh operation is conditional, that is, the controller 120 performs the second refresh operation on the memory cells including the second sub-memory cells only when the selected second sub-memory cells fail to pass the error check. In step 520, the controller 120 determines whether the error check is passed by checking whether the number of error bits of the selected second sub-memory cell exceeds a threshold. If the error checking result indicates that the number of error bits of at least a portion of a second memory cell is greater than a threshold value, the controller 120 reads the data stored in the first memory cell including the second memory cell, corrects the data, and writes the corrected data into another first memory cell. That is, if the number of error bits in one of the pages of super data is checked to be too high, the data of a first super block including the second super page of data is refreshed. And in step 530, a program time stamp for the first memory cell is established. This is the second refresh operation of the present invention.

In the present embodiment, the first memory cell to be refreshed is inserted into the sequence of the refresh list R L IST stored in the memory cell 124 of the controller 120. please refer to the description of fig. 7. as shown in fig. 7, the controller 120 originally performs the first refresh operation according to the refresh list R L IST, and periodically performs the sequence of UNT2, UNT3, UNT4 and UNT6, and also periodically performs the error check at the same time, however, when the controller 120 finds that a certain checked second memory cell sut 2 cannot pass the check at the time point T1, the controller inserts the corresponding second refresh operation of the first memory cell UNT3 including the second memory cell sut 2 into the refresh list R L IST, and performs the refresh operation of the data in the first memory cell UNT3 at the time point T2.

As described above, the present invention periodically refreshes the first memory cell (e.g., super block) to which data has been written. And in each use history, executing the memory unit written in the previous use history, thereby effectively reducing the number of required read retry tables. And, by periodically selecting part (e.g. data page) of the second memory unit to perform error check, it is better to ensure that the number of read retry tables can be reduced and read retry can be performed efficiently. Thus, the efficiency of read retries can be improved.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.