阅读说明：本技术 磁阻随机存取存储单元 (Magnetoresistive random access memory cell ) 是由 王慧琳 曾译苇 王明俊 翁宸毅 谢晋阳 张境尹 王裕平 林建廷 刘盈成 施易安 于 2019-01-14 设计创作，主要内容包括：本发明公开一种磁阻随机存取存储单元,其包含：一基底,其上具有一介电层；一导孔,设于该介电层中；一柱状堆叠,设于该导孔上,该柱状堆叠包含一底电极、一磁隧穿结层,设于该底电极上,以及一顶电极,设于该磁隧穿结层上；以及一间隙壁层,设于该柱状堆叠的侧壁上,其中该顶电极凸出于该间隙壁的一顶面。(The invention discloses a magnetic resistance random access memory unit, which comprises: a substrate having a dielectric layer thereon; a via hole in the dielectric layer; a columnar stack disposed on the via, the columnar stack comprising a bottom electrode, a magnetic tunneling junction layer disposed on the bottom electrode, and a top electrode disposed on the magnetic tunneling junction layer; and a spacer layer disposed on the sidewall of the columnar stack, wherein the top electrode protrudes from a top surface of the spacer.)

1. A magnetoresistive random access memory cell, comprising:

a substrate having a dielectric layer thereon;

a via hole disposed in the dielectric layer;

a columnar stack disposed on the via, the columnar stack comprising a bottom electrode, a magnetic tunneling junction layer disposed on the bottom electrode, and a top electrode disposed on the magnetic tunneling junction layer; and

and the spacer layer is arranged on the side wall of the columnar stack, wherein the top electrode protrudes out of the top surface of the spacer.

2. The MRAM cell of claim 1, wherein the top electrode comprises a ruthenium metal layer and a tantalum metal layer disposed on the ruthenium metal layer.

3. The MRAM cell of claim 2, wherein the top electrode has an upwardly-pointing conical shape above the top surface of the spacer layer.

4. The MRAM cell of claim 2, wherein the sidewall of the columnar stack tapers upward from the bottom electrode to the top electrode.

5. The MRAM cell of claim 1, wherein the top electrode comprises a ruthenium metal layer and a titanium nitride metal layer disposed on the ruthenium metal layer.

6. The MRAM cell of claim 5, wherein the top electrode comprises a convexly curved top surface profile.

7. The MRAM cell of claim 1, wherein the bottom electrode has a width greater than a width of the via.

8. The magnetoresistive random access memory cell of claim 1 wherein the via is a tungsten metal via.

9. The MRAM cell of claim 1, wherein the dielectric layer surrounds the via and has a tapered outer surface.

10. The MRAM cell of claim 9, wherein the spacer layer extends to the tapered outer surface.

11. The MRAM cell of claim 9, wherein the bottom electrode directly contacts the via and the dielectric layer surrounding the via.

12. The MRAM cell of claim 1, wherein the spacer layer is a silicon nitride spacer layer.

13. The magnetoresistive random access memory cell of claim 1 wherein the spacer layer has a thickness of between about 300 a and about 600 a.

14. The MRAM cell of claim 1, wherein the dielectric layer is a silicon oxide layer.

15. The magnetoresistive random access memory cell of claim 1 further comprising:

a first interlayer dielectric layer covering the dielectric layer, the columnar stack and the spacer layer;

a stop layer disposed on the first interlayer dielectric layer;

a second interlayer dielectric layer disposed on the stop layer; and

the dual damascene metal interconnect structure is embedded in the second inter-level dielectric layer, the stop layer and the first inter-level dielectric layer.

16. The magnetoresistive random access memory cell of claim 15 wherein the stop layer is a nitrogen doped silicon carbide layer.

17. The MRAM cell of claim 15, wherein the dual damascene metal interconnect structure comprises a via and a metal line integrally formed with the via.

18. The MRAM cell of claim 15, wherein the via is electrically connected to the top electrode.

Technical Field

The present invention relates to the field of semiconductor device technology, and more particularly, to a spin transfer torque magnetoresistive random access memory cell (STT-MRAM cell) structure.

Background

As known in the art, spin-transfer torque magnetoresistive random access memory (STT-MRAM) is a non-volatile memory that has recently received much attention in the memory technology field, which has several advantages over conventional magnetoresistive random access memories, including, for example, higher endurance, lower power consumption, and faster operating speed.

In a Magnetic Tunneling Junction (MTJ) having a thin insulating layer between two ferromagnetic layers (ferromagnetic layers), a tunneling resistance (tunnel resistance TMR) varies according to the relative magnetization directions of the two ferromagnetic layers. A magnetoresistive random access memory (mram) has a semiconductor element having a magnetic tunneling junction structure using a Tunneling Magnetoresistance (TMR) effect, and can be arranged in a matrix as memory cells.

Disclosure of Invention

The present invention provides an improved spin transfer torque magnetoresistive random access memory cell (STT-MRAMcell) structure.

In one aspect, the present invention provides a magnetoresistive random access memory cell, comprising: a substrate having a dielectric layer thereon; a via hole in the dielectric layer; a columnar stack disposed on the via, the columnar stack comprising a bottom electrode, a magnetic tunneling junction layer disposed on the bottom electrode, and a top electrode disposed on the magnetic tunneling junction layer; and a spacer layer disposed on the sidewall of the columnar stack, wherein the top electrode protrudes from a top surface of the spacer.

According to an embodiment of the present invention, the top electrode includes a ruthenium metal layer and a tantalum metal layer disposed on the ruthenium metal layer. The top electrode has a conical shape with an upward vertex above the top surface of the spacer layer.

According to another embodiment of the present invention, the top electrode comprises a ruthenium metal layer and a titanium nitride metal layer disposed on the ruthenium metal layer. The top electrode includes a convex curved top surface profile.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below. However, the following preferred embodiments and the accompanying drawings are only for reference and illustration purposes and are not intended to limit the present invention.

Drawings

FIG. 1 is a cross-sectional view of a MRAM cell according to an embodiment of the invention;

FIG. 2 is a cross-sectional view of a MRAM cell according to another embodiment of the invention;

FIG. 3 is a cross-sectional view of a MRAM cell according to yet another embodiment of the invention;

FIG. 4 is a cross-sectional view of a MRAM cell according to yet another embodiment of the invention.

Description of the main elements

1. 1a, 2a magnetoresistive random access memory cell

10 base

30 columnar stacks

30a side wall

40 columnar stack

40a side wall

50 dual damascene metal interconnect structure

100 dielectric layer Stack

110 dielectric layer

111 lower metal interconnection structure

112 stop layer

120 dielectric layer

120a outer surface

121 guide hole

123 concave structure

130 interlayer dielectric layer

140 stop layer

150 interlayer dielectric layer

310 bottom electrode

320 magnetic tunneling junction layer

330 top electrode

330a conical shape

331 Ru metal layer

332 tantalum metal layer

340 spacer

340a top surface

410 bottom electrode

420 magnetic tunneling junction layer

430 top electrode

430a convex curved top surface profile

431 ruthenium metal layer

432 titanium nitride metal layer

510 via plug

520 metal wire

Detailed Description

In the following, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the embodiments may be practiced. The following examples are described in sufficient detail to enable those skilled in the art to practice them.

Of course, other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the embodiments described herein. The following detailed description is, therefore, not to be taken in a limiting sense, and the embodiments included therein are defined by the appended claims.

FIG. 1 is a cross-sectional view of a MRAM cell according to an embodiment of the invention. As shown in fig. 1, the mram cell 1 includes a substrate 10, such as a silicon substrate, having a dielectric layer stack 100 thereon, including, but not limited to, a dielectric layer 110, a stop layer 112, a dielectric layer 120, an interlayer dielectric layer 130, a stop layer 140, and an interlayer dielectric layer 150. For example, the dielectric layer 110 may be an ultra low-k (ultra low-k) material layer, and the dielectric layer 120 may be a silicon oxide layer, but is not limited thereto. For example, the stop layer 112, 140 may be a nitrogen-doped silicon carbide (nitride-doped silicon carbide) layer or a silicon nitride layer, but is not limited thereto. The stop layer 140 is, for example, a nitrogen doped silicon carbide layer.

According to an embodiment of the present invention, a lower metal interconnect structure 111 may be formed in the dielectric layer 110. A via 121 is formed in the dielectric layer 120. According to an embodiment of the present invention, the lower metal interconnect structure 111 can be a copper wire, and the via can be a tungsten metal via, but is not limited thereto.

According to an embodiment of the present invention, a columnar stack 30 is disposed on the via 121. According to an embodiment of the present invention, the pillar stack 30 includes a bottom electrode 310, a Magnetic Tunneling Junction (MTJ) layer 320 disposed on the bottom electrode 310, and a top electrode 330 disposed on the MTJ layer 320. According to an embodiment of the present invention, the width of the bottom electrode 310 is greater than the width (or aperture) of the via 121. The bottom electrode 310 may include, for example, but not limited to, tantalum (Ta), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), and the like. According to an embodiment of the present invention, the sidewall 30a of the pillar stack 30 tapers upward from the bottom electrode 310 to the top electrode 330.

The multi-layer structure of the MTJ layer 320 is well known in the art and therefore not described in detail. For example, the MTJ layer 320 may include a fixed layer (fixed layer), a free layer (free layer), and a capping layer (capping layer), but is not limited thereto. The pinned layer may be made of an Antiferromagnetic (AFM) material, such as ferromanganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), etc., for pinning or limiting the magnetic moment direction of the adjacent layers. The free layer may be made of a ferromagnetic material, such as iron, cobalt, nickel, or alloys thereof, such as cobalt-iron-boron (CoFeB), but is not limited thereto.

According to an embodiment of the present invention, the top electrode 330 includes a ruthenium (Ru) metal layer 331 and a tantalum (Ta) metal layer 332 disposed on the Ru metal layer 331.

According to an embodiment of the present invention, the mram cell 1 further includes a spacer layer 340 disposed on the sidewall 30a of the pillar stack 30. According to an embodiment of the present invention, the spacer layer 340 may be a silicon nitride spacer layer. According to one embodiment of the present invention, spacer layer 340 has a thickness between about 300A and about 600A. According to an embodiment of the present invention, the top electrode 330 protrudes from the top surface 340a of the spacer 340.

According to one embodiment of the present invention, the dielectric layer 120 surrounds the via 121 and has a tapered outer surface 120 a. According to an embodiment of the present invention, the spacer layer 340 extends to the tapered outer surface 120a of the dielectric layer 120. According to an embodiment of the present invention, the bottom electrode 310 directly contacts the via 121 and the dielectric layer 120 surrounding the via 121. According to an embodiment of the present invention, the top electrode 330 has a conical shape 330a with its apex upward above the top surface 340a of the spacer layer 340.

According to an embodiment of the present invention, the interlayer dielectric layer 130 covers the dielectric layer 120, the pillar stack 30 and the spacer layer 340. The stop layer 140 is disposed on the interlayer dielectric layer 130. An interlayer dielectric 150 is disposed on the stop layer 140. A dual damascene (dual damascene) metal interconnect structure 50 is embedded in the inter-level dielectric layer 150, the stop layer 140 and the inter-level dielectric layer 130. The dual damascene metal interconnect structure 50 includes a via plug 510 and a metal line 520 integrally formed with the via plug 510. The dual damascene metal interconnect structure 50 may be formed by a copper dual damascene (cu dual damascene) process. The copper dual damascene process is well known in the art and therefore not described in detail.

According to an embodiment of the present invention, the via plug 510 is directly electrically connected to the top electrode 330. According to an embodiment of the present invention, the via plug 510 completely covers the portion of the conical shape 330a of the top electrode 330, and may cover a portion of the top surface 340a of the spacer layer 340.

Another feature in fig. 1 is that the spacer layer 340 is formed by etching and is formed only on the sidewalls 30a of the pillar stack 30 and extends slightly down to the upwardly tapered outer surface 120a of the dielectric layer 120. During the anisotropic dry etching of the spacer layer 340, a recess structure 123 is formed on the dielectric layer 120.

Referring to FIG. 2, a cross-sectional view of a MRAM cell according to another embodiment of the invention is shown, wherein the same regions, material layers, or devices are represented by the same symbols.

As shown in fig. 2, the structure of the mram cell 1a is substantially the same as that of the mram cell 1 in fig. 1, except that the spacer layer 340 of the mram cell 1a completely covers the surface of the dielectric layer 120 without being etched away, and thus the recess structure 123 on the dielectric layer 120 in fig. 1 is not formed. In addition, the via plug 510 needs to penetrate through the spacer layer 340 and electrically connect with the portion of the conical shape 330a of the top electrode 330.

Referring to FIG. 3, a cross-sectional view of a MRAM cell according to yet another embodiment of the invention is shown, wherein the same regions, material layers, or devices are represented by the same symbols.

As shown in fig. 3, the mram cell 2 is structurally substantially the same as the mram cell 1 of fig. 1, except that the top electrode of the pillar stack is different. The pillar stack 40 of the MRAM cell 2 includes a bottom electrode 410, a Magnetic Tunneling Junction (MTJ) layer 420 disposed on the bottom electrode 410, and a top electrode 430 disposed on the MTJ layer 420. According to an embodiment of the present invention, the top electrode 430 includes a ruthenium metal layer 431 and a titanium nitride (TiN) metal layer 432 disposed on the ruthenium metal layer 431.

According to an embodiment of the present invention, the mram cell 2 also includes a spacer layer 340 disposed on the sidewall 40a of the pillar stack 40. According to an embodiment of the present invention, the spacer layer 340 may be a silicon nitride spacer layer. According to one embodiment of the present invention, spacer layer 340 has a thickness between about 300A and about 600A. According to an embodiment of the present invention, the top electrode 430 protrudes from the top surface 340a of the spacer 340.

According to one embodiment of the present invention, the dielectric layer 120 surrounds the via 121 and has a tapered outer surface 120 a. According to an embodiment of the present invention, the spacer layer 340 extends to the tapered outer surface 120a of the dielectric layer 120. According to an embodiment of the present invention, the bottom electrode 410 directly contacts the via 121 and the dielectric layer 120 surrounding the via 121. According to an embodiment of the present invention, the top electrode 430 has a curved top surface profile 430a that is convex above the top surface 340a of the spacer layer 340.

Referring to FIG. 4, a cross-sectional view of a MRAM cell according to yet another embodiment of the invention is shown, wherein the same regions, material layers, or devices are represented by the same symbols.

As shown in fig. 4, the structure of the mram cell 2a is substantially the same as that of the mram cell 2 in fig. 3, except that the spacer layer 340 of the mram cell 2a completely covers the surface of the dielectric layer 120 without being etched away, and thus the recess structure 123 on the dielectric layer 120 in fig. 3 is not formed. In addition, the via plug 510 needs to penetrate through the spacer layer 340 and electrically connect with the portion of the convex curved top surface profile 430a of the top electrode 430.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.