阅读说明：本技术 磁性穿隧接面结构及其制造方法 (Magnetic tunnel junction structure and manufacturing method thereof ) 是由 杨毅 沈冬娜 桑达维格纳许 王郁仁 于 2019-08-27 设计创作，主要内容包括：描述蚀刻磁性穿隧接面结构的方法。磁性穿隧接面堆叠物沉积于底电极上,其中磁性穿隧接面堆叠物包括至少固定层、在固定层上的阻挡层及在阻挡层上的自由层。顶电极沉积于磁性穿隧接面堆叠物上,硬掩膜沉积于顶电极上,蚀刻顶电极和硬掩膜。之后,蚀刻未被硬掩膜覆盖的磁性穿隧接面堆叠物,此蚀刻停止于固定层上或固定层中。之后,封装层沉积于部分蚀刻的磁性穿隧接面堆叠物上方,且蚀刻封装层的水平表面,以在磁性穿隧接面堆叠物的侧壁上保留自对准硬掩膜。最后,蚀刻未被硬掩膜和自对准硬掩膜覆盖的磁性穿隧接面堆叠物,以完成磁性穿隧接面结构。(Methods of etching a magnetic tunnel junction structure are described. A magnetic tunnel junction stack is deposited on the bottom electrode, wherein the magnetic tunnel junction stack includes at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer. A top electrode is deposited over the MTJ stack, a hard mask is deposited over the top electrode, and the top electrode and the hard mask are etched. The mtj stack not covered by the hard mask is then etched, stopping on or in the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched mtj stack and a horizontal surface of the encapsulation layer is etched to leave a self-aligned hard mask on sidewalls of the mtj stack. Finally, the magnetic tunneling junction stack which is not covered by the hard mask and the self-aligned hard mask is etched to complete the magnetic tunneling junction structure.)

1. A method for fabricating a magnetic tunnel junction structure, comprising:

depositing a magnetic tunnel junction stack on a bottom electrode, wherein the magnetic tunnel junction stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer;

depositing a top electrode on the mtj stack;

depositing a hard mask over the top electrode;

performing a first etching process on the top electrode and the hard mask;

performing a second etching process on the MTJ stack not covered by the hard mask, the second etching process being stopped on or in the pinned layer;

depositing an encapsulation layer over the mtj stack and etching horizontal surfaces of the encapsulation layer to leave a self-aligned hard mask on sidewalls of the mtj stack; and

a third etch process is performed on the mtj stack not covered by the hard mask and the self-aligned hard mask.

2. The method of claim 1 wherein the hardmask and the top electrode are passed to include only CF₄Or CHF₃Or mixed with Ar and N₂A fluorocarbon-based plasma etch in which O is selectively added₂To reduce a pattern size of the hard mask, or by physical reactive ion etching or ion beam etching, followed by large angle ion beam etching trimming to reduce a pattern size of the hard mask.

3. The method of claim 1 wherein the second etch process and the third etch process comprise physical reactive ion etching or ion beam etching using an Ar or Xe gas plasma.

4. The method of claim 1, wherein no chemical damage is done to the sidewalls of the mtj stack, and wherein any redeposition of the first conductive metal after the second etch process and redeposition of the second conductive metal after the third etch process are separated from each other by the self-aligned hard mask.

5. The method according to claim 1, wherein a pattern size of the pinned layer is controlled by adjusting a thickness of the self-aligned hardmask.

6. The method according to claim 1, wherein a pattern size of the pinned layer is larger than a pattern size of the free layer.

7. A method for fabricating a magnetic tunnel junction structure, comprising:

depositing a mtj stack on a bottom electrode, wherein the mtj stack comprises at least a seed layer, a pinned layer on the seed layer, a barrier layer on the pinned layer, and a free layer on the barrier layer;

depositing a top electrode on the mtj stack;

depositing a hard mask over the top electrode;

performing a first etching process on the top electrode and the hard mask;

performing a second etching process on the mtj stack not covered by the hardmask, the second etching process being stopped on the pinned layer or in the pinned layer or the seed layer;

depositing an encapsulation layer over the mtj stack and etching horizontal surfaces of the encapsulation layer to leave a self-aligned hard mask on sidewalls of the mtj stack; and

a third etch process is performed on the mtj stack not covered by the hard mask and the self-aligned hard mask.

8. A magnetic tunnel junction structure comprising:

a plurality of magnetic tunnel junction stacks on a bottom electrode, the plurality of magnetic tunnel junction stacks being spaced apart from each other and not interacting, wherein each of the plurality of magnetic tunnel junction stacks comprises:

a seed layer on the bottom electrode;

a fixed layer on the seed layer;

a barrier layer on the fixed layer;

a free layer on the barrier layer;

a sidewall spacer on at least an upper portion of the fixed layer; and

a top electrode on the free layer.

9. The mtj structure of claim 8 wherein a pattern size of the pinned layer is controlled by a thickness of the sidewall spacer.

10. The mtj structure of claim 8 wherein a pattern size of the pinned layer or the pinned layer and the seed layer is larger than a pattern size of the free layer.

Technical Field

Embodiments of the present disclosure relate generally to the field of Magnetic Tunneling Junctions (MTJs), and more particularly, to methods for etching MTJ.

Background

The fabrication of a Magnetic Random Access Memory (MRAM) device is generally associated with a series of process steps in which a number of metal and dielectric layers are first deposited, followed by patterning to form a magnetoresistive stack and electrodes for electrical connection. To define the Magnetic Tunneling Junction (MTJ) in each MRAM device, a sophisticated patterning process is typically involved: including lithography and Reactive Ion Etching (RIE), Ion Beam Etching (IBE), or combinations thereof. During reactive ion etching, the high energy ions vertically remove material from the regions not shielded by the photo-resist, separating the mtj cells from each other.

However, high energy ions can react laterally with unremoved material (oxygen, moisture, and other chemicals), causing sidewall damage and reducing device performance. To address this problem, purely physical etching techniques, such as argon reactive ion etching (ar rie) or Ion Beam Etching (IBE), have been applied to etch the mtj stack. However, due to the non-volatile nature, physically etching the conductive material and the bottom electrode in the magnetic tunnel junction can form a continuous conductive path across the tunnel barrier, causing the device to short. Therefore, if one wants to exploit the full potential of physical etching to pattern future mram products smaller than 60nm (sub60nm), a new method for overcoming this dilemma is needed.

Many references teach multi-step etching methods to form the magnetic tunnel junction, including U.S. Pat. Nos. 9,793,126(Dhindsa et al), 9,722,174(Nagel et al), and 8,883,520(Satoh et al). All of these references differ from the disclosed embodiments.

Disclosure of Invention

It is an object of the disclosed embodiments to provide an improved method of forming a magnetic tunnel junction structure.

It is another object of the disclosed embodiments to provide a method for forming a mtj element by using a physical bottom etch (undercut) to avoid chemical damage and physical shorts.

It is another object of the disclosed embodiments to provide a method for forming a mtj element by using a physical bottom etch (undercut) to avoid chemical damage and physical shorts, wherein the separated and non-interacting mtj cells are fabricated by using a packaging material as a self-aligned process.

According to some embodiments of the present disclosure, a method of etching a Magnetic Tunnel Junction (MTJ) structure is achieved, the method comprising depositing a magnetic tunnel junction stack on a bottom electrode, wherein the magnetic tunnel junction stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer; depositing a top electrode on the mtj stack; depositing a hard mask on the top electrode; carrying out a first etching process on the top electrode and the hard mask; performing a second etching process on the MTJ stack uncovered by the hard mask, the second etching process being stopped on or in the pinned layer; depositing an encapsulation layer over the mtj stack and etching a horizontal surface of the encapsulation layer to leave a self-aligned hard mask on sidewalls of the mtj stack; and performing a third etching process on the MTJ stack not covered by the hard mask and the self-aligned hard mask.

In some other embodiments, a method of fabricating a mtj structure is provided, the method including depositing a mtj stack on a bottom electrode, wherein the mtj stack includes at least a seed layer, a pinned layer on the seed layer, a barrier layer on the pinned layer, and a free layer on the barrier layer; depositing a top electrode on the mtj stack; depositing a hard mask on the top electrode; carrying out a first etching process on the top electrode and the hard mask; performing a second etching process on the MTJ stack uncovered by the hard mask, the second etching process being stopped on the pinned layer or in the pinned layer or the seed layer; depositing an encapsulation layer over the mtj stack and etching a horizontal surface of the encapsulation layer to leave a self-aligned hard mask on sidewalls of the mtj stack; and performing a third etching process on the MTJ stack not covered by the hard mask and the self-aligned hard mask.

In some other embodiments, a magnetic tunnel junction structure is provided, the magnetic tunnel junction structure comprising a plurality of magnetic tunnel junction stacks on a bottom electrode, the magnetic tunnel junction stacks being spaced apart from each other and not interacting, wherein each magnetic tunnel junction stack comprises a seed layer on the bottom electrode; a fixed layer on the seed layer; the barrier layer is positioned on the fixed layer, and the free layer is positioned on the barrier layer; a sidewall spacer on at least an upper portion of the fixed layer; and a top electrode on the free layer.

Drawings

The embodiments of the present disclosure can be understood more readily by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components (features) in the drawings are not necessarily drawn to scale. In fact, the dimensions of the various elements may be arbitrarily expanded or reduced for clarity of illustration.

Fig. 1-6 show cross-sectional views representing steps of a preferred embodiment of the present disclosure.

Wherein the reference numerals are as follows:

10 bottom electrode

12 seed layer

14 anchoring layer

16 tunneling barrier layer

18 free layer

20 metal hard mask

22 dielectric hardmask materials

24 photoresist column pattern

26 encapsulating material

28 encapsulation spacer

d1, d2, d3, d7 size

d4, d5, d6, d8 thickness

Detailed Description

It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements thereof are described below to simplify the description of the disclosure. These are, of course, merely examples and are not intended to limit the disclosure. For example, the following disclosure describes forming a first feature over or on a second feature, including embodiments in which the first and second features are formed in direct contact, and embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, various examples of the disclosure may use repeated reference characters and/or wording. These repeated symbols or words are provided for simplicity and clarity and are not intended to limit the relationship between the various embodiments and/or the appearance structures described.

Furthermore, spatially relative terms, such as "under," "below," "lower," "above," "upper," and the like, may be used herein for ease of describing the relationship of one element or component to another element(s) or component(s) in the figures. Spatially relative terms encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In a typical process, the entire mtj stack is patterned by a single step etching process, such as chemical or physical reactive ion etching or ion beam etching. Thus, chemical damage or physical shorts are formed on the sidewalls of the magnetic tunnel junctions. In the process of the disclosed embodiment, the mtj stack is partially etched first to minimize physical redeposition. Next, the remaining mtj is etched using the encapsulant as a self-aligned hard mask. This new process avoids both chemical damage and physical shorts. Furthermore, the second step of etching is a self-aligned process, meaning that the etching step does not require a complicated photolithography step, wherein overlay alignment is difficult to control, especially for MRAM devices smaller than 60 nm.

In the process of the disclosed embodiments, the mtj stack is partially etched first by physical etching, such as reactive ion etching or ion beam etching using different gas plasmas (e.g., Ar and Xe), so that no chemical damage is caused on the sidewalls and only conduction redeposition occurs. The amount of redeposition depends on the amount of etching. The redeposition on the sidewalls of the tunnel barrier layer can be significantly reduced or completely removed by deliberate etching (e.g., etching the free layer, tunnel barrier layer and/or a portion of the pinned layer or seed layer. deposition of encapsulation material protects the etched magnetic tunnel junction. reactive ion etching or ion beam etching partially cleans a portion of the encapsulation material on the top and bottom of the mtj pattern.

Referring to fig. 1-6, the novel method of the disclosed embodiment will be described in detail. Specifically, referring to fig. 1, a bottom electrode 10 is formed on a substrate (not shown). At this point, layers are deposited on the bottom electrode 10 to form a magnetic tunneling junction. For example, seed layer 12, fixed layer 14, tunneling barrier layer 16, and free layer 18 are deposited.

There may be one or more pinned, barrier and/or free layers. A metal hard mask 20 (such as Ta, TaN, Ti, TiN, W, Cu, Mg, Ru, Cr, Co, Fe, Ni, or alloys of the foregoing), sometimes referred to as a top electrode, is deposited on top of the MTJ stack to a thickness of 10-100nm, and preferably a thickness ≧ 50 nm. Finally, a dielectric hard mask material 22 (e.g., SiO)₂SiN, SiON, SiC or SiCN) is deposited on the metal hard mask 20 to a thickness of greater than or equal to 20 nm. Then, the photoresist is patterned by 248nm lithography to form photoresist columns with a dimension d1 of 70-80nm and a height of 200nm or morePattern 24.

Next, referring to FIG. 2, a fluorocarbon-based plasma (e.g., CF only) is applied₄Or CHF₃Or mixed with Ar and N₂) The dielectric hard mask material 22 and the metal hard mask 20 are etched. O may be added₂The pillar size d2 is reduced from 50-60nm to 30-40 nm. The dielectric hardmask material 22 and the metal hardmask 20 may also be etched by physical reactive ion etching or ion beam etching (pure Ar), followed by trimming by high angle (70-90 deg. relative to the pillar normal) ion beam etching to form pillars having a dimension d2 of 30-40 nm.

Referring to fig. 3, the mtj stack is partially etched to a similar pattern size by physical reactive ion etching (pure Ar or Xe) or ion beam etching and stops on the pinned or seed layer. Due to the nature of physical etching, there is no chemical damage. The height of the partially etched mtj stack is between about 5nm and 30 nm.

Next, referring to FIG. 4, the packaging material 26 is made of a dielectric material having a thickness d4 of 5-30nm (and a thickness d5 on the sidewalls of the MTJ pattern), such as SiN, SiC, SiCN, carbon or TaC, or a metal oxide (e.g., Al)₂O₃Or MgO) deposited in-situ or ex-situ on the partially etched mtj pattern by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD). The portions of the encapsulation material 26 on the top and bottom of the mtj pattern are etched away by reactive ion etching or ion beam etching, leaving the encapsulation spacers 28 on the sidewalls, as shown in fig. 5, and the encapsulation spacers 28 have a thickness d6 of 10-30 nm. Depending on the spacer material, different plasmas may be used in this etching step. For example, fluorocarbon based plasma (e.g., CF)₄Or CHF₃) Can be used for SiN, SiC and SiCN, O₂Can be used for carbon, fluorocarbon (e.g. CF)₄Or CHF₃) Or halogen (e.g. Cl)₂) Or combinations of the foregoing may be used for TaC, e.g., with only Cl₂Halogen or mixed Ar of (2) can be used for Al₂O₃And MgO.

Finally, using the package spacer 28 left on the sidewalls of the mtj pattern as a self-aligned hard mask, the remaining mtj stack (e.g., the pinned layer 14 and/or the seed layer 12) may be etched by reactive ion etching or ion beam etching, as shown in fig. 6. When reactive ion etching is used, since the fixed layer and the seed layer manufactured by this method are larger than the free layer, chemical damage to the fixed layer and the seed layer does not affect the central portion of the fixed layer and the seed layer aligned with the free layer. When physical reactive ion etching or ion beam etching is used, metal redeposition of the pinned layer and the seed layer does not contact the tunneling barrier layer due to protection of the encapsulation material. It is noted that the pinned layer and the seed layer are etched in a self-aligned step, meaning that there is no overlay control problem typically associated with the fabrication of mram devices smaller than 60 nm.

More importantly, the dimensions of the pinned layer and the seed layer are largely dependent on the thickness of the encapsulation spacers, which are used as a hard mask, which is dependent on their initial deposition thickness and subsequent etching conditions. By adjusting these parameters, the dimensions of the pinned layer and the seed layer can be precisely controlled according to the device design. For example, a thick spacer having a thickness d8 of 10-20nm may be formed on the sidewalls of the free layer such that the dimension d7 of the subsequently defined tunneling barrier and pinned layers is 50-60nm, which is 40-50nm greater than the dimension d3 of the free layer. This size is particularly critical for small cell size devices as it allows for enhanced retention, increased energy blocking and reduced switching current.

In summary, the processes of the disclosed embodiments use physical underetching to avoid chemical damage and physical shorts. Furthermore, the use of the encapsulation material as a self-aligned process to form separate and non-interacting MTJ cells means that there are no overlay control problems typically associated with the fabrication of MRAM devices smaller than 60 nm. Therefore, this process may replace the widely used chemical reactive ion etching, which inevitably brings chemical damage on the sidewalls of the mtj. As the problems associated with the smaller size of the MRAM chip and the chemically damaged sidewalls and redeposition of the MTJ stack and bottom electrode become more severe, this process will be used for MRAM chips having a size less than 60 nm.

Some embodiments relate to a method of fabricating a magnetic tunnel junction structure, the method comprising depositing a magnetic tunnel junction stack on a bottom electrode, wherein the magnetic tunnel junction stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer; depositing a top electrode on the mtj stack; depositing a hard mask on the top electrode; carrying out a first etching process on the top electrode and the hard mask; performing a second etching process on the MTJ stack uncovered by the hard mask, the second etching process being stopped on or in the pinned layer; depositing an encapsulation layer over the mtj stack and etching a horizontal surface of the encapsulation layer to leave a self-aligned hard mask on sidewalls of the mtj stack; and performing a third etching process on the MTJ stack not covered by the hard mask and the self-aligned hard mask.

In some other embodiments, wherein the top electrode comprises Ta, TaN, Ti, TiN, W, Cu, Mg, Ru, Cr, Co, Fe, Ni, or alloys thereof, and the hard mask comprises SiO₂SiN, SiON, SiC or SiCN.

In some other embodiments, wherein the hardmask and the top electrode are passed to contain only CF₄Or CHF₃Or mixed with Ar and N₂In which O is selectively added₂To reduce the pattern size of the hard mask, or by physical reactive ion etching or ion beam etching, followed by a large angle ion beam etch trim to reduce the pattern size of the hard mask.

In some other embodiments, wherein the second etch process and the third etch process comprise physical reactive ion etching or ion beam etching using an Ar or Xe gas plasma.

In some other embodiments, wherein no chemical damage is caused to the sidewalls of the mtj stack, and wherein any redeposition of the first conductive metal after the second etch process and redeposition of the second conductive metal after the third etch process are separated from each other by a self-aligned hard mask.

In some other embodiments, the step in which the encapsulation layer is deposited comprises depositing SiN, SiC, SiCN, carbon or TaC or including Al in-situ or ex-situ by chemical vapor deposition, physical vapor deposition or atomic layer deposition₂O₃Or a dielectric layer of a metal oxide layer of MgO to a thickness of 5-30 nm.

In some other embodiments, the pattern size of the fixed layer is controlled by adjusting the thickness of the self-aligned hard mask.

In some other embodiments, the pattern size of the pinned layer is larger than the pattern size of the free layer.

Some embodiments relate to a method of fabricating a mtj structure, the method including depositing a mtj stack on a bottom electrode, wherein the mtj stack includes at least a seed layer, a pinned layer on the seed layer, a barrier layer on the pinned layer, and a free layer on the barrier layer; depositing a top electrode on the mtj stack; depositing a hard mask on the top electrode; carrying out a first etching process on the top electrode and the hard mask; performing a second etching process on the MTJ stack uncovered by the hard mask, the second etching process being stopped on the pinned layer or in the pinned layer or the seed layer; depositing an encapsulation layer over the mtj stack and etching a horizontal surface of the encapsulation layer to leave a self-aligned hard mask on sidewalls of the mtj stack; and performing a third etching process on the MTJ stack not covered by the hard mask and the self-aligned hard mask.

In some other embodiments, the pattern size of the pinned layer is larger than the pattern size of the free layer.

In some other embodiments, wherein the top electrode comprises Ta, TaN, Ti, TiN, W, Cu, Mg, Ru, Cr, Co, Fe, Ni, or alloys thereof, and the hard mask comprises SiO₂SiN, SiON, SiC or SiCN.

In some other embodiments, wherein the hardmask and the top electrode are passed to contain only CF₄Or CHF₃Or mixed with Ar and N₂In which O is selectively added₂To reduce the pattern size of the hard mask, or by physical reactive ion etching or ion beam etching, followed by a large angle ion beam etch trim to reduce the pattern size of the hard mask.

In some other embodiments, wherein the second etch process and the third etch process comprise physical reactive ion etching or ion beam etching using an Ar or Xe gas plasma.

In some other embodiments, wherein no chemical damage is caused to the sidewalls of the mtj stack, and wherein any redeposition of the first conductive metal after the second etch process and redeposition of the second conductive metal after the third etch process are separated from each other by a self-aligned hard mask.

In some other embodiments, the step in which the encapsulation layer is deposited comprises depositing SiN, SiC, SiCN, carbon or TaC or including Al in-situ or ex-situ by chemical vapor deposition, physical vapor deposition or atomic layer deposition₂O₃Or a dielectric layer of a metal oxide layer of MgO to a thickness of 5-30 nm.

In some other embodiments, the pattern size of the fixed layer is controlled by adjusting the thickness of the self-aligned hard mask.

Some embodiments relate to a mtj structure comprising a plurality of mtj stacks on a bottom electrode, the mtj stacks being spaced apart and non-interacting, wherein each mtj stack comprises a seed layer on the bottom electrode; a fixed layer on the seed layer; the barrier layer is positioned on the fixed layer, and the free layer is positioned on the barrier layer; a sidewall spacer on at least an upper portion of the fixed layer; and a top electrode on the free layer.

In some other embodiments, the pattern size of the pinned layer is controlled by the thickness of the sidewall spacer.

In some other embodiments, the sidewall spacers comprise a dielectric layer comprising SiN, SiC, SiCN, carbon, or TaC or comprisingAl₂O₃Or a metal oxide layer of MgO.

In some other embodiments, the pattern size of the fixed layer or the fixed layer and the seed layer is larger than the pattern size of the free layer.

The foregoing outlines features of many embodiments so that those skilled in the art may better understand the aspects of the present disclosure. It should be appreciated by those skilled in the art that other processes and structures may be devised or modified readily based on the embodiments of the present disclosure, and that other processes and structures may be devised or modified in order to achieve the same purposes and/or to achieve the same advantages as those of the embodiments described herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. Various changes, substitutions, or alterations may be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure.