阅读说明：本技术 数据处理系统及其操作方法 (Data processing system and method of operation thereof ) 是由 边谕俊 于 2019-08-27 设计创作，主要内容包括：数据处理系统及其操作方法。一种数据处理系统包括：主机,其检查电池状态信息并基于电池状态信息确定电池等级；以及存储器系统,其存储从所述主机提供的指示电池等级的信息,基于电池等级确定执行后台操作的方法,以及基于所确定的方法执行后台操作。(A data processing system and method of operation thereof. A data processing system comprising: a host which checks the battery state information and determines a battery level based on the battery state information; and a memory system storing information indicating a battery level provided from the host, determining a method of performing a background operation based on the battery level, and performing the background operation based on the determined method.)

1. A data processing system, the data processing system comprising:

a host that checks battery status information and determines a battery level based on the battery status information; and

a memory system to store information provided from the host indicating the battery level, to determine a method to perform a background operation based on the battery level, and to perform the background operation based on the determined method.

2. The data processing system of claim 1, wherein the host comprises:

a battery that supplies electric power; and

a battery manager that checks the battery status information and determines the battery grade based on the battery status information.

3. The data processing system of claim 1, wherein the host provides the information indicative of the battery level to the memory system when performing a boot operation.

4. The data processing system of claim 1, wherein the host provides the information indicative of the battery level to the memory system when the battery level changes.

5. The data processing system of claim 1, wherein the memory system comprises:

a memory device; and

a controller to store the information indicative of the battery level, to determine a method for performing the background operation based on the information indicative of the battery level, and to control the memory device to perform the background operation according to the determined method.

6. The data processing system of claim 5, wherein the controller comprises:

a battery information manager that stores the information indicating the battery grade; and

a processor to determine the method based on the information indicative of the battery level and to control the memory device to perform the background operation based on the determined method.

7. The data processing system of claim 6, wherein the processor sets an execution frequency corresponding to the battery level to a number of executions of the background operation.

8. The data processing system of claim 6, wherein the processor sets an execution time corresponding to the battery level to the execution time of the background operation.

9. The data processing system of claim 6, wherein the battery information manager updates the stored information indicative of the battery level when provided with an updated battery level.

10. The data processing system of claim 1, wherein the background operation comprises any one of a garbage collection operation, a read reclamation operation, and a wear leveling operation.

11. The data processing system of claim 1, wherein the battery status information includes information indicative of an available capacity of a battery.

12. A method for operating a data processing system including a host and a memory system, the method comprising the steps of:

checking battery status information;

determining a battery level based on the battery status information;

determining a method of performing a background operation based on the battery level; and

performing the background operation based on the determined method.

13. The method of claim 12, wherein the step of determining a method to perform a background operation based on the battery level comprises the steps of:

and setting the execution frequency corresponding to the battery grade as the execution times of the background operation.

14. The method of claim 12, wherein the step of determining a method to perform a background operation based on the battery level comprises the steps of:

and setting the execution time corresponding to the battery grade as the execution time of the background operation.

15. The method of claim 12, further comprising the steps of:

providing information indicating the battery level from the host to the memory system when performing a boot operation.

16. The method of claim 12, further comprising the steps of:

providing information from the host to the memory system indicating the battery level when the battery level changes.

17. The method of claim 12, further comprising the steps of:

a battery information manager to store information indicative of the battery level in the memory system.

18. A data processing system, the data processing system comprising:

a host including a battery, the host maintaining battery status information including a plurality of levels, each level of the plurality of levels indicating a capacity of the battery; and

a memory system, the memory system including a memory controller, the memory system:

receiving the battery status information including a current capacity level of the battery from the host, the plurality of levels being respectively associated with a plurality of methods of performing background operations,

identifying a method associated with a current level of the battery to perform the background operation, and

performing the background operation in association with the current level of the battery.

19. The data processing system of claim 18, wherein the memory system reduces the execution time of the background operation when the current level of the battery decreases.

20. The data processing system of claim 18, wherein the memory system reduces the frequency of execution of the background operation when the current level of the battery decreases.

Technical Field

Various embodiments of the present invention generally relate to data processing systems. In particular, embodiments relate to a data processing system capable of efficiently processing data and an operating method thereof.

Background

Computer environment paradigms have turned to ubiquitous computing, which enables computing systems to be used anytime and anywhere. As a result, the demand for portable electronic devices such as mobile phones, digital cameras, and laptop computers has rapidly increased. Those electronic devices typically include memory systems that use memory devices as data storage devices. The data storage device may be used as a primary memory unit or a secondary memory unit of the portable electronic device.

The data storage device used as a memory device provides advantages such as excellent stability and durability, high information access speed, and low power consumption due to the absence of a mechanical driving part. In addition, the data storage device can have a higher data access rate and lower power consumption than the hard disk device. Non-limiting examples of data storage devices having these advantages include Universal Serial Bus (USB) memory devices, memory cards of diverse interfaces, Solid State Drives (SSDs), and the like.

Disclosure of Invention

Various embodiments of the present invention relate to a memory system capable of efficiently performing background operations.

According to an embodiment of the present invention, a data processing system may include: a host which checks the battery state information and determines a battery level based on the battery state information; and a memory system storing information indicating a battery level provided from the host, determining a method of performing a background operation based on the battery level, and performing the background operation based on the determined method.

According to an embodiment of the present invention, a method of operation of a data processing system may include: checking battery status information; determining a battery level based on the battery status information; determining a method of performing a background operation based on the battery level; and performing a background operation based on the determined method.

According to an embodiment of the present invention, a data processing system may include: a host including a battery, the host maintaining battery status information including a plurality of levels, each level of the plurality of levels indicating a capacity of the battery; and a memory system including a memory controller, the memory system receiving battery status information including a current capacity level of the battery from the host, the plurality of levels being respectively associated with a plurality of methods of performing background operations, identifying a method of performing a background operation associated with the current level of the battery, and performing a background operation associated with the current level of the battery.

Drawings

The description herein makes reference to the accompanying drawings wherein like reference numerals refer to like parts throughout the several views, and wherein:

FIG. 1 is a block diagram illustrating a data processing system including a memory system according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram illustrating an exemplary configuration of a memory device of the memory system shown in fig. 1;

fig. 3 is a circuit diagram illustrating an exemplary configuration of a memory cell array of a memory block in the memory device shown in fig. 2;

FIG. 4 is a schematic diagram illustrating an exemplary three-dimensional (3D) structure of the memory device shown in FIG. 2;

5A-5F are diagrams illustrating the operation of a data processing system according to embodiments of the present disclosure;

6A-6F are diagrams illustrating the operation of a data processing system according to embodiments of the present disclosure;

FIG. 7 is a flowchart illustrating operation of a data processing system according to an embodiment of the present disclosure; and

fig. 8 to 16 are diagrams schematically illustrating application examples of data processing systems according to various embodiments of the present invention.

Detailed Description

Various embodiments of the present disclosure are described in more detail below with reference to the accompanying drawings. This invention may, however, be embodied in different forms and may be modified or varied from any of the disclosed embodiments. Accordingly, the present invention is not limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete and will fully convey the disclosure to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and examples of the disclosure. Note that references to "an embodiment," "another embodiment," etc., do not necessarily mean only one embodiment, and different references to any such phrases do not necessarily mean the same embodiment.

It will be understood that, although the terms first, second, third, etc. may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element having the same or similar designation. Thus, a first element in one instance can be termed a second element or a third element in another instance without departing from the spirit and scope of the present invention.

The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. The drawings are illustrative and not restrictive.

It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly on, connected or coupled to the other element or one or more intervening elements may be present. In addition, it will also be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Unless the context indicates otherwise, communication between two elements, whether directly indirectly connected/coupled or indirectly connected/coupled, may be wired or wireless.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms and vice versa, unless the context clearly indicates otherwise.

It will be further understood that the terms "comprises," "comprising," "includes" and "including," when used in this specification, specify the presence of stated elements and do not preclude the presence or addition of one or more other elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Unless defined otherwise, all terms used herein including technical and scientific terms have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs in light of this disclosure. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be practiced without some or all of these specific details. In other instances, well known process structures and/or processes have not been described in detail in order to not unnecessarily obscure the present invention.

It is also noted that, in some instances, features or elements described in connection with one embodiment may be used alone or in combination with other features or elements of another embodiment, unless specifically stated otherwise, as will be apparent to those skilled in the relevant art.

FIG. 1 is a block diagram illustrating a data processing system 100 according to an embodiment of the present invention.

Referring to FIG. 1, data processing system 100 may include a host 102 operably coupled to a memory system 110.

The host 102 may, for example, include a portable electronic device such as a mobile phone, MP3 player, and laptop computer, or an electronic device such as a desktop computer, game console, Television (TV), projector, and the like.

The host 102 may include a battery 104 and a battery manager 106 for managing the battery 104.

Battery 104 may provide power to data processing system 100. The battery 104 may have limited power.

Although the battery 104 is illustrated in fig. 1 as a constituent element included in the host 102, this is merely one embodiment; the present invention is not limited thereto. According to another embodiment of the invention, host 102 and battery 104 of data processing system 100 may be separate components. In the context of the following description, the host 102 includes a battery 104.

Battery manager 106 may manage battery 104. Specifically, battery manager 106 may check battery status information (e.g., the current available capacity of the battery).

Further, battery manager 106 may classify battery capacity into a plurality of battery levels based on the detected battery status information. For example, when the available capacity of the battery is less than 100% and more than 80%, the battery manager 106 may classify the battery status information into a fifth level. When the available capacity of the battery is less than 80% and more than 60%, the battery manager 106 may classify the battery status information into a fourth level. When the available capacity of the battery is less than 60% and more than 40%, the battery manager 106 may classify the battery status information into a third level. When the available capacity of the battery is less than 40% and more than 20%, the battery manager 106 may classify the battery status information into the second class. When the available capacity of the battery is less than 20% and more than 10%, the battery manager 106 may classify the battery status information into a first class. When the available capacity of the battery is less than 10% and more than 0%, the battery manager 106 may classify the battery status information into the 0 th level. However, this is only one embodiment of a battery status information classification scheme; the present invention is not limited thereto. Other suitable classification schemes may be used consistent with the teachings herein.

Battery manager 106 may determine a corresponding battery level based on the detected battery status information.

The host 102 may provide information indicative of the determined battery level to the memory system 110. In particular, host 102 may provide information indicative of the determined battery level to memory system 110 when data processing system 100 is booted. When the battery level changes, the host 102 may provide the changed battery level to the memory system 110. For example, host 102 may provide a changed battery level to memory system 110 each time the battery level rises or falls.

The memory system 110 may operate or perform particular functions or operations in response to requests from the host 102, and in particular, may store data to be accessed by the host 102. The memory system 110 may be used as a primary memory system or a secondary memory system for the host 102. Memory system 110 may be implemented with any of various types of storage devices that may be electrically coupled to host 102 according to the protocol of the host interface. Non-limiting examples of suitable storage devices include Solid State Drives (SSDs), multimedia cards (MMCs), embedded MMCs (emmcs), reduced-size MMCs (RS-MMCs) and micro-MMCs, Secure Digital (SD) cards, mini-SD cards and micro-SD cards, Universal Serial Bus (USB) storage devices, universal flash memory (UFS) devices, Compact Flash (CF) cards, Smart Media (SM) cards, memory sticks, and the like.

Storage devices for memory system 110 may be implemented with any of a variety of memory types including, for example, volatile memory devices such as Dynamic Random Access Memory (DRAM) and static RAM (sram), and/or non-volatile memory devices such as Read Only Memory (ROM), mask ROM (mrom), programmable ROM (prom), erasable programmable ROM (eprom), electrically erasable programmable ROM (eeprom), ferroelectric RAM (fram), phase change RAM (pram), magnetoresistive RAM (mram), resistive RAM (RRAM or ReRAM), and flash memory.

Memory system 110 may include a controller 130 and a memory device 150. Memory device 150 may store data to be accessed by host 102, and controller 130 may control the storage of data in memory device 150.

The controller 130 and the memory device 150 may be integrated into a single semiconductor device, which may be included in any of various types of memory systems as illustrated above.

The memory system 110 may be configured as part of, for example: a computer, an ultra mobile pc (umpc), a workstation, a netbook, a Personal Digital Assistant (PDA), a portable computer, a network tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an electronic book, a Portable Multimedia Player (PMP), a portable game machine, a navigation system, a black box, a digital camera, a Digital Multimedia Broadcasting (DMB) player, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configuring a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, one of various electronic devices configuring a remote information processing network, a computer, A Radio Frequency Identification (RFID) device, or configure one of various components of a computing system.

Memory device 150 may be a non-volatile memory device and may retain data stored therein even when power is not provided. The memory device 150 may store data provided from the host 102 through a write operation and provide data stored therein to the host 102 through a read operation. Memory device 150 may include a plurality of memory blocks. Each memory block may include a plurality of pages. Each of the plurality of pages may include a plurality of Word Lines (WLs) electrically coupled with a plurality of memory cells.

The controller 130 may control overall operations of the memory device 150, such as a read operation, a write operation, a program operation, and an erase operation. For example, the controller 130 may control the memory device 150 in response to a request from the host 102. The controller 130 may provide data read from the memory device 150 to the host 102 and/or may store data provided by the host 102 into the memory device 150.

The controller 130 may include a host interface (I/F)132, a processor 134, a memory interface (I/F)142, a memory 144, and a battery information manager 146, all operatively coupled via an internal bus.

The host interface 132 may process commands and data provided from the host 102, and may communicate with the host 102 through at least one of various interface protocols, such as Universal Serial Bus (USB), multimedia card (MMC), peripheral component interconnect express (PCI-e or PCIe), Small Computer System Interface (SCSI), serial attached SCSI (sas), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

Memory interface 142 may serve as an interface for handling commands and data transferred between controller 130 and memory devices 150 to allow controller 130 to control memory devices 150 in response to requests delivered from host 102. When memory device 150 is a flash memory, particularly a NAND flash memory, memory interface 142 may generate control signals for memory device 150 and may process data input to or output from memory device 150 under the control of processor 134.

The memory 144 may serve as a working memory of the memory system 110 and the controller 130, and may store temporary data or transaction data for operating or driving the memory system 110 and the controller 130. The controller 130 may control the memory device 150 in response to a request from the host 102. The controller 130 may deliver data read from the memory device 150 to the host 102, and may store data input through the host 102 within the memory device 150. Memory 144 may be used to store data needed by controller 130 and memory device 150 to perform these operations.

The memory 144 may be implemented with volatile memory. The memory 144 may be implemented with Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). Although fig. 1 illustrates the memory 144 disposed within the controller 130, the disclosure is not so limited. That is, the memory 144 may be located inside or outside the controller 130. For example, the memory 144 may be implemented by an external volatile memory having a memory interface that transfers data and/or signals transferred between the memory 144 and the controller 130.

The battery information manager 146 may store the battery level provided from the host 102 under the control of the processor 134. When a new battery level or grade is provided from the host 102, the battery information manager 146 may update the battery level under the control of the processor 134. Although the battery information manager 146 is shown in fig. 1 as a separate component from the memory 144, the battery information manager 146 may be included in the memory 144.

Processor 134 may be implemented with a microprocessor or Central Processing Unit (CPU). The memory system 110 may include one or more processors 134.

A management unit (not shown) may be included in processor 134. The management unit may perform bad block management of the memory device 150. The management unit may find a bad memory block that does not satisfy a further use condition in the memory device 150, and perform bad block management on the bad memory block. When the memory device 150 is a flash memory (e.g., a NAND flash memory), a program failure may occur during a write operation (i.e., a program operation) due to the characteristics of the NAND logic function. During bad block management, data of a memory block that failed programming or a bad memory block may be programmed into a new memory block. The bad block may seriously deteriorate the utilization efficiency of the memory device 150 having the 3D stacked structure and the reliability of the memory system 100, and thus reliable bad block management is required.

Processor 134 may perform background operations of memory device 150. Background operations may include garbage collection operations, wear leveling operations, mapping flush operations, and bad block management operations.

Background operations may be performed by the memory system 110 even in the absence of a request by the host 102. Background operations may excessively consume the limited power of the battery 104 if the background operations are frequently performed in the memory system 110.

The processor 134 may determine a method of performing a background operation based on the battery level stored in the battery information manager 146.

For example, the processor 134 may determine the number of times to perform the background operation based on the frequency of performance of the background operation corresponding to each battery level.

For another example, the processor 134 may determine an execution time for the background operation corresponding to each battery level.

However, the present invention is not limited to the above examples.

Processor 134 may perform the background operation according to the determined method of performing the background operation. Processor 134 may perform background operations in the idle state.

The controller 130 may also include an Error Correction Code (ECC) component and a Power Management Unit (PMU).

The ECC component may detect and correct errors in data read from the memory device 150 during a read operation. When the number of error bits is greater than or equal to the threshold number of correctable error bits, the ECC component may not correct the error bits, but may output an error correction failure signal indicating that the error bits failed to be corrected.

The ECC component may perform error correction operations based on coded modulation such as Low Density Parity Check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, Recursive Systematic Codes (RSC), Trellis Coded Modulation (TCM), Block Coded Modulation (BCM), and the like. An ECC component may include a circuit, module, system, or apparatus to perform all or some of the error correction operations based on at least one of the codes described above.

The PMU may provide and manage power for the controller 130.

Fig. 2 is a schematic diagram illustrating the memory device 150 of fig. 1.

Referring to FIG. 2, memory device 150 may include a plurality of memory blocks, e.g., block 0210, block 1220, block 2230 through block N-1240. Each of these blocks may include a number of pages that may vary depending on the circuit design, e.g., 2^MAnd (4) each page. Memory device 150 may include multiple memory blocks that are Single Level Cell (SLC) memory blocks and multi-level cell (MLC) memory blocks depending on the number of bits that may be stored or expressed in each memory cell. The SLC memory block may include a plurality of pages implemented with memory cells that are each capable of storing 1 bit of data. An MLC memory block may include multiple pages of memory cell implementations that are each capable of storing multiple bits of data (e.g., two or more bits of data). An MLC memory block including a plurality of pages implemented with memory cells each capable of storing 3-bit data may be defined as a Triple Level Cell (TLC) memory block.

Fig. 3 is a circuit diagram illustrating a memory block 330 in the memory device 150 of fig. 2.

Referring to fig. 3, the memory block 330 may correspond to any one of a plurality of memory blocks included in the memory device 150 of the memory system 110.

Memory block 330 of memory device 150 may include a plurality of cell strings 340 electrically coupled to bit lines BL0 through BLm-1, respectively. The cell string 340 of each column may include at least one drain select transistor DST and at least one source select transistor SST. A plurality of memory cells or a plurality of memory cell transistors MC0 through MCn-1 may be electrically coupled in series between select transistors DST and SST. The respective memory cells MC0 through MCn-1 may be configured by Single Level Cells (SLC) each of which may store 1 bit of information, or by Multi Level Cells (MLC) each of which may store multiple bits of data information. However, the present invention is not limited to only SLC or MLC. Strings 340 may be electrically coupled to corresponding bit lines BL 0-BLm-1, respectively. For reference, in fig. 3, "DSL" denotes a drain select line, "SSL" denotes a source select line, and "CSL" denotes a common source line.

Although fig. 3 illustrates the memory block 330 as being composed of NAND flash memory cells as an example, it should be noted that the memory block 330 of the memory device 150 according to the embodiment is not limited to the NAND flash memory. The memory block 330 may be implemented by a NOR flash memory, a hybrid flash memory combining at least two kinds of memory cells, or a one-NAND flash memory in which a controller is built in a memory chip. The operation characteristics of the semiconductor device can be applied not only to a flash memory device in which a charge storage layer is composed of a conductive floating gate but also to a charge trap type flash memory (CTF) in which a charge storage layer is composed of a dielectric layer.

The power supply circuit 310 of the memory device 150 may provide word line voltages (e.g., a program voltage, a read voltage, and a pass voltage) to be supplied to the respective lines according to an operation mode and provide a voltage to be supplied to a bulk (bulk) (e.g., a well region in which memory cells are formed). The power supply circuit 310 may perform a voltage generating operation under the control of a control circuit (not shown). The power supply circuit 310 may generate a plurality of variable read voltages to generate a plurality of read data, select one memory block or sector in the memory cell array under the control of the control circuit, select one word line of the selected memory block, and supply a word line voltage to the selected word line and the unselected word lines.

The read and write (read/write) circuits 320 of the memory device 150 may be controlled by the control circuit and may function as a read amplifier or a write driver depending on the mode of operation. During a verify operation or a normal read operation, the read/write circuit 320 may operate as a read amplifier for reading data from the memory cell array. During a programming operation, the read/write circuit 320 may operate as a write driver for driving bit lines according to data to be stored in the memory cell array. During a program operation, the read/write circuit 320 may receive data to be stored into the memory cell array from a buffer (not shown) and drive bit lines according to the received data. The read/write circuit 320 may include a plurality of page buffers 322 to 326 corresponding to columns (or bit lines) or column pairs (or bit line pairs), respectively. Each of the page buffers 322 to 326 may include a plurality of latches (not shown).

Fig. 4 is a schematic diagram illustrating a three-dimensional (3D) structure of the memory device 150 of fig. 1.

Although fig. 4 illustrates a 3D structure, the present invention is not limited to such a structure. In another embodiment, the memory device 150 may be implemented by a two-dimensional (2D) memory device. As illustrated in fig. 4, the memory device 150 may be implemented as a nonvolatile memory device having a 3D stacked structure. When the memory device 150 has a 3D structure, the memory device 150 may include a plurality of memory blocks BLK0 through BLKN-1 each having a 3D structure (or a vertical structure).

The operation of the data processing system 100 according to an embodiment of the present invention will be described. In the context of the following description as one example, the battery is classified into 0 th to fifth grades. Specifically, when the available capacity of the battery is 100% or less and more than 80%, the battery grade may be set to a fifth grade. The battery grade may be set to a fourth grade when the available capacity of the battery is less than 80% and more than 60%. The battery grade may be set to a third grade when the available capacity of the battery is less than 60% and more than 40%. The battery rating may be set to the second rating when the available capacity of the battery is less than 40% and more than 20%. The battery rating may be set to the first rating when the available capacity of the battery is less than 20% and more than 10%. When the available capacity of the battery is less than 10% and more than 0%, the battery rating may be set to the 0 th rating. However, the present invention is not limited to any particular number of levels, nor to the capacity range of any particular level.

Fig. 5A to 5F are diagrams illustrating the operation of the data processing system 100 according to an embodiment of the present invention. Specifically, fig. 5A-5F illustrate the operation of data processing system 100 to perform a certain number of background operations depending on the battery level. The number of times the background operation is performed may be different for different levels.

As an example, data processing system 100 performs a total of five background operations to complete the background operation. Further, as an example, data processing system 100 shown in fig. 5A through 5F performs a background operation of migrating data stored in a source storage block to a destination storage block. Further, as an example, the background operations of migrating the first to fifth data stored in the source storage block to the destination storage block shown in fig. 5A to 5F are performed five times in total. In other words, a background operation may have to be performed once to migrate the first data stored in the source storage block into the destination storage block.

Referring to fig. 5A, the host 102 may provide information indicating a fifth level (i.e., level 5) corresponding to the currently available capacity of the battery 104 to the controller 130. As a result, it can be seen that the currently available capacity of the battery is less than 100% and more than 80%.

The battery information manager 146 may store information indicating a battery level provided from the host 102. The processor 134 may determine the background operating method based on the battery level. Since the battery capacity is at the fifth level, the processor 134 may set the background operation to be performed five times.

Subsequently, the processor 134 may migrate all of the first to fifth data stored in the source storage block 510 into the destination storage block 515.

Referring to fig. 5B, the host 102 may provide information indicating a fourth level (i.e., level 4) corresponding to the currently available capacity of the battery 104 to the controller 130. As a result, it can be seen that the currently available capacity of the battery is less than 80% and more than 60%.

The battery information manager 146 may store information indicating a battery level provided from the host 102. The processor 134 may then determine a background operating method based on the battery level. Since the battery capacity is at the fourth level, processor 134 may set the background operation to be performed four times.

Then, the processor 134 may migrate the first to fourth data stored in the source storage block 520 into the destination storage block 525.

Referring to fig. 5C, the host 102 may provide information indicating a third level (i.e., level 3) corresponding to the currently available capacity of the battery 104 to the controller 130. As a result, it can be seen that the currently available capacity of the battery is less than 60% and more than 40%.

The battery information manager 146 may store information indicating a battery level provided from the host 102. The processor 134 may then determine a background operating method based on the battery level. Since the battery capacity is at the third level, the processor 134 may set the background operation to be performed three times.

Processor 134 may then migrate the first through third data stored in source storage block 530 into destination storage block 535.

Referring to fig. 5D, the host 102 may provide information indicating a second level (i.e., level 2) corresponding to the currently available capacity of the battery 104 to the controller 130. As a result, it can be seen that the currently available capacity of the battery is less than 40% and more than 20%.

The battery information manager 146 may store information indicating a battery level provided from the host 102. The processor 134 may then determine a background operating method based on the battery level. Since the battery capacity is at the second level, the processor 134 may set the background operation to be performed twice.

The processor 134 may then migrate the first data and the second data stored in the source storage block 540 to the destination storage block 545.

Referring to fig. 5E, the host 102 may provide information indicating a first level (i.e., level 1) corresponding to the currently available capacity of the battery 104 to the controller 130. As a result, it can be seen that the currently available capacity of the battery is less than 20% and more than 10%.

The battery information manager 146 may store information indicating a battery level provided from the host 102. The processor 134 may then determine a background operating method based on the battery level. Since the battery capacity is at the first level, the processor 134 may set the background operation to be performed once.

Processor 134 may then migrate only the first data stored in source storage block 550 to destination storage block 555.

Finally, referring to fig. 5F, the host 102 may provide information indicating a 0 th level (i.e., a level of 0) corresponding to the currently available capacity of the battery 104 to the controller 130. As a result, it can be seen that the currently available capacity of the battery is less than 10% and more than 0%.

The battery information manager 146 may store information indicating a battery level provided from the host 102. The processor 134 may then determine a background operating method based on the battery level. Since the battery capacity is at level 0, the processor 134 may not perform the background operation.

As described above, data processing system 100 may conserve battery power by varying the number of times background operations are performed based on the current available capacity of battery 104.

Fig. 6A to 6F are diagrams illustrating the operation of the data processing system 100 according to an embodiment of the present invention. Specifically, fig. 6A to 6F illustrate that the data processing system 100 performs a background operation within a specific execution time set differently according to each battery level.

In the context of the following description, memory system 110 may have an idle time of approximately 100 ms. Furthermore, the memory system 110 may have to perform a background operation for approximately 100ms in order to completely end the background operation.

Referring to fig. 6A, the host 102 may provide information indicating a fifth level (i.e., level 5) corresponding to a currently available battery capacity to the controller 130. As a result, it can be seen that the currently available capacity of the battery is less than 100% and more than 80%.

The battery information manager 146 may store information indicating a battery level provided from the host 102. The processor 134 included in the memory system 110 may determine the background operation method based on the battery level. Since the battery is at the fifth level, processor 134 may set the background operation to perform for approximately 100 ms.

The memory system 110 may then perform approximately 100ms of background operations (i.e., BKOP).

Referring to fig. 6B, the host 102 may provide information indicating a fourth level (i.e., level 4) corresponding to the currently available battery capacity to the controller 130. As a result, it can be seen that the currently available capacity of the battery is less than 80% and more than 60%.

Since the battery capacity is at the fourth level, the processor 134 included in the memory system 110 may set the background operation to be performed for about 80 ms.

The memory system 110 may then perform approximately 80ms of background operations (i.e., BKOP). The memory system 110 may not perform background operations for the remaining approximately 20ms, which may be idle time.

Referring to fig. 6C, the host 102 may provide information indicating a third level (i.e., level 3) corresponding to the currently available battery capacity to the controller 130. As a result, it can be seen that the currently available capacity of the battery is less than 60% and more than 40%.

Since the battery is at the third level, the processor 134 included in the memory system 110 may set the background operation to be performed for about 60 ms.

The memory system 110 may then perform approximately 60ms of background operations (i.e., BKOP). The memory system 110 may not perform background operations for the remaining approximately 40ms, which may be idle time.

Referring to fig. 6D, the host 102 may provide information indicating a second level (i.e., level 2) corresponding to the currently available battery capacity to the controller 130. As a result, it can be seen that the currently available capacity of the battery is less than 40% and more than 20%.

Since the battery capacity is at the second level, the processor 134 included in the memory system 110 may set the background operation to be performed for about 40 ms.

The memory system 110 may then perform approximately 40ms of background operations (i.e., BKOP). The memory system 110 may not perform background operations for the remaining approximately 60ms, which may be idle time.

Referring to fig. 6E, the host 102 may provide information indicating a first level (i.e., level 1) corresponding to a currently available battery capacity to the controller 130. As a result, it can be seen that the currently available capacity of the battery is less than 20% and more than 10%.

Since the battery capacity is at the first level, the processor 134 included in the memory system 110 may set the background operation to be performed for about 20 ms.

Processor 134 may perform approximately 20ms of background operations. Data processing system 100 may not perform background operations for the remaining approximately 80ms, which may be idle time.

Finally, referring to fig. 6F, the host 102 may provide information indicating a 0 th level (i.e., level 0) corresponding to the currently available battery capacity to the controller 130. As a result, it can be seen that the currently available capacity of the battery is less than 10% and more than 0%.

Since the battery capacity is at level 0, the memory system 110 may not perform a background operation at all.

As described above, data processing system 100 may conserve battery power by varying the time for performing background operations based on the current available capacity of the battery.

FIG. 7 is a flowchart illustrating operation of the memory system 110 according to an embodiment of the present invention. In particular, fig. 7 illustrates the performance of background operations of the memory system 110 depending on the determined battery level or grade. However, the background operation illustrated in fig. 7 is only one embodiment of the present invention at most, and the concept and spirit of the present invention are not limited thereto.

In step S701, the processor 134 may check information indicating the battery level stored in the battery information manager 146.

When it is determined as a result of the check that the battery is at the fifth level (i.e., level 5) (yes in step S703), the processor 134 may perform 100% of the background operation (i.e., BKOP) without limitation in step S705.

When it is determined as a result of the check that the battery is not at the fifth level (no at step S703) but at the fourth level (i.e., level 4) (yes at step S707), the processor 134 may perform only 80% of the background operation (i.e., BKOP) at step S709. For example, the processor 134 may limit the number of executions of the background operation or the execution time of the background operation to as much as 80%.

When it is determined as a result of the check that the battery is not at the fourth level (no in step S707) but at the third level (i.e., level 3) (yes in step S711), the processor 134 may limit the number of executions of the background operation (i.e., BKOP) or the execution time of the background operation to as much as 60% in step S713.

When it is determined as a result of the check that the battery is not at the third level (no in step S711) but at the second level (i.e., level 2) (yes in step S715), the processor 134 may limit the number of executions of the background operation (i.e., BKOP) or the execution time of the background operation to as much as 40% in step S717.

When it is determined as a result of the check that the battery is not at the second level (no at step S715) but at the first level (i.e., level 1) (yes at step S719), the processor 134 may limit the number of executions of the background operation (i.e., BKOP) or the execution time of the background operation to as much as 20% at step S721.

When it is determined as a result of the check that the battery is not at the first level (no at step S719), the processor 134 may not perform the background operation (i.e., BKOP) at step S723.

As described above, the controller 130 according to an embodiment of the present invention may classify the battery status into one of a plurality of classes based on the battery status information (e.g., available capacity) of the data processing system 100 and perform a background operation based on the battery class. The classification level may change as the battery state is re-evaluated. In this manner, the battery usage efficiency of data processing system 100 may be increased.

A data processing system and an electronic device that can be implemented with the memory system 110 including the memory device 150 and the controller 130, which have been described above, will be described in detail with reference to fig. 8 to 16.

Fig. 8-16 are diagrams schematically illustrating application examples of the data processing system of fig. 1-7, in accordance with various embodiments.

Fig. 8 is a diagram schematically illustrating an example of a data processing system including a memory system according to an embodiment. Fig. 8 schematically illustrates a memory card system 6100 as an application of the memory system according to the embodiment.

Referring to fig. 8, a memory card system 6100 may include a memory controller 6120, a memory device 6130, and a connector 6110.

More specifically, the memory controller 6120 may be connected to the memory device 6130 and may be configured to access the memory device 6130. The memory device 6130 may be implemented by a non-volatile memory (NVM). By way of example, and not limitation, the memory controller 6120 may be configured to control read operations, write operations, erase operations, and background operations to the memory device 6130. The memory controller 6120 may be configured to provide an interface between the memory device 6130 and a host (not shown) and/or drive firmware for controlling the memory device 6130. That is, the memory controller 6120 may correspond to the controller 130 in the memory system 110 described with reference to fig. 1 to 7, and the memory device 6130 may correspond to the memory device 150 described with reference to fig. 1 to 7.

Thus, as shown in FIG. 1, the memory controller 6120 may include Random Access Memory (RAM), a processor, a host interface, a memory interface, and error correction code components. The memory controller 6120 may also include the elements described in FIG. 1.

The memory controller 6120 may communicate with an external device, such as the host 102 of FIG. 1, through the connector 6110. For example, as described with reference to fig. 1, the memory controller 6120 may be configured to communicate with external devices through one or more of various communication protocols such as Universal Serial Bus (USB), multi-media card (MMC), embedded MMC (emmc), Peripheral Component Interconnect (PCI), PCI express (PCIe), Advanced Technology Attachment (ATA), serial-ATA, parallel-ATA, Small Computer System Interface (SCSI), enhanced small disk interface (EDSI), Integrated Drive Electronics (IDE), firewire, universal flash memory (UFS), wireless fidelity (Wi-Fi or WiFi), and bluetooth. Accordingly, the memory system and the data processing system according to the embodiments may be applied to wired electronic devices and/or wireless electronic devices, or particularly mobile electronic devices.

The memory device 6130 may be implemented by a non-volatile memory (NVM). For example, memory device 6130 may be implemented by any of a variety of non-volatile memory devices, such as erasable programmable rom (eprom), electrically erasable programmable rom (eeprom), NAND flash memory, NOR flash memory, phase change RAM (pram), resistive RAM (reram), ferroelectric RAM (fram), and spin transfer torque magnetic RAM (STT-RAM). Memory device 6130 may include multiple dies, as in memory device 150 of FIG. 1.

The memory controller 6120 and the memory device 6130 may be integrated into a single semiconductor device. For example, the memory controller 6120 and the memory device 6130 may be integrated to form a Solid State Drive (SSD). In another embodiment, the memory controller 6120 and the memory device 6130 may be integrated to form a memory card, such as a PC card (e.g., Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash (CF) card, a smart media card (e.g., SM and SMC), a memory stick, a multimedia card (e.g., MMC, RS-MMC, MMCmicro, and eMMC), a Secure Digital (SD) card (e.g., SD, miniSD, microSD, and SDHC), and/or a Universal Flash (UFS).

Fig. 9 is a diagram schematically illustrating another example of a data processing system 6200 including a memory system according to an embodiment.

Referring to fig. 9, a data processing system 6200 may include a memory device 6230 having one or more non-volatile memories (NVMs) and a memory controller 6220 for controlling the memory device 6230. The data processing system 6200 may be used as a storage medium such as a memory card (CF card, SD card, mini-SD card, or the like) or a USB device, as described with reference to fig. 1. The memory device 6230 may correspond to the memory device 150 in the memory system 110 described in fig. 1 to 7, and the memory controller 6220 may correspond to the controller 130 in the memory system 110 described in fig. 1 to 7.

The memory controller 6220 may control read, write, or erase operations to the memory device 6230 in response to requests by the host 6210, and the memory controller 6220 may include one or more Central Processing Units (CPUs) 6221, a buffer memory such as a Random Access Memory (RAM)6222, an Error Correction Code (ECC) circuit 6223, a host interface 6224, and a memory interface such as an NVM interface 6225.

The CPU 6221 may control operations on the memory device 6230, such as a read operation, a write operation, a file system management operation, and a bad page management operation. The RAM6222 can operate under the control of the CPU 6221, and functions as a work memory, a buffer memory, or a cache memory. When the RAM6222 is used as a working memory, data processed by the CPU 6221 may be temporarily stored in the RAM 6222. When RAM6222 is used as a buffer memory, the RAM6222 may be used to buffer data transferred from the host 6210 to the memory device 6230 or data transferred from the memory device 6230 to the host 6210. When RAM6222 is used as cache memory, the RAM6222 can operate at high speed with the auxiliary memory device 6230.

The ECC circuit 6223 may correspond to the ECC component 138 of the controller 130 illustrated in fig. 1. As described with reference to fig. 1, the ECC circuit 6223 may generate an Error Correction Code (ECC) for correcting failed or erroneous bits of data provided from the memory device 6230. ECC circuitry 6223 may perform error correction coding on the data provided to memory device 6230, thereby forming data having parity bits. The parity bits may be stored in the memory device 6230. The ECC circuit 6223 may perform error correction decoding on the data output from the memory device 6230. In this case, the ECC circuit 6223 may correct the error using the parity bit. For example, as described with reference to fig. 1, the ECC circuit 6223 may correct errors using a Low Density Parity Check (LDPC) code, a bose-chaudhuri-okay (BCH) code, a turbo code, a reed-solomon code, a convolutional code, a Recursive Systematic Code (RSC), or a coded modulation such as Trellis Coded Modulation (TCM) or Block Coded Modulation (BCM).

Memory controller 6220 may exchange data or signals with host 6210 through host interface 6224, and with memory device 6230 through NVM interface 6225. The host interface 6224 may be connected to the host 6210 by a Parallel Advanced Technology Attachment (PATA) bus, a Serial Advanced Technology Attachment (SATA) bus, a Small Computer System Interface (SCSI), a Universal Serial Bus (USB), a peripheral component interconnect express (PCIe), or a NAND interface. The memory controller 6220 may have a wireless communication function using a mobile communication protocol such as wireless fidelity (WiFi) or Long Term Evolution (LTE). The memory controller 6220 may connect to an external device (e.g., the host 6210) or another external device and then transmit and/or receive data to/from the external device. Since the memory controller 6220 is configured to communicate with an external device through one or more of various communication protocols, the memory system and the data processing system may be applied to a wired electronic device and/or a wireless electronic device, particularly a mobile electronic device.

FIG. 10 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment. Fig. 10 schematically illustrates a Solid State Drive (SSD)6300 to which the memory system according to the embodiment is applied.

Referring to fig. 10, the SSD 6300 may include a controller 6320 and a memory device 6340 including a plurality of nonvolatile memories (NVMs). The controller 6320 may correspond to the controller 130 in the memory system 110 of fig. 1, and the memory device 6340 may correspond to the memory device 150 in the memory system of fig. 1.

More specifically, the controller 6320 may be connected to the memory device 6340 through a plurality of channels CH1 through CHi. The controller 6320 may include one or more processors 6321, Error Correction Code (ECC) circuitry 6322, a host interface 6324, a buffer memory 6325, and a memory interface such as a non-volatile memory interface 6326.

The buffer memory 6325 may temporarily store data supplied from the host 6310 or data supplied from a plurality of flash NVMs included in the memory device 6340, or temporarily store metadata of the plurality of flash NVMs, for example, mapping data including a mapping table. The buffer memory 6325 may be implemented by any of various volatile memories such as Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate (DDR) SDRAM, low power DDR (lpddr) SDRAM, and graphics RAM (gram), or non-volatile memories such as ferroelectric RAM (fram), resistive RAM (RRAM or ReRAM), spin transfer torque magnetic RAM (STT-MRAM), and phase change RAM (pram). In the embodiment of fig. 10, the buffer memory 6325 is provided in the controller 6320, but in another embodiment, the buffer memory 6325 may be located or arranged outside the controller 6320.

The ECC circuit 6322 may calculate an Error Correction Code (ECC) value of data to be programmed to the memory device 6340 during a programming operation, perform an error correction operation on data read from the memory device 6340 based on the ECC value during a read operation, and perform an error correction operation on data recovered from the memory device 6340 during a failed data recovery operation.

The host interface 6324 may provide an interface function with an external device (e.g., a host 6310), and the nonvolatile memory interface 6326 may provide an interface function with the memory device 6340 connected through a plurality of channels.

Further, a plurality of SSDs 6300 to which the memory system 110 of fig. 1 is applied may be provided to implement a data processing system, for example, a Redundant Array of Independent Disks (RAID) system. The RAID system may include a plurality of SSDs 6300 and a RAID controller for controlling the plurality of SSDs 6300. When the RAID controller performs a programming operation in response to a write command provided from the host 6310, the RAID controller may select one or more memory systems or SSDs 6300 according to a plurality of RAID levels (i.e., RAID level information of the write command provided from the host 6310) in the SSD 6300, and may output data corresponding to the write command to the selected SSD 6300. Further, when the RAID controller performs a read operation in response to a read command provided from the host 6310, the RAID controller may select one or more memory systems or SSDs 6300 according to a plurality of RAID levels (i.e., RAID level information of the read command provided from the host 6310) in the SSD 6300 and provide the host 6310 with data read from the selected SSD 6300.

FIG. 11 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment. Fig. 11 schematically illustrates an embedded multimedia card (eMMC)6400 to which a memory system is applied.

Referring to fig. 11, the eMMC 6400 may include a controller 6430 and a memory device 6440 implemented by one or more NAND flash memories. The controller 6430 may correspond to the controller 130 in the memory system 110 of fig. 1, and the memory device 6440 may correspond to the memory device 150 in the memory system 110 of fig. 1.

More specifically, the controller 6430 may be connected to the memory device 6440 through a plurality of channels. The controller 6430 may include one or more cores 6432, a host interface (I/F)6431, and a memory interface such as a NAND interface (I/F) 6433.

The kernel 6432 may control operations of the eMMC 6400, and the host interface 6431 may provide interface functions between the controller 6430 and the host 6410. The NAND interface 6433 may provide an interface function between the memory device 6440 and the controller 6430. For example, the host interface 6431 may function as a parallel interface, e.g., an MMC interface as described with reference to fig. 1. In addition, the host interface 6431 may be used as a serial interface, for example, Ultra High Speed (UHS) -I and UHS-II interfaces.

Fig. 12 to 15 are diagrams schematically illustrating other examples of a data processing system including a memory system according to an embodiment. Fig. 12 to 15 schematically illustrate universal flash memory (UFS) systems 6500, 6600, 6700, and 6800 to which the memory system is applied.

Referring to fig. 12-15, UFS systems 6500, 6600, 6700, and 6800 may include hosts 6510, 6610, 6710, 6810, UFS devices 6520, 6620, 6720, 6820, and UFS cards 6530, 6630, 6730, 6830, respectively. Host 6510, 6610, 6710, 6810 can function as an application processor for wired electronic devices and/or wireless electronic devices, particularly mobile electronic devices, and UFS device 6520, 6620, 6720, 6820 can function as an embedded UFS device. UFS cards 6530, 6630, 6730, 6830 may function as external embedded UFS devices or removable UFS cards.

Hosts 6510, 6610, 6710, 6810, UFS devices 6520, 6620, 6720, 6820, and UFS cards 6530, 6630, 6730, 6830 in respective UFS systems 6500, 6600, 6700, and 6800 may communicate with external devices, such as wired electronic devices and/or wireless electronic devices, or in particular mobile electronic devices, via the UFS protocol. UFS devices 6520, 6620, 6720, 6820 and UFS cards 6530, 6630, 6730, 6830 may be implemented by memory system 110 illustrated in fig. 1. For example, in UFS systems 6500, 6600, 6700, 6800, UFS devices 6520, 6620, 6720, 6820 may be implemented in the form of a data processing system 6200, SSD 6300, or eMMC 6400 described with reference to fig. 9 through 11, and UFS cards 6530, 6630, 6730, 6830 may be implemented in the form of a memory card system 6100 described with reference to fig. 8.

Further, in UFS systems 6500, 6600, 6700, and 6800, hosts 6510, 6610, 6710, 6810, UFS devices 6520, 6620, 6720, 6820, and UFS cards 6530, 6630, 6730, 6830 may communicate with each other through UFS interfaces such as MIPI M-PHY and MIPI UniPro (unified protocol) in MIPI (mobile industry processor interface). Further, UFS devices 6520, 6620, 6720, 6820 and UFS cards 6530, 6630, 6730, 6830 may communicate with each other through various protocols other than the UFS protocol, such as universal memory bus (USB) flash drive (UFD), multimedia card (MMC), Secure Digital (SD), mini-SD card, and micro-SD card.

In UFS system 6500 illustrated in fig. 12, each of host 6510, UFS device 6520, and UFS card 6530 may include UniPro. Host 6510 may perform a switching operation to communicate with at least one of UFS device 6520 and UFS card 6530. Host 6510 may communicate with UFS device 6520 or UFS card 6530 through a link layer switch at UniPro (e.g., an L3 switch). In this case, UFS device 6520 and UFS card 6530 may communicate with each other through link layer switching at UniPro of host 6510. Fig. 12 illustrates a configuration in which one UFS device 6520 and one UFS card 6530 are connected to a host 6510. However, in another embodiment, multiple UFS devices and UFS cards may be connected to host 6510 in parallel or in a star, and multiple UFS cards may be connected to UFS device 6520 in parallel or in a star, or connected to UFS device 6520 in series or in a chain. In this context, the form of a star represents a layout in which a single device is coupled with a plurality of other devices or cards for centralized control.

In UFS system 6600 illustrated in fig. 13, each of host 6610, UFS device 6620, and UFS card 6630 may include UniPro, and host 6610 may communicate with UFS device 6620 or UFS card 6630 through switching module 6640 that performs a switching operation (e.g., through switching module 6640 that performs a link-layer switching at UniPro (e.g., L3 switching)). UFS device 6620 and UFS card 6630 may communicate with each other through link layer switching of switching module 6640 at UniPro. Fig. 13 illustrates a configuration in which one UFS device 6620 and one UFS card 6630 are connected to the switching module 6640. However, in another embodiment, multiple UFS devices and UFS cards may be connected to switching module 6640 in parallel or in a star format, and multiple UFS cards may be connected to UFS device 6620 in series or in a chain format.

In UFS system 6700 illustrated in fig. 14, each of host 6710, UFS device 6720, and UFS card 6730 may include UniPro. The host 6710 may communicate with the UFS device 6720 or UFS card 6730 through a switching module 6740 that performs a switching operation (e.g., a switching module 6740 that performs a link layer switching at UniPro (e.g., an L3 switching)). In this case, UFS device 6720 and UFS card 6730 may communicate with each other through link-layer switching of switching module 6740 at UniPro, and switching module 6740 may be integrated with UFS device 6720 as one module inside or outside UFS device 6720. Fig. 14 illustrates a configuration in which one UFS device 6720 and one UFS card 6730 are connected to a switching module 6740. However, in another embodiment, a plurality of modules each including the switching module 6740 and the UFS device 6720 may be connected to the host 6710 in parallel or in a star form, or connected to each other in series or in a chain form. Further, multiple UFS cards may be connected to UFS device 6720 in parallel or in a star format.

In UFS system 6800 illustrated in fig. 15, each of host 6810, UFS device 6820, and UFS card 6830 may include a M-PHY and UniPro. UFS device 6820 may perform a switching operation to communicate with host 6810 and UFS card 6830. UFS device 6820 may communicate with host 6810 or UFS card 6830 through a switchover operation (e.g., through a target Identifier (ID) switchover operation) between the M-PHY and UniPro modules for communicating with host 6810 and the M-PHY and UniPro modules for communicating with UFS card 6830. Here, the host 6810 and the UFS card 6830 can communicate with each other through target ID switching between the M-PHY of the UFS device 6820 and the UniPro module. Fig. 15 illustrates a configuration in which one UFS device 6820 is connected to the host 6810 and one UFS card 6830 is connected to the UFS device 6820. However, in another embodiment, multiple UFS devices may be connected to host 6810 in parallel or in a star, or connected to host 6810 in series or in a chain, and multiple UFS cards may be connected to UFS device 6820 in parallel or in a star, or connected to UFS device 6820 in series or in a chain.

Fig. 16 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment. Fig. 16 is a diagram schematically illustrating a user system 6900 to which a memory system according to an embodiment is applied.

Referring to fig. 16, the user system 6900 may include a user interface 6910, a memory module 6920, an application processor 6930, a network module 6940, and a storage module 6950.

More specifically, the application processor 6930 may drive components (e.g., an Operating System (OS)) included in the user system 6900, and include a controller, an interface, and a graphics engine that control the components included in the user system 6900. The application processor 6930 may be configured as a system on chip (SoC).

The memory module 6920 may serve as a main memory, a working memory, a buffer memory, or a cache memory for the user system 6900. Memory module 6920 may include volatile Random Access Memory (RAM) such as Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate (DDR) SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, LPDDR2 SDRAM, or LPDDR3 SDRAM, or non-volatile RAM such as phase change RAM (PRAM), resistive RAM (ReRAM), Magnetoresistive RAM (MRAM), or Ferroelectric RAM (FRAM). For example, the application processor 6930 and the memory module 6920 may be packaged and installed based on package (PoP).

The network module 6940 may communicate with external devices. For example, the network module 6940 may support not only wired communication but also various wireless communication protocols such as Code Division Multiple Access (CDMA), global system for mobile communications (GSM), wideband CDMA (wcdma), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), worldwide interoperability for microwave access (Wimax), Wireless Local Area Network (WLAN), Ultra Wide Band (UWB), bluetooth, wireless display (WI-DI), and the like, so as to communicate with wired/wireless electronic devices, especially mobile electronic devices. Accordingly, the memory system and the data processing system according to the embodiments of the present invention can be applied to wired/wireless electronic devices. The network module 6940 can be included in the application processor 6930.

The storage module 6950 can store data (e.g., data received from the application processor 6930) and can then send the stored data to the application processor 6930. The storage module 6950 may be implemented by a nonvolatile semiconductor memory device such as a phase change ram (pram), a magnetic ram (mram), a resistance ram (reram), a NAND flash memory, a NOR flash memory, and a 3D NAND flash memory, and is provided as a removable storage medium such as a memory card or an external drive of the user system 6900. The storage module 6950 may correspond to the memory system 110 described with reference to fig. 1. Further, the storage module 6950 may be implemented as an SSD, eMMC, and UFS as described above with reference to fig. 10-15.

The user interface 6910 may include an interface for inputting data or commands to the application processor 6930 or outputting data to an external device. For example, the user interface 6910 may include a user input interface such as a keyboard, keypad, button, touch panel, touch screen, touch pad, touch ball, camera, microphone, gyro sensor, vibration sensor, and piezoelectric element, and a user output interface such as a Liquid Crystal Display (LCD), Organic Light Emitting Diode (OLED) display device, active matrix OLED (amoled) display device, LED, speaker, and monitor.

Further, when the memory system 110 of fig. 1 is applied to a mobile electronic device of the user system 6900, the application processor 6930 may control the operation of the mobile electronic device, and the network module 6940 may serve as a communication module for controlling wired communication and/or wireless communication with an external device. The user interface 6910 may display data processed by the application processor 6930 on a display and touch module of the mobile electronic device or support a function of receiving data from a touch panel.

While the invention has been illustrated and described with reference to specific embodiments, it will be apparent to those skilled in the art in light of the teachings of this disclosure that: various modifications and variations may be made without departing from the spirit or scope of the invention as defined in the appended claims.

Cross Reference to Related Applications

The present application claims priority from korean patent application No.10-2018-0108308, filed on 11/9/2018, the disclosure of which is incorporated herein by reference in its entirety.