阅读说明：本技术 存储器电路及其数据比特状态检测器 (Memory circuit and data bit state detector thereof ) 是由 林哲逸 何文乔 于 2018-09-07 设计创作，主要内容包括：本发明提供一种存储器电路及其数据比特状态检测器。数据比特状态检测器包括感测放大电路、数据接收电路以及参考电路。感测放大电路具有第一感测输入端以及第二感测输入端。感测放大电路感测并放大第一感测输入端上的第一阻抗以及第二感测输入端上的第二阻抗的差值,以产生感测输出信号。数据接收电路接收数据信号的多个比特,并依据数据信号的比特在第一感测输入端与参考接地端间提供第一阻抗。参考电路接收多个偏压电压,并依据偏压电压在第二感测输入端与参考接地端间提供第二阻抗。(The invention provides a memory circuit and a data bit state detector thereof. The data bit state detector includes a sense amplifier circuit, a data receiver circuit, and a reference circuit. The sensing amplifying circuit is provided with a first sensing input end and a second sensing input end. The sensing amplifying circuit senses and amplifies a difference value of a first impedance on the first sensing input end and a second impedance on the second sensing input end to generate a sensing output signal. The data receiving circuit receives a plurality of bits of a data signal and provides a first impedance between the first sensing input terminal and the reference ground terminal according to the bits of the data signal. The reference circuit receives a plurality of bias voltages and provides a second impedance between the second sensing input terminal and the reference ground terminal according to the bias voltages.)

1. A data bit state detector, comprising:

a sense amplifier circuit having a first sense input terminal and a second sense input terminal, sensing and amplifying a difference between a first impedance at the first sense input terminal and a second impedance at the second sense input terminal to generate a sense output signal;

a data receiving circuit for receiving a plurality of bits of a data signal and providing the first impedance between the first sensing input terminal and a reference ground terminal according to the plurality of bits of the data signal; and

the reference circuit receives a plurality of bias voltages and provides the second impedance between the second sensing input terminal and the reference ground terminal according to the bias voltages.

2. The data bit state detector of claim 1, wherein the data receiving circuit comprises a plurality of first transistors coupled in parallel with each other between the first sensing input terminal and the reference ground terminal, control terminals of the plurality of first transistors receiving the plurality of bits of the data signal, respectively.

3. The data bit state detector of claim 2, wherein the reference circuit comprises a plurality of second transistors coupled in parallel with each other between the second sense input and the reference ground, control terminals of the plurality of second transistors receiving the plurality of bias voltages, respectively,

wherein each bias voltage is a power voltage or a reference ground voltage.

4. The data bit state detector of claim 3, wherein a number of the plurality of second transistors is the same as a number of the plurality of first transistors.

5. The data bit state detector of claim 3, wherein the reference circuit further comprises:

and a third transistor coupled in parallel to each of the second transistors, a control terminal of the third transistor receiving the power supply voltage.

6. The data bit state detector of claim 3, wherein the data receiving circuit further comprises:

a first pull-down switch coupled between the data receiving circuit and the reference ground terminal and turned on or off according to an enable signal,

wherein the reference circuit further comprises:

the second pull-down switch is coupled between the reference circuit and the reference ground terminal and is turned on or off according to the enabling signal.

7. The data bit state detector of claim 1, further comprising:

a first capacitor connected in series between the first sensing input terminal and the reference ground terminal; and

and the second capacitor is connected between the second sensing input end and the reference ground end in series.

8. The data bit state detector of claim 1, further comprising:

a first discharge switch connected in series between the first sensing input terminal and the reference ground terminal, and turned on or off according to a discharge enable signal; and

and a second discharge switch connected in series between the second sensing input terminal and the reference ground terminal and turned on or off according to the discharge enable signal.

9. The data bit state detector of claim 1, wherein the sense amplification circuit comprises:

a first inverter having an input coupled to the second sensing input, an output of the first inverter coupled to the first sensing input; and

a second inverter having an input coupled to the first sensing input, an output coupled to the second sensing input.

10. The data bit state detector of claim 9, wherein the sense amplification circuit further comprises:

a first enable switch controlled by an upper-end enable signal to be turned on or off, wherein the first inverter and the second inverter receive a power supply voltage through the first enable switch; and

and a second enable switch controlled by a lower-end enable signal to be turned on or off, wherein the first inverter and the second inverter receive a reference ground voltage through the second enable switch.

11. The data bit state detector of claim 1, further comprising:

a first output buffer having an input coupled to the first sensing input, an output of the first output buffer generating the sensing output signal; and

a second output buffer having an input coupled to the second sensing input, the output of the second output buffer being floating.

12. A memory circuit, comprising:

a data bit state detector as claimed in claim 1; and

a multiplexing circuit coupled to the plurality of memory cell arrays and the data bit state detector for sequentially selecting each of the plurality of memory cell arrays or simultaneously selecting the plurality of memory cell arrays to perform a programming operation according to the sensing output signal.

Technical Field

The present invention relates to a memory circuit and a data bit state detector thereof, and more particularly, to a data bit state detector in the form of an analog circuit.

Background

In the field of flash memory technology, when a data signal is written into a flash memory, the number of bits of a logic level 0 in the data signal is determined, and a programming capability is set according to the number of bits of the logic level 0 in the data signal, and a programming operation is performed. In the prior art, a data signal can be read from a static random access memory, and a bit counter in the form of a logic circuit is used to count the number of bits of a logic level 0 in the data signal. In addition, according to the calculated bit number of the logic level 0, the conventional flash memory can effectively complete the programming (writing) operation of the data signal by adjusting the driving capability of the drain voltage generated by the drain boosting circuit.

Disclosure of Invention

The invention provides a memory circuit and a data bit state detector thereof, wherein the data bit state detector is constructed in the form of an analog circuit, and the required circuit area is effectively reduced.

The data bit state detector of the present invention includes a sense amplifying circuit, a data receiving circuit, and a reference circuit. The sensing amplifying circuit is provided with a first sensing input end and a second sensing input end. The sensing amplifying circuit senses and amplifies a difference value of a first impedance on the first sensing input end and a second impedance on the second sensing input end to generate a sensing output signal. The data receiving circuit receives a plurality of bits of a data signal and provides a first impedance between the first sensing input terminal and the reference ground terminal according to the bits of the data signal. The reference circuit receives a plurality of bias voltages and provides a second impedance between the second sensing input terminal and the reference ground terminal according to the bias voltages.

The memory circuit of the present invention includes a data bit state detector as described above and a multiplexing circuit. The multiplexing circuit is coupled to the plurality of memory cell arrays and the data bit state detector, and is used for sequentially selecting each memory cell array or simultaneously selecting the memory cell arrays to execute a programming operation according to the sensing output signal.

Based on the above, the present invention provides a first impedance according to a data signal through a data receiving circuit by a data bit state detector in the form of an analog circuit, and determines the state of a logic level of the data signal by comparing the first impedance with a second impedance as a reference value, and generates a sensing output signal accordingly. Therefore, the invention can simplify the complexity of circuit setting and effectively reduce the required circuit area.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 shows a schematic diagram of a data bit state detector according to an embodiment of the invention.

Fig. 2 shows a schematic diagram of a data bit state detector according to another embodiment of the invention.

Fig. 3A and 3B are operation waveform diagrams respectively illustrating different operation states of the data bit state detector according to the embodiment of the present invention.

FIG. 4 shows a schematic diagram of a memory circuit of an embodiment of the invention.

Description of reference numerals:

100. 200 and 410: a data bit state detector;

110. 210: a sense amplifier circuit;

120. 220, and (2) a step of: a data receiving circuit;

130. 230: a reference circuit;

400: a memory circuit;

431. 432: an array of memory cells;

420: a multiplexing circuit;

421. 422: a multiplexer;

BUF1, BUF 2: an output buffer;

cell _ EN: enabling a signal;

DATA: a data signal;

DATA [0:15 ]: a plurality of bits of a data signal;

DISC: a discharge enable signal;

GND: a reference ground terminal;

IV1, IV 2: an inverter;

MC 10-MC 27: a storage unit;

mcap1, Mcap 2: a capacitor;

MP 0-MP 3, MN 0-MN 6, MI 0-MI 15, MR 1-MR 2, M _ MISC: a transistor;

NC: floating connection;

NL _ EN: a lower end enable signal;

PL _ EN: enabling a signal at the upper end;

SAIN, SAIN _ R: a voltage;

SAOUT: sensing the output signal;

ST 1: a first sensing input terminal;

ST 2: a second sensing input terminal;

TA 1-TA 4: a time interval;

VDD: a supply voltage;

WL: word lines.

Detailed Description

Fig. 1 shows a schematic diagram of a data bit state detector according to an embodiment of the invention. Referring to fig. 1, the data bit state detector 100 includes a sense amplifier circuit 110, a data receiver circuit 120, and a reference circuit 130. The sense amplifier circuit 110 has a first sense input terminal ST1 and a second sense input terminal ST 2. The sense amplifier circuit 110 is used for sensing and amplifying a difference between a first impedance at the first sense input terminal ST1 and a second impedance at the second sense input terminal ST2 to generate a sense output signal SAOUT. The data receiving circuit 120 is coupled between the first sensing input terminal ST1 and the ground GND. The DATA receiving circuit 120 receives the DATA signal DATA and provides a first impedance between the first sensing input ST1 and the ground GND according to a plurality of bits of the DATA signal DATA. The reference circuit 130 is coupled between the second sensing input terminal ST2 and the ground reference GND. The reference circuit 130 receives a plurality of bias voltages and provides a second impedance between the second sensing input terminal ST2 and the reference ground GND according to the bias voltages.

Specifically, the DATA receiving circuit 120 may provide the first impedance according to the number of bits of the logic level 0 among the plurality of bits of the received DATA signal DATA. On the other hand, the reference circuit 130 provides a second impedance according to a plurality of preset bias voltages. In this way, the sense amplifier circuit 110 can compare the first impedance provided by the DATA receiving circuit 120 with the second impedance provided by the reference circuit 130 to determine whether the number of bits of the logic level 0 in the DATA signal DATA is greater than a reference value, and the reference value can be set by setting the magnitude of the second impedance.

Taking the DATA signal DATA having 16 bits as an example, in the embodiment of the invention, if the DATA signal DATA has less than or equal to 8 bits as the logic level 0, the first impedance value provided by the DATA receiving circuit 120 is R1, and if the DATA signal DATA has more than 8 bits as the logic level 0, the first impedance value provided by the DATA receiving circuit 120 is R2. On the other hand, the reference circuit 130 may be set to provide a second impedance having a resistance value between R1 and R2 according to the received bias voltage. In this way, the DATA bit state detector 100 can be used to detect whether the number of bits included in the received DATA signal DATA equal to logic level 0 is greater than 8, and generate the sense output signal SAOUT equal to the first logic level when the DATA signal DATA includes more than 8 bits equal to logic level 0. The DATA bit state detector 100 may generate the sensing output signal SAOUT equal to the second logic level when the DATA signal DATA includes less than or equal to 8 bits equal to the logic level 0. Wherein the first logic level is different from the second logic level.

Fig. 2 shows a schematic diagram of a data bit state detector according to another embodiment of the invention. Referring to fig. 2, the data bit state detector 200 includes a sense amplifier circuit 210, a data receiver circuit 220, and a reference circuit 230. The sense amplifier circuit 210 has a first sense input terminal ST1 and a second sense input terminal ST 2. The sense amplifying circuit 210 includes inverters IV1 and IV 2. The input of the inverter IV1 is coupled to the second sensing input ST2, and the output of the inverter IV1 is coupled to the first sensing input ST 1. The input of the inverter IV2 is coupled to the first sensing input ST1, and the output of the inverter IV2 is coupled to the second sensing input ST 2. The inverter IV1 is formed of transistors MP1 and MN5, and the inverter IV2 is formed of transistors MP0 and MN 4.

The sense amplifier circuit 210 further includes an enable switch composed of transistors MP3 and MN 6. The transistor MP3 is controlled by the upper-end enable signal PL _ EN to be turned on or off, wherein the inverters IV1 and IV2 receive the power voltage VDD through the transistor MP 3. The transistor MN6 is controlled by the lower enable signal NL _ EN to be turned on or off, wherein the inverters IV1 and IV2 are coupled to the ground reference terminal GND and receive the ground reference voltage through the transistor MN 6.

The data receiving circuit 220 is coupled to the first sensing input terminal ST1 of the sense amplifying circuit 210. The data receiving circuit 220 includes a plurality of transistors MI0 to MI 15. The transistors MI 0-MI 15 are coupled in parallel and coupled between the first sensing input terminal ST1 and the reference ground GND. The control terminals of the transistors MI 0-MI 15 are respectively controlled by the bits DATA [0:15] of the DATA signal, and provide a first impedance between the first sensing input terminal ST1 and the ground reference GND according to the bits DATA [0:15] of the DATA signal.

On the other hand, the data receiving circuit 220 further includes a pull-down switch formed by a transistor MN 1. The transistor MN1 is serially connected between the paths of the transistors MI 0-MI 15 coupled to the reference ground GND. Transistor MN1 is also controlled by enable signal Cell _ EN to be turned on or off.

The reference circuit 230 is coupled to the second sensing input terminal ST2 of the sense amplifying circuit 210. The reference circuit 230 includes a plurality of transistors MR 1-MR 2. The transistors MR 1-MR 2 are coupled in parallel to each other and coupled between the second sensing input ST2 and the ground reference GND. The control terminals of the transistors MR 1-MR 2 respectively receive different bias voltages (the control terminal of the transistor MR1 receives the power voltage VDD as a bias voltage, and the control terminal of the transistor MR2 is coupled to the ground reference terminal GND to receive the ground reference terminal GND as a bias voltage), and provide a second impedance between the second sensing input terminal ST2 and the ground reference terminal GND. In the embodiment of the invention, the reference circuit 230 further includes another transistor M _ MISC, which is coupled in parallel to the plurality of transistors MR 1-MR 2, and the control terminal of which receives the power voltage VDD as the bias voltage.

On the other hand, the reference circuit 230 further includes a pull-down switch formed by the transistor MN 0. The transistor MN0 is serially connected between the paths of the transistors MR 1-MR 2 coupled to the ground GND. Transistor MN0 is also controlled by enable signal Cell _ EN to be turned on or off.

In the present embodiment, the number of the transistors MR1 and MR2 can be one or more, and the total number of the transistors MR1 and MR2 can be the same as the number of the transistors MI0 to MI 15. The on/off states of the transistors MN0 and MN1 are the same.

In the embodiment of the present invention, the data bit state detector 200 further includes capacitors Mcap1, Mcap2, discharge switches constructed by transistors MN2, MN3, and output buffers BUF1, BUF 2. The capacitors Mcap1 and Mcap2 may be transistor capacitors and are respectively coupled to the first sensing input ST1 and the second sensing input ST 2. The discharge switch constructed by the transistor MN3 is connected in series between the first sensing input terminal ST1 and the reference ground GND, and is turned on or off according to the discharge enable signal DISC. The discharge switch constructed by the transistor MN2 is connected in series between the second sensing input terminal ST2 and the reference ground GND, and is turned on or off according to the discharge enable signal DISC. When the transistors MN3, MN2 are turned on, the capacitors Mcap1, Mcap2 discharge and pull down the voltages at the first and second sensing inputs ST1, ST 2.

The output buffers BUF1 and BUF2 are respectively coupled to the first sensing input terminal ST1 and the second sensing input terminal ST 2. The output buffers BUF1, BUF2 are inverters, and the output buffers BUF1, BUF2 are used for inverting the logic levels at the first and second sensing input terminals ST1, ST 2. The output buffer BUF1 is used for generating the sensing output signal SAOUT. The output buffer BUF2 may maintain a floating NC.

Fig. 3A and 3B are operation waveform diagrams respectively illustrating different operation states of the data bit state detector according to the embodiment of the present invention. Referring to fig. 2 and fig. 3A, in a time interval TA1, an upper enable signal PL _ EN is pulled high to a logic high level, and a lower enable signal NL _ EN is pulled low to a logic low level, and accordingly, a transistor MP3 serving as an enable switch is turned on and a transistor MN6 is turned off. Similarly, during the time interval TA1, the enable signal Cell _ EN is pulled high to a logic high level, the transistors MN0 and MN1 are turned on, and the path connecting the reference circuit 230 and the data receiving circuit 220 to the ground reference voltage GND is turned on. In addition, the discharge enable signal DISC is pulled high to a logic high level during the time interval TA1, the transistors MN2 and MN3 are turned on, and the voltages SAIN and SAIN _ R at the first sensing input terminal ST1 and the second sensing input terminal ST2 are pulled low.

In the embodiment of the present invention, the reference circuit 230 includes eight transistors MR1 and eight transistors MR 2. The transistor MR1 receives a bias voltage equal to the power supply voltage VDD, and the transistor MR2 receives a bias voltage equal to the ground reference voltage. The DATA receiving circuit 220 receives a DATA signal having 16 bits of DATA [0:15 ].

In a time interval TA2 after the time interval TA1, the top enable signal PL _ EN and the discharge enable signal DISC are pulled low to logic low, and the enable signal Cell _ EN is maintained at logic high. Meanwhile, if the first impedance provided by the DATA receiving circuit 220 is greater than the second impedance provided by the reference circuit 230 (i.e. the number of bits with logic level 0 in the bits DATA [0:15] of the DATA signal is greater than 8), the sense amplifying circuit 210 starts the sense amplifying operation, and pulls down the voltage SAIN _ R at the second sense input terminal ST2 and synchronously pulls up the voltage SAIN at the first sense input terminal ST1 according to the magnitude relationship between the first impedance and the second impedance.

In a time interval TA3 after the time interval TA2, the upper enable signal PL _ EN is maintained at a logic low level (the transistor MP3 is turned on), and the lower enable signal NL _ EN is pulled high to a logic high level, so that the transistor MN6 is turned on, thereby increasing the rising rate of the voltage SAIN and also accelerating the falling rate of the voltage SAIN _ R.

During a time interval TA4 after the time interval TA3, the voltage value of the voltage SAIN rises to exceed the threshold voltage of the inverter IV 2. Therefore, the voltage SAIN is pulled up to a logic high level rapidly in time interval TA4, and the voltage SAIN _ R is pulled down to a logic low level rapidly in time interval TA 4.

In the time interval TA4, the voltage SAIN _ R equal to the logic low level and the voltage SAIN equal to the logic high level are latched in the sense amplifying circuit 210 and output the sense output signal SAOUT through the output buffer BUF 1.

In fig. 3B, the action in time interval TA1 is the same as described in fig. 3A. In a time interval TA2 after the time interval TA1, the top enable signal PL _ EN and the discharge enable signal DISC are pulled low to logic low, and the enable signal Cell _ EN is maintained at logic high. Meanwhile, if the first impedance provided by the DATA receiving circuit 220 is smaller than the second impedance provided by the reference circuit 230 (i.e. the number of bits with logic level 0 in the bits DATA [0:15] of the DATA signal is smaller than or equal to 8), the sense amplifying circuit 210 starts the sense amplifying operation, and pulls up the voltage SAIN _ R at the second sense input terminal ST2 and synchronously pulls down the voltage SAIN at the first sense input terminal ST1 according to the magnitude relationship between the first impedance and the second impedance.

In a time interval TA3 after the time interval TA2, the upper enable signal PL _ EN is pulled high to a logic low level (the transistor MP3 is turned on), and the lower enable signal NL _ EN is pulled high to a logic high level, so that the transistor MN6 is turned on, thereby increasing the falling rate of the voltage SAIN and accelerating the rising rate of the voltage SAIN _ R.

During a time interval TA4 after the time interval TA3, the voltage value of the voltage SAIN _ R rises to exceed the threshold voltage of the inverter IV 1. Therefore, the voltage SAIN _ R is pulled up to a logic high level rapidly during the time interval TA4, and the voltage SAIN is pulled down to a logic low level rapidly during the time interval TA 4.

Referring to fig. 4, fig. 4 is a schematic diagram of a memory circuit according to an embodiment of the invention. Memory circuit 400 includes memory cell arrays 431, 432, multiplexing circuit 420, and data bit state detector 410. The data bit state detector 410 is coupled to the multiplexing circuit 420. The DATA bit state detector 410 receives a DATA signal DATA to be programmed (written), and determines a logic level state of a plurality of bits of the DATA signal DATA to generate a sensing output signal SAOUT. The multiplexing circuit 420 includes multiplexers 421, 422. The multiplexers 421 and 422 are coupled to the memory cell arrays 431 and 432, respectively. The multiplexer 420 receives the sensing output signal SAOUT and determines to turn on the memory cell arrays 431 and 432 at the same time or turn on the memory cell arrays 431 and 432 sequentially according to the sensing output signal SAOUT, so as to perform a programming operation on the memory cells MC10 through MC17 in the memory cell array 431 and the memory cells MC20 through MC27 in the memory cell array 432.

It should be noted that when the DATA bit state detector 410 determines that the number of bits of the DATA signal DATA that are at logic level 0 is greater than 8, it indicates that more DATA bits need to be written and more power needs to be consumed. Thus, the multiplexers 421 and 422 are turned on sequentially (one at a time), and the memory cell arrays 431 and 432 are programmed sequentially. In contrast, when the DATA bit status detector 410 determines that the number of bits of logic level 0 in the DATA signal DATA is less than or equal to 8, it indicates that the number of DATA bits to be written is less and less power needs to be consumed. Therefore, the multiplexers 421 and 422 can be turned on simultaneously, and the memory cell arrays 431 and 432 can be programmed simultaneously.

In the embodiment of the invention, the gates of the memory cells MC 10-MC 27 are coupled to the word line WL, and the memory cells to be programmed are selected for access according to the word line signal on the word line WL.

In summary, the present invention utilizes the data bit state detector in the form of an analog circuit to sense the bit states of the bits of the data signal by generating the first impedance according to the bit states of the bits of the data signal and comparing the first impedance with the reference impedance. Therefore, the complexity of circuit design can be effectively reduced, the area required by the circuit can be reduced, the cost required by a memory circuit can be reduced, and the product competitiveness can be enhanced.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, and various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.