阅读说明：本技术 存储器装置中的存取线晶粒调制 (Access line die modulation in memory devices ) 是由 D·R·埃科诺米 S·W·鲁塞尔 于 2019-08-09 设计创作，主要内容包括：本申请针对存储器装置中的存取线晶粒调制。可形成交叉点存储器阵列中的存储器单元堆叠。在一些实例中，所述存储器单元堆叠可包括存储元件。阻隔材料可形成在所述存储器单元堆叠上方。所述阻隔材料可初始地具有波状顶部表面。在某些情况下，可使所述阻隔材料的所述顶部表面平面化。在使所述阻隔材料的所述顶部表面平面化之后，可在所述阻隔材料的所述顶部表面上形成用于存取线的金属层。使所述阻隔材料的所述顶部表面平面化可能影响所述金属层的晶粒尺寸。在某些情况下，使所述阻隔材料的所述顶部表面平面化可减小由所述金属层形成的存取线的电阻率，且因此增加遍及所述存储器装置的电流递送。(The present application is directed to access line die modulation in a memory device. A stack of memory cells in a cross-point memory array may be formed. In some examples, the stack of memory cells can include storage elements. A barrier material can be formed over the memory cell stack. The barrier material may initially have a contoured top surface. In some cases, the top surface of the barrier material may be planarized. After planarizing the top surface of the barrier material, a metal layer for access lines can be formed on the top surface of the barrier material. Planarizing the top surface of the barrier material may affect the grain size of the metal layer. In some cases, planarizing the top surface of the barrier material can reduce the resistivity of access lines formed from the metal layer and thus increase current delivery throughout the memory device.)

1. A method, comprising:

forming a memory cell stack in a cross-point memory array, the memory cell stack comprising storage elements;

forming a barrier material over the memory cell stack;

planarizing a top surface of the barrier material; and

forming a metal layer for an access line of the cross-point memory array on the top surface of the barrier material.

2. The method of claim 1, wherein planarizing the top surface of the barrier material comprises:

applying a chemical-mechanical planarization CMP process to the top surface of the barrier material.

3. The method of claim 1, wherein forming the barrier material comprises:

the barrier material is deposited via a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, or any combination thereof.

4. The method of claim 1, wherein forming the memory cell stack comprises:

forming an electrode layer, wherein the electrode layer comprises carbon.

5. The method of claim 4, wherein forming the electrode layer comprises:

the electrode layer is deposited via a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, or any combination thereof.

6. The method of claim 4, further comprising:

removing at least a portion of the electrode layer.

7. The method of claim 6, wherein the metal layer contacts the top surface of the barrier material.

8. The method of claim 1, wherein forming the memory cell stack comprises:

depositing a dielectric material, wherein the dielectric material is interposed between the memory cell stack and a second memory cell stack.

9. The method of claim 8, further comprising:

removing a portion of the dielectric material and a portion of an electrode layer of the memory cell stack.

10. The method of claim 9, wherein:

the removal of the electrode layer occurs at a first rate; and

the removal of the dielectric material occurs at a second rate different from the first rate, wherein removing a portion of the dielectric material and a portion of the electrode layer forms an undulating surface under the barrier material.

11. The method of claim 1, wherein:

the barrier material comprises tungsten nitride, tungsten silicide or tungsten silicon nitride; and

the metal layer for the access lines comprises tungsten, tantalum or molybdenum.

12. An apparatus, comprising:

a memory cell stack in a cross-point memory array, the memory cell stack comprising a storage element;

a barrier material disposed over the memory cell stack, the barrier material comprising a planarized top surface; and

a metal layer for access lines contacting the planarized top surface of the barrier material.

13. The apparatus of claim 12, wherein the barrier material comprises a contoured bottom surface.

14. The apparatus of claim 12, wherein:

the barrier material has a first thickness in a first region over the memory cell stack; and

the barrier material has a second thickness in a second region, wherein the second region is interposed between the first region and a third region over a second memory cell stack.

15. The apparatus of claim 14, further comprising:

a dielectric material surrounding the memory cell stack, wherein the dielectric material has a top surface that contacts the barrier material, wherein the second region is over the dielectric material.

16. The apparatus of claim 14, wherein the second thickness is less than the first thickness.

17. The apparatus of claim 12, wherein:

the barrier material comprises tungsten nitride, tungsten silicide or tungsten silicon nitride; and

the metal layer comprises tungsten, tantalum or molybdenum.

18. The apparatus of claim 12, further comprising:

an electrode layer within the memory cell stack, wherein the electrode layer has a top surface that contacts a bottom surface of the barrier material, wherein an interface between the top surface of the electrode layer and the bottom surface of the barrier material is separated from the metal layer by different distances.

19. The apparatus of claim 18, wherein the electrode layer comprises carbon.

20. The apparatus of claim 12, wherein:

a center of the memory cell stack is separated from a center of an immediately adjacent memory cell stack by a cell pitch distance; and

the metal layer has an average grain size greater than twice the cell pitch distance.

21. A method, comprising:

forming a memory cell stack;

forming a barrier material having a top surface and a bottom surface over the memory cell stack;

reducing the top surface of the barrier material by polishing the top surface of the barrier material; and

forming a metal layer for access lines over the top surface of the barrier material.

22. The method of claim 21, further comprising:

etching a top surface of an electrode layer of the memory cell stack;

etching a top surface of a dielectric material interposed between the electrode layer and a second memory cell stack; and

forming an undulating surface based at least in part on etching the top surface of the electrode layer and etching the top surface of the dielectric material.

23. The method of claim 22, further comprising:

forming the barrier material on top of the undulating surface.

24. The method of claim 21, wherein forming the barrier material comprises:

forming an interface between an electrode layer of the memory cell stack and the bottom surface of the barrier material, wherein the interface has a wavy pattern.

25. The method of claim 21, wherein shrinking the top surface of the barrier material comprises:

changing the barrier material from having a uniform thickness to having a varying thickness by applying a chemical-mechanical planarization (CMP) process to the top surface of the barrier material.

Technical Field

Background

The following generally relates to the fabrication of memory cell stacks in cross-point memory arrays, and more particularly to methods for access line die modulation in memory devices.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, binary devices have two states, typically represented as a logical "1" or a logical "0". In other systems, more than two states may be stored. To access the stored information, components of the electronic device may read or sense states stored in the memory device. To store information, components of the electronic device may write or program states in the memory device.

There are various types of memory devices including a magnetic hard disk, a Random Access Memory (RAM), a Read Only Memory (ROM), a Dynamic RAM (DRAM), a Synchronous Dynamic RAM (SDRAM), a ferroelectric RAM (FeRAM), a Magnetic RAM (MRAM), a Resistive RAM (RRAM), a flash memory, a Phase Change Memory (PCM), and the like. The memory device may be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for long periods of time, even when no external power source is present. Volatile memory devices (e.g., DRAMs) may lose their stored state over time unless periodically refreshed by an external power source. FeRAM may use a similar device architecture as volatile memory, but may have non-volatile characteristics due to the use of ferroelectric capacitors as storage devices. Thus, FeRAM devices may have improved performance compared to other non-volatile and volatile memory devices.

In some memory devices, the electrical characteristics of the memory device (e.g., the resistivity of the access lines) may depend, at least in part, on the configuration of one or more components of the memory device. A solution for improving the topography of (e.g., reducing variations in) a memory device may be needed.

Disclosure of Invention

A method is described. The method may include: forming a memory cell stack in a cross-point memory array, the memory cell stack comprising storage elements; forming a barrier material over the memory cell stack; planarizing a top surface of the barrier material; and forming a metal layer for an access line of a cross-point memory array on a top surface of the barrier material.

An apparatus is described. The apparatus may include: a memory cell stack in a cross-point memory array, the memory cell stack comprising a storage element; a barrier material disposed over the memory cell stack, the barrier material comprising a planarized top surface; and a metal layer for the access lines contacting the planarized top surface of the barrier material.

Another method is described. The method may include: forming a memory cell stack; forming a barrier material having a top surface and a bottom surface over the memory cell stack; reducing a top surface of the barrier material by polishing the top surface of the barrier material; and forming a metal layer for the access lines over a top surface of the barrier material.

Drawings

Fig. 1A and 1B illustrate an example of a manufacturing technique according to an embodiment of the present disclosure.

Fig. 2A and 2B illustrate an example of a fabrication technique according to an embodiment of the present disclosure.

Fig. 3A and 3B illustrate an example of a fabrication technique according to an embodiment of the present disclosure.

Fig. 4 illustrates an example of a manufacturing technique according to an embodiment of the present disclosure.

FIG. 5 illustrates an example memory array supporting access line die modulation in a memory device according to an example of the present disclosure.

Fig. 6 and 7 illustrate one or more methods for access line die modulation in a memory device, according to embodiments of the present disclosure.

Detailed Description

Some memory devices may be formed, at least in part, by forming a stack of various materials (e.g., a stack of materials may be formed and additional processing steps may be applied to the stack). In some cases, the different layers of the stack may be formed sequentially, and thus formation of the stack may involve forming additional layers on top of the first layer of the stack. The structure of the top surface of the first layer (e.g., topography of the top surface) may create additional layers having similar structures (e.g., topography). For example, if additional layers of the stack are formed to contact a non-planar (e.g., wavy) top surface of the first layer, the non-planar or wavy pattern of the first layer may propagate upward to the additional layers, resulting in a non-planar or wavy top surface in the additional layers as well.

The contoured top surface may affect the characteristics of an assembly that includes one or both layers over or on top of the contoured top surface of the additional layer and/or an assembly that includes other layers over or on top of the contoured top surface of the additional layer. For example, the properties of the material in a given layer or overall memory device (e.g., resistivity associated with components of the memory device, current delivery, or both) may depend on (e.g., be affected by) the presence of the undulating top surface of additional layers. Thus, minimizing the ripple of one or more layers may improve the performance of the memory device for a particular implementation.

According to the teachings herein, fabricating a memory cell may include planarizing (e.g., polishing or otherwise smoothing) one layer, then forming the next layer. For example, the barrier material may be fabricated using techniques that initially produce a contoured top surface of the barrier material (e.g., a top surface that is contoured or otherwise non-uniform in thickness or topography). In some cases, the barrier material may be planarized prior to forming a metal layer over the barrier material. Planarizing the barrier material prior to forming the metal layer may result in the resulting metal layer lacking corrugations or at least having reduced corrugations (relative to corrugations that may already be present in the metal layer that would have been formed without an intermediate planarization step of the barrier material). Thus, the metal layer may have more predictable and uniform characteristics or other more desirable characteristics.

For example, the grain size of the metal layer may increase, resulting in a decrease in resistivity in the access lines formed by the metal layer and an increase in current delivery throughout the memory device. Increasing the grain size of the metal layer by planarizing the top surface of the barrier material can also reduce the complexity of memory device formation (e.g., the complexity of the etching step is reduced due to the reduced amount of metal used to form the access lines). These and other fabrication techniques described herein may thus improve the characteristics and performance of memory cells, and have other benefits as can be appreciated by one of ordinary skill in the art.

The features of the present disclosure introduced above are further described below in the context of the example fabrication technique of fig. 1-4. These and other features of the present disclosure are further illustrated and described with reference to the example memory array of fig. 5 and the flowcharts of fig. 6 and 7 relating to the fabrication of memory cells.

Various techniques may be used to form the materials or components shown below in fig. 1-5. These techniques may include, for example, Chemical Vapor Deposition (CVD), metal-organic vapor deposition (MOCVD), Physical Vapor Deposition (PVD), sputter deposition, Atomic Layer Deposition (ALD), or Molecular Beam Epitaxy (MBE), among other thin film growth techniques. Materials may be removed using a number of techniques, which may include, for example, chemical etching (also referred to as "wet etching"), plasma etching (also referred to as "dry etching"), or chemical-mechanical planarization (CMP).

Fig. 1A and 1B are schematic drawings of an intermediate memory array structure illustrating methods of fabricating a memory cell stack at various stages of fabrication.

Referring to FIG. 1A, according to some examples, an intermediate array structure 100-a may include aspects of cell stacks that are to be processed to ultimately form a first memory cell stack 105-a, a second memory cell stack 105-b, and a third memory cell stack 105-c, as described in further detail below. In some cases, the region including the first memory cell stack 105-a, the second memory cell stack 105-b, and the third memory cell stack 105-c may be ultimately configured (e.g., fabricated) to include three distinct memory cells (e.g., storage components within the memory cell stack 105). Thus, the data stored in the first memory cell may be independent of the data stored in the second and third memory cells, the data stored in the second memory cell may be independent of the data stored in the first and third memory cells, and the data stored in the third memory cell may be independent of the data stored in the first and second memory cells.

Although three memory cell stacks 105-a, 105-b, and 105-c are shown, one of ordinary skill will appreciate that in practice any number of memory cell stacks 105 may be formed. In some cases, fabricating memory cell stack 105 may include forming metal layer 110 over a substrate (not shown). Metal layer 110 may be used to form one or more access lines, such as word lines or bit lines for memory cells included in memory cell stack 105.

In some cases, fabricating memory cell stack 105 may include forming first electrode material 115 over metal layer 110. The first electrode material 115 may be used to form one or more bottom electrode assemblies, such as bottom electrodes corresponding to memory cell stacks 105-a, 105-b, and 105-c, respectively.

The method may include forming a selector material 120 over the first electrode material 115. Selector material 120 may be used to form one or more selection elements, such as selector elements corresponding to memory cell stacks 105-a, 105-b, and 105-c, respectively. In some cases, selector material 120 may comprise a chalcogenide material.

The method may include forming a second electrode material 125 over the selector material 120. The second electrode material 125 may be used to form one or more intermediate electrode assemblies, such as intermediate electrodes corresponding to memory cell stacks 105-a, 105-b, and 105-c, respectively.

The method can include forming a storage material 130 over the second electrode material 125. Storage material 130 may be used to form one or more storage elements, such as storage elements corresponding to memory cell stacks 105-a, 105-b, and 105-c, respectively. In some cases, memory material 130 may comprise a chalcogenide material. Memory material 130 may be the same as or different from selector material 120. Also, although the example of intermediate array structure 100-a shows memory material 130 over selector material 120, the locations of memory material 130 and selector material 120 may be reversed in some examples. Furthermore, in some examples, memory cell stack 105 and the corresponding memory cell stack may lack separate selector material 120 and second electrode material 125, and storage material 130 may be self-selected.

The method can include forming a third electrode material 135 over the storage material 130. The third electrode material 135 may be used to form one or more top electrode assemblies, such as top electrodes corresponding to memory cell stacks 105-a, 105-b, and 105-c, respectively.

The electrode materials 115, 125, and 135 may each include carbon. In some cases, one or more of electrode materials 115, 125, and 135 may be comprised of two sub-layers (not shown), and thus the electrodes formed therefrom may be referred to as bi-layer electrodes. In this case, at least one sub-layer may include carbon, and may be referred to as a carbon-based material. Electrode materials 115, 125, and 135 can be formed, for example, by deposition techniques such as PVD, CVD, or ALD, among other deposition techniques.

Each layer of the intermediate array structure 100-a may be initially formed as a blanket layer over a surface area of an entire die or substrate (e.g., a wafer).

Referring now to the middle array structure 100-B of FIG. 1B, isolation regions 140-a and 140-B may be formed between the memory cell stacks 105-a and 105-B and/or 105-B and 105-c in order to separate and isolate the memory cell stacks 105 from each other. Isolation regions 140-a and 140-b may be formed using various etching or other removal techniques that may use a photomask and photolithography to define features as desired.

Fig. 1B shows a cross-section of an intermediate array structure 100-B in one plane (e.g., the x-z plane), and thus the isolation regions 140-a and 140-B are shown in one dimension (e.g., the x-dimension) as separating the memory cell stacks 105-a, 105-B, and 105-c, but one of ordinary skill in the art will appreciate that similar techniques may be applied in another plane (e.g., the y-z plane) in order to separate the memory cell stacks 105-a, 105-B, and 105-c and corresponding memory cell stacks in another dimension (e.g., the y-dimension) such that the memory cell stacks corresponding to the memory cell stacks 105-a, 105-B, and 105-c may each include pillars. Furthermore, one of ordinary skill in the art will appreciate that in some cases, the isolation regions presented in fig. 1B as separate isolation regions 140-a and 140-B may be combined in different planes, and thus may include one continuous isolation region 140 in some alternatives.

Fig. 2A and 2B are schematic depictions of additional intermediate memory array structures illustrating methods of fabricating a memory cell stack.

Fabricating the middle array structure 200-a of fig. 2A may include depositing a dielectric material 205. For example, the isolation regions 140-a and 140-b may be filled with a dielectric material 205. Thus, the dielectric material 205 may be deposited and interposed between individual memory cell stacks. In this case, the dielectric material 205 may surround one or more memory cell stacks 105.

Fabricating the intermediate array structure 200-B of fig. 2B may include forming a contoured surface 210. In some examples, the undulating surface 210 may be referred to as a "wrap" configuration and is formed over the third electrode material 135 and the dielectric material 205. For example, the wavy surface 210 may extend across at least some, if not all, of the memory cell stacks 105-a, 105-b, and 105-c and the isolation regions 140-a and 140-b. A wrap topography that may be replicated in one or more layers above the contoured surface 210 may, in certain cases, improve structural stability of the memory cell stack 105 and other aspects of the memory array.

In some cases, the contoured surface 210 may be formed by polishing or etching the top surface of the third electrode material 135 and the top surface of the dielectric material 205. In some examples, polishing or etching the top surface of third electrode material 135 and the top surface of dielectric material 205 may remove third electrode material 135 and dielectric material 205 at different rates. For example, the dielectric material 205 may be removed at a greater (faster) rate than the third electrode material 135, which may result in a contoured surface 210. Thus, in some examples, the contoured surface 210 may be formed by removing the third electrode material 135 at a first rate and/or removing the dielectric material 205 at a second rate different from the first rate.

In some examples, the contoured surface 210 may be formed by applying a CMP process to the top surface of the third electrode material 135 and the dielectric material 205. In some cases, polishing the top surface of the third electrode material 135 may include breaking a vacuum seal associated with the deposition process. In this case, the third electrode material 135 may become comprised of oxidized carbon, as polishing the intermediate array structure 200-b outside of the vacuum environment may expose the top of the third electrode material 135 and the dielectric material 205 to oxygen, and/or the polishing process itself may introduce oxidation. In some other cases, fabricating the memory cell stack may not include polishing of third electrode material 135 and dielectric material 205, and third electrode material 135 may not include oxidized carbon.

Figures 3A and 3B are schematic depictions of additional intermediate memory array structures illustrating a method of fabricating a memory cell stack with a barrier material 305. In some cases, barrier material 305 may be formed over third electrode material 135 and dielectric material 205 of intermediate array structure 300-a.

The middle array structure 300-a of figure 3A shows the deposition of the barrier material 305 over the upper surface of the third electrode material 135 and over the upper surface of the dielectric material 205-that is, the deposition of the barrier material 305 over the undulating surface 210 described with reference to figure 2B. In some cases, barrier material 305 may be in direct contact with third electrode material 135 and dielectric material 205. Various techniques may be used to deposit the barrier material 305. These may include, but are not limited to, PVD, CVD, MOCVD, sputter deposition, ALD, or MBE, among other thin film growth techniques. In some cases, the barrier material 305 may include a metal nitride such as tungsten nitride (WN), a metal silicide such as tungsten silicide (WSix), or a metal nitride such as tungsten silicon nitride (WSiN). In some examples, the barrier material 305 may be an example of a thermal barrier between the carbon of the third electrode material 135 and a layer (e.g., a metal layer as discussed in more detail below) deposited on top of the barrier material 305.

When initially formed, the barrier material 305 may include a contoured top surface 310. For example, the barrier material 305 may be deposited on top of the contoured surface 210. In some examples, when initially formed, the barrier material 305 can include a uniform thickness within the memory cell stacks 105-a, 105-b, and 105-c and the isolation regions 140-a and 140-b, and thus can include a top surface 310 having a wave pattern similar to a bottom wave surface (e.g., wave surface 210) of the barrier material 305.

Although not shown for clarity and ease of illustration, it should be understood that in some cases the illustrated array structure may also include a liner material deposited under the barrier material 305. For example, a liner material may be interposed between the bottom surface of the barrier material 305 and the top surface of the third electrode material 135 and the top surface of the dielectric material 205 (e.g., between the bottom surface of the barrier material 305 and the corrugated surface 210).

As shown in the middle array structure 300-B of fig. 3B, in some examples, the top surface 310 of the barrier material 305 may be planarized or otherwise smoothed. The top surface 310 of the barrier material 305 may be planarized using various techniques. These techniques may include, but are not limited to, chemical etching, plasma etching, or polishing (e.g., CMP).

In some examples, treating top surface 310 may change barrier material 305 from having a uniform thickness to having a varying thickness. For example, the thickness (e.g., the second thickness) of the barrier material 305 disposed in a region (e.g., a second region or a second type of region) above (e.g., overlapping) the memory cell stack 105-a may be less than the thickness (e.g., the first thickness) of the barrier material 305 disposed in a region (e.g., a first region) above (e.g., overlapping) the isolation region 140-a. In some examples, the thickness of the barrier material 305 does not affect the performance of the memory device as long as the interface corresponding to the contoured surface 210 is maintained. For example, the lack of thickness requirements or constraints may allow flexibility in the planarization process, as discussed with reference to fig. 3B.

Fig. 4 may be a schematic drawing of an additional intermediate memory array structure 400 illustrating a method of fabricating a memory cell stack with a metal layer 405. In some cases, the metal layer 405 may be formed over the barrier material 305 of the middle array structure 400. In some cases, the metal layer 405 may be in direct contact with the top surface 310 of the barrier material 305 (which may have been planarized or otherwise smoothed as described herein).

The middle array structure 400 of figure 4 shows a metal layer 405 deposited on the top surface 310 of the barrier material 305. Various techniques may be used to deposit the metal layer 405. These techniques may include, but are not limited to, PVD, CVD, MOCVD, sputter deposition, ALD, or MBE, among other thin film growth techniques. In some cases, metal layer 405 may be an instance of an access line (e.g., a word line, a bit line, etc.). For example, the metal layer 405 may comprise a refractory metal such as tungsten, tantalum, or molybdenum. In some cases, the barrier material 305 (e.g., comprising WN, WSix, or WSiN) may provide a reset current benefit or other benefit when deposited between the third electrode material 135 (e.g., comprising carbon) and the metal layer 405 (e.g., comprising tungsten, tantalum, or molybdenum).

In some cases, memory cell stack 105-a can include center point 410-a, and stack 105-b can include center point 410-b. Center point 410-a and center point 410-b may be examples of the center of a stack of memory cells. Distance 415 may be an example of the distance between center point 410-a and center point 410-b. For example, distance 415 may be an example of a cell pitch distance.

In some cases, where the metal layer 405 is not planarized or otherwise smoothed, the metal layer 405 may have an average grain size that substantially corresponds to (e.g., is substantially equal to) the distance 415. For example, where the metal layer 405 is not planarized or otherwise smoothed, the average grain size of the metal layer 405 may generally correspond to the topography of the contoured surface 210, which in turn may generally correspond to the distance 415 of the contoured surface 210.

However, where the top surface 310 of the barrier material 305 is planarized or otherwise smoothed as described herein, the metal layer 405 may have an average grain size that is greater than the distance 415 (e.g., greater than twice the distance 415). For example, where the top surface 310 of the barrier material 305 is planarized or otherwise smoothed as described herein, the grain size of the metal layer 405 may be close to or substantially equal to the grain size observed for blanket film deposition of the metal material included in the metal layer 405 (e.g., approximately 250nm, or in some cases 300nm or 350nm, where the metal layer 405 comprises tungsten, tantalum, or molybdenum). In some cases, increasing the average grain size in the metal layer 405 may result in a decrease in resistance of access lines in the memory device, an increase in current delivery, and an opportunity to reduce the thickness of the metal layer 405. In some cases, planarizing the top surface 310 of the barrier material 305 may reduce the etch complexity of the memory device (e.g., because the metal layer 405 may be formed using a reduced amount of metal) and increase the structural yield of the memory device.

Although not shown for clarity and ease of illustration, it should be understood that the illustrated array structure may be formed above or below other layers (e.g., above the substrate), which may include, among other things, various peripheral and support circuitry. For example, Complementary Metal Oxide Semiconductor (CMOS) transistors may be incorporated into column and row driver circuitry and sense amplifier circuitry, as well as sockets and wiring that connect such circuitry to the memory array via the columns and rows described above. Further, other layers may include one or more memory arrays, or "stacks" (deck) of arrays-the structure shown in the examples of fig. 1-4 may correspond to one stack of a memory array, and may be above or below any number of additional stacks of memory arrays.

Although not shown for clarity and ease of illustration, it should be understood that the illustrated array structure may also include conformal liners deposited adjacent to the dielectric material 205 (e.g., contacting the dielectric material 205). For example, a conformal liner may be interposed between a side surface of the dielectric material 205 and a side surface of the memory cell stack.

Fig. 5 illustrates an example memory array 500 that supports access line die modulation in a memory device according to various examples of the present disclosure. The memory array 500 may also be referred to as an electronic memory device. The memory array 500 includes a stack of memory cells 505 that are programmable to store different states. Each memory cell stack 505 may include one or more memory cells. In some cases, memory cell stack 505 may be programmable to store one of two states, denoted as a logic "0" and a logic "1". In some cases, memory cell stack 505 may be configured to store one of more than two logic states. Memory cell stack 505 may be an example of memory cell stack 105 as described with reference to fig. 1-4.

The memory array 500 may be a three-dimensional (3D) memory array, where two-dimensional (2D) memory arrays are formed on top of each other. This may increase the number of memory cells that may be formed on a single die or substrate as compared to a 2D array, which in turn may reduce production costs or improve performance of the memory array, or both. According to the example depicted in fig. 5, memory array 500 includes two levels of memory cell stacks 505, and thus can be considered a three-dimensional memory array; however, the number of levels is not limited to two. Each level may be aligned or positioned such that the stacks 505 of memory cells may be approximately aligned with each other across each level.

Each row of memory cell stacks 505 is connected to an access line 510 and an access line 515. Access lines 510 and 515 may be instances of or formed from corresponding metal layers 110 or 405, as described with reference to fig. 1-4. Access lines 510 and 415 may also be referred to as word lines 510 and bit lines 515, respectively. The bit lines 515 may also be referred to as digit lines 515. References to word lines and bit lines or the like may be interchanged without preventing understanding or operation.

The word lines 510 and bit lines 515 may be substantially perpendicular to each other to create an array. Two memory cell stacks 505 may share a common conductive line, such as digit line 515. That is, the digit line 515 can be in electronic communication with a bottom electrode of the upper memory cell stack 505 and a top electrode of the lower memory cell stack 505. Accordingly, in certain cases, a single access line 510, 515 may serve as a word line 510 for a first group of one or more memory cell stacks 505 (e.g., a group of one or more memory cell stacks 505 below the access line 510, 515) and may serve as a bit line 515 for a second group of one or more memory cell stacks 505 (e.g., a group of one or more memory cell stacks 505 above the access line 510, 515). Other configurations may be possible; (ii) a For example, memory cell stack 505 can include an asymmetric electrode interface with a memory storage element. In some examples, the grain size of access lines 510 and 515 may be increased by planarizing the top surface of the barrier material within memory cell stack 505, as described herein, including with reference to fig. 1-4.

In general, one stack of memory cells 505 can be located at the intersection of two conductive lines, such as word line 510 and digit line 515. This crossing may be referred to as an address of the memory cell. Target memory cell stack 505 can be a memory cell stack 505 located at the intersection of the activated word line 510 and digit line 515; that is, word line 510 and digit line 515 may be activated in order to read or write the memory cells contained in memory cell stack 505 at their intersections. Other memory cell stacks 505 in electronic communication with (e.g., connected to) the same word line 510 or digit line 515 may be referred to as non-target memory cell stacks 505.

As discussed above, electrodes (e.g., third electrode material 135 and first electrode material 115) may be coupled to memory cell stack 505 and word line 510 or digit line 515, respectively. The term electrode may refer to an electrical conductor, and in some cases may serve as an electrical contact to the memory cell stack 505. The electrodes may include traces, wires, conductive lines, conductive layers, etc., that provide conductive paths between elements or components of the memory array 500.

Operations such as reading and writing, which may include applying voltages or currents to the respective lines, may be performed on the memory cell stack 505 by activating or selecting the word line 510 and digit line 515. The word lines 510 and bit lines 515 may be made of a conductive material such as a metal (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti), etc.), a metal alloy, carbon, a conductively-doped semiconductor, or other conductive material, alloy, or compound.

Access to the stack of memory cells 505 may be controlled via a row decoder 520 and a column decoder 530. For example, the row decoder 520 may receive a row address from the memory controller 540 and activate the appropriate word line 510 based on the received row address. Similarly, a column decoder 530 receives a column address from the memory controller 540 and activates the appropriate digit lines 515. Thus, by activating wordline 510 and wordline 515, memory cell stack 505 can be accessed.

After access, the memory cell stack 505 may be read or sensed by the sensing component 525. For example, the sensing component 525 may be configured to determine a stored logic state of the stack of memory cells 505 based on a signal generated by accessing the stack of memory cells 505. The signal may comprise a voltage or a current, and the sensing component 525 may comprise a voltage sense amplifier, a current sense amplifier, or both. For example, a voltage may be applied to the memory cell stack 505 (using the corresponding word line 510 and digit line 515), and the magnitude of the resulting current may depend on the resistance of the memory cell stack 505, which may reflect the logic state stored by the memory cell stack 505. Likewise, a current can be applied to the memory cell stack 505, and the magnitude of the voltage used to create the current can depend on the resistance of the memory cell stack 505, which can reflect the logic state stored by the memory cell stack 505. The sensing component 525 may include various transistors or amplifiers in order to detect and amplify the signal, which may be referred to as latching. The detected logic state of memory cell stack 505 may then be output as output 535. In some cases, the sensing component 525 may be part of the column decoder 530 or the row decoder 520. Alternatively, the sensing element 525 may be connected to or in electronic communication with a column decoder 530 or a row decoder 520.

The memory controller 540 may control the operation (reading, writing, rewriting, refreshing, discharging, etc.) of the memory cell stack 505 via various components such as the row decoder 520, the column decoder 530, and the sensing component 525. In some cases, one or more of row decoder 520, column decoder 530, and sensing component 525 may be co-located with memory controller 540. The memory controller 540 may generate row and column address signals in order to activate the desired wordline 510 and the wordline 515. The memory controller 540 may also generate and control voltages or currents used during operation of the memory array 500. For example, it may apply a discharge voltage to the word line 510 or the digit line 515 after accessing one or more memory cell stacks 505.

In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may be adjusted or varied, and may be different for the various operations discussed in the process of operating the memory array 500. Further, one, more, or all of the memory cell stacks 505 within the memory array 500 may be accessed simultaneously; for example, multiple or all cells of the memory array 100 may be accessed simultaneously during a reset operation in which all of the stacks of memory cells 505 or groups of the stacks of memory cells 505 are set to a single logic state.

FIG. 6 shows a flow diagram illustrating a method 600 for access line die modulation in a memory device, according to an embodiment of the present disclosure. The operations of method 600 may be implemented in accordance with various manufacturing techniques as described herein. For example, the operations of the method 600 may be implemented by fabrication techniques as discussed with reference to fig. 1-5.

At 605, a stack of memory cells in a cross-point memory array can be formed. The memory cell stack may include a storage element. The operations of 605 may be performed in accordance with the methods described herein. In certain examples, aspects of the operations of 605 may be performed using the fabrication techniques discussed with reference to fig. 1-5.

At 610, a barrier material can be formed over the memory cell stack. The operations of 610 may be performed according to the methods described herein. In certain examples, aspects of the operations of 610 may be performed using the fabrication techniques discussed with reference to fig. 1-5.

At 615, a top surface of the barrier material may be planarized. The operations of 615 may be performed in accordance with the methods described herein. In certain examples, aspects of the operations of 615 may be performed using the fabrication techniques discussed with reference to fig. 1-5.

At 620, a metal layer for an access line of a cross-point memory array may be formed. In some cases, a metal layer may be formed on the top surface of the barrier material after planarization. In certain examples, aspects of the operations of 620 may be performed using the fabrication techniques discussed with reference to fig. 1-5.

In some examples, an apparatus may perform aspects of the manufacturing described above using general or special purpose hardware. An apparatus may include features, means, or instructions for forming a stack of memory cells in a cross-point memory array, the stack of memory cells including a storage element. The apparatus may further include features, means, or instructions for forming a barrier material over the memory cell stack. The apparatus may also include features, means, or instructions for planarizing the top surface of the barrier material. The apparatus may additionally include features, means, or instructions for forming a metal layer for access lines of a cross-point memory array on a top surface of the barrier material.

In some examples of the methods and apparatus described above, planarizing the top surface of the barrier material may include applying a CMP process to the top surface of the barrier material. In some examples of methods and apparatus, forming a barrier material may include depositing the barrier material via a PVD process, a CVD process, an ALD process, or any combination thereof. In some cases, forming the memory cell stack can include forming an electrode layer, wherein the electrode layer includes carbon. In certain cases, forming the electrode layer may include depositing the electrode layer via a PVD process, a CVD process, an ALD process, or any combination thereof.

Some examples of the above-described methods and apparatus may further include processes, features, means, or instructions for removing at least a portion of the electrode layer. In some examples of the methods and apparatus described above, the metal layer contacts a top surface of the barrier material. In some cases, forming the memory cell stack can include depositing a dielectric material, wherein the dielectric material is interposed between the memory cell stack and the second memory cell stack. Some examples of the above-described methods and apparatus may further include processes, features, means, or instructions for removing a portion of the dielectric material and a portion of the electrode layer of the memory cell stack.

In some examples of the methods and apparatus described above, the removing of the electrode layer occurs at a first rate, and the removing of the dielectric material occurs at a second rate different from the first rate, wherein removing a portion of the dielectric material and a portion of the electrode layer forms an undulating surface under the barrier material. In some examples of the methods and apparatus described above, the barrier material comprises WN, WSix, or WSiN, and the metal layer for the access lines comprises tungsten, tantalum, or molybdenum.

FIG. 7 shows a flow diagram illustrating a method 700 for access line die modulation in a memory device, according to an embodiment of the present disclosure. The operations of method 700 are performed in accordance with various manufacturing techniques as described herein. For example, the operations of method 700 may be implemented by fabrication techniques as discussed with reference to fig. 1-5.

At 705, a memory cell stack can be formed. The operations of 705 may be performed in accordance with the methods described herein. In certain examples, aspects of the operations of 705 may be performed using the fabrication techniques discussed with reference to fig. 1-5.

At 710, a barrier material having a top surface and a bottom surface over the memory cell stack can be formed. The operations of 710 may be performed according to methods described herein. In certain examples, aspects of the operations of 710 may be performed using the fabrication techniques discussed with reference to fig. 1-5.

At 715, the top surface of the barrier material may be reduced by polishing the top surface of the barrier material. The operations of 715 may be performed in accordance with methods described herein. In certain examples, aspects of the operations of 715 may be performed using the fabrication techniques discussed with reference to fig. 1-5.

At 720, a metal layer for the access lines can be formed over a top surface of the barrier material. The operations of 720 may be performed according to methods described herein. In certain examples, aspects of the operations of 720 may be performed using the fabrication techniques discussed with reference to fig. 1-5.

In some examples, an apparatus may perform the described aspects of manufacturing using general or special purpose hardware. An apparatus may include features, means, or instructions for forming a stack of memory cells. The apparatus may additionally include features, means, or instructions for forming a barrier material having a top surface and a bottom surface over the memory cell stack. The apparatus may further comprise features, means, or instructions for reducing the top surface of the barrier material by polishing the top surface of the barrier material. The apparatus may further include features, means, or instructions for forming a metal layer for the access lines over a top surface of the barrier material.

Some examples of the above-described methods and apparatus may further include processes, features, means, or instructions for etching a top surface of an electrode layer of a memory cell stack. Some examples of the above-described methods and apparatus may further include processes, features, means, or instructions for etching a top surface of a dielectric material interposed between the electrode layer and the second memory cell stack. Some examples of the above-described methods and apparatus may further include processes, features, means, or instructions for forming a contoured surface based at least in part on etching the top surface of the electrode layer and etching the top surface of the dielectric material.

Some examples of the above-described methods and apparatus may further include processes, features, means, or instructions for forming a barrier material on top of the contoured surface. In some examples of the methods and apparatus described above, forming the barrier material may include forming an interface between an electrode layer of the memory cell stack and a bottom surface of the barrier material, wherein the interface has a wavy pattern. In some examples of methods and apparatus, shrinking the top surface of the barrier material may include changing the barrier material from having a uniform thickness to having a varying thickness by applying a CMP process to the top surface of the barrier material.

It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and that other implementations are possible. Furthermore, two or more embodiments from the described methods may be combined.

In certain instances, a device, system, or apparatus manufactured in accordance with various manufacturing techniques as described herein may include: a memory cell stack in a cross-point memory array, the memory cell stack comprising a storage element; a barrier material disposed over the memory cell stack, the barrier material comprising a planarized top surface; and a metal layer for the access lines contacting the planarized top surface of the barrier material.

In some examples of the devices, systems, or apparatuses described above, the barrier material can include a contoured bottom surface. In some cases, the barrier material can have a first thickness in a first region over the stack of memory cells, and the barrier material can have a second thickness in a second region, wherein the second region is interposed between the first region and a third region over the second stack of memory cells.

In some examples, the device, system, or apparatus may further include a dielectric material surrounding the memory cell stack, wherein the dielectric material has a top surface that contacts the barrier material, wherein the second region is above the dielectric material. In certain cases of the apparatus, systems, or devices described above, the second thickness may be less than the first thickness.

In some examples, the barrier material may comprise a metal nitride such as WN, a metal silicide such as WSix, or a metal silicon nitride such as WSiN, and the metal layer may comprise a refractory metal such as tungsten, tantalum, or molybdenum. The device, system, or apparatus may also include an electrode layer within the memory cell stack, wherein the electrode layer has a top surface that contacts the bottom surface of the barrier material, wherein an interface between the top surface of the electrode layer and the bottom surface of the barrier material is separated from the metal layer by different distances. In some other examples, the electrode layer may include carbon.

In some examples, the center of a memory cell stack may be separated from the center of an immediately adjacent memory cell stack by a cell pitch distance. In some cases, the metal layer may have an average grain size greater than twice the cell pitch distance.

The term "layer" as used herein refers to a layer or sheet of geometric structure. Each layer may have three dimensions (e.g., height, width, and depth) and may cover some or all of the surface. For example, a layer may be a three-dimensional structure, where two dimensions are greater than the third dimension, such as a thin film. A layer may comprise different elements, components and/or materials. In some cases, a layer may be composed of two or more sub-layers. In some of the figures, two dimensions of a three-dimensional layer are depicted for illustrative purposes. However, one skilled in the art will recognize that the layers are three-dimensional in nature.

As used herein, the term "electrode" may refer to an electrical conductor, and in some cases, may serve as an electrical contact to a memory cell or other component of a memory array. The electrodes may include traces, wires, conductive lines, conductive layers, etc., that provide conductive paths between elements or components of the memory array.

The chalcogenide material may be a material or alloy comprising at least one of elements S, Se and Te. The phase change materials discussed herein may be chalcogenide materials. The chalcogenide material may include alloys of S, Se, Te, Ge, As, Al, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), or platinum (Pt). Example chalcogenide materials and alloys can include, but are not limited to, Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi-Se, Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd or Ge-Te-Sn-Pt. Hyphenated chemical composition notation, as used herein, indicates the elements included in a particular compound or alloy, and is intended to refer to all stoichiometric quantities related to the indicated elements. For example, Ge-Te may include Ge_xTe_yWhere x and y can be any positive integer. Other examples of variable resistance materials may include binary metal oxide materials or mixed oxides, including two or more metals, such as transition metals, alkaline earth metals, and/or rare earth metals. Embodiments are not limited to the particular variable resistance material or materials associated with the storage elements of the memory cells. For example, other examples of variable resistance materials may be used to form memory elements, and may include chalcogenide materials, colossal magnetoresistive materials, or polymer-based materials, among others.

The devices discussed herein may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as a silicon-on-glass (SOG) or silicon-on-Sapphire (SOP) substrate, or an epitaxial layer of a semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate may be controlled by doping using various chemistries including, but not limited to, phosphorous, boron, or arsenic. The doping may be performed during the initial formation or growth of the substrate, by ion implantation or by any other doping means.

Example configurations are described herein in connection with the implementations set forth in the figures and are not intended to represent all examples that may be implemented or within the scope of the claims. The detailed description contains specific details for the purpose of providing an understanding of the described technology. However, the techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

In the drawings, similar components or features may have the same reference numerals. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

As used herein, including in the claims, "or" as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B or C, for example, means a or B or C, or AB or AC or BC, or ABC (i.e., a and B and C). Also, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, exemplary steps described as "based on condition a" may be based on both condition a and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on".

The description herein is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.