Thin film transistor substrate and display device
阅读说明:本技术 薄膜晶体管基板和显示装置 (Thin film transistor substrate and display device ) 是由 朴世熙 赵寅晫 金大焕 白朱爀 卢智龙 于 2019-08-12 设计创作,主要内容包括:公开了一种薄膜晶体管基板和显示装置,包括能够防止漏电流的薄膜晶体管。该薄膜晶体管基板包括:基板、在基板上的第一缓冲层、在第一缓冲层上的第二缓冲层、在第二缓冲层上的半导体层、以及与半导体层分隔开的栅极电极,栅极电极的至少一部分与半导体层交叠,其中第一缓冲层的表面氧浓度高于第二缓冲层的表面氧浓度。(A thin film transistor substrate and a display device including a thin film transistor capable of preventing a leakage current are disclosed. The thin film transistor substrate includes: the semiconductor device includes a substrate, a first buffer layer on the substrate, a second buffer layer on the first buffer layer, a semiconductor layer on the second buffer layer, and a gate electrode spaced apart from the semiconductor layer, at least a portion of the gate electrode overlapping the semiconductor layer, wherein a surface oxygen concentration of the first buffer layer is higher than a surface oxygen concentration of the second buffer layer.)
1. A thin film transistor substrate comprising:
a substrate;
a first buffer layer on the substrate;
a second buffer layer on the first buffer layer;
a semiconductor layer on the second buffer layer; and
a gate electrode spaced apart from the semiconductor layer, at least a portion of the gate electrode overlapping the semiconductor layer,
wherein a surface oxygen concentration of the first buffer layer is higher than a surface oxygen concentration of the second buffer layer.
2. The thin film transistor substrate of claim 1, wherein a dipole moment is formed between the first buffer layer and the second buffer layer.
3. The thin film transistor substrate of claim 1, wherein the first buffer layer comprises ionic bonds, the second buffer layer comprises covalent bonds, and
wherein the ionic bond comprises a metal.
4. The thin film transistor substrate of claim 1, wherein the semiconductor layer comprises an oxide semiconductor material.
5. The thin film transistor substrate according to claim 1, wherein the semiconductor layer comprises a first semiconductor layer on the buffer layer and a second semiconductor layer on the first semiconductor layer.
6. The thin film transistor substrate of claim 1, further comprising:
a first gate insulating film on the semiconductor layer; and
a second gate insulating film on the first gate insulating film,
wherein a surface oxygen concentration of the second gate insulating film is higher than a surface oxygen concentration of the first gate insulating film.
7. The thin film transistor substrate according to claim 6, wherein a dipole moment is formed between the first gate insulating film and the second gate insulating film.
8. The thin film transistor substrate according to claim 6, wherein the first gate insulating film includes a covalent bond, the second gate insulating film includes an ionic bond, and
wherein the ionic bond comprises a metal.
9. The thin film transistor substrate according to claim 1, further comprising a light-shielding layer between the substrate and the first buffer layer.
10. A thin film transistor substrate comprising:
a semiconductor layer on the substrate;
a first gate insulating film on the semiconductor layer;
a second gate insulating film on the first gate insulating film; and
a gate electrode on the second gate insulating film,
wherein a surface oxygen concentration of the second gate insulating film is higher than a surface oxygen concentration of the first gate insulating film.
11. The thin film transistor substrate of claim 10, wherein a dipole moment is formed between the first gate insulating film and the second gate insulating film.
12. A display device, comprising:
a substrate;
a shift register on the substrate; and
a pixel connected to the shift register, and a pixel,
wherein the shift register includes a stage connected to the pixels through a gate line,
wherein the stage comprises at least one thin film transistor,
wherein the thin film transistor includes:
a first buffer layer on the substrate;
a second buffer layer on the first buffer layer;
a semiconductor layer on the second buffer layer; and
a gate electrode spaced apart from the semiconductor layer, at least a portion of the gate electrode overlapping the semiconductor layer,
wherein a surface oxygen concentration of the first buffer layer is higher than a surface oxygen concentration of the second buffer layer.
13. The display device according to claim 12, wherein a dipole moment is formed between the first buffer layer and the second buffer layer.
14. The display device according to claim 12, wherein the first buffer layer comprises an ionic bond, the second buffer layer comprises a covalent bond, and
wherein the ionic bond comprises a metal.
15. The display device according to claim 12, wherein the semiconductor layer comprises an oxide semiconductor material.
16. The display device according to claim 12, wherein the thin film transistor further comprises:
a first gate insulating film on the semiconductor layer; and
a second gate insulating film on the first gate insulating film,
wherein a surface oxygen concentration of the second gate insulating film is higher than a surface oxygen concentration of the first gate insulating film.
17. The display device according to claim 16, wherein a dipole moment is formed between the first gate insulating film and the second gate insulating film.
18. A display device, comprising:
a substrate; and
a plurality of pixels on the substrate,
wherein the pixel includes:
a pixel driver on the substrate; and
a display element connected to the pixel driver,
wherein the pixel driver comprises at least one thin film transistor,
wherein the thin film transistor includes:
a first buffer layer on the substrate;
a second buffer layer on the first buffer layer;
a semiconductor layer on the second buffer layer; and
a gate electrode spaced apart from the semiconductor layer, at least a portion of the gate electrode overlapping the semiconductor layer,
wherein a surface oxygen concentration of the first buffer layer is higher than a surface oxygen concentration of the second buffer layer.
19. The display device according to claim 18, wherein a dipole moment is formed between the first buffer layer and the second buffer layer.
20. The display device according to claim 18, wherein the thin film transistor further comprises:
a first gate insulating film on the semiconductor layer; and
a second gate insulating film on the first gate insulating film,
wherein a surface oxygen concentration of the second gate insulating film is higher than a surface oxygen concentration of the first gate insulating film.
21. The display device according to claim 20, wherein a dipole moment is formed between the first gate insulating film and the second gate insulating film.
22. A thin film transistor substrate comprising:
a substrate;
a semiconductor layer on the substrate; and
a gate electrode spaced apart from the semiconductor layer, at least a portion of the gate electrode overlapping the semiconductor layer,
wherein two layers different in surface oxygen concentration are sequentially stacked on at least one side of an upper side and a lower side of the semiconductor layer, and of the two layers located on the same side of the semiconductor layer, a layer farther from the semiconductor layer has a surface oxygen concentration higher than a layer closer to the semiconductor layer.
23. The thin film transistor substrate of claim 22, wherein a dipole moment is formed between two layers located on the same side of the semiconductor layer.
Technical Field
The present invention relates to a thin film transistor substrate including a thin film transistor capable of preventing a leakage current, a shift register, and a display device.
Background
With the development of multimedia, the importance of display devices increases. Recently, flat panel display devices such as liquid crystal display devices, plasma display devices, and organic light emitting display devices have been widely used.
The gate driver of the flat panel display device includes a shift register configured to sequentially supply a gate pulse to a plurality of gate lines. The shift register includes a plurality of stages having a plurality of transistors, wherein the stages are cascade-connected to sequentially output gate pulses.
In the case of a liquid crystal display device or an organic light emitting display device, transistors included in a shift register of a gate driver are provided as a thin film transistor type in a substrate of a display panel, which is called a gate-in-panel (GIP) structure.
The thin film transistor included in the shift register of the GIP structure supplies a gate pulse to the thin film transistor of each pixel disposed in the active region. Thus, in addition to basic transistor characteristics such as mobility and leakage current, the thin film transistor must have electrical reliability and durability capable of maintaining a long life.
The semiconductor layer of the thin film transistor included in the shift register of the GIP structure may be formed of amorphous silicon or polycrystalline silicon (polysilicon). When amorphous silicon is used, it has advantages of simplification of a film formation process and reduction in manufacturing cost, but it is difficult to ensure electrical reliability. When polycrystalline silicon is used, it is difficult to apply to a large-sized display device due to a high process temperature, and it is difficult to ensure uniformity according to a crystallization method. In order to overcome these problems, a method of using an oxide semiconductor for a semiconductor layer of a transistor is studied.
The oxide semiconductor is considered to be a stable material of a non-crystal form. When an oxide semiconductor is used for a semiconductor layer of a thin film transistor, the transistor can be manufactured at a low temperature by using related art equipment without additional equipment, and an ion implantation process can be omitted.
However, the oxide semiconductor transistor generally has a negative threshold voltage, thereby generating a leakage current when the gate voltage (Vg) is 0 (zero). Due to the leakage current, a normal gate pulse cannot be supplied from the shift register. Therefore, a method of preventing a leakage current in an oxide semiconductor transistor of a shift register is required.
Disclosure of Invention
The present invention has been made in view of the above problems, and it is an object of the present invention to provide a thin film transistor substrate including a thin film transistor capable of preventing a leakage current.
Another object of the present invention is to provide a shift register including a thin film transistor capable of preventing a leakage current.
It is still another object of the present invention to provide a display device including a thin film transistor capable of preventing a leakage current.
In accordance with one aspect of the present invention, the above and other objects can be accomplished by the provision of a thin film transistor substrate comprising: the method comprises the following steps: a substrate; a first buffer layer on the substrate; a second buffer layer on the first buffer layer; a semiconductor layer on the second buffer layer; and a gate electrode spaced apart from the semiconductor layer, at least a portion of the gate electrode overlapping the semiconductor layer, wherein a surface oxygen concentration of the first buffer layer is higher than a surface oxygen concentration of the second buffer layer.
According to one or more embodiments of the present invention, a dipole moment is formed between the first buffer layer and the second buffer layer.
According to one or more embodiments of the present invention, the first buffer layer includes an ionic bond and the second buffer layer includes a covalent bond, and wherein the ionic bond includes a metal.
According to one or more embodiments of the present invention, the semiconductor layer includes an oxide semiconductor material.
According to one or more embodiments of the present invention, the semiconductor layer includes a first semiconductor layer on the buffer layer and a second semiconductor layer on the first semiconductor layer.
According to one or more embodiments of the present invention, the thin film transistor substrate further includes: a first gate insulating film on the semiconductor layer; and a second gate insulating film on the first gate insulating film, wherein a surface oxygen concentration of the second gate insulating film is higher than a surface oxygen concentration of the first gate insulating film.
According to one or more embodiments of the present invention, a dipole moment is formed between the first gate insulating film and the second gate insulating film.
According to one or more embodiments of the present invention, the first gate insulating film includes a covalent bond, the second gate insulating film includes an ionic bond, and wherein the ionic bond includes a metal.
According to another aspect of the present invention, there is provided a thin film transistor substrate including: a semiconductor layer on the substrate; a first gate insulating film on the semiconductor layer; a second gate insulating film on the first gate insulating film; and a gate electrode on the second gate insulating film, wherein a surface oxygen concentration of the second gate insulating film is higher than a surface oxygen concentration of the first gate insulating film.
According to one or more embodiments of the present invention, a dipole moment is formed between the first gate insulating film and the second gate insulating film.
According to another aspect of the present invention, there is provided a display device including: a substrate; a shift register on the substrate; and a pixel connected to the shift register, wherein the shift register includes a stage connected to the pixel through a gate line, wherein the stage includes at least one thin film transistor, wherein the thin film transistor includes: a first buffer layer on the substrate; a second buffer layer on the first buffer layer; a semiconductor layer on the second buffer layer; and a gate electrode spaced apart from the semiconductor layer, at least a portion of the gate electrode overlapping the semiconductor layer, wherein a surface oxygen concentration of the first buffer layer is higher than a surface oxygen concentration of the second buffer layer.
According to one or more embodiments of the present invention, a dipole moment is formed between the first buffer layer and the second buffer layer.
According to one or more embodiments of the present invention, the first buffer layer includes an ionic bond and the second buffer layer includes a covalent bond, and wherein the ionic bond includes a metal.
According to one or more embodiments of the present invention, the semiconductor layer includes an oxide semiconductor material.
According to one or more embodiments of the present invention, the thin film transistor further includes: a first gate insulating film on the semiconductor layer; and a second gate insulating film on the first gate insulating film, wherein a surface oxygen concentration of the second gate insulating film is higher than a surface oxygen concentration of the first gate insulating film.
According to one or more embodiments of the present invention, a dipole moment is formed between the first gate insulating film and the second gate insulating film.
According to still another aspect of the present invention, there is provided a display device including: a substrate; and a plurality of pixels on the substrate, wherein the pixels include: a pixel driver on the substrate; and a display element connected to the pixel driver, wherein the pixel driver includes at least one thin film transistor, wherein the thin film transistor includes: a first buffer layer on the substrate; a second buffer layer on the first buffer layer; a semiconductor layer on the second buffer layer; and a gate electrode spaced apart from the semiconductor layer, at least a portion of the gate electrode overlapping the semiconductor layer, wherein a surface oxygen concentration of the first buffer layer is higher than a surface oxygen concentration of the second buffer layer.
According to one or more embodiments of the present invention, a dipole moment is formed between the first buffer layer and the second buffer layer.
According to one or more embodiments of the present invention, wherein the thin film transistor further includes: a first gate insulating film on the semiconductor layer; and a second gate insulating film on the first gate insulating film, wherein a surface oxygen concentration of the second gate insulating film is higher than a surface oxygen concentration of the first gate insulating film.
According to one or more embodiments of the present invention, a dipole moment is formed between the first gate insulating film and the second gate insulating film.
According to still another aspect of the present invention, there is provided a thin film transistor substrate comprising: a substrate; a semiconductor layer on the substrate; and a gate electrode spaced apart from the semiconductor layer, at least a portion of the gate electrode overlapping the semiconductor layer, wherein two layers different in surface oxygen concentration are sequentially stacked on at least one side of upper and lower sides of the semiconductor layer, and of the two layers located on the same side of the semiconductor layer, a layer farther from the semiconductor layer has a surface oxygen concentration higher than a layer closer to the semiconductor layer.
According to one embodiment of the present invention, a multi-layered buffer layer or a multi-layered gate insulating film is provided so that a semiconductor layer, which may include an oxide semiconductor material, may have a positive threshold voltage and may also prevent a leakage current in an off state.
According to another embodiment of the present invention, the thin film transistor is configured to be capable of preventing a leakage current, thereby making it unnecessary to additionally provide a thin film transistor capable of preventing a leakage current. Thus, the number of thin film transistors included in the shift register can be reduced, and the area of the shift register can be reduced. As a result, the area of the gate driver can be reduced.
According to another embodiment of the present invention, a display device includes a thin film transistor capable of preventing a leakage current. Accordingly, leakage of light emission due to a leakage current can be prevented, thereby improving the light emission efficiency of the display device.
In addition to the effects of the present invention as described above, other advantages and features of the present invention will be clearly understood from the description of the present invention by those skilled in the art.
Drawings
The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
fig. 1 is a schematic view illustrating a display device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram showing a shift register;
fig. 3 is a circuit diagram illustrating stages included in the shift register of fig. 2;
fig. 4 is a sectional view showing a thin film transistor substrate according to another embodiment of the present invention;
fig. 5 is a sectional view showing a thin film transistor substrate according to another embodiment of the present invention;
fig. 6 is a sectional view showing a thin film transistor substrate according to another embodiment of the present invention;
fig. 7 is a sectional view showing a thin film transistor substrate according to another embodiment of the present invention;
fig. 8 is a sectional view showing a thin film transistor substrate according to another embodiment of the present invention;
fig. 9A is a sectional view showing a thin film transistor substrate according to a comparative example;
fig. 9B is an energy band diagram showing a thin film transistor according to a comparative example;
fig. 9C is a graph showing a drain current according to a gate voltage in the thin film transistor according to the comparative example;
fig. 9D is a circuit diagram showing a stage according to a comparative example;
fig. 10 is a schematic diagram illustrating a principle of generation of dipole moment according to another embodiment of the present invention;
fig. 11A is a band diagram showing a thin film transistor according to another embodiment of the present invention;
fig. 11B is a band diagram showing a thin film transistor according to another embodiment of the present invention;
fig. 12 is a graph showing drain currents according to gate voltages in a thin film transistor according to a comparative example and a thin film transistor according to an embodiment of the present invention;
fig. 13 to 16 are circuit diagrams illustrating each pixel applied to a display device according to other embodiments of the present invention.
Detailed Description
Advantages and features of the present invention and methods of accomplishing the same will be set forth in the following embodiments which are described with reference to the accompanying drawings. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Furthermore, the invention is limited only by the scope of the claims.
The shapes, sizes, proportions, angles and numbers disclosed in the drawings for the purpose of describing embodiments of the invention are by way of example only, and are not intended to be limiting of the invention to the details shown. Like reference numerals refer to like elements throughout. In the following description, a detailed description of related known functions or configurations will be omitted when it is determined that the detailed description may unnecessarily obscure the present invention.
Where the description in this application uses "including", "having" and "including", additional components may also be present, unless "only" is used.
In explaining an element, although not explicitly stated, the element should be construed as including an error range.
In describing the positional relationship, for example, when the positional relationship is described as "on … …", "above … …", "below … …", "below … …", and "after … …", the case where there is no contact therebetween may be included unless "just" or "directly" is used. When a first element is referred to as being "on" a second element, it does not mean that the first element must be above the second element in the figures. The upper and lower parts of the object concerned may vary depending on the positioning of the object. Thus, a situation in which a first element is "on" a second element includes both a situation in which the first element is "below" the second element and a situation in which the first element is "above" the second element, whether in the figures or in actual configuration.
In describing temporal relationships, for example, when the temporal sequence is described as "after … …", "subsequently", "next", and "before … …", a discontinuous condition may be included unless "exactly" or "directly" is used.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention.
The terms "first horizontal axis direction", "second horizontal axis direction" and "vertical axis direction" should not be interpreted based only on a geometric relationship in which the respective directions are strictly perpendicular to each other, and may refer to a direction having a wider directivity within a range in which the member of the present invention can be functionally operated.
It is to be understood that the term "at least one" includes all combinations that relate to any one item. For example, "at least one of the first element, the second element, and the third element" may include all combinations of two or more elements selected from the first element, the second element, and the third element, and each of the first element, the second element, and the third element.
As can be well understood by those skilled in the art, the features of the embodiments of the present invention can be partially or integrally combined or combined with each other, and can be technically variously interoperated and driven with each other. Embodiments of the invention may be implemented independently of each other or jointly in an interdependent relationship.
In the drawings, the same or similar elements are denoted by the same reference numerals even though they are depicted in different drawings.
In the embodiment of the invention, the source electrode and the drain electrode are distinguished from each other for convenience of explanation. However, the source electrode and the drain electrode may be used interchangeably. Thus, the source electrode may be a drain electrode, and the drain electrode may be a source electrode. In addition, the source electrode in any one embodiment of the present invention may be a drain electrode in another embodiment of the present invention, and the drain electrode in any one embodiment of the present invention may be a source electrode in another embodiment of the present invention.
In one or more embodiments of the present invention, for convenience of explanation, the source region is separated from the source electrode region, and the drain region is separated from the drain electrode region. However, the embodiments of the present invention are not limited to this structure. For example, the source region may be a source electrode and the drain region may be a drain electrode. Further, the source region may be a drain electrode, and the drain region may be a source electrode.
Fig. 1 is a schematic view illustrating a
As shown in fig. 1, a
The
The
The
The
The pixel P includes a display element and at least one thin film transistor for driving the display element. An image is displayed on the
The
The gate control signal GCS includes a Gate Start Pulse (GSP), a Gate Shift Clock (GSC), a gate output enable signal (GOE), a start signal (Vst), and a Gate Clock (GCLK). In addition, various control signals for controlling the
The data control signal DCS includes a Source Start Pulse (SSP), a source shift clock signal (SSC), a source output enable Signal (SOE), and a polarity control signal (POL).
The
The
According to an embodiment of the present invention, the
The
The
In detail, the
The Gate Pulse (GP) has an on voltage capable of turning on a switching element (thin film transistor) formed in the pixel P.
Further, the
Fig. 2 is a schematic diagram showing the
The
The
Thus, when "g" gate lines GL are provided in the
According to one embodiment of the present invention, the thin film transistor of the
In general, each
As shown in fig. 3, each
The pull-up transistor Tu is turned on or off according to the logic state of the Q node. When the pull-up transistor Tu is turned on, the clock signal CLK is supplied to the pull-up transistor Tu and the pull-up transistor Tu outputs the Gate Pulse (GP).
The pull-down transistor Td is connected between the pull-up transistor Tu and the off-
The output signal Vout of the
The start transistor Tst charges the Q node to the high level voltage VD in response to the previous output PRE from the previous stage. When the
The reset transistor Trs discharges a low potential voltage VSS corresponding to a reset voltage into a Q node in response to a following output NXT of a following stage. When the
In general, when the Q-node is in a high state, the control signal supplied to the gate terminal of the reset transistor Trs maintains a low state.
When a high level signal is supplied to the Q node, the pull-up transistor Tu is turned on, so that the pull-up transistor Tu outputs the Gate Pulse (GP). In this case, when the reset transistor Trs is turned off, the low potential voltage VSS is not supplied to the reset transistor Trs.
When the Gate Pulse (GP) is output, a control signal of a high level is supplied to the gate terminal of the reset transistor Trs, whereby the reset transistor Trs is turned on and the pull-up transistor Tu is turned off. As a result, the Gate Pulse (GP) is not output through the pull-up transistor Tu.
When the Gate Pulse (GP) is not generated, the inverter I transfers a Qb node control signal for generating a gate off signal (Goff) through the Qb node pull-down transistor Td.
In detail, the data voltage is output to the data line DL every one horizontal period by the Gate Pulse (GP) capable of turning on the switching element of each pixel P connected to the gate line GL, and the gate-off signal (Goff) for maintaining the off-state of the switching element is supplied to the gate line GL for the remaining period except for 1 horizontal period in 1 frame.
For this reason, the inverter I transfers the Qb node control signal through the Qb node pull-down transistor Td in the remaining period except for 1 horizontal period in 1 frame.
The pull-down transistor Td is turned on by the Qb node control signal supplied from the inverter I, whereby a gate off signal (Goff) is output to the gate line GL.
When a leakage current is generated in the transistors (Tst, Trs, Tu, Td) included in the
For example, when the Q-node control signal for outputting the Gate Pulse (GP) is transmitted to the pull-up transistor Tu, the reset transistor Trs prevents the Q-node control signal from leaking to the outside. If a leakage current is generated in the reset transistor Trs, the Q node control signal may leak when the Q node control signal is supplied to the pull-up transistor Tu.
When the
In order to prevent a leakage current in the transistors, the
In detail, the
According to an embodiment of the present invention, a dipole moment (dipole moment) is formed between the first and second buffer layers 231 and 232. The
Further, a Thin Film Transistor (TFT) includes a first
Hereinafter, a Thin Film Transistor (TFT) capable of preventing a leakage current and a thin film transistor substrate including such a Thin Film Transistor (TFT) will be described in detail with reference to the accompanying drawings.
Fig. 4 is a cross-sectional view illustrating a thin film transistor substrate 200 according to another embodiment of the present invention. The thin film transistor substrate 200 includes a thin
The thin film transistor substrate 200 according to another embodiment of the present invention includes a
The
According to another embodiment of the present invention, the remaining portion of the thin film transistor substrate 200 other than the
Hereinafter, a detailed structure of each element of the thin film transistor substrate 200 will be described as follows.
The
The light-
The
The
Due to the difference in the surface oxygen concentration, oxygen transfer (oxygen ions) occurs between the
According to another embodiment of the invention, the dipole moment
May be formed in a direction away from theDue to dipole moment
The fermi level Ef of theIn more detail, the
Meanwhile, according to another embodiment of the present invention, when a dipole moment is formed between the
According to another embodiment of the present invention, the
According to another embodiment of the present invention, the
According to another embodiment of the present invention, the
The
According to another embodiment of the present invention, the
The
Referring to fig. 4, a
The
The
An interlayer insulating
Fig. 5 is a sectional view illustrating a thin film transistor substrate 300 according to another embodiment of the present invention. Hereinafter, detailed descriptions of the same parts will be omitted in order to avoid unnecessary repetition.
In comparison with the thin film transistor substrate 200 of fig. 4, the thin film transistor substrate 300 of fig. 5 further includes a source electrode 280 and a drain electrode 290 on the
Referring to fig. 5, the source electrode 280 and the drain electrode 290 are connected to the
The source electrode 280 and the drain electrode 290 may include at least one of: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. Each of the source electrode 280 and the drain electrode 290 may be formed in a single layer structure of any one material selected from among the above-described molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof, or may be formed in a multi-layer structure of two or more materials selected from among the above-described molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.
The thin film transistor TFT2 provided in the thin film transistor substrate 300 of fig. 5 may be formed of a Thin Film Transistor (TFT) of the
Fig. 6 is a sectional view illustrating a thin
The thin
The
The first and
The thin film transistor TFT3 provided in the thin
Fig. 7 is a cross-sectional view illustrating a thin
In comparison with the thin film transistor substrate 200 of fig. 4, the thin
In detail, the thin
Oxygen (O) due to the difference in surface oxygen concentration2-) Transfer from the second
As a dipole moment is formed between the first
The first
According to another embodiment of the present invention, the first
In another mode, the first
The thin film transistor TFT4 provided in the thin
Fig. 8 is a cross-sectional view illustrating a thin film transistor substrate 600 according to another embodiment of the present invention.
The thin film transistor substrate 600 of fig. 8 includes a
The
Oxygen (O) due to the difference in surface oxygen concentration2-) Transfer from the second
As a dipole moment is formed between the first
The thin film transistor TFT5 provided in the thin film transistor substrate 600 of fig. 8 may be formed of a Thin Film Transistor (TFT) of the
As can be seen from this, the thin film transistor substrate according to the present invention may include two layers having different surface oxygen concentrations sequentially stacked on at least one side of the upper and lower sides of the semiconductor layer, and among the layers located on the same side of the semiconductor layer, a layer farther from the semiconductor layer may have a higher surface oxygen concentration than a layer closer to the semiconductor layer.
Fig. 9A is a sectional view showing a thin
Referring to fig. 9B, the
Fig. 9C is a graph showing a drain current according to a gate voltage in the thin film transistor according to the comparative example. Referring to fig. 9C, the thin film transistor TFT0 of the thin
When the thin film transistor TFT0 having a leakage current is used for the thin film transistor of the
Fig. 9D is a circuit diagram showing the
Compared to the
A T1 transistor is disposed between the start transistor Tst and the Q node, a T2 transistor is disposed between the transistor Tst and the third voltage V3, a T3 transistor is disposed between the reset transistor Trs and the low potential voltage VSS, and a T4 transistor is disposed between the reset transistor Trs and the fourth voltage V4.
When the thin film transistor TFT0 having a leakage current is used for the thin film transistors included in the
Meanwhile, when the thin film transistors (TFT1, TFT2, TFT3, TFT4) according to the embodiment of the present invention are used for the thin film transistors included in the
Fig. 10 is a schematic view illustrating a principle of generation of dipole moment in a thin film transistor substrate 200 according to another embodiment of the present invention;
as described above, in the interface between the
As shown in fig. 7 and 8, even though the second gate is insulatedThe surface oxygen concentration of the insulating
Due to dipole moment
The fermi level Ef of theFig. 11A is a band diagram illustrating a thin film transistor TFT1 according to another embodiment of the present invention. Fig. 11B is a band diagram illustrating a thin film transistor TFT5 according to another embodiment of the present invention. Fig. 12 is a graph showing the drain current Id according to the gate voltage Vg in the thin film transistor (TFT0, TFT1) according to the comparative example and one embodiment of the present invention.
Referring to fig. 11A, a dipole moment is formed between the first and second buffer layers 231 and 232
The fermi level Ef of theThus, a leak current in the thin film transistor TFT1 can be prevented.
Fig. 11B shows the fermi level Ef of the
Referring to fig. 11B, when a dipole moment is formed between the first
The thin film transistors (TFT1, TFT2, TFT3, TFT4, TFT5) according to the embodiments of the present invention can be applied to pixels of a display device.
Hereinafter,
Fig. 13 to 16 are circuit diagrams illustrating each pixel P applied to a display device according to other embodiments of the present invention.
The
In detail, the thin film transistor (TR1c, TR1, TR2, TR3, TR4) of the pixel P includes a
In addition, the thin film transistors (TR1c, TR1, TR2, TR3, TR4) of the pixel P may include a first
The thin film transistors (TFT1, TFT2, TFT3, TFT4, TFT5) and their components including the
Fig. 13 is a circuit diagram illustrating a pixel P applied to a
Referring to fig. 13, the pixel P of the
The pixel driver PDC includes a thin film transistor TR1c connected to the gate line GL and the data line DL, and a storage capacitor Cst connected between the thin film transistor TR1c and the common electrode. The liquid crystal capacitor Clc and the storage capacitor Cst are connected in parallel between the thin film transistor TR1c and the common electrode.
The liquid crystal capacitor Clc corresponding to the display element is charged with a differential voltage between a common voltage Vcom supplied to the common electrode and a data signal supplied to the pixel electrode through the thin film transistor TR1c, and controls light transmittance by driving the liquid crystal according to the charged voltage. The storage capacitor Cst stably maintains the voltage charged in the liquid crystal capacitor Clc.
Fig. 14 is a circuit diagram illustrating a pixel P applied to a
The pixel P of the
The pixel driver PDC includes a first thin film transistor TR1 corresponding to the switching transistor and a second thin film transistor TR2 corresponding to the driving transistor.
The first thin-film transistor TR1 is connected to the gate line GL and the data line DL, and the first thin-film transistor TR1 is turned on or off by a gate pulse GP supplied via the gate line GL.
When the first thin film transistor TR1 is turned on, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the second thin film transistor TR2 connected to the organic light emitting diode OLED. The data voltage Vdata is charged into the storage capacitor Cst formed between the source electrode and the gate electrode of the second thin
The amount of current supplied to the organic light emitting diode OLED through the second thin film transistor TR2 is controlled according to the data voltage Vdata, and thus the gray level of light emitted from the organic light emitting diode OLED can be controlled.
Fig. 15 is a circuit diagram illustrating a pixel P applied to a
The pixel P of the
In the pixel P, there is a signal line (DL, GL, PLA, PLB, SL, SPL) configured to supply a drive signal to the pixel driver PDC.
The data voltage Vdata is supplied to the data line DL, the gate pulse GP is supplied to the gate line GL, the first driving power ELVDD is supplied to the power line PLA, the second driving power EVSS is supplied to the driving power line PLB, the reference voltage Vref is supplied to the sensing line SL, and the sensing pulse SP is supplied to the sensing pulse line SPL.
Referring to fig. 15, when the gate line of the (n) th pixel P is referred to as "GLnWhen the gate line of the adjacent (n-1) th pixel P is called "GLn-1", corresponding to" GL of the gate line of the (n-1) th pixel Pn-1"serves as the sensing pulse line SPL of the (n) th pixel P.
For example, as shown in fig. 15, the pixel driver PDC includes: a first thin film transistor TR1 (switching transistor) connected to the gate line GL and the data line DL; a second thin film transistor TR2 (driving transistor) configured to control a current level supplied to the organic light emitting diode OLED according to the data voltage Vdata transferred through the first thin
The first capacitor C1 is located between the organic light emitting diode OLED and the gate electrode of the second thin
As the first thin-film transistor TR1 is turned on by the gate pulse GP supplied to the gate line GL, the first thin-film transistor TR1 transfers the data voltage Vdata supplied to the data line DL to the gate electrode of the second thin-
The third thin film transistor TR3 is connected to the sensing line SL and the first node n1 between the organic light emitting diode OLED and the second thin
The second node n2 connected to the gate electrode of the second thin film transistor TR2 is connected to the first thin
When the first thin film transistor TR1 is turned on, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the second thin
When the second thin film transistor TR2 is turned on, a current is supplied from the first driving power source ELVDD to the organic light emitting diode OLED through the second thin film transistor TR2, thereby emitting light from the organic light emitting diode OLED.
Fig. 16 is a circuit diagram illustrating a pixel P applied to a
The pixel P of the
The pixel driver PDC includes thin film transistors (TR1, TR2, TR3, TR 4). According to another embodiment of the present invention, the thin film transistors (TR1, TR2, TR3, TR4) may be formed of any one of the thin film transistors (TFT1, TFT2, TFT3, TFT4, TFT5) shown in fig. 4 to 8.
In the pixel P, there is a signal line (DL, EL, GL, PLA, PLB, SL, SPL) configured to supply a drive signal to the pixel driver PDC.
The pixel P of fig. 16 further includes a light emitting line EL, compared to the pixel P of fig. 15. The emission control signal EM is supplied to the emission line EL. In addition, the pixel driver PDC of fig. 16 further includes a fourth thin film transistor TR4 corresponding to the light emitting transistor configured to control a light emitting time point of the second thin film transistor TR2, as compared with the pixel driver PDC of fig. 15.
However, the embodiments of the present invention are not limited to the above-described structure. The pixel driver PDC may be formed in various structures known to those skilled in the art. For example, the pixel driver PDC may include five or more thin film transistors.
Referring to fig. 16, when the gate line of the (n) th pixel P is referred to as "GLnWhen the gate line of the adjacent (n-1) th pixel P is called "GLn-1", corresponding to" GL of the gate line of the (n-1) th pixel Pn-1"serves as the sensing pulse line SPL of the (n) th pixel P.
The first capacitor C1 is located between one electrode of the organic light emitting diode OLED and the gate electrode of the second thin
As the first thin-film transistor TR1 is turned on by the gate pulse GP supplied to the gate line GL, the first thin-film transistor TR1 transfers the data voltage Vdata supplied to the data line DL to the gate electrode of the second thin-
The third thin film transistor TR3 is connected to the sensing line SL. The third thin film transistor TR3 is turned on or off by the sensing pulse SP, and the third thin film transistor TR3 senses a characteristic of the second thin film transistor TR2 corresponding to the driving transistor in the sensing period.
The fourth thin film transistor TR4 transfers the first driving power ELVDD to the second thin film transistor TR2 or blocks the first driving power ELVDD according to the emission control signal EM. When the fourth thin film transistor TR4 is turned on, a current is supplied to the second thin film transistor TR2, thereby emitting light from the organic light emitting diode OLED.
It will be apparent to those skilled in the art that the present invention described above is not limited to the above embodiments and the accompanying drawings, and that various substitutions, modifications and changes can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the scope of the present invention is defined by the appended claims, and all variations or modifications derived from the meaning, scope and equivalent concept of the claims fall within the scope of the present invention.
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