阅读说明：本技术 一种阵列基板、其制备方法及其显示面板 (Array substrate, preparation method thereof and display panel thereof ) 是由 肖军城 艾飞 尹国恒 许勇 于 2019-10-28 设计创作，主要内容包括：本发明提供了一种TFT阵列基板、其制备方法及其显示面板。其中所述TFT阵列基板，其定义有第一区域和第二区域，其中所述第一区域上设置有第一TFT，所述第二区域上设置有第二TFT。其中所述第一TFT为顶栅型TFT，所述第二TFT为底栅型TFT，其中所述第一TFT的源漏极层采用的材料与所述第二TFT的栅极层所采用的材料一致。本发明提供了一种TFT阵列基板，其采用新型的膜层结构设计，使得其上设置的第一TFT和第二TFT在设计和制程工艺上能够得到很好的兼容，从而有效的减小两者所在阵列基板的制程风险。(The invention provides a TFT array substrate, a preparation method thereof and a display panel thereof. The TFT array substrate is defined with a first area and a second area, wherein the first area is provided with a first TFT, and the second area is provided with a second TFT. The first TFT is a top gate type TFT, the second TFT is a bottom gate type TFT, and the source and drain electrode layers of the first TFT are made of the same material as the gate electrode layer of the second TFT. The invention provides a TFT array substrate, which adopts a novel film layer structure design, so that a first TFT and a second TFT arranged on the TFT array substrate can be well compatible in design and process technology, and the process risk of the array substrate on which the first TFT and the second TFT are arranged can be effectively reduced.)

1. A TFT array substrate is defined with a first area and a second area; the TFT-LCD device is characterized by comprising a substrate layer, wherein the substrate layer is provided with a first TFT on the first area, and a second TFT on the second area;

the first TFT is a top gate type TFT, and the second TFT is a bottom gate type TFT; and the source drain layer of the first TFT is made of the same material as the gate layer of the second TFT.

2. The TFT array substrate of claim 1; the method is characterized in that the source drain layer of the first TFT and the gate layer of the second TFT are formed in the same process step.

3. The TFT array substrate of claim 1; wherein the first region is a GOA region, and the first TFT is a LTPS type TFT.

4. The TFT array substrate of claim 1; wherein the second region is a display region, and the second TFT is an oxide semiconductor type TFT.

5. The TFT array substrate of claim 4; the material used for the oxide semiconductor layer used as the active layer In the second TFT includes one of oxide semiconductor materials such as In-Ga-Zn-O, In-Ga-O, Ga-Zn-O, In-Hf-Zn-O, In-Sn-Zn-O, In-Sn-O, In-Zn-O, Zn-Sn-O and In-Al-Zn-O.

6. A manufacturing method of manufacturing the TFT array substrate according to claim 1; it is characterized by comprising the following steps:

step S1, providing a substrate layer, which defines a first area and a second area, and completing the first TFT in the first area of the substrate layer; and

step S2, preparing the second TFT in a second area of the substrate layer;

in step S1, the gate layer of the second TFT is also fabricated at the same time as the source/drain layer of the first TFT is fabricated, so that both are completed in the same step.

7. The production method according to claim 6; wherein, in the step S1, the preparation of the first TFT includes the following sub-steps:

s11, preparing a Poly type active layer on the first area;

s12, preparing a first gate insulation layer on the active layer;

s13, preparing a first metal layer used as a grid layer on the grid insulating layer;

s14, preparing an interlayer dielectric layer on the first metal layer; and

s15, preparing a second metal layer on the interlayer dielectric layer to be used as a source drain layer;

in step S15, the second metal layer is deposited entirely on the first region and the second region, and after patterning and etching, the second metal layer forms a source/drain layer of the first TFT in the first region, and forms a gate layer serving as the second TFT in the second region.

8. The production method according to claim 6; wherein, in the step S2, the preparation of the second TFT comprises the following sub-steps:

s21, preparing a second gate insulating layer on the first region and the second region, and preparing a semiconductor metal oxide layer used as an active layer on the second gate insulating layer on the second region;

s22, preparing an etching barrier layer on the first area and the second area, wherein the etching barrier layer is arranged on the semiconductor metal oxide layer in the second area; and

s23, preparing a third metal layer serving as a source drain layer of the second TFT on the etching barrier layer of the second area.

9. The production method according to claim 6; the method is characterized by further comprising a step S3 of preparing a flat layer, a common electrode layer, a passivation layer and a pixel electrode layer which are included in the TFT array substrate.

10. A display device; characterized in that it comprises a TFT array substrate according to claim 1.

Technical Field

The invention relates to the technical field of flat panel display, in particular to an array substrate, a preparation method thereof and a display panel thereof.

Background

As the development of display technology advances, new flat panel displays have begun to replace CRT displays, and become the mainstream display devices in the market.

Among them, Liquid Crystal Displays (LCDs) are widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body, and wide application range, and become the mainstream of Display devices.

LCD devices have recently been developed with high resolution, narrow bezel, and low power consumption. In order to find a more power-saving method in a limited space and battery capacity, a Low Temperature polysilicon oxide (Low Temperature Poly-oxide) (ltpo) display technology is available. According to the technology, a Low Temperature Poly-silicon (LTPS) thin film transistor is adopted in a GOA area of a display panel, an oxide thin film transistor is adopted in an AA area, the LTPS technology is high in mobility, small in size, fast in charging and capable of effectively reducing the size of a frame, the IGZO technology is Low in dark current and capable of being driven at Low frequency, and therefore the functions of narrow frames and Low power consumption are achieved at the same time.

However, for the LTPO type array substrate, there are many design and process incompatibility problems between the LTPS TFT and Oxide TFT disposed thereon at the same time. For example, the Pre-Clean (HF solution) solution used in the SD process of the LTPS TFT may etch the IGZO layer of the Oxide TFT, a large amount of residual H contained in the ILD layer of the LTPS TFT after completion may destroy the electrical property of the IGZO layer of the Oxide TFT, and the different film thickness requirements of the common film layers of the LTPS TFT and the Oxide TFT, and the different etching of the deep and shallow holes due to the different thicknesses of the two, and so on.

Therefore, there is a need to develop a new TFT array substrate to overcome the defects of the prior art.

Disclosure of Invention

One aspect of the present invention is to provide a TFT array substrate, which adopts a novel film structure design, so that a Low Temperature Poly-Silicon (LTPS) TFT and an Oxide TFT disposed thereon can be well compatible in design and process, thereby effectively reducing the process risk of the LTPO type array substrate on which the LTPS TFT and the Oxide TFT are disposed.

The technical scheme adopted by the invention is as follows:

a TFT array substrate is defined with a first area and a second area; the TFT-LCD panel comprises a substrate layer, wherein the substrate layer is provided with a first TFT on a first area, and a second TFT on a second area. The first TFT is a top gate type TFT, the second TFT is a bottom gate type TFT, and the source and drain electrode layers of the first TFT are made of the same material as the gate electrode layer of the second TFT.

Further, in various embodiments, the source/drain layer of the first TFT and the gate layer of the second TFT are formed in the same process step in the manufacturing process.

Further, in various embodiments, wherein the first region is a GOA region, the first TFT is a LTPS-type TFT.

Further, in various embodiments, wherein the second region is a display region (AA region), the second TFT is an oxide semiconductor type TFT.

Further, In various embodiments, the material used for the oxide semiconductor layer used as the Active layer (Active) In the second TFT includes one of In-Ga-Zn-O, In-Ga-O, Ga-Zn-O, In-Hf-Zn-O, In-Sn-Zn-O, In-Sn-O, In-Zn-O, Zn-Sn-O and In-Al-Zn-O.

Further, another aspect of the present invention is to provide a method for manufacturing the TFT array substrate, including the following steps:

step S1, providing a substrate layer, which defines a first area and a second area, and completing the first TFT in the first area of the substrate layer;

step S2, preparing the second TFT in a second area of the substrate layer;

in step S1, the gate layer of the second TFT is also fabricated at the same time as the source/drain layer of the first TFT is fabricated, so that both are completed in the same step. That is, the source/drain layer of the first TFT and the gate layer of the second TFT are completed simultaneously, wherein in one embodiment, a conductive layer is deposited on the substrate, and then the conductive layer is patterned, and as a result of the etching, the conductive layer becomes the source/drain layer of the first TFT and the gate layer of the second TFT, respectively.

Further, in a different embodiment, in the step S1, the preparation of the first TFT includes the following sub-steps:

s11, preparing a Poly type active layer on the first area;

s12, preparing a first gate insulation layer (GI) on the active layer;

s13, preparing a first metal layer (M1) used as a gate electrode layer (GE1) on the gate insulating layer;

s14, preparing an interlayer dielectric layer (ILD) on the first metal layer; and

s15, preparing a second metal layer (M2) on the interlayer dielectric layer to be used as a source drain layer;

in step S15, the second metal layer is deposited entirely on the first region and the second region, and after patterning and etching, the second metal layer forms a source/drain layer of the first TFT in the first region, and forms a gate layer (GE2) serving as the second TFT in the second region, respectively.

Further, in a different embodiment, in the step S2, the preparation of the second TFT includes the following sub-steps:

s21, preparing a second gate insulation layer (GI2) on the first area and the second area, and preparing a semiconductor metal oxide layer used as an Active layer (Active) on the second gate insulation layer on the second area;

s22, preparing an Etch Stop Layer (ESL) on the first region and the second region, wherein the Etch Stop Layer is disposed on the semiconductor metal oxide Layer in the second region; and

s23, preparing a third metal layer (M3) serving as a source drain layer of the second TFT on the etching barrier layer of the second area.

Further, in various embodiments, the method for manufacturing a TFT array substrate according to the present invention further includes step S3, in which the method includes preparing a planarization layer, a common electrode layer, a passivation layer, and a pixel electrode layer included in the TFT array substrate.

Further, another aspect of the present invention is to provide a display panel using the TFT array substrate according to the present invention.

Further, in various embodiments, the display panel is preferably an LCD display panel.

Compared with the prior art, the invention has the beneficial effects that: according to the TFT array substrate, the novel process is adopted and the novel functional layer structure is combined, two different types of TFT preparation are carried out backwards in different areas on the glass substrate, so that the preparation of the first TFT cannot influence the preparation of the second TFT, the process risk of the whole TFT array substrate is reduced, and the stability of devices on the TFT array substrate is improved.

Furthermore, the novel functional layer setting scheme adopted by the invention also correspondingly optimizes the manufacturing process of the TFT array substrate where the novel functional layer setting scheme is located, and the process of the first TFT and the process of the second TFT are skillfully connected together in the step by setting the material adopted by the source drain layer of the first TFT to be consistent with the material adopted by the gate layer of the second TFT, namely the source drain layer of the first TFT and the gate layer of the second TFT are simultaneously completed by patterning the same conductive layer in the same photomask (Mask) process step, rather than the two types of TFTs are completely and independently prepared front and back; correspondingly, a Mask (Mask) process in the whole array substrate manufacturing process is also saved, so that the whole manufacturing steps of the TFT array substrate related by the invention are saved to a certain extent, and the preparation cost is also saved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a TFT array substrate according to an embodiment of the present invention, after completing the S11 substep in the step S1;

fig. 2 is a schematic structural diagram of the TFT array substrate of fig. 1 after completion of the S12 substep in the step S1;

fig. 3 is a schematic structural diagram of the TFT array substrate of fig. 1 after completion of the S13 substep of step S1;

fig. 4 is a schematic structural diagram of the TFT array substrate of fig. 1 after completion of the S14 substep of step S1;

fig. 5 is a schematic structural diagram of the TFT array substrate of fig. 1 after completion of the S15 substep of step S1;

fig. 6 is a schematic structural diagram of the TFT array substrate of fig. 1 after completion of the S21 substep of step S2;

fig. 7 is a schematic structural diagram of the TFT array substrate of fig. 1 after completion of the S22 substep of step S2;

fig. 8 is a schematic structural view of the TFT array substrate of fig. 1 after completion of the S23 substep of step S2; and

fig. 9 is a schematic structural diagram of the method for manufacturing the TFT array substrate shown in fig. 1 after step S3 is completed.

Detailed Description

The following describes a TFT array substrate, a method for manufacturing the same, and a display panel according to embodiments of the present invention in further detail with reference to the accompanying drawings.

Since the present invention relates to a TFT array substrate and a method for manufacturing the same, the structure of the TFT array substrate related to the present invention will be described below by way of example in conjunction with the method for manufacturing the TFT array substrate related to the present invention in order to avoid unnecessary details.

One embodiment of the present invention provides a method for manufacturing a TFT array substrate, which includes the steps of:

step S1, providing a substrate layer, which defines a first area 100 and a second area 200, and completing the first TFT in the first area of the substrate layer. The first area 100 is preferably a GOA area, the second area 200 is preferably a display area (AA area), and the substrate layer may specifically include a Glass substrate layer (Array Glass)101 and a Buffer layer (Buffer)102 disposed thereon, but is not limited thereto.

The specific implementation comprises the following substeps:

s11, sequentially performing Mask 1 and Mask 2 processes on the buffer layer 102 in the first region 100 to prepare a Poly type active layer 103, and referring to fig. 1, a schematic diagram of the completed structure is shown;

s12, forming a first gate insulation layer (GI)104 on the active layer 103, the structure of which is shown in fig. 2;

s13, preparing a first metal layer (M1)105 serving as a gate electrode layer (GE1) on the gate insulating layer 104 by a Mask 3 process, and the structure after completion is shown in fig. 3;

s14, forming an inter-layer dielectric (ILD)106 on the first metal layer 105 by Mask 4 process, and referring to fig. 4 for a structural diagram after completion; and

s15, preparing a second metal layer (M2) on the interlayer dielectric layer by a Mask 5 process to serve as the source/drain layer 107 of the first TFT, and referring to fig. 5 for a structural diagram after completion;

in step S15, the second metal layer is deposited on the first area 100 and the second area 200 in a whole layer, and after patterning and etching the second metal layer, the source and drain layers 107 of the first TFT are formed in the first area, respectively, and the gate layer (GE2)201 serving as the second TFT is formed in the second area.

Step S2, completing the second TFT in the second area 200 of the substrate layer;

s21, preparing a second gate insulating layer (GI2)202 on the first region 100 and the second region 200 by a Mask 6 process, and preparing a semiconductor metal oxide layer (IGZO)203 used as an Active layer (Active) on the second gate insulating layer 202 on the second region 200, wherein the completed structure is shown in fig. 6;

s22, preparing an Etch Stop Layer (ESL) 204 on the first region 100 and the second region 200 by a Mask 7 process, wherein the etch stop Layer 204 is disposed on the semiconductor metal oxide Layer 203 in the second region 200, and the completed structure diagram is shown in fig. 7; and

s23, a Mask 8 process is performed to form a third metal layer (M3)205 on the etch stop layer 204 of the second region, which is used as a source/drain layer of the second TFT, and the completed structure is shown in fig. 8.

Step S3, in which the TFT array substrate includes a Planarization Layer (PLN)206, a common electrode layer (BITO)207, a passivation layer (PV)208, and a pixel electrode layer (ITO)209, which are respectively prepared by Mask 9 to Mask 12 processes, and a structure diagram is shown after the completion, please refer to fig. 9. Meanwhile, the array substrate structure shown in fig. 9 is also a complete diagram of the array substrate according to the present invention.

Further, another aspect of the present invention is to provide a display panel using the TFT array substrate according to the present invention. Wherein the display panel is preferably an LCD display panel.

According to the TFT array substrate, the novel process is adopted and the novel functional layer structure is combined, two different types of TFT preparation are carried out backwards in different areas on the glass substrate, so that the preparation of the first TFT cannot influence the preparation of the second TFT, the process risk of the whole TFT array substrate is reduced, and the stability of devices on the TFT array substrate is improved.

Furthermore, the novel functional layer setting scheme adopted by the invention also correspondingly optimizes the manufacturing process of the TFT array substrate where the novel functional layer setting scheme is located, and the process of the first TFT and the process of the second TFT are skillfully connected together in the step by setting the material adopted by the source drain layer of the first TFT to be consistent with the material adopted by the gate layer of the second TFT, namely the source drain layer of the first TFT and the gate layer of the second TFT are simultaneously completed by patterning the same conductive layer in the same photomask (Mask) process step, rather than the two types of TFTs are completely and independently prepared front and back; correspondingly, a Mask (Mask) process in the whole array substrate manufacturing process is also saved, so that the whole manufacturing steps of the TFT array substrate related by the invention are saved to a certain extent, and the preparation cost is also saved.

The technical scope of the present invention is not limited to the contents described in the above description, and those skilled in the art can make various changes and modifications to the above-described embodiments without departing from the technical spirit of the present invention, and these changes and modifications should fall within the scope of the present invention.