阅读说明：本技术 一种显示基板及其制备方法、显示装置 (Display substrate, preparation method thereof and display device ) 是由 刘宁 苏同上 王庆贺 王东方 周斌 闫梁臣 于 2019-11-19 设计创作，主要内容包括：本发明公开了一种显示基板及其制备方法、显示装置，所述显示基板包括：基底，设置在所属基底上的驱动结构层，所述驱动结构层包括：有源层、设置在所述有源层上的第一绝缘层，设置在所述第一绝缘层上的栅极和栅极信号走线，设置在所述栅极和栅极信号走线上的第二绝缘层，设置在所述第二绝缘层上的源漏电极和辅助阴极，其中，至少满足以下之一：所述栅极信号走线的厚度大于所述栅极的厚度，所述辅助阴极的厚度大于所述源漏电极的厚度。本实施例提供的方案，通过改变栅极信号走线与栅极的厚度差，辅助阴极与源漏电极的厚度差，减少了落差，减少了后续的过孔的深度，有利于实现搭接，提高了产品质量。(The invention discloses a display substrate, a preparation method thereof and a display device, wherein the display substrate comprises: the substrate, set up the drive structure layer on affiliated substrate, the drive structure layer includes: the active layer, set up in the first insulating layer on the active layer, set up grid and grid signal on the first insulating layer are walked, set up in the second insulating layer on grid and grid signal are walked, set up source-drain electrode and auxiliary cathode on the second insulating layer, wherein, satisfy one of following at least: the thickness of the gate signal wiring is larger than that of the gate, and the thickness of the auxiliary cathode is larger than that of the source and drain electrodes. According to the scheme provided by the embodiment, the thickness difference between the grid signal wiring and the grid is changed, the thickness difference between the auxiliary cathode and the source and drain electrodes is reduced, the fall is reduced, the depth of subsequent via holes is reduced, the lap joint is facilitated, and the product quality is improved.)

1. A display substrate, comprising: the substrate, set up the drive structure layer on affiliated substrate, the drive structure layer includes: the active layer, set up in the first insulating layer on the active layer, set up grid and grid signal on the first insulating layer are walked, set up in the second insulating layer on grid and grid signal are walked, set up source-drain electrode and auxiliary cathode on the second insulating layer, wherein, satisfy one of following at least: the thickness of the gate signal wiring is larger than that of the gate, and the thickness of the auxiliary cathode is larger than that of the source and drain electrodes.

2. The display substrate of claim 1, wherein the driving structure layer further comprises a passivation layer disposed on the source and drain electrodes and the auxiliary cathode, a planarization layer disposed on the passivation layer, and a reflective anode and a connection electrode disposed on the planarization layer, wherein the reflective anode is connected to the source and drain electrodes through a first via, and the connection electrode is connected to the auxiliary cathode through a second via.

3. The display substrate of claim 2, wherein the planarization layer is made of an organosiloxane material.

4. The display substrate of claim 1, wherein the driving structure layer further comprises: and the light shielding layer and the buffer layer are sequentially arranged between the substrate and the active layer.

5. The display substrate according to any one of claims 1 to 4, wherein the thickness of the gate is 1/3-1/2 of the thickness of the gate signal trace.

6. The display substrate according to any one of claims 1 to 4, wherein the thickness of the source and drain electrodes is 1/3-1/2 of the thickness of the auxiliary cathode.

7. A display device comprising the display substrate according to any one of claims 1 to 6.

8. A method for preparing a display substrate is characterized by comprising the following steps:

forming a substrate;

forming a drive structure layer disposed on the substrate, the drive structure layer comprising: the active layer, set up in the first insulating layer on the active layer, set up grid and grid signal on the first insulating layer are walked, set up in the second insulating layer on grid and grid signal are walked, set up source-drain electrode and auxiliary cathode on the second insulating layer, wherein, satisfy one of following at least: the thickness of the gate signal wiring is larger than that of the gate, and the thickness of the auxiliary cathode is larger than that of the source and drain electrodes.

9. The method of claim 8, wherein the gate and gate signal traces are prepared based on:

depositing a first metal film on the first insulating layer, and forming a pattern at a position corresponding to the gate signal wiring by patterning;

and depositing the first metal film again, and forming a grid pattern and a grid signal wiring pattern by composition.

10. The method for manufacturing a display substrate according to claim 8 or 9, wherein the source-drain electrode and the auxiliary cathode are manufactured based on the following method:

depositing a second metal film on the second insulating layer, and patterning to form a pattern at a position corresponding to the auxiliary cathode;

and depositing the second metal film again, and patterning to form a source and drain electrode pattern and an auxiliary cathode pattern.

Technical Field

The present invention relates to display technologies, and in particular, to a display substrate, a method for manufacturing the same, and a display device.

Background

A top gate TFT (Thin Film Transistor) has a short channel characteristic, so that an on-state current Ion thereof is effectively increased, thereby significantly improving a display effect and effectively reducing power consumption. In addition, since the overlap area between the Gate and the source/drain of the top Gate TFT is small, the parasitic capacitance generated is small, and thus the possibility of occurrence of defects such as GDS (Gate Data Short), etc. is reduced. The top gate type TFT has been receiving more and more attention because of its remarkable advantages as described above.

In recent years, large-sized AMOLED (Active-matrix Organic Light-Emitting Diode) display products have the advantages of high color gamut, high contrast, self-luminescence, and the like, and are widely applied to the fields of televisions and the like. In the manufacturing process of an AMOLED display panel with large size and high resolution, such as 8K and the like, because the density of 8K display pixels is extremely high, if the traditional evaporation and bottom emission combined mode is still adopted, the aperture ratio of the pixels is too low to meet the brightness requirement, and the like, the technology of printing primary color luminescent materials by combining top emission with bottom emission is mainly adopted for the current products. In order to make the primary color luminescent material printed on the array substrate TFT emit light more uniformly and have different colors without interfering with each other, it is necessary to perform planarization processing on the array substrate by using an SOG (Silicon Organic Glass, Organic siloxane material), and the subsequent reflective anode film layer is difficult to overlap with an SD (source/drain), and thus poor overlapping is likely to occur, which seriously affects the display quality of the product.

Disclosure of Invention

At least one embodiment of the invention provides a display substrate, a preparation method thereof and a display device, and the display quality of a product is improved.

To achieve the above object, at least one embodiment of the present invention provides a display substrate, including: the substrate, set up the drive structure layer on affiliated substrate, the drive structure layer includes: the active layer, set up in the first insulating layer on the active layer, set up grid and grid signal on the first insulating layer are walked, set up in the second insulating layer on grid and grid signal are walked, set up source-drain electrode and auxiliary cathode on the second insulating layer, wherein, satisfy one of following at least: the thickness of the gate signal wiring is larger than that of the gate, and the thickness of the auxiliary cathode is larger than that of the source and drain electrodes.

In an embodiment, the driving structure layer further includes a passivation layer disposed on the source-drain electrode and the auxiliary cathode, a planarization layer disposed on the passivation layer, and a reflective anode and a connection electrode disposed on the planarization layer, wherein the reflective anode is connected to the source-drain electrode through a first via hole, and the connection electrode is connected to the auxiliary cathode through a second via hole.

In one embodiment, the planarization layer is made of an organosiloxane material.

In one embodiment, the driving structure layer further includes: and the light shielding layer and the buffer layer are sequentially arranged between the substrate and the active layer.

In one embodiment, the thickness of the gate is 1/3-1/2 of the thickness of the gate signal trace.

In one embodiment, the thickness of the source and drain electrodes is 1/3-1/2 of the thickness of the auxiliary cathode.

At least one embodiment of the present invention provides a display device, which includes the display substrate described in the above embodiment.

At least one embodiment of the present invention provides a method for manufacturing a display substrate, including:

forming a substrate;

forming a drive structure layer disposed on the substrate, the drive structure layer comprising: the active layer, set up in the first insulating layer on the active layer, set up grid and grid signal on the first insulating layer are walked, set up in the second insulating layer on grid and grid signal are walked, set up source-drain electrode and auxiliary cathode on the second insulating layer, wherein, satisfy one of following at least: the thickness of the gate signal wiring is larger than that of the gate, and the thickness of the auxiliary cathode is larger than that of the source and drain electrodes.

In one embodiment, the gate and the gate signal traces are prepared based on the following method:

depositing a first metal film on the first insulating layer, and forming a pattern at a position corresponding to the gate signal wiring by patterning;

and depositing the first metal film again, and forming a grid pattern and a grid signal wiring pattern by composition.

In one embodiment, the source-drain electrode and the auxiliary cathode are prepared based on the following method:

depositing a second metal film on the second insulating layer, and patterning to form a pattern at a position corresponding to the auxiliary cathode;

and depositing the second metal film again, and patterning to form a source and drain electrode pattern and an auxiliary cathode pattern.

Compared with the related art, the display substrate provided by the embodiment of the invention comprises: the substrate, set up the drive structure layer on affiliated substrate, the drive structure layer includes: the active layer, set up in the first insulating layer on the active layer, set up grid and grid signal on the first insulating layer are walked, set up in the second insulating layer on grid and grid signal are walked, set up source-drain electrode and auxiliary cathode on the second insulating layer, wherein, satisfy one of following at least: the thickness of the gate signal wiring is larger than that of the gate, and the thickness of the auxiliary cathode is larger than that of the source and drain electrodes. According to the scheme provided by the embodiment, the thickness difference between the grid signal wiring and the grid is changed, the thickness difference between the auxiliary cathode and the source and drain electrodes is reduced, the fall is reduced, the depth of subsequent via holes is reduced, the lap joint is facilitated, and the product quality is improved.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.

FIGS. 1 to 4 are schematic views of a display substrate provided in the related art;

fig. 5 is a schematic view of a display substrate according to an embodiment of the present application;

FIG. 6 is a schematic diagram illustrating a substrate, a light-shielding layer and a buffer layer after patterning according to an embodiment of the present disclosure;

FIG. 7 is a schematic view illustrating the deposition of a first metal film according to one embodiment of the present disclosure;

FIG. 8 is a schematic view of a first metal film patterned according to an embodiment of the present disclosure;

FIG. 9 is a schematic view of a second deposition of a first metal film according to an embodiment of the present application;

FIG. 10 is a schematic view illustrating a gate pattern and a gate signal trace pattern formed according to an embodiment of the present application;

fig. 11 is a schematic view illustrating a source electrode pattern, a drain electrode pattern, and an auxiliary cathode pattern formed according to an embodiment of the present application;

FIG. 12 is a schematic view of a planarized layer formed according to an embodiment of the present application;

FIG. 13 is a schematic view of a planarization layer after forming a via in accordance with an embodiment of the present disclosure;

FIG. 14 is a schematic view of a reflective anode and a connecting electrode formed in accordance with an embodiment of the present application;

fig. 15 is a flowchart of a method for manufacturing a display substrate according to an embodiment of the present disclosure.

Description of reference numerals:

1-a glass carrier plate; 10-a substrate; 11a — a light-shielding layer;

11 b-a buffer layer; 12-an active layer; 13 — a first insulating layer;

14-a gate; 15-routing of grid signals; 16 — a second insulating layer;

19-source electrode; 20-a drain electrode; 21-an auxiliary cathode;

22 — a third insulating layer; 23-a planarization layer; 31-an anode;

32-connecting electrodes; 15a — a first metal film; 15b — initial pattern.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

As shown in fig. 1, a display substrate includes a substrate 10, a light shielding layer (Lightshield)11a, a buffer layer 11b, an active layer 12, a first insulating layer 13, a gate 14, a gate signal trace 15, a second insulating layer 16, a source electrode 19, a drain electrode 20, an auxiliary cathode 21, and a third insulating layer 22 sequentially disposed on the substrate 10. Due to the influence of the TFT patterning process of the array substrate, the film profile difference of different regions is large as shown in fig. 1, so that a thick SOG material is required to perform a good planarization process, as shown in fig. 2, the planarization layer 23 has a large thickness. The thicker SOG material (SOG thickness required to form the via is shown as h1 and h2 in fig. 2) results in the need of using a very thick PR (photoresist) resist for protection when etching the via and long dry etching time, and the profile of the SOG via is large due to the large profile angle (profile) formed by the thick PR resist and the long dry etching time (shown as fig. 3). The via hole profile is large and the SOG via hole is deep, so that the subsequent reflective anode 31 and the connection electrode 32 are difficult to lap on the SD (the source electrode 19 and the auxiliary cathode 21), as shown in fig. 4, a poor lap joint is easy to occur, and the display quality of the product is seriously affected.

An embodiment of the invention provides a display substrate, a manufacturing method thereof and a display device, wherein a brand-new TFT metal wiring design is adopted, so that the depth and the profile of an SOG through hole can be greatly reduced, the overlapping condition of a reflective anode is greatly improved, and the display quality of a product is improved. The display substrate provided by the embodiment of the invention comprises: the substrate, set up the drive structure layer on affiliated substrate, the drive structure layer includes: the active layer, set up in the first insulating layer on the active layer, set up grid and grid signal on the first insulating layer are walked, set up in the second insulating layer on grid and grid signal are walked, set up source-drain electrode and auxiliary cathode on the second insulating layer, wherein, satisfy one of following at least: the thickness of the gate signal wiring is larger than that of the gate, and the thickness of the auxiliary cathode is larger than that of the source and drain electrodes. According to the scheme provided by the embodiment, through changing the thickness difference of the grid and the grid signal wiring and at least one of the thickness difference of the source drain electrode and the auxiliary cathode, the offset between a TFT area and a non-TFT area is obviously reduced, the thickness of the planarization layer to be coated is thinned, so that the depth of the via hole is shallow, thinner PR glue can be used, and shorter dry etching time can be used, so that the slope angle profile of the formed via hole can be also slowed down, the overlapping of a subsequent reflection anode film layer is facilitated, and the display quality of a product is improved.

Fig. 5 is a schematic diagram of a display substrate according to an embodiment of the invention, illustrating a structure of a display area on a plane perpendicular to the display substrate. As shown in fig. 5, the main structure of the display area includes a driving structure layer disposed on the substrate in a plane perpendicular to the display substrate, the driving structure layer includes a plurality of thin film transistors, and only one thin film transistor is illustrated in fig. 5 as an example. The display substrate provided by the embodiment comprises: the organic light emitting diode comprises a substrate 10, a light shielding layer 11a arranged on the substrate 10, a buffer layer 11b covering the light shielding layer 11a, an active layer 12 arranged on the buffer layer 11b, a first insulating layer 13 arranged on the active layer 12, a gate 14 and a gate signal trace 15 arranged on the first insulating layer 13, a second insulating layer 16 covering the gate 14 and the gate signal trace 15, a source electrode 19, a drain electrode 20 and an auxiliary cathode 21 arranged on the second insulating layer 16, a third insulating layer 22 covering the source electrode 19, the drain electrode 20 and the auxiliary cathode 21, and a planarization layer 23 covering the third insulating layer 22, a reflective anode 31 and a connecting electrode 32 arranged on the planarization layer 23, wherein the reflective anode 31 is connected with the source electrode 19 through a first via, and the connecting electrode 32 is connected with the auxiliary cathode 21 through a second via. The thickness of the gate signal trace 15 is greater than that of the gate 14, and the thickness of the auxiliary cathode 21 is greater than that of the source electrode 19 and the drain electrode 20. According to the scheme provided by the embodiment, the thickness of the grid 14 is smaller than that of the grid signal wiring, the thickness of the source electrode 19 and the drain electrode 20 is smaller than that of the auxiliary cathode, so that the difference between a TFT area and a non-TFT area is obviously reduced, the thickness of a planarization layer to be coated is thinned, the depth of the SOG via hole is shallow, thinner PR glue can be used, shorter dry etching time is shortened, the slope angle profile of the formed via hole can be reduced, the overlapping of a subsequent reflection anode film layer is facilitated, and the display quality is improved.

The following further illustrates the technical solution of the embodiment of the present invention through the manufacturing process of the display substrate of this embodiment. The "patterning process" in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, the "photolithography process" in this embodiment includes processes such as film coating, mask exposure, and development, and the evaporation, deposition, coating, and coating in this embodiment are well-established preparation processes in the related art.

FIGS. 6-14 are schematic diagrams illustrating a manufacturing process of the display substrate of this embodiment. The preparation process of the display substrate comprises the following steps:

(1) and forming a substrate, a light-shielding layer and a buffer layer pattern. Forming the substrate, the light-shielding layer, and the buffer layer pattern includes: a substrate 10 is formed on a glass carrier 1. Subsequently, depositing a light shielding layer film on the substrate 10, and patterning to form a light shielding layer 11a pattern; a buffer layer thin film is deposited on the light-shielding layer 11a, and a buffer layer 11b covering the light-shielding layer 11a is formed as shown in fig. 6. The buffer layer 11b is, for example, an inorganic insulating layer.

The substrate 10 may include a plurality of layers, the light-shielding layer 11a may have a single-layer or stacked-layer structure of Mo, Al/Mo, Mo/Ti, or the like, and the buffer layer film may have a single-layer or multi-layer structure of silicon nitride/silicon oxide, such as silicon nitride SiNx or silicon oxide SiOx.

(2) An active layer pattern (Act pattern), a gate pattern and a gate signal routing pattern are formed on the buffer layer. Forming an active layer pattern, a gate pattern and a gate signal routing pattern on the buffer layer includes:

depositing an active layer film on the basis of the structure, and patterning the active layer film through a patterning process to form an active layer 12 pattern arranged on the buffer layer 11 b;

subsequently, a first insulating film is deposited to form a first insulating layer 13 covering the active layer 12; the first insulating layer 13 may be referred to as a gate insulating layer (GI).

Subsequently, the first metal thin film 15a is sequentially deposited. As shown in fig. 7. Then, an exposure patterning and etching process is performed to pattern the first metal film, so that all the metal on which the gate is to be formed is etched away, and the metal on which the gate signal trace is to be formed is left to form a corresponding initial pattern 15b, that is, the initial pattern 15b is formed at a position corresponding to the gate signal trace, where the width of the initial pattern 15b of the gate signal trace needs to be greater than the width of the final gate trace signal layer pattern, as shown in fig. 8.

The first metal film is deposited again as shown in fig. 9, and the first metal film is patterned to form a gate 14 pattern and a gate signal trace 15 pattern as shown in fig. 10. It can be seen that the metal layer of the gate 14 is thin and the metal layer of the gate signal trace 15 is thick, and since the gate 14 only plays a role of introducing voltage to turn on the TFT, too strong conductivity is not needed and the gate signal trace 15 needs strong conductivity in consideration of the voltage drop problem, the thin metal layer of the gate 14 and the thick metal layer of the gate signal trace 15 just can meet different requirements. In an embodiment, the thickness of the gate 14 is 1/3-1/2 of the thickness of the gate signal trace 15, and this thickness relationship is only an example, and other relationships are also possible. In this embodiment, the thickness of the gate signal trace 15 may be the same as that of the gate signal trace in fig. 4, and the thickness of the gate 14 is smaller than that of the gate in fig. 4. In this way, the height difference between the TFT region (where the gate 14 is located) and the non-TFT region (where the gate signal trace 14 is located) can be reduced subsequently. Of course, in other embodiments, the thickness of the gate signal trace 15 may be greater than that of the gate signal trace in fig. 4.

(3) A second insulating layer pattern, a source electrode pattern, a drain electrode pattern, and an auxiliary cathode pattern are formed.

Forming the second insulating layer pattern, the source electrode pattern, the drain electrode pattern, and the auxiliary cathode pattern includes: on the basis of forming the structure, depositing a second insulating film, patterning the second insulating film through a patterning process, forming a second insulating layer 16 pattern provided with a first via hole, a second via hole and a third via hole in the display area, and etching the second insulating layer 16 in the first via hole and the second via hole to expose the active layer 12; the second insulating layer 16 and the buffer layer 11b in the third via hole are etched away to expose the light shielding layer 11 a.

Depositing a second metal film, patterning the second metal film through a patterning process, and forming a pattern at a position corresponding to the auxiliary cathode;

a second metal film is again deposited and patterned through a patterning process to form a source electrode 19 pattern, a drain electrode 20 pattern, and an auxiliary cathode 21 pattern, as shown in fig. 11.

It can be seen that the metal layers of the source electrode 19, the drain electrode 20 are thin and the metal layer of the auxiliary cathode 21 is thick. In one embodiment, the thickness of the source electrode 19 and the drain electrode 20 is 1/3-1/2 of the thickness of the auxiliary cathode 21. It should be noted that the thicknesses are only examples, and the thicknesses may be in other relationships. The thickness of the auxiliary cathode 21 in this embodiment may be the same as that of the auxiliary cathode layer in fig. 4, and the thickness of the source electrode 19 and the drain electrode 20 is smaller than that of the source electrode 19 and the drain electrode 20 in fig. 4. In this way, the height difference between the TFT region (where the gate 14 is located) and the non-TFT region (where the gate signal trace 14 is located) can be reduced subsequently. Of course, in other embodiments, the thickness of the auxiliary cathode 21 may be greater than that of the auxiliary cathode layer in fig. 4.

The drain electrode 20 and the source electrode 19 are connected to the active layer 12 through a first via hole and a second via hole, respectively, the source electrode 19 is further connected to the light shielding layer 11a through a third via hole, and a junction of the active layer 12 and the drain electrode 20 and the source electrode 19 is made conductive (not shown in fig. 11).

The second insulating layer 16 is also referred to as an interlayer Insulating Layer (ILD).

(4) Forming a passivation layer pattern and a planarization layer pattern

On the basis of forming the above structure, a third insulating film is coated, and a passivation layer (PVX)22 pattern covering the source electrode 19, the drain electrode 20, and the auxiliary cathode 21 is formed by a photolithography process of mask exposure and development;

subsequently, a fourth insulating film is applied, and a planarization layer 23 is patterned to cover the passivation layer 22 by a photolithography process of mask exposure and development, as shown in fig. 12. The fourth insulating film is SOG, for example. The passivation layer 22 is opened with a fourth via and a fifth via as shown in fig. 13.

Since the Gate and the SD of the TFT region are significantly thinned compared to the conventional process, so that the step between the TFT region and the non-TFT region is significantly reduced, the SOG planarization layer to be coated may be significantly thinned (the SOG thickness at the via to be formed is shown as h3 and h4 in fig. 12), it can be seen that the heights of h3 and h4 are significantly less than the heights of h1 and h2 in fig. 2, i.e. the depth of the via to be formed is significantly shallower, so that a thinner PR gel and a shorter dry etching time may be used, and the slope angle profile of the formed via may also be slowed down, thereby being very beneficial to the overlapping of the subsequent reflective anode film layer.

(5) Forming a reflective anode and a connection electrode pattern.

Forming the reflective anode pattern and the connection electrode includes: on the basis of forming the structure, a conductive film is deposited, the conductive film is patterned through a patterning process to form a pattern of a reflective anode 31 and a pattern of a connection electrode 32, the reflective anode 31 is connected with the source electrode 19 through a fourth via hole, and the connection electrode 32 is connected with the auxiliary cathode 21 through a fifth via hole. As shown in fig. 14. The conductive film can be made of Mo/Al/ITO-T, Al alloy/ITO-T material.

By adopting the TFT metal wiring design provided by the embodiment, the depth and the profile of the SOG through hole can be greatly reduced, so that the overlapping condition of the reflective anode is greatly improved, and the quality improvement of a display product is facilitated.

According to the preparation process, the thickness proportion of the source-drain electrode and the auxiliary cathode and the thickness proportion of the grid electrode and the grid electrode wiring are changed, so that the offset of a TFT (thin film transistor) area and a non-TFT (thin film transistor) area is reduced, the depth of a via hole is reduced, the slope angle of the via hole is slowed down, the display quality of a product is improved by utilizing the lap joint of the reflective anode and the source electrode, and the display substrate has practical application value and good application prospect.

It should be noted that, in another embodiment, only the thickness ratio of the gate to the gate trace is changed, and the thickness ratio of the source electrode, the drain electrode and the auxiliary cathode is retained, or only the thickness ratio of the source electrode, the drain electrode and the auxiliary cathode is changed while the thickness ratio of the gate to the gate trace is retained.

It should be noted that the structure and the manufacturing process thereof shown in this embodiment are only an exemplary illustration. In practical implementation, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, other electrodes, leads, and structural film layers may also be disposed in the driving structural layer. The embodiments of the present invention are not limited specifically herein.

It should be noted that, in another embodiment, another preparation method may also be adopted to form the gate pattern and the gate signal trace pattern, the source electrode pattern, the drain electrode pattern, and the auxiliary cathode pattern.

The formation of the gate pattern and the gate signal trace pattern is taken as an example for illustration. After the first insulating layer 13 is formed, a first metal film is deposited on the first insulating layer 13, the thickness of the first metal film is equal to the thickness of the two first metal films deposited in the previous embodiment, patterning is performed, and a gate pattern and a gate signal trace pattern with different thicknesses are formed by controlling the etching rate.

As shown in fig. 15, based on the technical idea of the embodiment of the present invention, an embodiment of the present invention further provides a method for manufacturing a display substrate, including:

step 1501, forming a substrate;

step 1502, forming a driving structure layer disposed on the substrate, the driving structure layer including: the active layer, set up in the first insulating layer on the active layer, set up grid and grid signal on the first insulating layer are walked, set up in the second insulating layer on grid and grid signal are walked, set up source-drain electrode and auxiliary cathode on the second insulating layer, wherein, satisfy one of following at least: the thickness of the gate signal wiring is larger than that of the gate, and the thickness of the auxiliary cathode is larger than that of the source and drain electrodes.

In one embodiment, in the step 1502, the gate and gate signal traces are prepared based on:

depositing a first metal film on the first insulating layer, and forming a pattern at a position corresponding to the gate signal wiring by patterning;

and depositing the first metal film again, and forming a grid pattern and a grid signal wiring pattern by composition.

In an embodiment, in step 1502, the source-drain electrode and the auxiliary cathode are prepared based on the following steps:

depositing a second metal film on the second insulating layer, and patterning to form a pattern at a position corresponding to the auxiliary cathode;

and depositing the second metal film again, and patterning to form a source and drain electrode pattern and an auxiliary cathode pattern.

In this embodiment, the structure, material, related parameters, and detailed preparation process of each film layer have been described in detail in the foregoing embodiments, and are not described herein again.

The embodiment provides a preparation method of a display substrate, by changing at least one of the thickness difference of a grid electrode and a grid electrode signal wiring and the thickness difference of a source drain electrode and an auxiliary cathode, the offset between a TFT area and a non-TFT area is obviously reduced, the thickness of a planarization layer to be coated is thinned, so that the depth of a via hole is shallow, a thinner PR glue can be used, and a shorter dry etching time is used, so that the slope angle profile of the formed via hole is also slowed down, the overlapping of a subsequent reflection anode film layer is facilitated, and the display quality of a product is improved.

Based on the technical idea of the embodiment of the present invention, an embodiment of the present invention further provides a display device, including the display substrate of the foregoing embodiment. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

The following points need to be explained:

(1) the drawings of the embodiments of the invention only relate to the structures related to the embodiments of the invention, and other structures can refer to common designs.

(2) The thickness of layers or regions in the figures used to describe embodiments of the invention may be exaggerated or reduced for clarity, i.e., the figures are not drawn on a true scale. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

(3) Without conflict, embodiments of the present invention and features of the embodiments may be combined with each other to arrive at new embodiments.

Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.